- added double buffer

- added INT_O on buffer change
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git-svn-id: http://moon:8086/svn/vhdl/trunk@641 cc03376c-175c-47c8-b038-4cd826a8556b

lib/VGA_ctrl/src/tb_vga_frontend64.vhd

@@ -40,6 +40,7 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
 	signal RST_O			: std_logic := '1';
 
 	-- Master
+	signal INT_O			: std_logic;
 	signal CYC_O			: std_logic;
 	signal STB_O			: std_logic;
 	signal WE_O				: std_logic;
@@ -103,6 +104,7 @@ inst_vga_frontend64 : entity work.vga_frontend64
 		MDAT_O			=> MDAT_I,
 
 		-- JBUS Slave signals
+		INT_O			=> INT_O,
 		CYC_I			=> CYC_O,
 		STB_I			=> STB_O,
 		WE_I			=> WE_O,