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- made GPIO 0 bidirectional (added GPIO_DIR register)

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- removed GPIO 1
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git-svn-id: http://moon:8086/svn/vhdl/trunk@792 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-03-13 16:46:21 +00:00
parent db662f411f
commit fcce3dcf32
7 changed files with 1377 additions and 1378 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/misc/gpio_wb.vhd
+52 -68
View File
@@ -23,47 +23,45 @@ ENTITY gpio_wb IS
DAT_O : out unsigned(31 downto 0);
INT_TIM_O : out STD_LOGIC;
sys_gpo0 : out unsigned(31 downto 0);
sys_gpo1 : out unsigned(31 downto 0);
sys_gpi0 : in unsigned(31 downto 0);
sys_gpi1 : in unsigned(31 downto 0)
sys_gpi_0 : in unsigned(31 downto 0);
sys_gpo_0 : out unsigned(31 downto 0)
);
END gpio_wb;
ARCHITECTURE behavior OF gpio_wb IS
constant num_timers : natural := 2;
constant ncycles_usec : natural := natural(f_sysclk);
constant num_timers : natural := 2;
constant ncycles_usec : natural := natural(f_sysclk);
signal gpo0_reg : unsigned(31 downto 0);
signal gpo1_reg : unsigned(31 downto 0);
signal gpi0_reg : unsigned(31 downto 0);
signal gpi1_reg : unsigned(31 downto 0);
signal gpio_0_dout_reg : unsigned(31 downto 0);
signal gpio_0_dir_reg : unsigned(31 downto 0);
signal gpio_0_din_reg : unsigned(31 downto 0);
-- Signals to form an timer generating an interrupt every microsecond
subtype tick_usec_t is natural range 0 to ncycles_usec-1;
signal tick_usec : tick_usec_t := 0;
signal cnt_usec : unsigned(31 downto 0);
signal cnt_sec : unsigned(31 downto 0);
signal cnt_usec_preset : unsigned(31 downto 0);
signal cnt_sec_preset : unsigned(31 downto 0);
signal cnt_usec_en : std_logic;
signal cnt_usec_we : std_logic;
signal cnt_sec_en : std_logic;
signal cnt_sec_we : std_logic;
signal tick_usec : tick_usec_t := 0;
signal cnt_usec : unsigned(31 downto 0);
signal cnt_sec : unsigned(31 downto 0);
signal cnt_usec_preset : unsigned(31 downto 0);
signal cnt_sec_preset : unsigned(31 downto 0);
signal cnt_usec_en : std_logic;
signal cnt_usec_we : std_logic;
signal cnt_sec_en : std_logic;
signal cnt_sec_we : std_logic;
type timer_array_t is array (0 to num_timers-1) of unsigned(31 downto 0);
signal timer_cnt : timer_array_t;
signal timer_cmp : timer_array_t;
signal timer_en : unsigned(0 to num_timers-1);
signal timer_inten : unsigned(0 to num_timers-1);
signal timer_irq : unsigned(0 to num_timers-1);
signal timer_ovl : unsigned(0 to num_timers-1);
signal timer_irq_ack : unsigned(0 to num_timers-1);
signal timer_cnt_we : unsigned(0 to num_timers-1);
signal timer_cmp_we : unsigned(0 to num_timers-1);
signal timer_cnt : timer_array_t;
signal timer_cmp : timer_array_t;
signal timer_en : unsigned(0 to num_timers-1);
signal timer_inten : unsigned(0 to num_timers-1);
signal timer_irq : unsigned(0 to num_timers-1);
signal timer_ovl : unsigned(0 to num_timers-1);
signal timer_irq_ack : unsigned(0 to num_timers-1);
signal timer_cnt_we : unsigned(0 to num_timers-1);
signal timer_cmp_we : unsigned(0 to num_timers-1);
signal reg_data_wr : unsigned(31 downto 0);
signal reg_data_wr : unsigned(31 downto 0);
begin
@@ -81,25 +79,33 @@ tim_irq:
end process;
------------------------------------------------------------------
led_out:
process(CLK_I)
gpio_0_out:
process(gpio_0_dir_reg, gpio_0_dout_reg)
begin
if rising_edge(CLK_I) then
sys_gpo0 <= gpo0_reg;
sys_gpo1 <= gpo1_reg;
end if;
for i in 0 to 31 loop
sys_gpo_0(i) <= 'Z';
if gpio_0_dir_reg(i) = '1' then
sys_gpo_0(i) <= gpio_0_dout_reg(i);
end if;
end loop;
end process;
------------------------------------------------------------------
btn_ps2_in:
gpio_0_in:
process(CLK_I)
begin
if rising_edge(CLK_I) then
gpi0_reg <= sys_gpi0;
gpi1_reg <= sys_gpi1;
for i in 0 to 31 loop
if gpio_0_dir_reg(i) = '1' then
gpio_0_din_reg(i) <= gpio_0_dout_reg(i);
else
gpio_0_din_reg(i) <= sys_gpi_0(i);
end if;
end loop;
end if;
end process;
------------------------------------------------------------------
registers_write:
process(CLK_I)
@@ -111,41 +117,19 @@ registers_write:
timer_cmp_we <= (others => '0');
timer_irq_ack <= (others => '0');
if RST_I = '1' then
gpo0_reg <= (others => '0');
gpo1_reg <= (others => '0');
timer_en <= (others => '0');
timer_inten <= (others => '0');
gpio_0_dout_reg <= (others => '0');
gpio_0_dir_reg <= (others => '0');
timer_en <= (others => '0');
timer_inten <= (others => '0');
elsif (STB_I and CYC_I and WE_I) = '1' then
reg_data_wr <= DAT_I;
case ADDR_I(6 downto 2) is
when "00000" =>
if SEL_I(0) = '1' then
gpo0_reg(7 downto 0) <= DAT_I(7 downto 0);
end if;
if SEL_I(1) = '1' then
gpo0_reg(15 downto 8) <= DAT_I(15 downto 8);
end if;
if SEL_I(2) = '1' then
gpo0_reg(23 downto 16) <= DAT_I(23 downto 16);
end if;
if SEL_I(3) = '1' then
gpo0_reg(31 downto 24) <= DAT_I(31 downto 24);
end if;
gpio_0_dout_reg <= DAT_I;
when "00001" =>
if SEL_I(0) = '1' then
gpo1_reg(7 downto 0) <= DAT_I(7 downto 0);
end if;
if SEL_I(1) = '1' then
gpo1_reg(15 downto 8) <= DAT_I(15 downto 8);
end if;
if SEL_I(2) = '1' then
gpo1_reg(23 downto 16) <= DAT_I(23 downto 16);
end if;
if SEL_I(3) = '1' then
gpo1_reg(31 downto 24) <= DAT_I(31 downto 24);
end if;
gpio_0_dir_reg <= DAT_I;
when "00010" =>
cnt_usec_we <= '1';
@@ -192,10 +176,10 @@ registers_read:
case ADDR_I(6 downto 2) is
when "00000" =>
DAT_O <= gpi0_reg;
DAT_O <= gpio_0_din_reg;
when "00001" =>
DAT_O <= gpi1_reg;
DAT_O <= gpio_0_dir_reg;
when "00010" =>
DAT_O <= cnt_usec;