- blitter FIFO is reseted on every new request
- blitter always avaliable regardless of MSTEN - blit writes finish on blit_fifo_empty. Chunk counter only used for reads - premature finish of blit reads if NX*NY satisfied. No more chunk granularity - set BLIT_CHUNK_SIZE to 128 double-pixels Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@676 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -148,11 +148,12 @@ architecture Behavioral of vga_frontend64 is
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signal blit_complete : std_logic;
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signal blit_complete_ack : std_logic;
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signal blit_complete_inten : std_logic;
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signal blit_reset : std_logic;
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signal vga_scan_rdy : std_logic;
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signal vga_master_en : std_logic;
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signal vga_scan_dma_en : std_logic;
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signal vga_scan_dma_en2 : std_logic;
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signal request_cnt_rst : std_logic;
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signal request_en : std_logic;
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signal pixel_cnt_rst : std_logic;
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signal read_bus_en : std_logic;
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signal request_cnt : unsigned(28 downto 0);
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signal read_cnt : unsigned(28 downto 0);
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@@ -166,14 +167,12 @@ architecture Behavioral of vga_frontend64 is
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signal back : unsigned(31 downto 0);
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-- Blitter vars
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constant BLIT_CHUNK_SIZE : natural := 32;
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constant BLIT_CHUNK_SIZE : natural := 128;
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signal blit_chunk_cnt : natural range 0 to BLIT_CHUNK_SIZE-1;
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-- Blitter FIFO signals
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signal blitfifo_full : std_logic;
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signal blitfifo_empty : std_logic;
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signal blitfifo_almost_empty : std_logic;
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signal blitfifo_almost_full : std_logic;
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signal blitfifo_color_re : std_logic;
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signal blitfifo_color_we : std_logic;
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signal blitfifo_color_out : unsigned(63 downto 0);
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@@ -218,17 +217,29 @@ architecture Behavioral of vga_frontend64 is
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alias bus_fifo_sel_out is bus_fifo_dout(103 downto 96);
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alias bus_fifo_we_out is bus_fifo_dout(104);
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type vm_state_t is (init, idle, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, blit_dst_bus_fin);
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type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_bus_request, blit_dst_bus_fin);
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signal s, sn : vm_state_t;
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begin
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proc_synced_vga_scan_en:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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vga_scan_dma_en2 <= '0';
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elsif vga_scan_rdy = '1' then
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vga_scan_dma_en2 <= vga_scan_dma_en;
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end if;
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end if;
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end process;
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proc_bufchg_irq:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if pixel_cnt_rst = '1' or bufchg_flag_ack = '1' then
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if vga_scan_dma_en2 = '0' or bufchg_flag_ack = '1' then
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bufchg_flag <= '0';
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elsif bufchg = '1' then
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bufchg_flag <= '1';
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@@ -242,7 +253,7 @@ proc_blit_request_flags:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if pixel_cnt_rst = '1' then
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if RST_I = '1' then
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blit_request <= '0';
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elsif blit_request = '0' then
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if blit_request_set = '1' then
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@@ -258,7 +269,7 @@ proc_blit_complete_flag:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if pixel_cnt_rst = '1' or blit_request_set = '1' or blit_complete_ack = '1' then
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if RST_I = '1' or blit_request_set = '1' or blit_complete_ack = '1' then
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blit_complete <= '0';
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elsif blit_dst_finish = '1' and blitfifo_empty = '1' then
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blit_complete <= '1';
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@@ -357,14 +368,12 @@ inst_linefifo: entity work.fifo_async
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inst_blitfifo: entity work.fifo_sync
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GENERIC MAP
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(
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addr_width => NextExpBaseTwo(32),
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data_width => 64,
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almost_full_thresh => 24,
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almost_empty_thresh => 8
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addr_width => NextExpBaseTwo(BLIT_CHUNK_SIZE),
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data_width => 64
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)
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PORT MAP
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(
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rst => RST_I,
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rst => blit_reset,
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clk => CLK_I,
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we => blitfifo_color_we,
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re => blitfifo_color_re,
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@@ -372,13 +381,13 @@ inst_blitfifo: entity work.fifo_sync
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data_r => blitfifo_color_out,
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fifo_full => blitfifo_full,
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fifo_empty => blitfifo_empty,
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fifo_afull => blitfifo_almost_full,
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fifo_aempty => blitfifo_almost_empty
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fifo_afull => open,
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fifo_aempty => open
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);
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blitfifo_color_in <= MDAT_I;
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blitfifo_color_re <= CYC_O_blit_dst and bus_rdy;
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blitfifo_color_re <= STB_O_blit_dst and bus_rdy;
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blitfifo_color_we <= ACK_I and read_bus_en and CYC_O_blit_src; -- TODO:
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-- Instantiate synchronous FIFO
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@@ -403,14 +412,13 @@ inst_bus_fifo: entity work.fifo_sync
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);
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bus_rdy <= not bus_fifo_full;
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bus_fifo_re <= not bus_fifo_empty and SRDY_I;
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bus_fifo_we <= request_en;
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bus_fifo_we <= STB_O_scan or STB_O_blit_src or STB_O_blit_dst;
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bus_fifo_data_in <= blitfifo_color_out;
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bus_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
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ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
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ADDR_O_scan;
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bus_fifo_sel_in <= (others => '1');
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bus_fifo_we_in <= CYC_O_blit_dst;
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ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
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CYC_O <= CYC_O_scan or CYC_O_blit_src or CYC_O_blit_dst;
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@@ -427,7 +435,7 @@ vga_master_next:
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end process;
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vga_master:
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process(s, stat_vga_rdy, vga_master_en, vga_scan_rdy, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, bus_read_fin, bus_fifo_empty, blit_chunk_cnt)
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process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, bus_read_fin, bus_fifo_empty, blit_chunk_cnt, blitfifo_empty, blit_src_finish)
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begin
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CYC_O_scan <= '0';
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@@ -436,7 +444,6 @@ vga_master:
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STB_O_blit_src <= '0';
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CYC_O_blit_dst <= '0';
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STB_O_blit_dst <= '0';
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pixel_cnt_rst <= '0';
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request_cnt_rst <= '0';
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request_en <= '0';
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read_bus_en <= '0';
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@@ -445,18 +452,12 @@ vga_master:
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case s is
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when init =>
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if stat_vga_rdy = '1' then
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sn <= idle;
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end if;
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when idle =>
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pixel_cnt_rst <= '1';
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if vga_master_en = '1' and vga_scan_rdy = '1' then
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sn <= rdy;
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end if;
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when rdy =>
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request_cnt_rst <= '1';
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if fifo_almost_empty = '1' then
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if fifo_almost_empty = '1' and vga_scan_dma_en2 = '1' then
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sn <= scan_bus_request;
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elsif blit_request = '1' then
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if blitfifo_empty = '1' then
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@@ -480,9 +481,6 @@ vga_master:
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read_bus_en <= '1';
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if bus_read_fin = '1' then
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sn <= rdy;
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if vga_master_en = '0' then
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sn <= idle;
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end if;
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end if;
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when blit_src_bus_request =>
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@@ -490,8 +488,8 @@ vga_master:
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STB_O_blit_src <= '1';
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request_en <= '1';
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read_bus_en <= '1';
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if blit_chunk_cnt = 0 then
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sn <= blit_src_bus_read;
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if blit_chunk_cnt = 0 or blit_src_finish = '1' then
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sn <= blit_src_bus_read;
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end if;
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when blit_src_bus_read =>
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@@ -504,9 +502,9 @@ vga_master:
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when blit_dst_bus_request =>
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CYC_O_blit_dst <= '1';
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STB_O_blit_dst <= '1';
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request_en <= '1';
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if blit_chunk_cnt = 0 then
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sn <= blit_dst_bus_fin;
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if blitfifo_empty = '1' then
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STB_O_blit_dst <= '0';
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sn <= blit_dst_bus_fin;
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end if;
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when blit_dst_bus_fin =>
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@@ -516,7 +514,7 @@ vga_master:
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end if;
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when others =>
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sn <= idle;
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sn <= rdy;
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end case;
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end process;
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@@ -556,12 +554,30 @@ proc_bus_read_finish:
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end if;
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end process;
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proc_blit_chunk_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if STB_O_blit_src = '1' then
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if blit_chunk_cnt /= 0 and bus_rdy = '1' then
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blit_chunk_cnt <= blit_chunk_cnt - 1;
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end if;
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else
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blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
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end if;
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end if;
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end process;
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blit_reset <= RST_I or (blit_request_set and not blit_request);
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ADDR_O_scan <= front + (to_unsigned(pixel_cnt, 29) & "000");
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proc_scan_addr:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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bufchg <= '0';
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if pixel_cnt_rst = '1' then
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if vga_scan_dma_en2 = '0' then
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pixel_cnt <= 0;
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front <= host_fb_front;
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elsif STB_O_scan = '1' and bus_rdy = '1' then
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@@ -580,23 +596,11 @@ proc_scan_addr:
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ADDR_O_blit_src <= blit_addr_src_0 + blit_src_offset;
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proc_blit_chunk_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if request_en = '0' then
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blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
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elsif blit_chunk_cnt /= 0 and bus_rdy = '1' and (STB_O_blit_src = '1' or STB_O_blit_dst = '1') then
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blit_chunk_cnt <= blit_chunk_cnt - 1;
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end if;
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end if;
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end process;
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proc_blit_addr_src:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' or (blit_request_set and not blit_request) = '1' then
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if blit_reset = '1' then
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blit_src_cnt_x <= (others => '0');
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blit_src_cnt_y <= (others => '0');
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blit_src_offset <= (others => '0');
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@@ -626,7 +630,7 @@ proc_blit_addr_dst:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' or (blit_request_set and not blit_request) = '1' then
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if blit_reset = '1' then
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blit_dst_cnt_x <= (others => '0');
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blit_dst_cnt_y <= (others => '0');
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blit_dst_offset <= (others => '0');
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@@ -703,7 +707,7 @@ registers_read:
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-- sys_vga_ctrl 0
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when "0000" =>
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SDAT_O(0) <= cg_rdy;
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SDAT_O(1) <= vga_master_en;
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SDAT_O(1) <= vga_scan_dma_en;
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SDAT_O(2) <= bufchg_irq_en;
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SDAT_O(3) <= bufchg_flag;
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SDAT_O(8) <= blit_request;
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@@ -792,7 +796,7 @@ registers_write:
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blit_complete_ack <= '0';
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if RST_I = '1' then
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cg_din <= (others => '0');
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vga_master_en <= '0';
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vga_scan_dma_en <= '0';
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bufchg_irq_en <= '0';
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blit_complete_inten <= '0';
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blit_func_sel <= (others => '0');
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@@ -805,7 +809,7 @@ registers_write:
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-- sys_vga_ctrl 0
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when "0000" =>
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vga_master_en <= SDAT_I(1);
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vga_scan_dma_en <= SDAT_I(1);
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bufchg_irq_en <= SDAT_I(2);
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bufchg_flag_ack <= SDAT_I(3);
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cg_clr_screen <= SDAT_I(4);
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