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- Cleaned up

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git-svn-id: http://moon:8086/svn/vhdl/trunk@164 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-12-28 19:04:18 +00:00
parent ef5da14068
commit fb625665d2
8 changed files with 274 additions and 571 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/radio/nco/sim/tb_mix_cordic.fdo
-2
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@@ -8,8 +8,6 @@ vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd" vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd" vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd" vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd"
vcom -explicit -93 "../src/nco_pkg.vhd"
vcom -explicit -93 "../src/nco_cordic.vhd"
vcom -explicit -93 "../src/mix_cordic.vhd" vcom -explicit -93 "../src/mix_cordic.vhd"
vcom -explicit -93 "../src/tb_mix_cordic.vhd" vcom -explicit -93 "../src/tb_mix_cordic.vhd"
vsim -t 1ps -lib work tb_mix vsim -t 1ps -lib work tb_mix
lib/radio/nco/sim/tb_mix_cordic.wdo
+23 -11
View File
@@ -2,16 +2,28 @@ onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_mix/clk add wave -noupdate -format Logic /tb_mix/clk
add wave -noupdate -format Logic /tb_mix/srst add wave -noupdate -format Logic /tb_mix/srst
add wave -noupdate -format Logic /tb_mix/pacc_clr add wave -noupdate -format Logic /tb_mix/clk
add wave -noupdate -format Logic /tb_mix/pacc_inc add wave -noupdate -format Logic /tb_mix/srst
add wave -noupdate -format Logic /tb_mix/phase_load add wave -noupdate -format Logic /tb_mix/mix_nco_rst
add wave -noupdate -format Logic /tb_mix/freq_load add wave -noupdate -format Logic /tb_mix/mix_nco_en
add wave -noupdate -format Literal -radix decimal /tb_mix/freq_in add wave -noupdate -format Literal /tb_mix/mix_freq_in
add wave -noupdate -format Literal -radix decimal /tb_mix/phase_in add wave -noupdate -format Literal /tb_mix/mix_phase_in
add wave -noupdate -format Analog-Step -radix decimal -scale 0.00050000000000000001 /tb_mix/wave_in_i add wave -noupdate -format Literal /tb_mix/mix_din_i
add wave -noupdate -format Analog-Step -radix decimal -scale 0.00050000000000000001 /tb_mix/wave_in_q add wave -noupdate -format Literal /tb_mix/mix_din_q
add wave -noupdate -format Analog-Step -radix decimal -scale 0.0001 /tb_mix/wave_out_i add wave -noupdate -format Literal /tb_mix/mix_dout_i
add wave -noupdate -format Analog-Step -radix decimal -scale 0.0001 /tb_mix/wave_out_q add wave -noupdate -format Literal /tb_mix/mix_dout_q
add wave -noupdate -format Logic /tb_mix/mix_dout_vld
add wave -noupdate -format Logic /tb_mix/mix_din_vld
add wave -noupdate -format Logic /tb_mix/rfgen_nco_rst
add wave -noupdate -format Logic /tb_mix/rfgen_nco_en
add wave -noupdate -format Literal /tb_mix/rfgen_freq_in
add wave -noupdate -format Literal /tb_mix/rfgen_phase_in
add wave -noupdate -format Literal /tb_mix/rfgen_din_i
add wave -noupdate -format Literal /tb_mix/rfgen_din_q
add wave -noupdate -format Literal /tb_mix/rfgen_dout_i
add wave -noupdate -format Literal /tb_mix/rfgen_dout_q
add wave -noupdate -format Logic /tb_mix/rfgen_dout_vld
add wave -noupdate -format Logic /tb_mix/fileout_enable
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {249834550 ps} 0} WaveRestoreCursors {{Cursor 1} {249834550 ps} 0}
configure wave -namecolwidth 193 configure wave -namecolwidth 193
@@ -27,4 +39,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40 configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
update update
WaveRestoreZoom {150625 ns} {413125 ns} WaveRestoreZoom {146645950 ps} {228944950 ps}
lib/radio/nco/sim/tb_nco_cordic.fdo
+1 -2
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@@ -8,8 +8,7 @@ vcom -explicit -93 "../../cordic/src/cordic_pipe_stage.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd" vcom -explicit -93 "../../cordic/src/cordic_pipe_pre.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd" vcom -explicit -93 "../../cordic/src/cordic_pipe_post.vhd"
vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd" vcom -explicit -93 "../../cordic/src/cordic_pipe_top.vhd"
vcom -explicit -93 "../src/nco_pkg.vhd" vcom -explicit -93 "../src/mix_cordic.vhd"
vcom -explicit -93 "../src/nco_cordic.vhd"
vcom -explicit -93 "../src/tb_nco_cordic.vhd" vcom -explicit -93 "../src/tb_nco_cordic.vhd"
vsim -t 1ps -lib work tb_nco vsim -t 1ps -lib work tb_nco
do {tb_nco_cordic.wdo} do {tb_nco_cordic.wdo}
lib/radio/nco/sim/tb_nco_cordic.wdo
+9 -18
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@@ -1,30 +1,21 @@
onerror {resume} onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_nco/uut/srst
add wave -noupdate -format Logic /tb_nco/uut/clk add wave -noupdate -format Logic /tb_nco/uut/clk
add wave -noupdate -format Logic /tb_nco/uut/pacc_clr
add wave -noupdate -format Logic /tb_nco/uut/pacc_inc
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in
add wave -noupdate -format Logic /tb_nco/uut/freq_load
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in
add wave -noupdate -format Logic /tb_nco/uut/phase_load
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out
add wave -noupdate -format Analog-Step -radix decimal -scale 7.6294199999999999e-005 /tb_nco/uut/wave_out_i
add wave -noupdate -format Analog-Step -radix decimal -scale 7.6294199999999999e-005 /tb_nco/uut/wave_out_q
add wave -noupdate -format Logic /tb_nco/uut/out_valid
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r
add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/wave_i_ud
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/wave_q_ud
add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid
add wave -noupdate -divider Cordic add wave -noupdate -divider Cordic
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/zin_ud
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/xin add wave -noupdate -format Literal -radix decimal /tb_nco/uut/xin
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/yin add wave -noupdate -format Literal -radix decimal /tb_nco/uut/yin
add wave -noupdate -format Literal -radix decimal /tb_nco/uut/zout_ud add wave -noupdate -format Literal /tb_nco/mix_din_i
add wave -noupdate -format Literal /tb_nco/mix_din_q
add wave -noupdate -format Literal /tb_nco/mix_dout_i
add wave -noupdate -format Literal /tb_nco/mix_dout_q
add wave -noupdate -format Logic /tb_nco/mix_dout_vld
add wave -noupdate -format Logic /tb_nco/mix_din_vld
add wave -noupdate -format Logic /tb_nco/fileout_enable
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {239431582 ps} 0} WaveRestoreCursors {{Cursor 1} {243331511 ps} 0}
configure wave -namecolwidth 193 configure wave -namecolwidth 193
configure wave -valuecolwidth 100 configure wave -valuecolwidth 100
configure wave -justifyvalue left configure wave -justifyvalue left
@@ -38,4 +29,4 @@ configure wave -gridperiod 1
configure wave -griddelta 40 configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
update update
WaveRestoreZoom {241709760 ps} {250436329 ps} WaveRestoreZoom {239972168 ps} {248698737 ps}
lib/radio/nco/src/mix_cordic.vhd
+42 -72
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@@ -33,27 +33,27 @@ use work.cordic_pkg.all;
entity mix is entity mix is
Generic Generic
( (
nbits_wave_in : integer := 18; nbits_din : integer := 18;
nbits_wave_in_frac : integer := 16; nbits_din_frac : integer := 16;
nbits_wave_out : integer := 18; nbits_dout : integer := 18;
nbits_wave_out_frac : integer := 16; nbits_dout_frac : integer := 16;
nbits_phase : integer := 16 nbits_phase : integer := 16;
nbits_freq : integer := 16
); );
Port Port
( (
srst : in std_logic; rst : in std_logic;
clk : in std_logic; clk : in std_logic;
pacc_clr : in std_logic; nco_rst : in std_logic;
pacc_inc : in std_logic; nco_en : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0); freq_in : in unsigned(nbits_freq-1 downto 0);
freq_load : in std_logic; phase_in : in unsigned(nbits_phase-1 downto 0);
phase_in : in unsigned(nbits_phase-1 downto 0); din_i : in sfixed;
phase_load : in std_logic; din_q : in sfixed;
wave_in_i : in sfixed; dout_i : out sfixed;
wave_in_q : in sfixed; dout_q : out sfixed;
wave_out_i : out sfixed; din_vld : in std_logic;
wave_out_q : out sfixed; dout_vld : out std_logic
out_valid : out std_logic
); );
end mix; end mix;
@@ -99,12 +99,10 @@ architecture Behavioral of mix is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
signal phase : signed(nbits_phase-1 downto 0); signal phase : signed(nbits_phase-1 downto 0);
signal freq_in_r : signed(nbits_phase-1 downto 0); signal xin, yin : sfixed(shi(nbits_din, nbits_din_frac) downto slo(nbits_din, nbits_din_frac));
signal phase_in_r : signed(nbits_phase-1 downto 0); signal xout, yout : sfixed(shi(nbits_dout, nbits_dout_frac) downto slo(nbits_dout, nbits_dout_frac));
signal xin, yin : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
signal xout, yout : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
signal wave_out_valid : std_logic; signal dout_valid : std_logic;
signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac)); signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
@@ -112,12 +110,12 @@ architecture Behavioral of mix is
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
begin begin
wave_out_i <= xout; dout_i <= xout;
wave_out_q <= yout; dout_q <= yout;
xin <= wave_in_i; xin <= din_i;
yin <= wave_in_q; yin <= din_q;
out_valid <= wave_out_valid; dout_vld <= dout_valid;
------------------------------------------------------------ ------------------------------------------------------------
proc_phase_accu: process(clk) proc_phase_accu: process(clk)
@@ -125,44 +123,16 @@ begin
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if srst = '1' then if rst = '1' or nco_rst = '1' then
phase_accu := (others => '0'); phase_accu := (others => '0');
else elsif nco_en = '1' then
phase <= phase_accu + phase_in_r; phase <= phase_accu + signed(phase_in);
if pacc_clr = '1' then phase_accu := phase_accu + signed(freq_in);
phase_accu := (others => '0');
elsif pacc_inc = '1' then
phase_accu := phase_accu + freq_in_r;
end if;
end if; end if;
end if; end if;
zin <= sfixed(phase); zin <= sfixed(phase);
end process; end process;
------------------------------------------------------------
freq_in_reg: process(srst, clk, freq_load, freq_in)
begin
if rising_edge(clk) then
if srst = '1' then
freq_in_r <= (others => '0');
elsif freq_load = '1' then
freq_in_r <= signed(freq_in);
end if;
end if;
end process;
------------------------------------------------------------
phase_in_reg: process(srst, clk, phase_load, phase_in)
begin
if rising_edge(clk) then
if srst = '1' then
phase_in_r <= (others => '0');
elsif phase_load = '1' then
phase_in_r <= signed(phase_in);
end if;
end if;
end process;
------------------------------------------------------------ ------------------------------------------------------------
inst_cordic_ud: cordic_pipe_top inst_cordic_ud: cordic_pipe_top
GENERIC MAP GENERIC MAP
@@ -171,31 +141,31 @@ begin
z_range => 1.0, z_range => 1.0,
gain_corr_mode => gain_mode_disabled, gain_corr_mode => gain_mode_disabled,
nstages => nbits_phase, nstages => nbits_phase,
nbits_x_in => nbits_wave_in, nbits_x_in => nbits_din,
nbits_frac_x_in => nbits_wave_in_frac, nbits_frac_x_in => nbits_din_frac,
nbits_y_in => nbits_wave_in, nbits_y_in => nbits_din,
nbits_frac_y_in => nbits_wave_in_frac, nbits_frac_y_in => nbits_din_frac,
nbits_z_in => nbits_phase, nbits_z_in => nbits_phase,
nbits_frac_z_in => nbits_phase_frac, nbits_frac_z_in => nbits_phase_frac,
nbits_x_out => nbits_wave_out, nbits_x_out => nbits_dout,
nbits_frac_x_out => nbits_wave_out_frac, nbits_frac_x_out => nbits_dout_frac,
nbits_y_out => nbits_wave_out, nbits_y_out => nbits_dout,
nbits_frac_y_out => nbits_wave_out_frac, nbits_frac_y_out => nbits_dout_frac,
nbits_z_out => nbits_phase, nbits_z_out => nbits_phase,
nbits_frac_z_out => nbits_phase_frac nbits_frac_z_out => nbits_phase_frac
) )
PORT MAP PORT MAP
( (
rst => srst, rst => rst,
clk => clk, clk => clk,
vld_in => '1', vld_in => din_vld,
xin => xin, xin => xin,
yin => yin, yin => yin,
zin => zin, zin => zin,
xout => xout, xout => xout,
yout => yout, yout => yout,
zout => zout, zout => zout,
vld_out => wave_out_valid vld_out => dout_valid
); );
------------------------------------------------------------ ------------------------------------------------------------
lib/radio/nco/src/nco_cordic.vhd
-201
View File
@@ -1,201 +0,0 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:16:14 10/02/05
-- Design Name:
-- Module Name: cordic_stage - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
USE ieee.numeric_std.ALL;
use work.fixed_pkg.all;
use work.fixed_util_pkg.all;
use work.cordic_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity nco is
Generic
(
nbits_wave : integer := 18;
nbits_wave_frac : integer := 16;
nbits_phase : integer := 16
);
Port
(
srst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
phase_out : out unsigned(nbits_phase-1 downto 0);
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic
);
end nco;
architecture Behavioral of nco is
COMPONENT cordic_pipe_top
GENERIC
(
cordic_mode : cordic_mode_t;
z_range : real;
gain_corr_mode : gain_corr_mode_t;
nstages : integer;
nbits_x_in : integer;
nbits_y_in : integer;
nbits_z_in : integer;
nbits_frac_x_in : integer;
nbits_frac_y_in : integer;
nbits_frac_z_in : integer;
nbits_x_out : integer;
nbits_y_out : integer;
nbits_z_out : integer;
nbits_frac_x_out : integer;
nbits_frac_y_out : integer;
nbits_frac_z_out : integer
);
PORT
(
rst : in std_logic;
clk : in std_logic;
vld_in : in std_logic;
xin : in sfixed;
yin : in sfixed;
zin : in sfixed;
xout : out sfixed;
yout : out sfixed;
zout : out sfixed;
vld_out : out std_logic
);
END COMPONENT;
-------------------------------------------------------------------------------
constant nbits_phase_frac : integer := nbits_phase;
-------------------------------------------------------------------------------
signal phase : signed(nbits_phase-1 downto 0);
signal freq_in_r : signed(nbits_phase-1 downto 0);
signal phase_in_r : signed(nbits_phase-1 downto 0);
signal wave_i_ud, wave_q_ud : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac));
signal wave_ud_valid, phase_vld : std_logic;
signal zin_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
signal xin : sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(0.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac));
signal yin :sfixed(shi(nbits_wave, nbits_wave_frac) downto slo(nbits_wave, nbits_wave_frac)) := to_sfixed(1.0, shi(nbits_wave, nbits_wave_frac), slo(nbits_wave, nbits_wave_frac));
signal zout_ud : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
-------------------------------------------------------------------------------
begin
wave_out_i <= wave_i_ud;
wave_out_q <= wave_q_ud;
out_valid <= wave_ud_valid;
------------------------------------------------------------
proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r)
variable phase_accu : signed(nbits_phase-1 downto 0);
begin
if rising_edge(clk) then
phase_vld <= '0';
if srst = '1' then
phase_accu := (others => '0');
else
phase_vld <= '1';
phase <= phase_accu + phase_in_r;
if pacc_clr = '1' then
phase_accu := (others => '0');
elsif pacc_inc = '1' then
phase_accu := phase_accu + freq_in_r;
end if;
end if;
end if;
phase_out <= unsigned(phase);
zin_ud <= sfixed(phase);
end process;
------------------------------------------------------------
freq_in_reg: process(srst, clk, freq_load, freq_in)
begin
if rising_edge(clk) then
if srst = '1' then
freq_in_r <= (others => '0');
elsif freq_load = '1' then
freq_in_r <= signed(freq_in);
end if;
end if;
end process;
------------------------------------------------------------
phase_in_reg: process(srst, clk, phase_load, phase_in)
begin
if rising_edge(clk) then
if srst = '1' then
phase_in_r <= (others => '0');
elsif phase_load = '1' then
phase_in_r <= signed(phase_in);
end if;
end if;
end process;
------------------------------------------------------------
inst_cordic_ud: cordic_pipe_top
GENERIC MAP
(
cordic_mode => cordic_mode_rotate,
z_range => 1.0,
gain_corr_mode => gain_mode_disabled,
nstages => nbits_phase,
nbits_x_in => nbits_wave,
nbits_frac_x_in => nbits_wave_frac,
nbits_y_in => nbits_wave,
nbits_frac_y_in => nbits_wave_frac,
nbits_z_in => nbits_phase,
nbits_frac_z_in => nbits_phase_frac,
nbits_x_out => nbits_wave,
nbits_frac_x_out => nbits_wave_frac,
nbits_y_out => nbits_wave,
nbits_frac_y_out => nbits_wave_frac,
nbits_z_out => nbits_phase,
nbits_frac_z_out => nbits_phase_frac
)
PORT MAP
(
rst => srst,
clk => clk,
vld_in => phase_vld,
xin => xin,
yin => yin,
zin => zin_ud,
xout => wave_i_ud,
yout => wave_q_ud,
zout => zout_ud,
vld_out => wave_ud_valid
);
------------------------------------------------------------
end Behavioral;
lib/radio/nco/src/tb_mix_cordic.vhd
+113 -163
View File
@@ -28,7 +28,8 @@ ENTITY tb_mix IS
( (
nbits_wave_in : integer := 16; nbits_wave_in : integer := 16;
nbits_wave_out : integer := 18; -- Gain of 2.6 (mix + rfgen) nbits_wave_out : integer := 18; -- Gain of 2.6 (mix + rfgen)
nbits_phase : integer := 20 nbits_phase : integer := 20;
nbits_freq : integer := 20
); );
END tb_mix; END tb_mix;
@@ -36,52 +37,29 @@ ARCHITECTURE behavior OF tb_mix IS
-- Component Declaration for the Unit Under Test (UUT) -- Component Declaration for the Unit Under Test (UUT)
COMPONENT mix COMPONENT mix
GENERIC GENERIC
( (
nbits_wave_in : integer; nbits_din : integer;
nbits_wave_in_frac : integer; nbits_din_frac : integer;
nbits_wave_out : integer; nbits_dout : integer;
nbits_wave_out_frac : integer; nbits_dout_frac : integer;
nbits_phase : integer nbits_phase : integer;
); nbits_freq : integer
PORT(
srst : in std_logic;
clk : in std_logic;
pacc_clr : in std_logic;
pacc_inc : in std_logic;
freq_in : in unsigned(nbits_phase-1 downto 0);
freq_load : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0);
phase_load : in std_logic;
wave_in_i : in sfixed;
wave_in_q : in sfixed;
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic
); );
END COMPONENT; PORT
-- Rf-Generator
COMPONENT nco
GENERIC
( (
nbits_wave : integer; rst : in std_logic;
nbits_wave_frac : integer; clk : in std_logic;
nbits_phase : integer nco_rst : in std_logic;
); nco_en : in std_logic;
PORT( freq_in : in unsigned(nbits_freq-1 downto 0);
srst : in std_logic; phase_in : in unsigned(nbits_phase-1 downto 0);
clk : in std_logic; din_i : in sfixed;
pacc_clr : in std_logic; din_q : in sfixed;
pacc_inc : in std_logic; dout_i : out sfixed;
freq_in : in unsigned(nbits_phase-1 downto 0); dout_q : out sfixed;
freq_load : in std_logic; din_vld : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0); dout_vld : out std_logic
phase_load : in std_logic;
phase_out : out unsigned(nbits_phase-1 downto 0);
wave_out_i : out sfixed;
wave_out_q : out sfixed;
out_valid : out std_logic
); );
END COMPONENT; END COMPONENT;
@@ -96,38 +74,37 @@ ARCHITECTURE behavior OF tb_mix IS
constant nbits_wave_in_frac : integer := nbits_wave_in-2; constant nbits_wave_in_frac : integer := nbits_wave_in-2;
constant nbits_wave_out_frac : integer := nbits_wave_out-2; constant nbits_wave_out_frac : integer := nbits_wave_out-2;
SIGNAL rfgen_freq_word : integer := integer(frf/fa*2.0**nbits_phase); SIGNAL rfgen_freq_word : integer := integer(frf/fa*2.0**nbits_freq);
SIGNAL freq_word : integer := integer(flo/fa*2.0**nbits_phase); SIGNAL freq_word : integer := integer(flo/fa*2.0**nbits_freq);
SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase); SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_freq);
--Inputs --Inputs
SIGNAL clk : std_logic := '0'; SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1'; SIGNAL srst : std_logic := '1';
SIGNAL pacc_clr : std_logic := '0'; SIGNAL mix_nco_rst : std_logic := '0';
SIGNAL pacc_inc : std_logic := '0'; SIGNAL mix_nco_en : std_logic := '0';
SIGNAL phase_load : std_logic := '0'; SIGNAL mix_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0');
SIGNAL freq_load : std_logic := '0'; SIGNAL mix_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0');
SIGNAL freq_in : unsigned(nbits_phase-1 downto 0);
SIGNAL phase_in : unsigned(nbits_phase-1 downto 0);
--Outputs --Outputs
SIGNAL wave_in_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); SIGNAL mix_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL wave_in_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); SIGNAL mix_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL wave_out_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac)); SIGNAL mix_dout_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
SIGNAL wave_out_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac)); SIGNAL mix_dout_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
SIGNAL mix_out_valid : std_logic; SIGNAL mix_dout_vld : std_logic;
SIGNAL mix_din_vld : std_logic := '0';
SIGNAL rfgen_pacc_clr : std_logic := '0'; SIGNAL rfgen_nco_rst : std_logic := '0';
SIGNAL rfgen_pacc_inc : std_logic := '0'; SIGNAL rfgen_nco_en : std_logic := '0';
SIGNAL rfgen_phase_load : std_logic := '0'; SIGNAL rfgen_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0');
SIGNAL rfgen_freq_load : std_logic := '0'; SIGNAL rfgen_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0');
SIGNAL rfgen_freq_in : unsigned(nbits_phase-1 downto 0);
SIGNAL rfgen_phase_in : unsigned(nbits_phase-1 downto 0);
--Outputs --Outputs
SIGNAL rfgen_out_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); signal rfgen_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(0.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL rfgen_out_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)); signal rfgen_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(1.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL rfgen_out_valid : std_logic; SIGNAL rfgen_dout_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL rfgen_dout_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL rfgen_dout_vld : std_logic;
SIGNAL fileout_enable : std_logic := '0'; SIGNAL fileout_enable : std_logic := '0';
BEGIN BEGIN
@@ -136,50 +113,53 @@ BEGIN
uut: mix uut: mix
GENERIC MAP GENERIC MAP
( (
nbits_wave_in => nbits_wave_in, nbits_din => nbits_wave_in,
nbits_wave_in_frac => nbits_wave_in_frac, nbits_din_frac => nbits_wave_in_frac,
nbits_wave_out => nbits_wave_out, nbits_dout => nbits_wave_out,
nbits_wave_out_frac => nbits_wave_out_frac, nbits_dout_frac => nbits_wave_out_frac,
nbits_phase => nbits_phase nbits_phase => nbits_phase,
nbits_freq => nbits_freq
) )
PORT MAP PORT MAP
( (
srst => srst, rst => srst,
clk => clk, clk => clk,
pacc_clr => pacc_clr, nco_rst => mix_nco_rst,
pacc_inc => pacc_inc, nco_en => mix_nco_en,
freq_in => freq_in, freq_in => mix_freq_in,
freq_load => freq_load, phase_in => mix_phase_in,
phase_in => phase_in, din_i => mix_din_i,
phase_load => phase_load, din_q => mix_din_q,
wave_in_i => wave_in_i, dout_i => mix_dout_i,
wave_in_q => wave_in_q, dout_q => mix_dout_q,
wave_out_i => wave_out_i, din_vld => mix_din_vld,
wave_out_q => wave_out_q, dout_vld => mix_dout_vld
out_valid => mix_out_valid
); );
rfgen1: nco rfgen1: mix
GENERIC MAP GENERIC MAP
( (
nbits_wave => nbits_wave_in, nbits_din => nbits_wave_in,
nbits_wave_frac => nbits_wave_in_frac, nbits_din_frac => nbits_wave_in_frac,
nbits_phase => nbits_phase nbits_dout => nbits_wave_in,
nbits_dout_frac => nbits_wave_in_frac,
nbits_phase => nbits_phase,
nbits_freq => nbits_freq
) )
PORT MAP PORT MAP
( (
srst => srst, rst => srst,
clk => clk, clk => clk,
pacc_clr => rfgen_pacc_clr, nco_rst => rfgen_nco_rst,
pacc_inc => rfgen_pacc_inc, nco_en => rfgen_nco_en,
freq_in => rfgen_freq_in, freq_in => rfgen_freq_in,
freq_load => rfgen_freq_load,
phase_in => rfgen_phase_in, phase_in => rfgen_phase_in,
phase_load => rfgen_phase_load, din_i => rfgen_din_i,
phase_out => open, din_q => rfgen_din_q,
wave_out_i => rfgen_out_i, dout_i => rfgen_dout_i,
wave_out_q => rfgen_out_q, dout_q => rfgen_dout_q,
out_valid => rfgen_out_valid din_vld => '1',
dout_vld => rfgen_dout_vld
); );
tb_clk : PROCESS tb_clk : PROCESS
@@ -188,10 +168,10 @@ BEGIN
wait for PERIOD/2; wait for PERIOD/2;
END PROCESS; END PROCESS;
-- wave_in_i <= resize(1.0*rfgen_out_i, wave_in_i, false, true); mix_din_i <= rfgen_dout_i;
wave_in_i <= rfgen_out_i; mix_din_q <= to_sfixed(0.0, mix_din_q);
wave_in_q <= to_sfixed(0.0, wave_in_q); mix_din_vld <= rfgen_dout_vld;
tb : PROCESS tb : PROCESS
file RESULT_FREQ: text open write_mode is "freq.txt"; file RESULT_FREQ: text open write_mode is "freq.txt";
variable L: line; variable L: line;
@@ -207,62 +187,41 @@ BEGIN
wait for 2*PERIOD; wait for 2*PERIOD;
------------------------------------------- -------------------------------------------
-- 1 -- 1
phase_in <= to_unsigned(0,nbits_phase); mix_phase_in <= to_unsigned(0,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
freq_in <= to_unsigned(1411,nbits_phase); mix_freq_in <= to_unsigned(1411,nbits_freq);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 2*PERIOD; wait for 2*PERIOD;
pacc_inc <= '1'; mix_nco_en <= '1';
wait for 2*PERIOD; wait for 2*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
wait for 40*PERIOD; wait for 40*PERIOD;
------------------------------------------- -------------------------------------------
freq_in <= to_unsigned(643,nbits_phase); mix_freq_in <= to_unsigned(643,nbits_freq);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 40*PERIOD; wait for 40*PERIOD;
------------------------------------------- -------------------------------------------
phase_in <= to_unsigned(800,nbits_phase); mix_phase_in <= to_unsigned(800,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
------------------------------------------- -------------------------------------------
phase_in <= to_unsigned(45072,nbits_phase); mix_phase_in <= to_unsigned(45072,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
------------------------------------------- -------------------------------------------
phase_in <= to_unsigned(20593,nbits_phase); mix_phase_in <= to_unsigned(20593,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
------------------------------------------- -------------------------------------------
freq_in <= to_unsigned(freq_word,nbits_phase); mix_freq_in <= to_unsigned(freq_word,nbits_freq);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
fileout_enable <= '1'; fileout_enable <= '1';
@@ -277,55 +236,49 @@ BEGIN
wait for 20*PERIOD; wait for 20*PERIOD;
freq_word <= freq_word + dfreq_word; freq_word <= freq_word + dfreq_word;
freq_in <= to_unsigned(freq_word,nbits_phase); mix_freq_in <= to_unsigned(freq_word,nbits_freq);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
end loop; end loop;
pacc_inc <= '0'; mix_nco_en <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
fileout_enable <= '0'; fileout_enable <= '0';
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_clr <= '1'; mix_nco_rst <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_clr <= '0'; mix_nco_rst <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
pacc_inc <= '1'; mix_nco_en <= '1';
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_clr <= '1'; mix_nco_rst <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_clr <= '0'; mix_nco_rst <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
pacc_inc <= '0'; mix_nco_en <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_inc <= '1'; mix_nco_en <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_inc <= '0'; mix_nco_en <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
srst <= '1'; srst <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
srst <= '0'; srst <= '0';
freq_in <= to_unsigned(freq_word,nbits_phase); mix_freq_in <= to_unsigned(freq_word,nbits_freq);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
pacc_inc <= '1'; mix_nco_en <= '1';
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
srst <= '1'; srst <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
srst <= '0'; srst <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
pacc_inc <= '0'; mix_nco_en <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
@@ -339,21 +292,18 @@ BEGIN
BEGIN BEGIN
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk) and srst = '0'; wait until rising_edge(clk) and srst = '0';
rfgen_freq_in <= to_unsigned(rfgen_freq_word,nbits_phase); rfgen_freq_in <= to_unsigned(rfgen_freq_word,nbits_freq);
wait until rising_edge(clk); wait until rising_edge(clk);
rfgen_freq_load <= '1';
wait until rising_edge(clk);
rfgen_freq_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
rfgen_pacc_inc <= '1'; rfgen_nco_en <= '1';
wait for 20*PERIOD; wait for 20*PERIOD;
wait; wait;
END PROCESS; END PROCESS;
tb_fo : PROCESS(clk, fileout_enable, mix_out_valid) tb_fo : PROCESS(clk)
file RESULT_Ii: text open write_mode is "i_in.txt"; file RESULT_Ii: text open write_mode is "i_in.txt";
file RESULT_Qi: text open write_mode is "q_in.txt"; file RESULT_Qi: text open write_mode is "q_in.txt";
file RESULT_Io: text open write_mode is "i_out.txt"; file RESULT_Io: text open write_mode is "i_out.txt";
@@ -362,13 +312,13 @@ BEGIN
BEGIN BEGIN
if rising_edge(clk) and fileout_enable = '1' then if rising_edge(clk) and fileout_enable = '1' then
if rfgen_out_valid = '1' then if rfgen_dout_vld = '1' then
fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_out_i))); fprint(RESULT_Ii, L,"%s\n", REAL'image(to_real(rfgen_dout_i)));
fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_out_q))); fprint(RESULT_Qi, L,"%s\n", REAL'image(to_real(rfgen_dout_q)));
end if; end if;
if mix_out_valid = '1' then if mix_dout_vld = '1' then
fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(wave_out_i))); fprint(RESULT_Io, L,"%s\n", REAL'image(to_real(mix_dout_i)));
fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(wave_out_q))); fprint(RESULT_Qo, L,"%s\n", REAL'image(to_real(mix_dout_q)));
end if; end if;
end if; end if;
lib/radio/nco/src/tb_nco_cordic.vhd
+86 -102
View File
@@ -25,34 +25,40 @@ use work.PCK_FIO.all;
ENTITY tb_nco IS ENTITY tb_nco IS
Generic Generic
( (
nbits_wave : integer := 16; nbits_wave_in : integer := 16;
nbits_phase : integer := 20 nbits_wave_out : integer := 16;
nbits_phase : integer := 20;
nbits_freq : integer := 20
); );
END tb_nco; END tb_nco;
ARCHITECTURE behavior OF tb_nco IS ARCHITECTURE behavior OF tb_nco IS
-- Component Declaration for the Unit Under Test (UUT) -- Component Declaration for the Unit Under Test (UUT)
COMPONENT nco COMPONENT mix
GENERIC GENERIC
( (
nbits_wave : integer; nbits_din : integer;
nbits_wave_frac : integer; nbits_din_frac : integer;
nbits_phase : integer nbits_dout : integer;
); nbits_dout_frac : integer;
PORT( nbits_phase : integer;
srst : in std_logic; nbits_freq : integer
clk : in std_logic; );
pacc_clr : in std_logic; PORT
pacc_inc : in std_logic; (
freq_in : in unsigned(nbits_phase-1 downto 0); rst : in std_logic;
freq_load : in std_logic; clk : in std_logic;
phase_in : in unsigned(nbits_phase-1 downto 0); nco_rst : in std_logic;
phase_load : in std_logic; nco_en : in std_logic;
phase_out : out unsigned(nbits_phase-1 downto 0); freq_in : in unsigned(nbits_freq-1 downto 0);
wave_out_i : out sfixed; phase_in : in unsigned(nbits_phase-1 downto 0);
wave_out_q : out sfixed; din_i : in sfixed;
out_valid : out std_logic din_q : in sfixed;
dout_i : out sfixed;
dout_q : out sfixed;
din_vld : in std_logic;
dout_vld : out std_logic
); );
END COMPONENT; END COMPONENT;
@@ -61,7 +67,9 @@ ARCHITECTURE behavior OF tb_nco IS
constant f : REAL := 5.0*fa/24.0; constant f : REAL := 5.0*fa/24.0;
constant df : REAL := 10.0E3; constant df : REAL := 10.0E3;
constant PERIOD : time := 10 ns; constant PERIOD : time := 10 ns;
constant nbits_wave_frac : integer := nbits_wave-2;
constant nbits_wave_in_frac : integer := nbits_wave_in-2;
constant nbits_wave_out_frac : integer := nbits_wave_out-2;
SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase); SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase);
SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase); SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase);
@@ -69,45 +77,48 @@ ARCHITECTURE behavior OF tb_nco IS
--Inputs --Inputs
SIGNAL clk : std_logic := '0'; SIGNAL clk : std_logic := '0';
SIGNAL srst : std_logic := '1'; SIGNAL srst : std_logic := '1';
SIGNAL pacc_clr : std_logic := '0'; SIGNAL mix_nco_rst : std_logic := '0';
SIGNAL pacc_inc : std_logic := '0'; SIGNAL mix_nco_en : std_logic := '0';
SIGNAL phase_load : std_logic := '0'; SIGNAL mix_freq_in : unsigned(nbits_freq-1 downto 0) := (others => '0');
SIGNAL freq_load : std_logic := '0'; SIGNAL mix_phase_in : unsigned(nbits_phase-1 downto 0) := (others => '0');
SIGNAL freq_in : unsigned(nbits_phase-1 downto 0);
SIGNAL phase_in : unsigned(nbits_phase-1 downto 0);
--Outputs --Outputs
SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); SIGNAL mix_din_i : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(0.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); SIGNAL mix_din_q : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac)) := to_sfixed(1.0, shi(nbits_wave_in, nbits_wave_in_frac), slo(nbits_wave_in, nbits_wave_in_frac));
SIGNAL out_valid : std_logic; SIGNAL mix_dout_i : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
SIGNAL phase_out : unsigned(nbits_phase-1 downto 0); SIGNAL mix_dout_q : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
SIGNAL mix_dout_vld : std_logic;
SIGNAL mix_din_vld : std_logic := '1';
SIGNAL fileout_enable : std_logic := '0'; SIGNAL fileout_enable : std_logic := '0';
BEGIN BEGIN
-- Instantiate the Unit Under Test (UUT) -- Instantiate the Unit Under Test (UUT)
uut: nco uut: mix
GENERIC MAP GENERIC MAP
( (
nbits_wave => nbits_wave, nbits_din => nbits_wave_in,
nbits_wave_frac => nbits_wave_frac, nbits_din_frac => nbits_wave_in_frac,
nbits_phase => nbits_phase nbits_dout => nbits_wave_out,
nbits_dout_frac => nbits_wave_out_frac,
nbits_phase => nbits_phase,
nbits_freq => nbits_freq
) )
PORT MAP PORT MAP
( (
srst => srst, rst => srst,
clk => clk, clk => clk,
pacc_clr => pacc_clr, nco_rst => mix_nco_rst,
pacc_inc => pacc_inc, nco_en => mix_nco_en,
freq_in => freq_in, freq_in => mix_freq_in,
freq_load => freq_load, phase_in => mix_phase_in,
phase_in => phase_in, din_i => mix_din_i,
phase_load => phase_load, din_q => mix_din_q,
phase_out => phase_out, dout_i => mix_dout_i,
wave_out_i => wave_out_i, dout_q => mix_dout_q,
wave_out_q => wave_out_q, din_vld => mix_din_vld,
out_valid => out_valid dout_vld => mix_dout_vld
); );
tb_clk : PROCESS tb_clk : PROCESS
@@ -131,62 +142,41 @@ BEGIN
wait for 2*PERIOD; wait for 2*PERIOD;
------------------------------------------- -------------------------------------------
-- 1 -- 1
phase_in <= to_unsigned(0,nbits_phase); mix_phase_in <= to_unsigned(0,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
freq_in <= to_unsigned(1411,nbits_phase); mix_freq_in <= to_unsigned(1411,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 2*PERIOD; wait for 2*PERIOD;
pacc_inc <= '1'; mix_nco_en <= '1';
wait for 2*PERIOD; wait for 2*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
wait for 40*PERIOD; wait for 40*PERIOD;
------------------------------------------- -------------------------------------------
freq_in <= to_unsigned(643,nbits_phase); mix_freq_in <= to_unsigned(643,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 40*PERIOD; wait for 40*PERIOD;
------------------------------------------- -------------------------------------------
phase_in <= to_unsigned(800,nbits_phase); mix_phase_in <= to_unsigned(800,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
------------------------------------------- -------------------------------------------
phase_in <= to_unsigned(45072,nbits_phase); mix_phase_in <= to_unsigned(45072,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
------------------------------------------- -------------------------------------------
phase_in <= to_unsigned(20593,nbits_phase); mix_phase_in <= to_unsigned(20593,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
phase_load <= '1';
wait until rising_edge(clk);
phase_load <= '0';
------------------------------------------- -------------------------------------------
freq_in <= to_unsigned(freq_word,nbits_phase); mix_freq_in <= to_unsigned(freq_word,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
fileout_enable <= '1'; fileout_enable <= '1';
@@ -201,55 +191,49 @@ BEGIN
wait for 20*PERIOD; wait for 20*PERIOD;
freq_word <= freq_word + dfreq_word; freq_word <= freq_word + dfreq_word;
freq_in <= to_unsigned(freq_word,nbits_phase); mix_freq_in <= to_unsigned(freq_word,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
end loop; end loop;
pacc_inc <= '0'; mix_nco_en <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
fileout_enable <= '0'; fileout_enable <= '0';
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_clr <= '1'; mix_nco_rst <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_clr <= '0'; mix_nco_rst <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
pacc_inc <= '1'; mix_nco_en <= '1';
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_clr <= '1'; mix_nco_rst <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_clr <= '0'; mix_nco_rst <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
pacc_inc <= '0'; mix_nco_en <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_inc <= '1'; mix_nco_en <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
pacc_inc <= '0'; mix_nco_en <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
srst <= '1'; srst <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
srst <= '0'; srst <= '0';
freq_in <= to_unsigned(freq_word,nbits_phase); mix_freq_in <= to_unsigned(freq_word,nbits_phase);
wait until rising_edge(clk); wait until rising_edge(clk);
freq_load <= '1';
wait until rising_edge(clk);
freq_load <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
pacc_inc <= '1'; mix_nco_en <= '1';
wait for 20*PERIOD; wait for 20*PERIOD;
wait until rising_edge(clk); wait until rising_edge(clk);
srst <= '1'; srst <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
srst <= '0'; srst <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
pacc_inc <= '0'; mix_nco_en <= '0';
wait for 20*PERIOD; wait for 20*PERIOD;
@@ -257,7 +241,7 @@ BEGIN
wait; wait;
END PROCESS; END PROCESS;
tb_fo : PROCESS(clk, fileout_enable, out_valid) tb_fo : PROCESS(clk)
file RESULT_I: text open write_mode is "i_ud.txt"; file RESULT_I: text open write_mode is "i_ud.txt";
file RESULT_Q: text open write_mode is "q_ud.txt"; file RESULT_Q: text open write_mode is "q_ud.txt";
file RESULT_ID: text open write_mode is "i_d.txt"; file RESULT_ID: text open write_mode is "i_d.txt";
@@ -265,11 +249,11 @@ BEGIN
variable L: line; variable L: line;
BEGIN BEGIN
if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then if rising_edge(clk) and fileout_enable = '1' and mix_dout_vld = '1' then
fprint(RESULT_I, L,"%s\n", REAL'image(to_real(wave_out_i))); fprint(RESULT_I, L,"%s\n", REAL'image(to_real(mix_dout_i)));
fprint(RESULT_Q, L,"%s\n", REAL'image(to_real(wave_out_q))); fprint(RESULT_Q, L,"%s\n", REAL'image(to_real(mix_dout_q)));
fprint(RESULT_ID, L,"%s\n", REAL'image(to_real(wave_out_i))); fprint(RESULT_ID, L,"%s\n", REAL'image(to_real(mix_dout_i)));
fprint(RESULT_QD, L,"%s\n", REAL'image(to_real(wave_out_q))); fprint(RESULT_QD, L,"%s\n", REAL'image(to_real(mix_dout_q)));
end if; end if;
END PROCESS; END PROCESS;