- Cleaned up
git-svn-id: http://moon:8086/svn/vhdl/trunk@164 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -33,27 +33,27 @@ use work.cordic_pkg.all;
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entity mix is
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Generic
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(
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nbits_wave_in : integer := 18;
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nbits_wave_in_frac : integer := 16;
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nbits_wave_out : integer := 18;
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nbits_wave_out_frac : integer := 16;
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nbits_phase : integer := 16
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nbits_din : integer := 18;
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nbits_din_frac : integer := 16;
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nbits_dout : integer := 18;
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nbits_dout_frac : integer := 16;
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nbits_phase : integer := 16;
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nbits_freq : integer := 16
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);
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Port
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(
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srst : in std_logic;
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clk : in std_logic;
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pacc_clr : in std_logic;
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pacc_inc : in std_logic;
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freq_in : in unsigned(nbits_phase-1 downto 0);
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freq_load : in std_logic;
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phase_in : in unsigned(nbits_phase-1 downto 0);
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phase_load : in std_logic;
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wave_in_i : in sfixed;
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wave_in_q : in sfixed;
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wave_out_i : out sfixed;
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wave_out_q : out sfixed;
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out_valid : out std_logic
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rst : in std_logic;
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clk : in std_logic;
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nco_rst : in std_logic;
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nco_en : in std_logic;
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freq_in : in unsigned(nbits_freq-1 downto 0);
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phase_in : in unsigned(nbits_phase-1 downto 0);
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din_i : in sfixed;
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din_q : in sfixed;
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dout_i : out sfixed;
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dout_q : out sfixed;
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din_vld : in std_logic;
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dout_vld : out std_logic
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);
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end mix;
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@@ -99,12 +99,10 @@ architecture Behavioral of mix is
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-------------------------------------------------------------------------------
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signal phase : signed(nbits_phase-1 downto 0);
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signal freq_in_r : signed(nbits_phase-1 downto 0);
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signal phase_in_r : signed(nbits_phase-1 downto 0);
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signal xin, yin : sfixed(shi(nbits_wave_in, nbits_wave_in_frac) downto slo(nbits_wave_in, nbits_wave_in_frac));
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signal xout, yout : sfixed(shi(nbits_wave_out, nbits_wave_out_frac) downto slo(nbits_wave_out, nbits_wave_out_frac));
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signal xin, yin : sfixed(shi(nbits_din, nbits_din_frac) downto slo(nbits_din, nbits_din_frac));
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signal xout, yout : sfixed(shi(nbits_dout, nbits_dout_frac) downto slo(nbits_dout, nbits_dout_frac));
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signal wave_out_valid : std_logic;
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signal dout_valid : std_logic;
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signal zin : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
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signal zout : sfixed(shi(nbits_phase, nbits_phase_frac) downto slo(nbits_phase, nbits_phase_frac));
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@@ -112,12 +110,12 @@ architecture Behavioral of mix is
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-------------------------------------------------------------------------------
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begin
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wave_out_i <= xout;
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wave_out_q <= yout;
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xin <= wave_in_i;
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yin <= wave_in_q;
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dout_i <= xout;
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dout_q <= yout;
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xin <= din_i;
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yin <= din_q;
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out_valid <= wave_out_valid;
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dout_vld <= dout_valid;
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------------------------------------------------------------
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proc_phase_accu: process(clk)
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@@ -125,44 +123,16 @@ begin
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begin
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if rising_edge(clk) then
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if srst = '1' then
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phase_accu := (others => '0');
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else
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phase <= phase_accu + phase_in_r;
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if pacc_clr = '1' then
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phase_accu := (others => '0');
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elsif pacc_inc = '1' then
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phase_accu := phase_accu + freq_in_r;
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end if;
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if rst = '1' or nco_rst = '1' then
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phase_accu := (others => '0');
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elsif nco_en = '1' then
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phase <= phase_accu + signed(phase_in);
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phase_accu := phase_accu + signed(freq_in);
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end if;
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end if;
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zin <= sfixed(phase);
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end process;
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------------------------------------------------------------
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freq_in_reg: process(srst, clk, freq_load, freq_in)
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begin
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if rising_edge(clk) then
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if srst = '1' then
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freq_in_r <= (others => '0');
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elsif freq_load = '1' then
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freq_in_r <= signed(freq_in);
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end if;
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end if;
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end process;
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------------------------------------------------------------
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phase_in_reg: process(srst, clk, phase_load, phase_in)
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begin
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if rising_edge(clk) then
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if srst = '1' then
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phase_in_r <= (others => '0');
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elsif phase_load = '1' then
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phase_in_r <= signed(phase_in);
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end if;
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end if;
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end process;
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------------------------------------------------------------
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inst_cordic_ud: cordic_pipe_top
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GENERIC MAP
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@@ -171,31 +141,31 @@ begin
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z_range => 1.0,
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gain_corr_mode => gain_mode_disabled,
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nstages => nbits_phase,
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nbits_x_in => nbits_wave_in,
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nbits_frac_x_in => nbits_wave_in_frac,
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nbits_y_in => nbits_wave_in,
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nbits_frac_y_in => nbits_wave_in_frac,
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nbits_x_in => nbits_din,
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nbits_frac_x_in => nbits_din_frac,
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nbits_y_in => nbits_din,
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nbits_frac_y_in => nbits_din_frac,
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nbits_z_in => nbits_phase,
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nbits_frac_z_in => nbits_phase_frac,
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nbits_x_out => nbits_wave_out,
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nbits_frac_x_out => nbits_wave_out_frac,
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nbits_y_out => nbits_wave_out,
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nbits_frac_y_out => nbits_wave_out_frac,
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nbits_x_out => nbits_dout,
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nbits_frac_x_out => nbits_dout_frac,
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nbits_y_out => nbits_dout,
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nbits_frac_y_out => nbits_dout_frac,
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nbits_z_out => nbits_phase,
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nbits_frac_z_out => nbits_phase_frac
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)
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PORT MAP
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(
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rst => srst,
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rst => rst,
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clk => clk,
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vld_in => '1',
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vld_in => din_vld,
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xin => xin,
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yin => yin,
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zin => zin,
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xout => xout,
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yout => yout,
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zout => zout,
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vld_out => wave_out_valid
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vld_out => dout_valid
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);
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------------------------------------------------------------
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