diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
index 782169a..812310c 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb32.vhd
@@ -230,6 +230,6 @@ begin
 	cat_fifo_re			<= u_cmd_we;
 	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
 	read_fifo_we		<= phy_out.rd_data_we;
-	read_fifo_data_in	<= phy_out.rd_data(31 downto 0) when phy_out.tag_rd(0) = '0' else phy_out.rd_data(63 downto 32);	
+	read_fifo_data_in	<= phy_out.rd_data(BUS_DATA_WIDTH/2-1 downto 0) when phy_out.tag_rd(0) = '0' else phy_out.rd_data(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2);	
 
 end architecture struct;
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
index f15ed5b..80d8f00 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
@@ -224,12 +224,12 @@ begin
 	u_addr				<= addr_fifo_out;
 	phy_in.wr_dm		<= (write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-5 downto BUS_DATA_WIDTH) & write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH+4)) when phy_out.tag_wr(0) = '1' else write_fifo_dm_out(BUS_DATA_WIDTH+BUS_DM_WIDTH-1 downto BUS_DATA_WIDTH);
 	u_tag_in			<= tag_fifo_out;
-	phy_in.wr_data		<= (write_fifo_data_out(31 downto 0) & write_fifo_data_out(63 downto 32)) when phy_out.tag_wr(0) = '1' else write_fifo_data_out(63 downto 0);
+	phy_in.wr_data		<= (write_fifo_data_out(BUS_DATA_WIDTH/2-1 downto 0) & write_fifo_data_out(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2)) when phy_out.tag_wr(0) = '1' else write_fifo_data_out(BUS_DATA_WIDTH-1 downto 0);
 	
 	write_fifo_re		<= phy_out.wr_data_re and (not write_fifo_empty);
 	cat_fifo_re			<= u_cmd_we;
 	read_fifo_re 		<= (not read_fifo_empty) and MRDY_I;
 	read_fifo_we		<= phy_out.rd_data_we;
-	read_fifo_data_in	<= (phy_out.rd_data(31 downto 0) & phy_out.rd_data(63 downto 32)) when phy_out.tag_rd(0) = '1' else phy_out.rd_data(63 downto 0);	
+	read_fifo_data_in	<= (phy_out.rd_data(BUS_DATA_WIDTH/2-1 downto 0) & phy_out.rd_data(BUS_DATA_WIDTH-1 downto BUS_DATA_WIDTH/2)) when phy_out.tag_rd(0) = '1' else phy_out.rd_data(BUS_DATA_WIDTH-1 downto 0);	
 
 end architecture struct;