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[SPI master]

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- added XFER Busy to status
- don't enqueue data or commands if in reset state

git-svn-id: http://moon:8086/svn/vhdl/trunk@1295 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-13 09:56:57 +00:00
parent ec40c08234
commit f96a017bc7
2 changed files with 11 additions and 6 deletions
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lib/spi/src/spi_master.vhd
+10 -5
View File
@@ -62,11 +62,13 @@ ARCHITECTURE behavior OF spi_master IS
signal cat_fifo_full : std_logic; signal cat_fifo_full : std_logic;
signal cat_fifo_empty : std_logic; signal cat_fifo_empty : std_logic;
signal cat_fifo_re : std_logic; signal cat_fifo_re : std_logic;
signal cat_fifo_we : std_logic;
signal write_fifo_din : unsigned(WORD_WIDTH-1 downto 0); signal write_fifo_din : unsigned(WORD_WIDTH-1 downto 0);
signal write_fifo_dout : unsigned(WORD_WIDTH-1 downto 0); signal write_fifo_dout : unsigned(WORD_WIDTH-1 downto 0);
signal write_fifo_full : std_logic; signal write_fifo_full : std_logic;
signal write_fifo_empty : std_logic; signal write_fifo_empty : std_logic;
signal write_fifo_we : std_logic;
signal read_fifo_full : std_logic; signal read_fifo_full : std_logic;
signal read_fifo_empty : std_logic; signal read_fifo_empty : std_logic;
@@ -104,7 +106,7 @@ begin
status.write_fifo_empty <= write_fifo_empty; status.write_fifo_empty <= write_fifo_empty;
status.read_fifo_full <= read_fifo_full; status.read_fifo_full <= read_fifo_full;
status.read_fifo_empty <= read_fifo_empty; status.read_fifo_empty <= read_fifo_empty;
status.rx_valid <= read_fifo_we; status.xfer_busy <= '0' when state = idle else '1';
mso <= slv_enable; mso <= slv_enable;
-------------------------------------------------------------------------- --------------------------------------------------------------------------
@@ -120,7 +122,7 @@ begin
rst => spi_rst, rst => spi_rst,
clk_w => clk, clk_w => clk,
clk_r => spi_clk, clk_r => spi_clk,
we => cmd_vld, we => cat_fifo_we,
re => cat_fifo_re, re => cat_fifo_re,
fifo_full => cat_fifo_full, fifo_full => cat_fifo_full,
fifo_empty => cat_fifo_empty, fifo_empty => cat_fifo_empty,
@@ -142,7 +144,7 @@ begin
rst => spi_rst, rst => spi_rst,
clk_w => clk, clk_w => clk,
clk_r => spi_clk, clk_r => spi_clk,
we => din_vld, we => write_fifo_we,
re => data_load_en, re => data_load_en,
fifo_full => write_fifo_full, fifo_full => write_fifo_full,
fifo_empty => write_fifo_empty, fifo_empty => write_fifo_empty,
@@ -249,7 +251,7 @@ begin
end process; end process;
proc_fsm: proc_fsm:
process(state, cat_fifo_empty, cat_fifo_full, write_fifo_empty, write_fifo_full, read_fifo_full, xfer_count_busy, data_count_busy, word_cnt_pipe, ctrl_reg) process(state, cat_fifo_empty, cat_fifo_full, write_fifo_empty, write_fifo_full, read_fifo_full, xfer_count_busy, data_count_busy, word_cnt_pipe, ctrl_reg, cmd_vld, din_vld)
begin begin
state_next <= state; state_next <= state;
@@ -263,13 +265,16 @@ begin
slv_enable <= '1'; slv_enable <= '1';
read_fifo_we <= '0'; read_fifo_we <= '0';
cat_fifo_re <= '0'; cat_fifo_re <= '0';
cat_fifo_we <= cmd_vld;
write_fifo_we <= din_vld;
case state is case state is
when reset => when reset =>
cmd_rdy <= '0'; cmd_rdy <= '0';
din_rdy <= '0'; din_rdy <= '0';
slv_enable <= '0'; slv_enable <= '0';
cat_fifo_we <= '0';
write_fifo_we <= '0';
state_next <= idle; state_next <= idle;
when idle => when idle =>
lib/spi/src/spi_types.vhd
+1 -1
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@@ -30,7 +30,7 @@ package spi_types is
write_fifo_empty : std_logic; write_fifo_empty : std_logic;
read_fifo_full : std_logic; read_fifo_full : std_logic;
read_fifo_empty : std_logic; read_fifo_empty : std_logic;
rx_valid : std_logic; xfer_busy : std_logic;
end record; end record;
-- Functions -- Functions