diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd
index 4727eb9..fe8d081 100644
--- a/lib/CPUs/MIPS/src/core/mips_bui.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_bui.vhd
@@ -186,7 +186,29 @@ begin
 
 
 	MRDY_O			<= '1';
-	CYC_O			<= not bout_fifo_empty or dmem_mem_rd_gnt or dcache_mem_gnt or icache_mem_gnt;
+
+cyc_registered_out:
+	process(CLK_I)
+	variable cyc	: std_logic;
+	begin
+		if rising_edge(CLK_I) then
+			if RST_I = '1' then
+				cyc		:= '0';
+				CYC_O	<= '0';
+			else
+				CYC_O	<= cyc or not bout_fifo_empty;
+				if cyc = '0' then
+					if (bout_fifo_we and bout_rdy) = '1' then
+						cyc		:= '1';
+					end if;
+				elsif SRDY_I = '1' then
+					cyc		:= dmem_mem_rd_gnt or dcache_mem_gnt or icache_mem_gnt;
+				end if;
+			end if;
+		end if;
+	end process;	
+
+--	CYC_O			<= not bout_fifo_empty or dmem_mem_rd_gnt or dcache_mem_gnt or icache_mem_gnt;
 	STB_O			<= not bout_fifo_empty;
 	ADDR_O			<= bout_fifo_addr_out;
 	DAT_O			<= bout_fifo_data_out;
@@ -255,7 +277,7 @@ inst_dcache : dcache
 	dcache_en		<= cpu_dmem_en and not busy;
 	
 -- Instantiate synchronous FIFO
-inst_bout_fifo: entity work.fifo_sync
+inst_bout_fifo: entity work.fifo_sync_dist
 	GENERIC MAP
 	(
 		addr_width	=> 4,
@@ -294,7 +316,7 @@ inst_bout_fifo: entity work.fifo_sync
 	bout_fifo_we_in		<= '1' when dmem_mem_wr_gnt = '1' else '0';
 
 -- Instantiate synchronous FIFO
-inst_write_fifo: entity work.fifo_sync
+inst_write_fifo: entity work.fifo_sync_dist
 	GENERIC MAP
 	(
 		addr_width			=> 4,