diff --git a/lib/uart/juart_rx.vhd b/lib/uart/juart_rx.vhd
index ca6e337..177ac58 100644
--- a/lib/uart/juart_rx.vhd
+++ b/lib/uart/juart_rx.vhd
@@ -41,14 +41,19 @@ architecture behavior of juart_rx is
 --
 ------------------------------------------------------------------------------------
 --
+constant OVERSAMPLING : natural := 16;
+
+subtype bit_count_t is natural range 0 to OVERSAMPLING-1;
+subtype idle_count_t is natural range 0 to OVERSAMPLING-1;
+
 signal bit_count_rst	    : std_logic;
-signal bit_count			: natural range 0 to 15;
+signal bit_count			: bit_count_t;
 signal data_valid		    : std_logic;
 signal shiftreg_en		    : std_logic;
 signal shiftreg				: unsigned (7 downto 0);
 signal sample_count_rst		: std_logic;
-signal sample_count			: unsigned (15 downto 0);
-signal idle_count			: natural range 0 to 15;
+signal sample_count			: unsigned (OVERSAMPLING-1 downto 0);
+signal idle_count			: idle_count_t;
 signal is_idle				: std_logic;
 signal bit_sample		    : std_logic;
 
@@ -60,7 +65,7 @@ signal state_next	: state_t;
 --	
 begin
 
-bit_sample	<= sample_count(8);
+bit_sample	<= sample_count(OVERSAMPLING/2);
 is_idle		<= '1' when idle_count = 0 else '0';
 
 data_out_reg:
@@ -157,7 +162,7 @@ begin
 	if rising_edge(clk) then
 		if bit_count_rst = '1' then
 			bit_count <= 0;
-		elsif bit_count /= 15 and bit_sample = '1' then
+		elsif bit_count /= bit_count_t'high and bit_sample = '1' then
 			bit_count <= bit_count + 1;
 		end if;
 	end if;
@@ -168,11 +173,9 @@ process(clk)
 begin
 	if rising_edge(clk) then
 		if serial_in = '0' then
-			idle_count <= 15;
+			idle_count <= idle_count_t'high;
 		elsif idle_count /= 0 then
 			idle_count <= idle_count - 1;
-		else
-			idle_count <= 15;
 		end if;
 	end if;
 end process;