From f72d1deb1009d1c9779dbf8b25800e58f9ff2091 Mon Sep 17 00:00:00 2001
From: Jens Ahrensfeld <jens@jayfield.org>
Date: Wed, 24 Mar 2021 18:19:03 +0000
Subject: [PATCH] - added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1527 cc03376c-175c-47c8-b038-4cd826a8556b
---
 lib/JBUS/ghdl/tb_ram_wb.gtkw | 30 ++++++++++++++++++++++++++++++
 lib/JBUS/ghdl/tb_ram_wb.make | 18 ++++++++++++++++++
 lib/JBUS/ghdl/tb_rom_wb.gtkw | 30 ++++++++++++++++++++++++++++++
 lib/JBUS/ghdl/tb_rom_wb.make | 17 +++++++++++++++++
 4 files changed, 95 insertions(+)
 create mode 100644 lib/JBUS/ghdl/tb_ram_wb.gtkw
 create mode 100644 lib/JBUS/ghdl/tb_ram_wb.make
 create mode 100644 lib/JBUS/ghdl/tb_rom_wb.gtkw
 create mode 100644 lib/JBUS/ghdl/tb_rom_wb.make

diff --git a/lib/JBUS/ghdl/tb_ram_wb.gtkw b/lib/JBUS/ghdl/tb_ram_wb.gtkw
new file mode 100644
index 0000000..423fc96
--- /dev/null
+++ b/lib/JBUS/ghdl/tb_ram_wb.gtkw
@@ -0,0 +1,30 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Wed Mar 24 18:10:46 2021
+[*]
+[dumpfile] "/home/jens/work/vhdl/trunk/lib/JBUS/ghdl/build/tb_ram_wb/tb_ram_wb.vcd"
+[dumpfile_mtime] "Wed Mar 24 18:09:02 2021"
+[dumpfile_size] 39259
+[savefile] "/home/jens/work/vhdl/trunk/lib/JBUS/ghdl/build/tb_ram_wb/tb_ram_wb.gtkw"
+[timestart] 0
+[size] 1856 1136
+[pos] -51 -51
+*-27.715721 354000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] tb_ram_wb.
+[treeopen] tb_ram_wb.inst_ram_wb.
+[sst_width] 233
+[signals_width] 212
+[sst_expanded] 1
+[sst_vpaned_height] 331
+@28
+tb_ram_wb.rst_o
+tb_ram_wb.clk_o
+tb_ram_wb.ack_i
+@29
+tb_ram_wb.we_o
+@22
+tb_ram_wb.addr_o[31:0]
+tb_ram_wb.dat_i[31:0]
+tb_ram_wb.dat_o[31:0]
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/lib/JBUS/ghdl/tb_ram_wb.make b/lib/JBUS/ghdl/tb_ram_wb.make
new file mode 100644
index 0000000..0ef15b6
--- /dev/null
+++ b/lib/JBUS/ghdl/tb_ram_wb.make
@@ -0,0 +1,18 @@
+ROOT_PATH := ../../..
+LIB_PATH := $(ROOT_PATH)/lib
+MOD_PATH := $(LIB_PATH)/JBUS
+
+SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
+SRCS += $(LIB_PATH)/rams/sim/dpram_1w1r1c_ra.vhd
+SRCS += $(MOD_PATH)/src/memory/ram_wb.vhd
+SRCS += $(MOD_PATH)/src/memory/tb_ram_wb.vhd
+
+# Compile
+TARGET := tb_ram_wb
+ENTITY := tb_ram_wb
+WITH_VCD := y
+RUN_TIME := 1500ns
+
+include $(ROOT_PATH)/Common/make/ghdl.mk
+
+
diff --git a/lib/JBUS/ghdl/tb_rom_wb.gtkw b/lib/JBUS/ghdl/tb_rom_wb.gtkw
new file mode 100644
index 0000000..05105f4
--- /dev/null
+++ b/lib/JBUS/ghdl/tb_rom_wb.gtkw
@@ -0,0 +1,30 @@
+[*]
+[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
+[*] Wed Mar 24 18:18:00 2021
+[*]
+[dumpfile] "/home/jens/work/vhdl/trunk/lib/JBUS/ghdl/build/tb_rom_wb/tb_rom_wb.vcd"
+[dumpfile_mtime] "Wed Mar 24 18:17:07 2021"
+[dumpfile_size] 24044
+[savefile] "/home/jens/work/vhdl/trunk/lib/JBUS/ghdl/build/tb_rom_wb/tb_rom_wb.gtkw"
+[timestart] 0
+[size] 1856 1136
+[pos] -51 -51
+*-27.727428 114000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[sst_width] 233
+[signals_width] 223
+[sst_expanded] 1
+[sst_vpaned_height] 331
+@28
+tb_rom_wb.clk_o
+tb_rom_wb.rst_o
+@22
+tb_rom_wb.addr_o[31:0]
+tb_rom_wb.dat_i[31:0]
+@28
+tb_rom_wb.mrdy_o
+tb_rom_wb.srdy_i
+tb_rom_wb.stb_o
+@29
+tb_rom_wb.cyc_o
+[pattern_trace] 1
+[pattern_trace] 0
diff --git a/lib/JBUS/ghdl/tb_rom_wb.make b/lib/JBUS/ghdl/tb_rom_wb.make
new file mode 100644
index 0000000..daf2fe9
--- /dev/null
+++ b/lib/JBUS/ghdl/tb_rom_wb.make
@@ -0,0 +1,17 @@
+ROOT_PATH := ../../..
+LIB_PATH := $(ROOT_PATH)/lib
+MOD_PATH := $(LIB_PATH)/JBUS
+
+SRCS += $(MOD_PATH)/src/memory/rom_sim.vhd
+SRCS += $(MOD_PATH)/src/memory/rom_wb.vhd
+SRCS += $(MOD_PATH)/src/memory/tb_rom_wb.vhd
+
+# Compile
+TARGET := tb_rom_wb
+ENTITY := tb_rom_wb
+WITH_VCD := y
+RUN_TIME := 1500ns
+
+include $(ROOT_PATH)/Common/make/ghdl.mk
+
+