From f59e4dd7d14724cae1c2df0bad3d737ed80361ca Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sun, 19 Oct 2008 20:23:27 +0000 Subject: [PATCH] - Added Sync. SRAM git-svn-id: http://moon:8086/svn/vhdl/trunk@78 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/sim/tb_mips_sys.fdo | 30 ++++- projects/mips_sys/sim/tb_mips_sys.wdo | 168 ++++++++++++++++++++------ 2 files changed, 158 insertions(+), 40 deletions(-) diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo index 7e0fe04..934bff7 100644 --- a/projects/mips_sys/sim/tb_mips_sys.fdo +++ b/projects/mips_sys/sim/tb_mips_sys.fdo @@ -17,6 +17,13 @@ vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd" vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd" vcom -explicit -93 "../../../lib/misc/dpram_1w1r_dist.vhd" +# FIFOS +vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" +vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd" +vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd" +vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd" +vcom -explicit -93 "../../../lib/FIFO/src/async_fifo_ctrl.vhd" + # CPU vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd" vcom -explicit -93 "../../../lib/CPUs/MIPS/src/core/mips_reg.vhd" @@ -35,6 +42,18 @@ vcom -explicit -93 "../src/bootloader.ROM.vhd" vcom -explicit -93 "../src/ram_wb.vhd" vcom -explicit -93 "../src/rom_wb.vhd" +# VGA +vcom -explicit -93 "../../../lib/VGA_ctrl/src/fonts/char_rom_c64.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_types.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/dpram.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/linefifo.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/char_gen.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_sync.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_timing.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_backend.vhd" +vcom -explicit -93 "../../../lib/VGA_ctrl/src/vga_frontend.vhd" + # UART vcom -explicit -93 "../../../lib/uart/bbfifo_16x8.vhd" vcom -explicit -93 "../../../lib/uart/kcuart_rx.vhd" @@ -53,9 +72,10 @@ vcom -explicit -93 "../../../lib/misc/lcd_port.vhd" vcom -explicit -93 "../src/sys_types.vhd" vcom -explicit -93 "../../../lib/misc/async_port_wb.vhd" -# FIFOS -vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/sync_fifo_ctrl.vhd" +# Sync SRAM +vcom -explicit -93 "../src/package_utility.vhd" +vcom -explicit -93 "../src/CY7C1354B.vhd" +vcom -explicit -93 "../src/ssram_frontend_wb.vhd" # SDRAM vcom -explicit -93 "../../../lib/misc/clockgen_virtex4.vhd" @@ -63,7 +83,6 @@ vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd" @@ -76,5 +95,4 @@ do {tb_mips_sys.wdo} view wave view structure view signals -run 5ms - \ No newline at end of file +run 20ms diff --git a/projects/mips_sys/sim/tb_mips_sys.wdo b/projects/mips_sys/sim/tb_mips_sys.wdo index 3e37d0f..0d3990c 100644 --- a/projects/mips_sys/sim/tb_mips_sys.wdo +++ b/projects/mips_sys/sim/tb_mips_sys.wdo @@ -13,6 +13,11 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_e add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rs add wave -noupdate -format Logic /tb_mips_sys/sys_lcd_rw add wave -noupdate -format Logic /tb_mips_sys/refresh +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_addr +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/u_bank_addr add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_fb add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_p add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_clk_n @@ -21,17 +26,26 @@ add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cs_qn add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_ras_qn add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_cas_qn add wave -noupdate -format Logic /tb_mips_sys/sys_sdr_we_qn -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dqs_q add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_ba_q -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_a_q -add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_data +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_a_q +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_sdr_data +add wave -noupdate -format Literal /tb_mips_sys/sys_sdr_dm_q +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_dm_wr_in +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_in +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_rd +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_tag_wr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_data_r +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/u_data_vld +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/u_data_req_w +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/read_fifo_data_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_sdram_ctrl_frontend_wb/read_fifo_data_out add wave -noupdate -format Literal /tb_mips_sys/sys_error add wave -noupdate -format Logic /tb_mips_sys/uut/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/dat_o add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o add wave -noupdate -format Logic /tb_mips_sys/uut/we_o add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o @@ -39,26 +53,92 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o add wave -noupdate -format Literal /tb_mips_sys/uut/mem_area +add wave -noupdate -divider Arbiter +add wave -noupdate -format Literal /tb_mips_sys/uut/arb_idx +add wave -noupdate -format Literal /tb_mips_sys/uut/arb_req +add wave -noupdate -format Literal /tb_mips_sys/uut/arb_gnt +add wave -noupdate -divider {CPU Master} +add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_cpu +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_cpu +add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_cpu +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_cpu +add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_cpu +add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_cpu +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_cpu +add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_cpu +add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_cpu +add wave -noupdate -divider {VGA Master} +add wave -noupdate -format Logic /tb_mips_sys/uut/ack_i_vga +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/mdat_o_vga +add wave -noupdate -format Logic /tb_mips_sys/uut/mrdy_o_vga +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/addr_o_vga +add wave -noupdate -format Literal /tb_mips_sys/uut/sel_o_vga +add wave -noupdate -format Logic /tb_mips_sys/uut/we_o_vga +add wave -noupdate -format Logic /tb_mips_sys/uut/cyc_o_vga +add wave -noupdate -format Logic /tb_mips_sys/uut/stb_o_vga +add wave -noupdate -format Logic /tb_mips_sys/uut/srdy_i_vga +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_full +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_empty +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_almost_empty +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_almost_full +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/request_cnt +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/read_cnt +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_vga_frontend/s +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/vga_master_en +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/vga_scan_rdy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_color_re +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/fifo_color_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/fifo_color_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_vga_frontend/fifo_color_in +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_vga_frontend/scan_rdy add wave -noupdate -divider BUI add wave -noupdate -format Logic /tb_mips_sys/uut/clk +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_icache +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dcache +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_rd +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cyc_o_dmem_wr +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_icache +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dcache +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_rd +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/stb_o_dmem_wr add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s_ca -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy2 +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/uncached_access add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcache_busy1 -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval -add wave -noupdate -format Literal -label .addr -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.addr -add wave -noupdate -format Literal -label .dout -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.dout -add wave -noupdate -format Logic -label .en -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.en -add wave -noupdate -format Logic -label .re -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.re -add wave -noupdate -format Literal -label .we -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bui_eval.we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout_cnt +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bus_timeout +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_re +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_full +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_empty +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_out +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_out +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_we_in +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_sel_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_data_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/bout_fifo_addr_in +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_dout +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_re +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_full +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_fifo_empty +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/write_busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr -add wave -noupdate -divider USB -add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/s add wave -noupdate -format Literal -label .op -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/ex_stage.op +add wave -noupdate -divider USB +add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Logic /tb_mips_sys/sys_usb_rstn add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_d add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_usb_a @@ -71,12 +151,25 @@ add wave -noupdate -divider Flash add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/as add wave -noupdate -format Literal /tb_mips_sys/uut/inst_flash_port/s -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_a +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a add wave -noupdate -format Logic /tb_mips_sys/sys_flash_ce add wave -noupdate -format Logic /tb_mips_sys/sys_flash_wrn add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rdn add wave -noupdate -format Logic /tb_mips_sys/sys_flash_rstn +add wave -noupdate -divider {Sync SRAM} +add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_clk +add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_cke_n +add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_ce_n +add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_we_n +add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_oe_n +add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_dp +add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_adv +add wave -noupdate -format Literal /tb_mips_sys/sys_ssram_bw_n +add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_mode +add wave -noupdate -format Logic /tb_mips_sys/sys_ssram_zz +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_d +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/sys_flash_ssram_a add wave -noupdate -divider {MIPS TOP} add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_pipeline/hdu @@ -132,8 +225,8 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_rdy add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_re -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_we +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_be add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_dout add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/cpu_dmem_addr @@ -189,35 +282,42 @@ add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_ic add wave -noupdate -divider D-Cache add wave -noupdate -format Logic /tb_mips_sys/uut/clk add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_en -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_r_wn +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_addr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_din add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dout add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we_reg add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/s -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_read_miss -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_write_miss add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_busy +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cache_hit add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_reg_en add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/was_miss add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/data_write +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/mem_index_count +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/word_index_reg +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_word_index +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/instant_raw add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_addr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_data_reg -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_we_reg -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_force_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_was_write +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_hit_we +add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_en add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_addr add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_din add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/ctrl_dram_we -add wave -noupdate -format Literal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/cpu_dram_we -add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/dcached +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_rd +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_dout +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_addr_wr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_din +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_re +add wave -noupdate -format Logic /tb_mips_sys/uut/inst_mips_top/inst_bui/inst_dcache/tram_we TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {1129563255 ps} 0} +WaveRestoreCursors {{Cursor 2} {49999842932 ps} 0} {{Cursor 100} {115147600 ps} 0} configure wave -namecolwidth 218 -configure wave -valuecolwidth 100 +configure wave -valuecolwidth 130 configure wave -justifyvalue left configure wave -signalnamewidth 1 configure wave -snapdistance 10 @@ -229,4 +329,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {1129448646 ps} {1129766075 ps} +WaveRestoreZoom {2390724794 ps} {3001528274 ps}