From f3c5702a67b4d437e8dcf81705310d554c75a4ef Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 6 Feb 2010 18:45:30 +0000 Subject: [PATCH] - removed module reset_virtex4 Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@713 cc03376c-175c-47c8-b038-4cd826a8556b --- projects/mips_sys/ise101/mips_sys/mips_sys.prj | 1 - projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj | 1 - projects/mips_sys/sim/tb_mips_sys.fdo | 3 +-- 3 files changed, 1 insertion(+), 4 deletions(-) diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys.prj b/projects/mips_sys/ise101/mips_sys/mips_sys.prj index c75d8ad..b8b35cd 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys.prj +++ b/projects/mips_sys/ise101/mips_sys/mips_sys.prj @@ -15,7 +15,6 @@ vhdl work "../../../../lib/uart/kcuart_rx.vhd" vhdl work "../../../../lib/uart/bbfifo_16x8.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" vhdl work "../../../../lib/FIFO/src/fifo_sync_ctrl.vhd" vhdl work "../../../../lib/FIFO/src/fifo_async.vhd" diff --git a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj index 7a5b9a4..db0d3e8 100644 --- a/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj +++ b/projects/mips_sys/ise101/mips_sys/mips_sys_vhdl.prj @@ -15,7 +15,6 @@ vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd" vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd" vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd" vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd" vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd" vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_ctrl.vhd" vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd" diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo index b5575a2..2adac16 100644 --- a/projects/mips_sys/sim/tb_mips_sys.fdo +++ b/projects/mips_sys/sim/tb_mips_sys.fdo @@ -81,7 +81,6 @@ vcom -explicit -93 "../../../lib/SSRAM/src/ssram_port_wb.vhd" # SDRAM vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd" -vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd" vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd" @@ -105,4 +104,4 @@ do {tb_mips_sys.wdo} view wave view structure view signals -run 50ms +run 1ms