diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt
index 02dbb35..488c8e6 100644
--- a/lib/CPUs/MIPS/dist/tmpl/notes.txt
+++ b/lib/CPUs/MIPS/dist/tmpl/notes.txt
@@ -23,7 +23,7 @@ Changes in release 12
 - gpio_wb.vhd: added 32 bit timer with interrupt and auto reload
 - added debugger in libsys. New files are mipsdis.c/h and dbg.c/h
 - exception handlers can now be registered to any exception type 
-- bugfix: cop0 registers were not written during exception commit. Cop registers now behave like general registers.
+- bugfix mips_pipeline/mips_cop: cop0 registers were not written during exception commit. Cop registers now behave like general registers.
 - added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian)
 - Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode
 - Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of an MMU.
@@ -36,7 +36,7 @@ Changes in release 12
   Drawback of using NMI/RST: Unitialized/unreseted periphery may cause trouble (e.g. firing unwanted interrupts), but I think you know that already.
 - Bootloader: Startup.S now invalidates I/D-Caches at boot.
 - uart_wb.vhd: fixed crappy tx-empty interrupt, Added Tx-IRQ acknowledge.
-- Bugfix: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.
+- Bugfix in mips_pipeline: register bypass with same target register, used for unaligned loads (LWL, LWR), was incorrect.
   Newlib's MIPS-optimized version of memcpy() uses this for unaligned copy which revealed the bug.  
   Symptom: Consecutive load instructions without nops using same target register (which is legal) like
    lw $1, 0(mem)
@@ -45,6 +45,15 @@ Changes in release 12
    lwl $1, 0(mem)
    lwr $1, 1(mem)
   or similar, lead to incorrect result. Now it's fixed.
+- Bugfix mips_biu: instructions uncached LW => cached LW (with cache-miss) was buggy.
+  Symptom:
+  ...
+  1.: lw     $a0, 32($s0)  # Uncached load from memory mapped I/O
+  2.: lw     $a2, 4($v0)   # Cached load and cache-miss.
+                           # $a0 receives same value as $a2.
+                           # CPU skips writing $a0 due to busy flag of D-Cache,
+                           # which is already active in the previous cycle
+  ...
 
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 Changes in release 11