From f2ebee97038ee510cf92d7b681b6f30debfc605b Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Tue, 7 Oct 2008 17:19:52 +0000 Subject: [PATCH] - Registered ACK - 32bit Host I/F git-svn-id: http://moon:8086/svn/vhdl/trunk@25 cc03376c-175c-47c8-b038-4cd826a8556b --- .../src/sdram_ctrl_frontend_wb.vhd | 70 +++++++++++-------- 1 file changed, 40 insertions(+), 30 deletions(-) diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd index 3a9aee5..7f23f19 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd @@ -48,7 +48,8 @@ entity sdram_ctrl_frontend_wb is SEL_I : in unsigned(3 downto 0); WE_I : in STD_LOGIC; ACK_O : out STD_LOGIC; - RDY_O : out STD_LOGIC; + MRDY_I : in STD_LOGIC; + SRDY_O : out STD_LOGIC; ADDR_I : in unsigned(31 downto 0); DAT_I : in unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0); @@ -89,7 +90,7 @@ architecture struct of sdram_ctrl_frontend_wb is signal u_req_wr : std_logic; signal rdy : std_logic; - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + SDR_DM_WIDTH; + constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + 4; signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); signal cat_fifo_re : std_logic; @@ -99,8 +100,8 @@ architecture struct of sdram_ctrl_frontend_wb is -- signal cat_fifo_almost_full : std_logic; -- signal cat_fifo_almost_empty : std_logic; - signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); + signal write_fifo_din : unsigned(35 downto 0); + signal write_fifo_dout : unsigned(35 downto 0); signal write_fifo_re : std_logic; signal write_fifo_we : std_logic; signal write_fifo_full : std_logic; @@ -108,8 +109,8 @@ architecture struct of sdram_ctrl_frontend_wb is -- signal write_fifo_almost_full : std_logic; -- signal write_fifo_almost_empty : std_logic; - signal read_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal read_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); + signal read_fifo_din : unsigned(35 downto 0); + signal read_fifo_dout : unsigned(35 downto 0); signal read_fifo_re : std_logic; signal read_fifo_we : std_logic; signal read_fifo_full : std_logic; @@ -119,22 +120,22 @@ architecture struct of sdram_ctrl_frontend_wb is alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH); - alias dm_rd_fifo_in is cat_fifo_din(SDR_DM_WIDTH-1 downto 0); + alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 4); + alias dm_rd_fifo_in is cat_fifo_din(4-1 downto 0); alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH); - alias dm_rd_fifo_out is cat_fifo_dout(SDR_DM_WIDTH-1 downto 0); + alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 4); + alias dm_rd_fifo_out is cat_fifo_dout(4-1 downto 0); - alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH); - alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0); - alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH); - alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); + alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-4); + alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-4-1 downto 0); + alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-4); + alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-4-1 downto 0); - alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-SDR_DM_WIDTH); - alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-SDR_DM_WIDTH-1 downto 0); - alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-SDR_DM_WIDTH); - alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); + alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-4); + alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-4-1 downto 0); + alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-4); + alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-4-1 downto 0); begin @@ -164,7 +165,7 @@ begin GENERIC MAP ( addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH + data_width => 36 ) PORT MAP ( @@ -185,7 +186,7 @@ begin GENERIC MAP ( addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH + data_width => 36 ) PORT MAP ( @@ -251,33 +252,42 @@ begin ); ------------------------------------------------------------------------------------------ - RDY_O <= rdy and CYC_I; + SRDY_O <= rdy and CYC_I; rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full); write_fifo_we <= STB_I and CYC_I and WE_I and rdy; write_fifo_data_in <= DAT_I; write_fifo_dm_in <= not SEL_I; cat_fifo_we <= STB_I and CYC_I and rdy; cmd_fifo_in <= UCMD_WRITE when WE_I = '1' else UCMD_READ; - addr_fifo_in <= ADDR_I(user_addr_t'range); + addr_fifo_in <= ADDR_I(24 downto 2) & "0"; dm_rd_fifo_in <= not SEL_I; tag_fifo_in <= (others=>'0'); - DAT_O <= read_fifo_data_out; - ACK_O <= write_fifo_we or (CYC_I and not (WE_I or read_fifo_empty)); u_cmd_we <= (not cat_fifo_empty) and (not u_busy); u_cmd <= cmd_fifo_out; u_addr <= addr_fifo_out; - u_dm_rd_in <= dm_rd_fifo_out; - u_dm_wr_in <= write_fifo_dm_out; + u_dm_rd_in <= dm_rd_fifo_out & dm_rd_fifo_out; + u_dm_wr_in <= write_fifo_dm_out & write_fifo_dm_out; u_tag_in <= tag_fifo_out; write_fifo_re <= u_req_wr and (not write_fifo_empty); cat_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_data_out; - read_fifo_re <= (not read_fifo_empty); -- and dout_re; + u_data_w <= write_fifo_data_out & write_fifo_data_out; + read_fifo_re <= (not read_fifo_empty) and MRDY_I; read_fifo_we <= u_data_vld; - read_fifo_data_in <= u_data_r; - read_fifo_dm_in <= u_dm_rd_out; + read_fifo_data_in <= u_data_r(31 downto 0); + read_fifo_dm_in <= u_dm_rd_out(3 downto 0); +data_register: + process(CLK_I) + begin + if rising_edge(CLK_I) then + ACK_O <= '0'; + if MRDY_I = '1' then + ACK_O <= write_fifo_we or (CYC_I and not (WE_I or read_fifo_empty)); + DAT_O <= read_fifo_data_out; + end if; + end if; + end process; end architecture struct;