diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb.fdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb.fdo index 85e50ae..7d04c47 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb.fdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb.fdo @@ -19,12 +19,12 @@ vcom -explicit -93 "../src/ddr_clk_virtex4.vhd" vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" vcom -explicit -93 "../src/sdram_ctrl_top.vhd" vcom -explicit -93 "../src/sdram_ctrl_frontend64_wb.vhd" +vcom -explicit -93 "../src/ctrl_ddr_wb.vhd" vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdram_ctrl_frontend64_wb.vhd" +vcom -explicit -93 "../src/tb_ctrl_ddr_wb.vhd" -#restart -force -vsim -t 1ps -lib work tb_sdram_ctrl_frontend64_wb -do {tb_sdram_ctrl_frontend64_wb.wdo} +vsim -t 1ps -lib work tb_ctrl_ddr_wb +do {tb_ctrl_ddr_wb.wdo} view wave view structure view signals diff --git a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb.wdo b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb.wdo index fb51533..40001c7 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb.wdo +++ b/lib/SDRAM/ddr_sdr_v1_5/sim/tb_ctrl_ddr_wb.wdo @@ -1,43 +1,42 @@ onerror {resume} quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/clk_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/rst_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/cyc_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/stb_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/we_o -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sel_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/ack_i -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/mrdy_o -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dat_o -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/dout_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/dout_cnt -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/sdram_clk -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/sdram_clk_fb -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/sdram_clk0 -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/sdram_rst0 -add wave -noupdate -divider Part -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cs_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_we_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_ras_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend64_wb/part_cas_n -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_ba -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dm -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/part_dqs -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/part_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_col_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/col_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_row_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/row_addr_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/u_bank_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend64_wb/sdram_ctrl_frontend64_wb/inst_sdram_ctrl_top/inst_sdram_ctrl/bank_addr_reg -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend64_wb/sd_cmd +add wave -noupdate -divider J-Bus +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/clk_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/rst_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/cyc_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/stb_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/we_o +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/sel_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/ack_i +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/mrdy_o +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/srdy_i +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/addr_o +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dat_i +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dat_o +add wave -noupdate -divider SDRAM +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/sdclk +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/sdclk_fb +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_clk_p +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_clk_n +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cke +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cs_n +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_we_n +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_ras_n +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/part_cas_n +add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_ba +add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_dm +add wave -noupdate -format Literal /tb_ctrl_ddr_wb/part_dqs +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/part_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/part_data +add wave -noupdate -divider Test +add wave -noupdate -format Literal /tb_ctrl_ddr_wb/sd_cmd +add wave -noupdate -format Logic /tb_ctrl_ddr_wb/dout_rst +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/sddat +add wave -noupdate -format Literal /tb_ctrl_ddr_wb/sdsel +add wave -noupdate -format Literal -radix hexadecimal /tb_ctrl_ddr_wb/dout_reg +add wave -noupdate -format Literal /tb_ctrl_ddr_wb/dout_cnt TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {38990166 ps} 0} +WaveRestoreCursors {{Cursor 1} {189465865 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -51,4 +50,4 @@ configure wave -gridperiod 1 configure wave -griddelta 40 configure wave -timeline 0 update -WaveRestoreZoom {38975716 ps} {39081070 ps} +WaveRestoreZoom {0 ps} {210 us} diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd index c0c3a83..634c9cb 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend64_wb.vhd @@ -55,7 +55,7 @@ entity sdram_ctrl_frontend64_wb is DAT_I : in unsigned(SDR_DATA_WIDTH-1 downto 0); DAT_O : out unsigned(SDR_DATA_WIDTH-1 downto 0); - -- Phy interface + -- PHY interface phy_ctrl : out phy_ctrl_t; phy_in : out phy_in_t; phy_out : in phy_out_t; @@ -215,7 +215,7 @@ begin u_cmd => u_cmd, u_cmd_we => u_cmd_we, - -- Phy controll interface + -- Phy control interface phy_ctrl => phy_ctrl ); diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd index c206416..d06b589 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd @@ -32,17 +32,17 @@ use work.sdram_types.all; entity sdram_ctrl_frontend_wb is Generic ( - BL : natural := 2; + BURST_LEN : natural := 2; F_SYSCLK : real := 100.0; - f_sdrclk : real := 100.0; - fifo_depth : integer := 4 + F_SDRCLK : real := 100.0; + FIFO_DEPTH : integer := 4 ); Port ( RST_I : in STD_LOGIC; CLK_I : in STD_LOGIC; - SDRAM_CLK_I : in STD_LOGIC; - SDRAM_CLK_FB_I : in STD_LOGIC; + SDRAM_RST0 : in STD_LOGIC; + SDRAM_CLK0 : in STD_LOGIC; CYC_I : in STD_LOGIC; STB_I : in STD_LOGIC; @@ -55,6 +55,11 @@ entity sdram_ctrl_frontend_wb is DAT_I : in unsigned(31 downto 0); DAT_O : out unsigned(31 downto 0); + -- PHY interface + phy_ctrl : out phy_ctrl_t; + phy_in : out phy_in_t; + phy_out : in phy_out_t; + -- SDRAM signals sd_clk_p : out STD_LOGIC; sd_clk_n : out STD_LOGIC; @@ -74,24 +79,11 @@ end sdram_ctrl_frontend_wb; architecture struct of sdram_ctrl_frontend_wb is - signal SDRAM_CLK0 : std_logic; - signal SDRAM_RST0 : std_logic; - - signal phy_in : phy_in_t; - signal phy_out : phy_out_t; - signal u_addr : user_addr_t; signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; signal u_cmd : user_cmd_t; signal u_cmd_we : std_logic; signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_rd_data_we : std_logic; - signal u_wr_data_re : std_logic; signal rdy : std_logic; constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; @@ -137,7 +129,7 @@ begin inst_cat_fifo: entity work.fifo_sync GENERIC MAP ( - addr_width => fifo_depth, + addr_width => FIFO_DEPTH, data_width => CAT_FIFO_WIDTH ) PORT MAP @@ -158,7 +150,7 @@ begin inst_write_fifo: entity work.fifo_async GENERIC MAP ( - addr_width => fifo_depth, + addr_width => FIFO_DEPTH, data_width => write_fifo_din'length ) PORT MAP @@ -180,7 +172,7 @@ begin inst_read_fifo: entity work.fifo_async GENERIC MAP ( - addr_width => fifo_depth, + addr_width => FIFO_DEPTH, data_width => read_fifo_din'length ) PORT MAP @@ -202,7 +194,7 @@ begin inst_sdram_ctrl_top : entity work.sdram_ctrl_top Generic map ( - BL => BL, + BURST_LEN => BURST_LEN, F_SYSCLK => F_SYSCLK, F_SDRCLK => F_SDRCLK, FIFO_DEPTH => FIFO_DEPTH @@ -213,10 +205,8 @@ begin sys_rst_in => RST_I, sys_clk_in => CLK_I, - sdram_clk => SDRAM_CLK_I, - sdram_clk_fb => SDRAM_CLK_FB_I, - sdram_clk_out => SDRAM_CLK0, - sdram_rst_out => SDRAM_RST0, + sdram_rst0 => SDRAM_RST0, + sdram_clk0 => SDRAM_CLK0, -- User interface u_tag => u_tag_in, @@ -225,23 +215,8 @@ begin u_cmd => u_cmd, u_cmd_we => u_cmd_we, - -- Phy user interface - phy_in => phy_in, - phy_out => phy_out, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data + -- Phy control interface + phy_ctrl => phy_ctrl ); diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb.vhd index 3544e01..93bf85f 100644 --- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb.vhd +++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb.vhd @@ -28,14 +28,13 @@ use IEEE.numeric_std.ALL; use work.sdram_config.all; use work.sdram_types.all; -entity tb_sdram_ctrl_frontend_wb is +entity tb_ctrl_ddr_wb is end; -architecture struct of tb_sdram_ctrl_frontend_wb is +architecture struct of tb_ctrl_ddr_wb is - -- Number of user data words for simulation constant CLK_PERIOD : time := 10 ns; - constant SDCLK_PERIOD : time := 8 ns; + constant SDCLK_PERIOD : time := 7.5 ns; constant BURST_LEN : natural := 2; signal sdclk : std_logic := '1'; @@ -110,13 +109,13 @@ begin sdclk_fb <= part_clk_p after 1 ns; -- DDR SDRAM Controller Core - sdram_ctrl_frontend_wb : entity work.sdram_ctrl_frontend_wb + uut : entity work.ctrl_ddr_wb GENERIC MAP ( - BL => BURST_LEN, - f_sysclk => 100.0, - f_sdrclk => 100.0, - fifo_depth => 4 + BURST_LEN => BURST_LEN, + F_SYSCLK => 100.000, + F_SDRCLK => 133.333, + FIFO_DEPTH => 4 ) PORT MAP (