From f046307aa985ce1883a15cdb74bb73c89f7b8d9c Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Wed, 6 May 2009 21:30:23 +0000 Subject: [PATCH] - removed reference to fifo_sync_dist. Use fifo_sync instead and specified ditributed ram_style in XCF-file during synthesis Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@473 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/sim/tb_mips_top.fdo | 5 +- lib/CPUs/MIPS/sim/tb_mips_top.wdo | 289 ++++++-------------------- projects/mips_sys/sim/tb_mips_sys.fdo | 2 - 3 files changed, 65 insertions(+), 231 deletions(-) diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo index b64f076..768f397 100644 --- a/lib/CPUs/MIPS/sim/tb_mips_top.fdo +++ b/lib/CPUs/MIPS/sim/tb_mips_top.fdo @@ -5,12 +5,11 @@ vlib work # RAMS vcom -explicit -93 "../../../misc/dpram_2w2r.vhd" vcom -explicit -93 "../../../misc/dpram_1w1r.vhd" -vcom -explicit -93 "../../../misc/dpram_1w1r_dist.vhd" # FIFOS vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" vcom -explicit -93 "../../../FIFO/src/fifo_sync_ctrl.vhd" -vcom -explicit -93 "../../../FIFO/src/fifo_sync_dist.vhd" +vcom -explicit -93 "../../../FIFO/src/fifo_sync.vhd" # UART vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd" @@ -53,4 +52,4 @@ do {tb_mips_top.wdo} view wave view structure view signals -run 1600us +run 12000us diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo index 0588232..022ff87 100644 --- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo +++ b/lib/CPUs/MIPS/sim/tb_mips_top.wdo @@ -20,6 +20,16 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 +add wave -noupdate -divider {Interrupt Timer} +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cnt +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/timer_cmp +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_en +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_inten +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_ovl +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_irq_ack +add wave -noupdate -format Literal /tb_mips_top/inst_gpio/timer_cmp_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_gpio/reg_data_wr add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Logic /tb_mips_top/rx add wave -noupdate -format Logic /tb_mips_top/tx @@ -52,12 +62,28 @@ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/ add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/dcache_info add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_id add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cop_pipe_ex +add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/ctrl_in +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_cop/ctrl_out +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/epc +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/cause +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/status +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_cop/badvaddr +add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/eflags +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_save +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/status_rest +add wave -noupdate -format Logic /tb_mips_top/uut/inst_cop/stat_reg_we +add wave -noupdate -format Literal /tb_mips_top/uut/inst_cop/exc_state add wave -noupdate -divider Pipestages add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Logic -label .stall_all /tb_mips_top/uut/inst_pipeline/sdu.stall_all add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage @@ -65,6 +91,9 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem add wave -noupdate -divider I-Cache +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/ctrl +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/flush_count +add wave -noupdate -format Logic /tb_mips_top/clk add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr @@ -76,30 +105,36 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_mis add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/word_index_reg add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_index_reg -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_reg_en add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_req +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_ack add wave -noupdate -divider D-Cache +add wave -noupdate -format Logic /tb_mips_top/clk +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/ctrl +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/dcached -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_rd -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_wr -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tram_we -add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_en +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_reg add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/word_index_reg add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr_windex_reg add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_index_reg add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy @@ -109,220 +144,22 @@ add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_cou add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_en add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_reg_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw -add wave -noupdate -divider {TOP interface} -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/debug -add wave -noupdate -format Logic /tb_mips_top/stb_o -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Logic /tb_mips_top/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o -add wave -noupdate -format Logic /tb_mips_top/we_o -add wave -noupdate -format Literal /tb_mips_top/sel_o -add wave -noupdate -format Logic /tb_mips_top/cyc_o -add wave -noupdate -format Logic /tb_mips_top/mrdy_o -add wave -noupdate -format Literal /tb_mips_top/int -add wave -noupdate -divider {External components} -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/rx -add wave -noupdate -format Logic /tb_mips_top/tx -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/mem_area -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d -add wave -noupdate -format Logic /tb_mips_top/flash_cs_n -add wave -noupdate -format Logic /tb_mips_top/flash_oe_n -add wave -noupdate -format Literal /tb_mips_top/flash_be_n -add wave -noupdate -format Logic /tb_mips_top/sram_cs_n -add wave -noupdate -format Literal /tb_mips_top/sram_wr_n -add wave -noupdate -format Logic /tb_mips_top/sram_oe_n -add wave -noupdate -format Literal /tb_mips_top/sram_be_n -add wave -noupdate -divider ALU -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu -add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/sdu -add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc -add wave -noupdate -divider COP0 -add wave -noupdate -divider Pipestages -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem -add wave -noupdate -divider I-Cache -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_busy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_miss -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/word_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_index_reg -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_reg_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count -add wave -noupdate -divider D-Cache -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_rd -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_wr -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tram_we -add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/word_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr_windex_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_index_reg -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rdy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_reg_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw -add wave -noupdate -divider {TOP interface} -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/debug -add wave -noupdate -format Logic /tb_mips_top/stb_o -add wave -noupdate -format Logic /tb_mips_top/ack_i -add wave -noupdate -format Logic /tb_mips_top/srdy_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/addr_o -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_i -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dat_o -add wave -noupdate -format Logic /tb_mips_top/we_o -add wave -noupdate -format Literal /tb_mips_top/sel_o -add wave -noupdate -format Logic /tb_mips_top/cyc_o -add wave -noupdate -format Logic /tb_mips_top/mrdy_o -add wave -noupdate -format Literal /tb_mips_top/int -add wave -noupdate -divider {External components} -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpo1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi0 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/gpi1 -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/rx -add wave -noupdate -format Logic /tb_mips_top/tx -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/mem_area -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram_d -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/flash_d -add wave -noupdate -format Logic /tb_mips_top/flash_cs_n -add wave -noupdate -format Logic /tb_mips_top/flash_oe_n -add wave -noupdate -format Literal /tb_mips_top/flash_be_n -add wave -noupdate -format Logic /tb_mips_top/sram_cs_n -add wave -noupdate -format Literal /tb_mips_top/sram_wr_n -add wave -noupdate -format Logic /tb_mips_top/sram_oe_n -add wave -noupdate -format Literal /tb_mips_top/sram_be_n -add wave -noupdate -divider ALU -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu -add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_pipeline/sdu -add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/pc -add wave -noupdate -divider COP0 -add wave -noupdate -divider Pipestages -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/rst -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/inst_reg_dual/reg_mem -add wave -noupdate -divider I-Cache -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cpu_dout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_busy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/s -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_busy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cache_miss -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/tag_match -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/word_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/cache_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_icache/tag_index_reg -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/cpu_reg_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_icache/was_miss -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/cache_entry_out -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/request_count -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_icache/fill_count -add wave -noupdate -divider D-Cache -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/s -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_addr -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_din -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_dout -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_busy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_rd -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/tram_addr_wr -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tram_we -add wave -noupdate -format Literal -expand /tb_mips_top/uut/inst_biu/inst_dcache/cache_entry_out -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_busy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cache_hit -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_match -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/word_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/addr_windex_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cache_index_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_index_reg -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/fill_count -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/fill_count_rdy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/flush_count -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/flush_count_rdy -add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/request_count -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/request_count_rdy -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_reg_en -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/was_miss -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_hit_we -add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/instant_raw +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_reg +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_be_reg +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we_reg +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_data_ram_addr +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/ctrl_data_ram_we +add wave -noupdate -format Literal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_data_ram_we +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/cpu_we2 +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_addr_rd +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_addr_wr +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_din +add wave -noupdate -format Logic /tb_mips_top/uut/inst_biu/inst_dcache/tag_ram_we +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_tag +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_cache_index +add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_biu/inst_dcache/cpu_word_index TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2248160 ps} 0} +WaveRestoreCursors {{Cursor 1} {3452235915 ps} 0} configure wave -namecolwidth 188 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -336,4 +173,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {2141949 ps} {2449858 ps} +WaveRestoreZoom {417380225 ps} {3435174725 ps} diff --git a/projects/mips_sys/sim/tb_mips_sys.fdo b/projects/mips_sys/sim/tb_mips_sys.fdo index 2eea9b0..a040e2f 100644 --- a/projects/mips_sys/sim/tb_mips_sys.fdo +++ b/projects/mips_sys/sim/tb_mips_sys.fdo @@ -15,13 +15,11 @@ vcom -explicit -93 "../../../lib/SDRAM/ddr_sdr_v1_5/src/mt46v16m16.vhd" # RAMs vcom -explicit -93 "../../../lib/misc/dpram_2w2r.vhd" vcom -explicit -93 "../../../lib/misc/dpram_1w1r.vhd" -vcom -explicit -93 "../../../lib/misc/dpram_1w1r_dist.vhd" # FIFOS vcom -explicit -93 "../../../lib/FIFO/src/gray_counter.vhd" vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_ctrl.vhd" vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync.vhd" -vcom -explicit -93 "../../../lib/FIFO/src/fifo_sync_dist.vhd" vcom -explicit -93 "../../../lib/FIFO/src/fifo_async_ctrl.vhd" vcom -explicit -93 "../../../lib/FIFO/src/fifo_async.vhd"