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- added GHDL makefiles for cordic

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git-svn-id: http://moon:8086/svn/vhdl/trunk@1440 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2021-03-21 18:36:23 +00:00
parent 272d7f0f7d
commit f045dc1592
2 changed files with 69 additions and 0 deletions
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lib/radio/cordic/sim/Makefile.cordic_pipe_top
+34
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# -------------------------------------------------
# Global options
# -------------------------------------------------
LANG_STD := 93c
IEEE_STD := standard
WORK_DIR := work
WORK_LIB := work
# -------------------------------------------------
# Target options
# -------------------------------------------------
LIB_PATH := ../../../../lib
SRCS := $(LIB_PATH)/fixed/fixed_util_pkg.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
SRCS += ../src/cordic_pkg.vhd
SRCS += ../src/cordic_pipe_stage.vhd
SRCS += ../src/cordic_pipe_pre.vhd
SRCS += ../src/cordic_pipe_post.vhd
SRCS += ../src/cordic_pipe_top.vhd
SRCS += ../src/tb_cordic_pipe_top.vhd
# -------------------------------------------------
# Compile
TARGET := cordic_pipe_top
ENTITY := tb_cordic_pipe_top
WITH_GHW := y
RUN_TIME := 2000us
GHDL_OPTS := -P../../../../Common/sim/ieee_proposed/modelsim/build/ghdl/ieee_proposed
include ../../../../Common/make/ghdl.mk
# -------------------------------------------------
lib/radio/cordic/sim/Makefile.cordic_top
+35
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@@ -0,0 +1,35 @@
# -------------------------------------------------
# Global options
# -------------------------------------------------
LANG_STD := 93c
IEEE_STD := standard
WORK_DIR := work
WORK_LIB := work
# -------------------------------------------------
# Target options
# -------------------------------------------------
LIB_PATH := ../../../../lib
SRCS := $(LIB_PATH)/fixed/fixed_util_pkg.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993.vhd
SRCS += $(LIB_PATH)/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd
SRCS += ../src/cordic_pkg.vhd
SRCS += ../src/cordic_rom.vhd
SRCS += ../src/cordic_stage.vhd
SRCS += ../src/cordic_stage_pre.vhd
SRCS += ../src/cordic_stage_post.vhd
SRCS += ../src/cordic_top.vhd
SRCS += ../src/tb_cordic_top.vhd
# -------------------------------------------------
# Compile
TARGET := cordic_top
ENTITY := tb_cordic_top
WITH_GHW := y
RUN_TIME := 2000us
GHDL_OPTS := -P../../../../Common/sim/ieee_proposed/modelsim/build/ghdl/ieee_proposed
include ../../../../Common/make/ghdl.mk
# -------------------------------------------------