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- added BLIT command FIFO

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git-svn-id: http://moon:8086/svn/vhdl/trunk@960 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-05-06 21:52:44 +00:00
parent a2a1d6f5b9
commit f0093103fa
2 changed files with 438 additions and 336 deletions
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lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+19 -22
View File
@@ -463,12 +463,6 @@ VGA_CLK_GEN: process
ack_v(i) := '0';
end loop;
else
if blit_count_rst = '1' then
for i in 0 to 127 loop
-- ram_dst(i) <= X"DEADBEEF" & X"DEADBEEF";
ram_dst(i) <= (others => '-');
end loop;
end if;
if (CYC_I and STB_I) = '1' and rdy = '1' then
if WE_I = '0' then
if ADDR_I(30) = '1' then
@@ -490,6 +484,7 @@ VGA_CLK_GEN: process
ack_v := ack_v(10 downto 0) & '1';
else -- WE=1
ram_data := ram_dst(to_integer(ADDR_I(31 downto 3)));
ram_data := (others => '-');
if ADDR_I(2) = '0' then
if SEL_I = "11111111" then
ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I;
@@ -560,9 +555,9 @@ STIMULUS: process
STB_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
result := SDAT_I;
CYC_O <= '0';
end procedure reg_read;
@@ -572,15 +567,17 @@ STIMULUS: process
RST_O <= '0';
wait for 60*CLK_PERIOD;
reg_write(X"0000_0018", X"4000_0000"); -- set frontbuffer address
reg_write(X"0000_001C", X"4000_0000"); -- set backbuffer address
reg_write(X"0000_0020", X"0000_0002"); -- set BLIT source address 0
reg_write(X"0000_0028", X"0000_0002"); -- set BLIT source dimension 0
reg_write(X"0000_0030", X"0000_0002"); -- set BLIT source address 1
reg_write(X"0000_0038", X"0000_0002"); -- set BLIT source dimension 1
reg_write(X"0000_0050", X"0000_0002"); -- set BLIT destination address
reg_write(X"0000_0058", X"0000_0002"); -- set BLIT destination dimension
-- Enable master
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"0000_0002";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
reg_write(X"0000_0000", X"0000_0002");
-- Read status
CYC_O <= '1';
@@ -713,7 +710,7 @@ STIMULUS: process
for i in 0 to blit_size_array_t'length-1 loop
wait for 600*CLK_PERIOD;
-- wait for 600*CLK_PERIOD;
-------------------------------------------------
-- BLIT aligned => aligned test
@@ -755,7 +752,7 @@ STIMULUS: process
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
wait for 600*CLK_PERIOD;
-- wait for 600*CLK_PERIOD;
-------------------------------------------------
-- BLIT unaligned => aligned test
-------------------------------------------------
@@ -795,7 +792,7 @@ STIMULUS: process
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
wait for 600*CLK_PERIOD;
-- wait for 600*CLK_PERIOD;
-------------------------------------------------
-- BLIT aligned => unaligned test
@@ -836,7 +833,7 @@ STIMULUS: process
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
wait for 600*CLK_PERIOD;
-- wait for 600*CLK_PERIOD;
-------------------------------------------------
-- BLIT unaligned => unaligned test
-------------------------------------------------
@@ -876,7 +873,7 @@ STIMULUS: process
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
wait for 600*CLK_PERIOD;
-- wait for 600*CLK_PERIOD;
-------------------------------------------------
-- BLIT const => aligned test
-------------------------------------------------
@@ -918,7 +915,7 @@ STIMULUS: process
reg_read(X"0000_0000");
reg_write(X"0000_0000", result or X"0001_0100");
wait for 600*CLK_PERIOD;
-- wait for 600*CLK_PERIOD;
-------------------------------------------------
-- BLIT const => unaligned test
-------------------------------------------------
@@ -960,7 +957,7 @@ STIMULUS: process
reg_read(X"0000_0000");
reg_write(X"0000_0000", result or X"0001_0100");
wait for 600*CLK_PERIOD;
-- wait for 600*CLK_PERIOD;
end loop;
state <= IDLE;
lib/VGA_ctrl/src/vga_frontend64.vhd
+419 -314
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