diff --git a/lib/filter/sim/tb_fir_semi_parallel.wdo b/lib/filter/sim/tb_fir_semi_parallel.wdo index c85e95e..aba8fb1 100644 --- a/lib/filter/sim/tb_fir_semi_parallel.wdo +++ b/lib/filter/sim/tb_fir_semi_parallel.wdo @@ -27,24 +27,20 @@ add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/accu add wave -noupdate -format Literal -radix decimal -expand /tb_fir_semi_parallel/uut/y add wave -noupdate -divider {stage 1} add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/clk -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/xin add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/yin -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/hin add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/prod add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/x_out add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__0/inst_fir_stage/y_out add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__0/inst_delay_line/inst_dpram_1w1r/ram add wave -noupdate -divider {stage 2} add wave -noupdate -format Logic /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/clk -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/xin add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/yin -add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/hin add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/prod add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/x_out add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_stages__1/inst_fir_stage/y_out add wave -noupdate -format Literal -radix decimal /tb_fir_semi_parallel/uut/gen_delays__1/inst_delay_line/inst_dpram_1w1r/ram TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {486552931 ps} 0} {{Cursor 2} {14808343 ps} 0} {{Cursor 3} {148250000 ps} 0} +WaveRestoreCursors {{Cursor 1} {486552931 ps} 0} {{Cursor 2} {49902384 ps} 0} {{Cursor 3} {148250000 ps} 0} configure wave -namecolwidth 150 configure wave -valuecolwidth 100 configure wave -justifyvalue left @@ -58,4 +54,4 @@ configure wave -gridperiod 100 configure wave -griddelta 40 configure wave -timeline 1 update -WaveRestoreZoom {14757354 ps} {14943057 ps} +WaveRestoreZoom {0 ps} {52500 ns} diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd index 8b33fd2..68493c1 100644 --- a/lib/filter/src/fir_semi_parallel.vhd +++ b/lib/filter/src/fir_semi_parallel.vhd @@ -40,7 +40,7 @@ Generic ( ntaps_per_stage : integer := 32; nstages : integer := 2; - mul_latency : integer := 1; + pipe_latency : integer := 4; nbits_in : integer := 12; nbits_in_frac : integer := 11; nbits_stages : integer := 13; @@ -68,9 +68,6 @@ architecture Behavioral of fir_semi_parallel is ------------------------------------------------------------------------------- constant coef_addr_nbits : natural := NextExpBaseTwo(ntaps_per_stage) + NextExpBaseTwo(nstages); - constant input_latency : natural := 1; - constant coef_latency : natural := 1; - constant pipe_latency : natural := mul_latency + 1; subtype coef_t is sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); subtype count_t is natural range 0 to ntaps_per_stage-1; @@ -93,7 +90,7 @@ architecture Behavioral of fir_semi_parallel is SIGNAL act : std_logic := '0'; SIGNAL start_r : std_logic := '0'; signal accu_load : std_logic; - signal accu_ld_pipe : unsigned(nstages+input_latency+coef_latency+pipe_latency-2 downto 0); + signal accu_ld_pipe : unsigned(nstages+pipe_latency-1 downto 0); signal din_r : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); signal coef_we : unsigned(nstages-1 downto 0); @@ -244,8 +241,6 @@ gen_stages: nbits_in_frac => nbits_stages_frac, nbits_out => nbits_stages, nbits_out_frac => nbits_stages_frac, - input_latency => input_latency, - coef_latency => coef_latency, pipe_latency => pipe_latency ) PORT MAP diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd index e34411b..95d6aa2 100644 --- a/lib/filter/src/fir_stage_sys.vhd +++ b/lib/filter/src/fir_stage_sys.vhd @@ -42,9 +42,7 @@ Generic nbits_in_frac : integer := 12; nbits_out : integer := 12; nbits_out_frac : integer := 12; - input_latency : integer := 1; - coef_latency : integer := 1; - pipe_latency : integer := 2 + pipe_latency : integer := 4 ); Port ( @@ -60,77 +58,37 @@ end fir_stage_sys; architecture Behavioral of fir_stage_sys is -constant min_input_lat : integer := 1; -constant min_pipe_lat : integer := 2; -constant mult_latency : integer := pipe_latency-1; +constant min_pipe_lat : integer := 4; subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); -type input_pipe_t is array (0 to input_latency) of in_t; -type coef_pipe_t is array (0 to coef_latency) of in_t; -type mult_pipe_t is array (0 to mult_latency) of out_t; +type input_pipe_t is array (min_pipe_lat-2 downto 0) of in_t; +type coef_pipe_t is array (min_pipe_lat-2 downto 0) of in_t; -signal h_pipe : coef_pipe_t; -signal x_pipe : input_pipe_t; -signal mult_pipe : mult_pipe_t; -signal xin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); signal yin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); -signal hin : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); signal prod : sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); ------------------------------------------------------------ begin - assert input_latency >= min_input_lat report "Input latency must be greater than " & natural'image(min_input_lat-1) & "!" severity failure; - assert coef_latency >= min_input_lat report "Coeff. latency must be greater than " & natural'image(min_input_lat-1) & "!" severity failure; assert pipe_latency >= min_pipe_lat report "Pipe latency must be greater than " & natural'image(min_pipe_lat-1) & "!" severity failure; - prod <= mult_pipe(mult_latency); yin <= resize(y_in, yin); - hin <= h_pipe(coef_latency); - xin <= x_pipe(input_latency); - x_out <= resize(xin, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac)); ------------------------------------------------------------ - proc_xin: process(clk, x_in, x_pipe(0)) + proc_pipe_reg: process(clk) + variable h_pipe : coef_pipe_t; + variable x_pipe : input_pipe_t; begin - x_pipe(0) <= resize(x_in, x_pipe(0)); if rising_edge(clk) then if ce = '1' then - for i in 1 to input_latency loop - x_pipe(i) <= x_pipe(i-1); - end loop; - end if; - end if; - - end process; - ------------------------------------------------------------- - proc_hin: process(clk, h_in, h_pipe(0)) - begin - h_pipe(0) <= resize(h_in, h_pipe(0)); - if rising_edge(clk) then - if ce = '1' then - for i in 1 to coef_latency loop - h_pipe(i) <= h_pipe(i-1); - end loop; - end if; - end if; - - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk, xin, hin, mult_pipe(0)) - begin - mult_pipe(0) <= resize(xin * hin, mult_pipe(0), fixed_wrap, fixed_truncate); - if rising_edge(clk) then - if ce = '1' then - for i in 1 to mult_latency loop - mult_pipe(i) <= mult_pipe(i-1); - end loop; + x_pipe := x_pipe(x_pipe'left-1 downto 0) & resize(x_in, x_pipe(0)); + h_pipe := h_pipe(h_pipe'left-1 downto 0) & resize(h_in, h_pipe(0)); + prod <= resize(x_pipe(x_pipe'left) * h_pipe(h_pipe'left), prod, fixed_wrap, fixed_truncate); end if; + x_out <= resize(x_pipe(x_pipe'left), shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac)); end if; end process; diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd index b0ec1b7..e540caf 100644 --- a/lib/filter/src/tb_fir_semi_parallel.vhd +++ b/lib/filter/src/tb_fir_semi_parallel.vhd @@ -48,7 +48,7 @@ ARCHITECTURE behavior OF tb_fir_semi_parallel IS --Constants constant PERIOD : time := 10 ns; constant nsamples : integer := 32; - constant M : integer := 2; + constant M : integer := 1; --Inputs SIGNAL clk : std_logic := '0'; @@ -141,7 +141,7 @@ BEGIN ( ntaps_per_stage => ntaps_per_stage, nstages => nstages, - mul_latency => 2, + pipe_latency => 4, nbits_in => nbits_in, nbits_in_frac => nbits_in_frac, nbits_stages => nbits_stages, diff --git a/lib/radio/ddc/src/ddc.vhd b/lib/radio/ddc/src/ddc.vhd index f24cad1..a70b50b 100644 --- a/lib/radio/ddc/src/ddc.vhd +++ b/lib/radio/ddc/src/ddc.vhd @@ -139,7 +139,7 @@ ARCHITECTURE behavior OF ddc IS ( ntaps_per_stage : integer; nstages : integer; - mul_latency : integer; + pipe_latency : integer; nbits_in : integer; nbits_in_frac : integer; nbits_stages : integer; @@ -172,7 +172,7 @@ ARCHITECTURE behavior OF ddc IS constant cic_nbits_out : integer := nbits_out; constant cic_nbits_out_frac : integer := nbits_out_frac; - constant cfir_mul_latency : integer := 5; + constant cfir_pipe_latency : integer := 5; constant cfir_ntaps : integer := 63; constant cfir_nstages : integer := 2; constant cfir_nbits_in : integer := cic_nbits_out; @@ -324,7 +324,7 @@ BEGIN ( ntaps_per_stage => cfir_ntaps_per_stage, nstages => cfir_nstages, - mul_latency => cfir_mul_latency, + pipe_latency => cfir_pipe_latency, nbits_in => cfir_nbits_in, nbits_in_frac => cfir_nbits_in_frac, nbits_stages => cfir_nbits_stages, @@ -352,7 +352,7 @@ BEGIN ( ntaps_per_stage => cfir_ntaps_per_stage, nstages => cfir_nstages, - mul_latency => cfir_mul_latency, + pipe_latency => cfir_pipe_latency, nbits_in => cfir_nbits_in, nbits_in_frac => cfir_nbits_in_frac, nbits_stages => cfir_nbits_stages,