From ee627567f24323946fd53dd52178bb9cda9e1497 Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 24 Oct 2015 08:39:35 +0000 Subject: [PATCH] - fixed fir_stage_sys-based filters git-svn-id: http://moon:8086/svn/vhdl/trunk@1320 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/filter/sim/tb_fir_iterative.fdo | 5 +- lib/filter/sim/tb_fir_iterative.wdo | 286 ++++++++++++------------ lib/filter/src/fir_iterative.vhd | 18 +- lib/filter/src/fir_semi_parallel.vhd | 6 +- lib/filter/src/fir_stage_sys.vhd | 7 +- lib/filter/src/tb_fir_iterative.vhd | 72 +++--- lib/filter/src/tb_fir_semi_parallel.vhd | 2 +- 7 files changed, 199 insertions(+), 197 deletions(-) diff --git a/lib/filter/sim/tb_fir_iterative.fdo b/lib/filter/sim/tb_fir_iterative.fdo index 5260669..3ba5056 100644 --- a/lib/filter/sim/tb_fir_iterative.fdo +++ b/lib/filter/sim/tb_fir_iterative.fdo @@ -1,5 +1,3 @@ -vmap ieee_proposed ../../../Common/sim/ieee_proposed - vlib work vcom -explicit -93 "../../../lib/misc/utils_pkg.vhd" vcom -explicit -93 "../../../lib/fixed/fixed_util_pkg.vhd" @@ -7,6 +5,7 @@ vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" vcom -explicit -93 "../src/filter_pkg.vhd" vcom -explicit -93 "../src/fir_pkg.vhd" +vcom -explicit -93 "../src/fir_stage_sys.vhd" vcom -explicit -93 "../src/fir_stage.vhd" vcom -explicit -93 "../src/fir_iterative.vhd" vcom -explicit -93 "../src/tb_fir_iterative.vhd" @@ -15,4 +14,4 @@ do {tb_fir_iterative.wdo} view wave view structure view signals -run 20us +run 6us diff --git a/lib/filter/sim/tb_fir_iterative.wdo b/lib/filter/sim/tb_fir_iterative.wdo index cb193af..8a949b2 100644 --- a/lib/filter/sim/tb_fir_iterative.wdo +++ b/lib/filter/sim/tb_fir_iterative.wdo @@ -1,144 +1,142 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Literal /tb_fir_iterative/xi -add wave -noupdate -format Literal /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem -add wave -noupdate -divider {Xmem Dual} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Logic /tb_fir_iterative/y_valid -add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -divider {FIR Stage} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Literal /tb_fir_iterative/xi -add wave -noupdate -format Literal /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem -add wave -noupdate -divider {Xmem Dual} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Logic /tb_fir_iterative/y_valid -add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -divider {FIR Stage} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {5100000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {42 us} +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo +add wave -noupdate -format Literal /tb_fir_iterative/coeffs +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt +add wave -noupdate -format Literal /tb_fir_iterative/xi +add wave -noupdate -format Literal /tb_fir_iterative/yo +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem +add wave -noupdate -divider {Xmem Dual} +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo +add wave -noupdate -format Literal /tb_fir_iterative/coeffs +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt +add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi +add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid +add wave -noupdate -format Logic /tb_fir_iterative/y_valid +add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem +add wave -noupdate -divider {FIR Stage} +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo +add wave -noupdate -format Literal /tb_fir_iterative/coeffs +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt +add wave -noupdate -format Literal /tb_fir_iterative/xi +add wave -noupdate -format Literal /tb_fir_iterative/yo +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_fir_iterative/ymem +add wave -noupdate -format Literal -radix hexadecimal -expand /tb_fir_iterative/uut_fir_iterative/xmem +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_stage_vld +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_stage_vld +add wave -noupdate -divider {Xmem Dual} +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo +add wave -noupdate -format Literal /tb_fir_iterative/coeffs +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt +add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi +add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid +add wave -noupdate -format Logic /tb_fir_iterative/y_valid +add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem +add wave -noupdate -divider {FIR Stage} +add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out +add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out +add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {2700000 ps} 0} {{Cursor 2} {0 ps} 0} {{Cursor 3} {148250000 ps} 0} +configure wave -namecolwidth 140 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 1 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +update +WaveRestoreZoom {0 ps} {6300 ns} diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd index bc1dba5..0a9829b 100644 --- a/lib/filter/src/fir_iterative.vhd +++ b/lib/filter/src/fir_iterative.vhd @@ -75,7 +75,7 @@ architecture Behavioral of fir_iterative is type state_t is (init, idle, start, proc, p1, p2, output); signal s, sn : state_t; - signal x_stage, xo, y_stage : stage_t; + signal x_stage, xo, y_stage, y_stage_in : stage_t; signal stage_en, cnt_en, new_round : std_logic; subtype tap_cnt_t is natural range 0 to ntaps-1; @@ -93,11 +93,15 @@ architecture Behavioral of fir_iterative is signal y_out_reg : out_t; signal y_reg_valid : std_logic; + signal x_stage_vld : std_logic := '1'; + signal y_stage_vld : std_logic; + ------------------------------------------------------------------------------- begin h_addr_out <= h_addr; x_stage <= resize(xmem_dout, x_stage, fixed_wrap, fixed_truncate); + y_stage_in <= to_sfixed(0, y_stage_in) when new_round = '1' else y_stage; ---------------------------------------- process (clk) @@ -301,19 +305,19 @@ begin nbits_in_frac => nbits_stages_frac, nbits_out => nbits_stages, nbits_out_frac => nbits_stages_frac, - input_latency => 1, - coef_latency => 1, - pipe_latency => 3 + pipe_latency => 2 ) PORT MAP ( - rst => fir_stage_clr, + rst => srst, + ce => x_stage_vld, clk => clk, x_in => x_stage, - y_in => y_stage, + y_in => y_stage_in, h_in => h_din, x_out => xo, - y_out => y_stage + y_out => y_stage, + vld_out => y_stage_vld ); ---------------------------------------- diff --git a/lib/filter/src/fir_semi_parallel.vhd b/lib/filter/src/fir_semi_parallel.vhd index 948a947..f2e5dce 100644 --- a/lib/filter/src/fir_semi_parallel.vhd +++ b/lib/filter/src/fir_semi_parallel.vhd @@ -40,7 +40,7 @@ Generic ( ntaps_per_stage : integer := 32; nstages : integer := 2; - pipe_latency : integer := 4; + pipe_latency : integer := 2; nbits_in : integer := 12; nbits_in_frac : integer := 11; nbits_stages : integer := 13; @@ -239,11 +239,11 @@ gen_stages: nbits_in => nbits_stages, nbits_in_frac => nbits_stages_frac, nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - pipe_latency => pipe_latency + nbits_out_frac => nbits_stages_frac ) PORT MAP ( + rst => rst, clk => clk, ce => en_array(i), x_in => x(i+1), diff --git a/lib/filter/src/fir_stage_sys.vhd b/lib/filter/src/fir_stage_sys.vhd index 6021526..7d636e9 100644 --- a/lib/filter/src/fir_stage_sys.vhd +++ b/lib/filter/src/fir_stage_sys.vhd @@ -41,7 +41,8 @@ Generic nbits_in : integer := 12; nbits_in_frac : integer := 12; nbits_out : integer := 12; - nbits_out_frac : integer := 12 + nbits_out_frac : integer := 12; + pipe_latency : integer := 2 ); Port ( @@ -59,8 +60,6 @@ end fir_stage_sys; architecture Behavioral of fir_stage_sys is -constant min_pipe_lat : integer := 4; - subtype in_t is sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); subtype out_t is sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); @@ -73,6 +72,8 @@ signal vld : unsigned(1 downto 0); ------------------------------------------------------------ begin + assert pipe_latency = 2 report "Pipe latency must be two !" severity failure; + yin <= resize(y_in, yin); vld_out <= vld(vld'left); y_out <= y_reg; diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd index 76b6024..535c88c 100644 --- a/lib/filter/src/tb_fir_iterative.vhd +++ b/lib/filter/src/tb_fir_iterative.vhd @@ -31,11 +31,11 @@ use work.PCK_FIO.all; ENTITY tb_fir_iterative IS Generic ( ntaps : integer := 11; - nbits_in : integer := 15; + nbits_in : integer := 16; nbits_in_frac : integer := 15; - nbits_stages : integer := 15; + nbits_stages : integer := 16; nbits_stages_frac : integer := 15; - nbits_out : integer := 15; + nbits_out : integer := 16; nbits_out_frac : integer := 15; fir_mode : fir_iterative_mode_t := symmetric; rounding : boolean := true; @@ -96,43 +96,43 @@ ARCHITECTURE behavior OF tb_fir_iterative IS SIGNAL fileout_enable : std_logic := '1'; -- Test coefficients --- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, 10, 0.999)(0 to ntaps_addr(ntaps, fir_mode)-1); - SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1); + SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, (ntaps-1)/2, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1); +-- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1); -- SIGNAL coeffs : real_array_t(0 to ntaps-1) := FilterTestCoef(ntaps); signal x_input : real_array_t(0 to nsamples-1) := ( - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, + 0.01, + 0.02, + 0.03, + 0.04, + 0.05, + 0.06, + 0.07, + 0.08, + 0.09, + 0.10, + 0.11, + 0.12, + 0.13, + 0.14, + 0.15, 0.9999, - -0.0000, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0 + -0.9999, + -0.15, + -0.14, + -0.13, + -0.12, + -0.11, + -0.10, + -0.09, + -0.08, + -0.07, + -0.06, + -0.05, + -0.04, + -0.03, + -0.02, + -0.01 ); type ymem_t is array (0 to nsamples-1) of sfixed(shi(nbits_out, nbits_out_frac) downto slo(nbits_out, nbits_out_frac)); diff --git a/lib/filter/src/tb_fir_semi_parallel.vhd b/lib/filter/src/tb_fir_semi_parallel.vhd index 33da80f..e319e0c 100644 --- a/lib/filter/src/tb_fir_semi_parallel.vhd +++ b/lib/filter/src/tb_fir_semi_parallel.vhd @@ -141,7 +141,7 @@ BEGIN ( ntaps_per_stage => ntaps_per_stage, nstages => nstages, - pipe_latency => 5, + pipe_latency => 2, nbits_in => nbits_in, nbits_in_frac => nbits_in_frac, nbits_stages => nbits_stages,