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[spi_flash_wb.vhd]

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- removed register interface
- first write data, then command

git-svn-id: http://moon:8086/svn/vhdl/trunk@1302 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2015-06-13 13:52:35 +00:00
parent 2b459949bb
commit ed3a943777
1 changed files with 25 additions and 87 deletions
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lib/spi/src/spi_flash_wb.vhd
+24 -86
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@@ -60,29 +60,30 @@ ARCHITECTURE rtl OF spi_flash_wb IS
signal tag_reg : unsigned(FLASH_ADDR_BITS-1 downto CACHE_ADDR_BITS); signal tag_reg : unsigned(FLASH_ADDR_BITS-1 downto CACHE_ADDR_BITS);
signal tag_valid : std_logic; signal tag_valid : std_logic;
signal tag_match : std_logic; signal tag_match : std_logic;
signal register_access : std_logic;
signal state : state_t; signal state : state_t;
signal state_next : state_t; signal state_next : state_t;
signal SRDY_mem : std_logic; signal SRDY_mem : std_logic;
signal ACK_mem : std_logic; signal ACK_mem : std_logic;
signal ACK_reg : std_logic;
signal DAT_mem : unsigned(31 downto 0); signal DAT_mem : unsigned(31 downto 0);
signal DAT_reg : unsigned(31 downto 0); signal data_vld : std_logic;
begin begin
mst_dout_re <= '1'; mst_ctrl.clk_div <= to_unsigned(0, 8);
mst_ctrl.cpol <= '0';
mst_ctrl.cpha <= '0';
mst_ctrl.msb_first <= '1';
mst_dout_re <= mst_dout_vld;
mst_shift_en <= not spi_hold; mst_shift_en <= not spi_hold;
mst_cmd <= to_cmd(32 + 8 * 2**CACHE_ADDR_BITS, 32); mst_cmd <= to_cmd(32 + 8 * 2**CACHE_ADDR_BITS, 32);
mst_din <= X"03" & ADDR_I(FLASH_ADDR_BITS-1 downto CACHE_ADDR_BITS) & (CACHE_ADDR_BITS-1 downto 0 => '0'); mst_din <= X"03" & ADDR_I(FLASH_ADDR_BITS-1 downto CACHE_ADDR_BITS) & (CACHE_ADDR_BITS-1 downto 0 => '0');
INT_O <= '0'; INT_O <= '0';
ACK_O <= ACK_mem or ACK_reg; ACK_O <= ACK_mem;
DAT_O <= DAT_mem; DAT_O <= DAT_mem;
SRDY_O <= SRDY_mem; SRDY_O <= SRDY_mem;
tag_match <= tag_valid when ADDR_I(tag_reg'range) = tag_reg else '0';
tag_match <= tag_valid when ADDR_I(tag_reg'range) = tag_reg else '0'; tag_match <= tag_valid when ADDR_I(tag_reg'range) = tag_reg else '0';
data_ram_addr_rd <= word_addr_reg when tag_we = '1' else ADDR_I(CACHE_ADDR_BITS-1 downto 2); data_ram_addr_rd <= word_addr_reg when tag_we = '1' else ADDR_I(CACHE_ADDR_BITS-1 downto 2);
@@ -139,7 +140,7 @@ word_addr_register:
word_addr_register: word_addr_register:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if (CYC_I and STB_I and SRDY_mem and not WE_I) = '1' then if (CYC_I and STB_I and SRDY_mem and not WE_I) = '1' then
word_addr_reg <= ADDR_I(CACHE_ADDR_BITS-1 downto 2); word_addr_reg <= ADDR_I(CACHE_ADDR_BITS-1 downto 2);
end if; end if;
@@ -149,7 +150,7 @@ read_cache_ack:
read_cache_ack: read_cache_ack:
process(CLK_I) process(CLK_I)
begin begin
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
ACK_mem <= data_vld; ACK_mem <= data_vld;
end if; end if;
end process; end process;
@@ -191,13 +192,15 @@ begin
end if; end if;
end process; end process;
proc_fsm: proc_fsm:
process(state, CYC_I, STB_I, WE_I, tag_match, mst_cmd_rdy, mst_din_rdy, mst_status) process(state, CYC_I, STB_I, WE_I, tag_match, mst_cmd_rdy, mst_din_rdy, mst_status)
begin begin
state_next <= state; state_next <= state;
SRDY_mem <= '0'; SRDY_mem <= '0';
mst_cmd_vld <= '0'; mst_cmd_vld <= '0';
mst_din_vld <= '0'; mst_din_vld <= '0';
tag_we <= '0';
data_vld <= '0';
case state is case state is
@@ -205,21 +208,23 @@ begin
state_next <= idle; state_next <= idle;
when idle => when idle =>
SRDY_mem <= CYC_I; SRDY_mem <= CYC_I;
if (CYC_I and STB_I and not WE_I) = '1' then if (CYC_I and STB_I and not WE_I) = '1' then
if tag_match = '0' then if tag_match = '0' then
state_next <= spi_data;
else
data_vld <= '1'; data_vld <= '1';
end if; end if;
end if; end if;
when spi_cmd =>
mst_cmd_vld <= '1';
if mst_cmd_rdy = '1' then
state_next <= spi_data;
end if;
when spi_data => when spi_data =>
mst_din_vld <= '1'; mst_din_vld <= '1';
if mst_din_rdy = '1' then
state_next <= spi_cmd;
end if;
when spi_cmd =>
mst_cmd_vld <= '1';
if mst_cmd_rdy = '1' then if mst_cmd_rdy = '1' then
state_next <= cache_fill_start; state_next <= cache_fill_start;
end if; end if;
@@ -235,6 +240,7 @@ begin
end if; end if;
when finish => when finish =>
tag_we <= '1';
data_vld <= '1'; data_vld <= '1';
state_next <= idle; state_next <= idle;
@@ -243,72 +249,4 @@ begin
end case; end case;
end process; end process;
------------------------------------------------------------------
registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if RST_I = '1' then
mst_ctrl.clk_div <= to_unsigned(0, 8);
mst_ctrl.cpol <= '0';
mst_ctrl.cpha <= '0';
mst_ctrl.msb_first <= '1';
elsif (CYC_I and STB_I and register_access and WE_I) = '1' then
case ADDR_I(5 downto 2) is
when "0000" =>
when "0001" =>
when "0010" =>
when "0011" =>
when "0100" =>
mst_ctrl.clk_div <= DAT_I(7 downto 0);
mst_ctrl.cpol <= DAT_I(8);
mst_ctrl.cpha <= DAT_I(9);
mst_ctrl.msb_first <= DAT_I(10);
when others => null;
end case;
end if;
end if;
end process;
registers_read:
process(CLK_I)
begin
if rising_edge(CLK_I) then
ACK_reg <= '0';
if (CYC_I and STB_I and register_access) = '1' then
ACK_reg <= not WE_I;
DAT_reg <= (others => '0');
case ADDR_I(5 downto 2) is
when "0000" =>
DAT_reg(2 downto 0) <= mst_dout_vld & mst_din_rdy & mst_cmd_rdy;
DAT_reg(15 downto 8) <= spi_hold & mst_status.xfer_busy & mst_status.read_fifo_empty & mst_status.read_fifo_full & mst_status.write_fifo_empty & mst_status.write_fifo_full & mst_status.cmd_fifo_empty & mst_status.cmd_fifo_full;
when "0001" =>
DAT_reg <= mst_cmd.xfer_size;
when "0010" =>
DAT_reg <= mst_cmd.data_size;
when "0011" =>
DAT_reg <= mst_dout;
when "0100" =>
DAT_reg(7 downto 0) <= mst_ctrl.clk_div;
DAT_reg(8) <= mst_ctrl.cpol;
DAT_reg(9) <= mst_ctrl.cpha;
DAT_reg(10) <= mst_ctrl.msb_first;
when others => null;
end case;
end if;
end if;
end process;