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- operate UART2 and UART1 in parallel for monitoring

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git-svn-id: http://moon:8086/svn/vhdl/trunk@539 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-10-27 21:49:40 +00:00
parent 5ecfef0595
commit ecb22dfeee
1 changed files with 7 additions and 3 deletions
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projects/mips_sys/src/mips_sys.vhd
+7 -3
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@@ -320,6 +320,8 @@ ARCHITECTURE behavior OF mips_sys IS
signal int_timer : std_logic;
signal int_uart0 : std_logic;
signal int_uart1 : std_logic;
signal uart1_tx : std_logic;
signal uart1_rx : std_logic;
signal locked : std_logic;
signal usb_addr : unsigned(31 downto 0);
signal flash_addr : unsigned(31 downto 0);
@@ -461,7 +463,9 @@ BEGIN
SEL_I_sdram <= "0000" & SEL_O;
sys_flash_ac97_rstn <= ac97_rstn and flash_rstn;
sys_uart2_tx <= sys_uart2_rx;
sys_uart1_tx <= uart1_tx;
sys_uart2_tx <= uart1_tx;
uart1_rx <= sys_uart1_rx and sys_uart2_rx;
sys_uart3_tx <= sys_uart3_rx;
---------------------------------------------------------------
@@ -779,8 +783,8 @@ inst_uart_wb_1 : uart_wb
DAT_I => MDAT_O,
DAT_O => SDAT_O_uart1,
INT_O => int_uart1,
ser_rx => sys_uart1_rx,
ser_tx => sys_uart1_tx
ser_rx => uart1_rx,
ser_tx => uart1_tx
);