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- added procedures for register R/W

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git-svn-id: http://moon:8086/svn/vhdl/trunk@916 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-05-16 12:24:07 +00:00
parent 26a0a30fdc
commit ec301f5710
1 changed files with 215 additions and 480 deletions
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lib/VGA_ctrl/src/tb_vga_frontend64.vhd
+215 -480
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@@ -79,6 +79,11 @@ ARCHITECTURE behavior OF tb_vga_frontend64 IS
signal vga_vsync : std_logic; signal vga_vsync : std_logic;
signal vga_en : std_logic; signal vga_en : std_logic;
type blit_size_array_t is array (0 to 6) of natural;
constant blit_size_x : blit_size_array_t := (32, 31, 32, 31, 1, 32, 1);
constant blit_size_y : blit_size_array_t := (32, 32, 31, 31, 32, 1, 1);
BEGIN BEGIN
inst_vga_frontend64 : entity work.vga_frontend64 inst_vga_frontend64 : entity work.vga_frontend64
@@ -208,6 +213,39 @@ VGA_CLK_GEN: process
-- Master -- Master
STIMULUS: process STIMULUS: process
variable result : unsigned(31 downto 0);
procedure reg_write(reg, val : unsigned) is
begin
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
WE_O <= '1';
ADDR_O <= reg;
SDAT_O <= val;
STB_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
end procedure reg_write;
procedure reg_read(reg : unsigned) is
begin
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
WE_O <= '0';
ADDR_O <= reg;
STB_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
result := SDAT_I;
end procedure reg_read;
begin begin
wait for 6*CLK_PERIOD; wait for 6*CLK_PERIOD;
@@ -353,524 +391,221 @@ STIMULUS: process
wait for 60000*CLK_PERIOD; wait for 60000*CLK_PERIOD;
for i in 0 to 99 loop for i in 0 to blit_size_array_t'length-1 loop
while(true) loop -------------------------------------------------
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit;
end if;
end loop;
-- BLIT aligned => aligned test -- BLIT aligned => aligned test
-- Read status -------------------------------------------------
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= const_color;
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= (read_reg and not X"0001_0000") or X"0000_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
while(true) loop while(true) loop
-- read blit request reg_read(X"0000_0000");
CYC_O <= '1'; if result(8) = '0' then
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit; exit;
end if; end if;
end loop; end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0000");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0000");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-------------------------------------------------
-- BLIT unaligned => aligned test -- BLIT unaligned => aligned test
-- Read status -------------------------------------------------
CYC_O <= '1'; while(true) loop
wait until rising_edge(CLK_O) and SRDY_I = '1'; reg_read(X"0000_0000");
STB_O <= '1'; if result(8) = '0' then
WE_O <= '0'; exit;
ADDR_O <= X"0000_0000"; end if;
wait until rising_edge(CLK_O) and SRDY_I = '1'; end loop;
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address -- set source start address
CYC_O <= '1'; reg_write(X"0000_0020", X"4100_0004");
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0004";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x -- set src dim-x
CYC_O <= '1'; reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address -- set destination start address
CYC_O <= '1'; reg_write(X"0000_0050", X"4200_0000");
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color -- set constant color
CYC_O <= '1'; reg_write(X"0000_0054", const_color);
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= const_color;
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x -- set dst dim-x
CYC_O <= '1'; reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx -- set nx
CYC_O <= '1'; reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny -- set ny
CYC_O <= '1'; reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request -- set blit request
CYC_O <= '1'; reg_read(X"0000_0000");
wait until rising_edge(CLK_O) and SRDY_I = '1'; reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
STB_O <= '1';
WE_O <= '1';
SDAT_O <= (read_reg and not X"0001_0000") or X"0000_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
while(true) loop -------------------------------------------------
-- read blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit;
end if;
end loop;
-- BLIT aligned => unaligned test -- BLIT aligned => unaligned test
-- Read status -------------------------------------------------
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0004";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= const_color;
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= (read_reg and not X"0001_0000") or X"0000_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
while(true) loop while(true) loop
-- read blit request reg_read(X"0000_0000");
CYC_O <= '1'; if result(8) = '0' then
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit; exit;
end if; end if;
end loop; end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0000");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0004");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-------------------------------------------------
-- BLIT unaligned => unaligned test
-------------------------------------------------
while(true) loop
reg_read(X"0000_0000");
if result(8) = '0' then
exit;
end if;
end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0004");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0004");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100");
-------------------------------------------------
-- BLIT const => aligned test -- BLIT const => aligned test
-- Read status -------------------------------------------------
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0000";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= const_color;
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= read_reg or X"0001_0100";
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
while(true) loop while(true) loop
-- read blit request reg_read(X"0000_0000");
CYC_O <= '1'; if result(8) = '0' then
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
CYC_O <= '0';
WE_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
wait until rising_edge(CLK_O);
if read_reg(8) = '0' then
exit; exit;
end if; end if;
end loop; end loop;
-- BLIT const => unaligned test
-- Read status
CYC_O <= '1';
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '0';
ADDR_O <= X"0000_0000";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
wait until rising_edge(CLK_O) and ACK_I = '1';
-- set source start address -- set source start address
CYC_O <= '1'; reg_write(X"0000_0020", X"4100_0000");
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4100_0000";
ADDR_O <= X"0000_0020";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set src dim-x -- set src dim-x
CYC_O <= '1'; reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0028";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set destination start address -- set destination start address
CYC_O <= '1'; reg_write(X"0000_0050", X"4200_0000");
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= X"4200_0004";
ADDR_O <= X"0000_0050";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set constant color -- set constant color
CYC_O <= '1'; reg_write(X"0000_0054", const_color);
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= const_color;
ADDR_O <= X"0000_0054";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set dst dim-x -- set dst dim-x
CYC_O <= '1'; reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(4*tsvga.ts_h.ncyc_scan, 32);
ADDR_O <= X"0000_0058";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set nx -- set nx
CYC_O <= '1'; reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0060";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set ny -- set ny
CYC_O <= '1'; reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '1';
WE_O <= '1';
SDAT_O <= to_unsigned(256-1, 32);
ADDR_O <= X"0000_0064";
wait until rising_edge(CLK_O) and SRDY_I = '1';
STB_O <= '0';
-- set blit request -- set blit request
CYC_O <= '1'; reg_read(X"0000_0000");
wait until rising_edge(CLK_O) and SRDY_I = '1'; reg_write(X"0000_0000", result or X"0001_0100");
STB_O <= '1';
WE_O <= '1'; -------------------------------------------------
SDAT_O <= read_reg or X"0001_0100"; -- BLIT const => unaligned test
ADDR_O <= X"0000_0000"; -------------------------------------------------
wait until rising_edge(CLK_O) and SRDY_I = '1'; while(true) loop
STB_O <= '0'; reg_read(X"0000_0000");
CYC_O <= '0'; if result(8) = '0' then
WE_O <= '0'; exit;
end if;
end loop;
-- set source start address
reg_write(X"0000_0020", X"4100_0000");
-- set src dim-x
reg_write(X"0000_0028", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set destination start address
reg_write(X"0000_0050", X"4200_0004");
-- set constant color
reg_write(X"0000_0054", const_color);
-- set dst dim-x
reg_write(X"0000_0058", to_unsigned(4*tsvga.ts_h.ncyc_scan, 32));
-- set nx
reg_write(X"0000_0060", to_unsigned(blit_size_x(i)-1, 32));
-- set ny
reg_write(X"0000_0064", to_unsigned(blit_size_y(i)-1, 32));
-- set blit request
reg_read(X"0000_0000");
reg_write(X"0000_0000", result or X"0001_0100");
wait for 60000*CLK_PERIOD; wait for 60000*CLK_PERIOD;
const_color <= const_color + X"1111_1111"; const_color <= const_color + X"1111_1111";