- added

git-svn-id: http://moon:8086/svn/vhdl/trunk@1329 cc03376c-175c-47c8-b038-4cd826a8556b

lib/fixed_ja/eval_fixed_ja.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    00:28:57 07/10/2006 
+-- Design Name: 
+-- Module Name:    adder_registered - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+use IEEE.MATH_REAL.ALL;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+use work.fixed_ja.all;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eval_fixed_ja is
+	Generic (
+	        nbits : integer := 32;
+	        nbits_int : integer := 2);
+end eval_fixed_ja;
+
+architecture Behavioral of eval_fixed_ja is
+---------------------------------------------------------------------
+
+type my_range is range 0 downto -10;
+
+begin
+
+process
+constant c1 : ufixed_t (0 downto -10) := "11111111000";
+constant c2 : ufixed_t := to_ufixed(3.141592654, nbits, 4);
+constant c3 : ufixed_t := to_ufixed(1.0/3.141592654, nbits, 1);
+variable t1 : ufixed_t (uproto(8,1)'range);
+variable L : line;
+
+variable slv : string (15 downto 1) := (others => '-');
+constant jens : string (10 downto 7) := "JENS";
+
+
+begin
+
+
+--  slv := (1 => '1', 2 => 'J', jens'range => jens(jens'range), others => '1');
+  
+  slv(jens'range) := "Jens";
+  slv(jens'range) := jens;
+  
+  print_info(c2, "c2");
+  print_info(c3, "c3");
+  
+  t1 := to_ufixed(c1, t1, round_to_zero, saturate);
+  print_info(c1, "c1");
+  print_info(t1, "t1");
+  
+  t1 := to_ufixed(c1, t1, round_half_up, saturate);
+  print_info(c1, "c1");
+  print_info(t1, "t1");
+
+  print_info(to_ufixed(c2*c2, 32, 2, none, saturate), "c2*c2");
+  print_info(to_ufixed(c2*c3, 32, 0, round_half_up, none), "c2*c3");
+
+  write (L, slv);
+  writeline (output, L);
+  
+  wait;
+end process;
+
+---------------------------------------------------------------------
+end Behavioral;
+

lib/fixed_ja/eval_fixed_ja_syn.vhd

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+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    00:28:57 07/10/2006 
+-- Design Name: 
+-- Module Name:    adder_registered - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library ieee_proposed;
+use ieee_proposed.fixed_pkg.all;
+use std.textio.all; --  Imports the standard textio package.
+
+library work;
+
+---- Uncomment the following library declaration if instantiating
+---- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity eval_fixed_ja is
+	Generic (
+	        nbits : integer := 8;
+	        nbits_int : integer := 0
+			  );
+	Port
+	(
+		srst			: in std_logic;
+		clk			: in std_logic;
+		di1			: in std_logic_vector(nbits-1 downto 0);
+		di2			: in std_logic_vector(nbits-1 downto 0);
+		in_valid		: in std_logic;
+		do				: out std_logic_vector(nbits-1 downto 0);
+		out_valid	: out std_logic
+	);
+			  
+end eval_fixed_ja;
+
+architecture Behavioral of eval_fixed_ja is
+signal op1, op2 : sfixed(nbits_int downto -(nbits-1));
+signal result : sfixed(2*nbits_int downto -(2*nbits-1));
+begin
+
+op1 <= to_sfixed(di1, op1);
+op2 <= to_sfixed(di2, op2);
+
+do <= to_slv(resize(result, op1, false, false));
+
+---------------------------------------------------------------------
+process(srst, clk, in_valid, di1, di2)
+begin
+	if rising_edge(clk) then
+		if srst = '1' then
+			result <= (others => '0');
+		elsif in_valid = '1' then
+			result <= op1 * op2;
+		end if;
+		out_valid <= in_valid;
+	end if;	
+end process;
+
+
+---------------------------------------------------------------------
+end Behavioral;
+

lib/fixed_ja/tb_eval_fixed_ja_syn.vhd

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+
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   20:01:25 05/22/2007
+-- Design Name:   eval_fixed_ja
+-- Module Name:   H:/vhdl/projects/eval_fixed_ja/ise/tb_eval_fixed_ja.vhd
+-- Project Name:  eval_fixed
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: eval_fixed_ja
+--
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
+-- that these types always be used for the top-level I/O of a design in order 
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.ALL;
+
+ENTITY tb_eval_fixed_ja_vhd IS
+END tb_eval_fixed_ja_vhd;
+
+ARCHITECTURE behavior OF tb_eval_fixed_ja_vhd IS 
+
+	-- Component Declaration for the Unit Under Test (UUT)
+	COMPONENT eval_fixed_ja
+	PORT(
+		srst : IN std_logic;
+		clk : IN std_logic;
+		di1 : IN std_logic_vector(7 downto 0);
+		di2 : IN std_logic_vector(7 downto 0);
+		in_valid : IN std_logic;          
+		do : OUT std_logic_vector(7 downto 0);
+		out_valid : OUT std_logic
+		);
+	END COMPONENT;
+
+	--Inputs
+	SIGNAL srst :  std_logic := '1';
+	SIGNAL clk :  std_logic := '0';
+	SIGNAL in_valid :  std_logic := '0';
+	SIGNAL di1 :  std_logic_vector(7 downto 0) := (others=>'0');
+	SIGNAL di2 :  std_logic_vector(7 downto 0) := (others=>'0');
+
+	--Outputs
+	SIGNAL do :  std_logic_vector(7 downto 0);
+	SIGNAL out_valid :  std_logic;
+
+BEGIN
+
+	-- Instantiate the Unit Under Test (UUT)
+	uut: eval_fixed_ja PORT MAP(
+		srst => srst,
+		clk => clk,
+		di1 => di1,
+		di2 => di2,
+		in_valid => in_valid,
+		do => do,
+		out_valid => out_valid
+	);
+
+	clk_gen : PROCESS
+	BEGIN
+		wait for 10 ns;
+		clk <= not clk;
+	END PROCESS;	
+
+	tb : PROCESS
+	BEGIN
+
+		-- Wait 100 ns for global reset to finish
+		wait for 100 ns;
+		srst <= '0';
+		di1 <= X"40";
+		di2 <= X"20";
+		
+		wait for 20 ns;
+		wait until rising_edge(clk);
+		in_valid <= '1';
+		wait until rising_edge(clk);
+		in_valid <= '0';
+		wait for 20 ns;
+		
+
+		-- Place stimulus here
+
+		wait; -- will wait forever
+	END PROCESS;
+
+END;