- added
git-svn-id: http://moon:8086/svn/vhdl/trunk@1329 cc03376c-175c-47c8-b038-4cd826a8556b
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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 00:28:57 07/10/2006
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-- Design Name:
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-- Module Name: adder_registered - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library ieee_proposed;
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use ieee_proposed.fixed_pkg.all;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity eval_fixed_ja is
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Generic (
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nbits : integer := 8;
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nbits_int : integer := 0
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);
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Port
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(
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srst : in std_logic;
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clk : in std_logic;
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di1 : in std_logic_vector(nbits-1 downto 0);
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di2 : in std_logic_vector(nbits-1 downto 0);
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in_valid : in std_logic;
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do : out std_logic_vector(nbits-1 downto 0);
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out_valid : out std_logic
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);
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end eval_fixed_ja;
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architecture Behavioral of eval_fixed_ja is
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signal op1, op2 : sfixed(nbits_int downto -(nbits-1));
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signal result : sfixed(2*nbits_int downto -(2*nbits-1));
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begin
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op1 <= to_sfixed(di1, op1);
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op2 <= to_sfixed(di2, op2);
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do <= to_slv(resize(result, op1, false, false));
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---------------------------------------------------------------------
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process(srst, clk, in_valid, di1, di2)
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begin
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if rising_edge(clk) then
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if srst = '1' then
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result <= (others => '0');
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elsif in_valid = '1' then
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result <= op1 * op2;
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end if;
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out_valid <= in_valid;
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end if;
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end process;
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---------------------------------------------------------------------
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end Behavioral;
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