diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys.prj b/projects/mips_sys/ise92/mips_sys/mips_sys.prj
index 02ef212..0399c87 100644
--- a/projects/mips_sys/ise92/mips_sys/mips_sys.prj
+++ b/projects/mips_sys/ise92/mips_sys/mips_sys.prj
@@ -1,38 +1,36 @@
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_types.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
 vhdl work "../../src/sdram_config.vhd"
 vhdl work "../../../../lib/misc/utils_pkg.vhd"
-vhdl work "../../../../lib/FIFO/src/fifo_ctrl_pkg.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_instr.vhd"
-vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
-vhdl work "../../../../lib/misc/dpram_1w1r_dist.vhd"
 vhdl work "../../../../lib/misc/dpram_1w1r.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_sync.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd"
 vhdl work "../../../../lib/FIFO/src/sync_fifo_ctrl.vhd"
+vhdl work "../../../../lib/FIFO/src/gray_counter.vhd"
 vhdl work "../../../../lib/uart/kcuart_tx.vhd"
 vhdl work "../../../../lib/uart/kcuart_rx.vhd"
 vhdl work "../../../../lib/uart/bbfifo_16x8.vhd"
+vhdl work "../../../../lib/misc/dpram_2w2r_virtex4.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_timing.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/dpram.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/clkgen_virtex4.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/reset_virtex4.vhd"
-vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/fifo_sync.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_shifter.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_reg.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_muldiv.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_cop.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bcu.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_alu.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/icache.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/dcache.vhd"
+vhdl work "../../../../lib/FIFO/src/fifo_sync.vhd"
+vhdl work "../../../../lib/FIFO/src/async_fifo_ctrl.vhd"
 vhdl work "../../src/sys_types.vhd"
 vhdl work "../../src/ram_ld.vhd"
 vhdl work "../../src/bootloader.ROM_ld.vhd"
 vhdl work "../../../../lib/uart/uart_tx.vhd"
 vhdl work "../../../../lib/uart/uart_rx.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_backend.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/linefifo.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/char_gen.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_pipeline.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_bui.vhd"
+vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_types.vhd"
 vhdl work "../../src/rom_wb.vhd"
 vhdl work "../../src/ram_wb.vhd"
 vhdl work "../../src/gpio_wb.vhd"
@@ -40,6 +38,6 @@ vhdl work "../../../../lib/uart/uart_wb.vhd"
 vhdl work "../../../../lib/misc/lcd_port.vhd"
 vhdl work "../../../../lib/misc/clockgen_virtex4.vhd"
 vhdl work "../../../../lib/misc/async_port_wb.vhd"
+vhdl work "../../../../lib/VGA_ctrl/src/vga_frontend.vhd"
 vhdl work "../../../../lib/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb.vhd"
-vhdl work "../../../../lib/CPUs/MIPS/src/core/mips_top.vhd"
 vhdl work "../../src/mips_sys.vhd"
diff --git a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
index 8f1056a..9eeca44 100644
--- a/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
+++ b/projects/mips_sys/ise92/mips_sys/mips_sys_vhdl.prj
@@ -1,38 +1,36 @@
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
 vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
-vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_instr.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
-vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
 vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
 vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
 vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
 vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
 vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
+vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\dpram.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
-vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\fifo_sync.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_shifter.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_reg.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_muldiv.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_idecode_rom.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_cop.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bcu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_alu.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\icache.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\dcache.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
+vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
 vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\linefifo.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_pipeline.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_bui.vhd"
+vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\rom_wb.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\ram_wb.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\gpio_wb.vhd"
@@ -40,6 +38,6 @@ vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
 vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
 vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
 vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
+vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend.vhd"
 vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend_wb.vhd"
-vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_top.vhd"
 vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"