jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- added preamble genration

Browse Source 
- simplified design
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@853 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-04-04 09:55:22 +00:00
parent 4d41635f19
commit e8deef86a6
2 changed files with 413 additions and 249 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/emac/src/pkt_gen.vhd
+194 -111
View File
@@ -51,33 +51,37 @@ ARCHITECTURE behavior OF pkt_gen IS
signal xfer_size : word_ptr_t;
signal xfer_ptr : word_ptr_t;
signal xfer_cnt : word_ptr_t;
signal xfer_ptr_set : std_logic;
signal xfer_ptr_adv : std_logic;
signal xfer_cnt_set : std_logic;
signal xfer_cnt_adv : std_logic;
signal xfer_rdy : std_logic;
signal xfer_tag : unsigned(3 downto 0);
signal xfer_remain : unsigned(1 downto 0);
signal xfer_odd : std_logic;
signal xfer_remain_en : std_logic;
signal commit_en : std_logic;
signal xfer_set : std_logic;
signal xfer_en : std_logic;
signal xfer_sync : unsigned(1 downto 0);
signal xfer_cnt_en : std_logic;
signal xfer_bsy : std_logic;
signal xfer_pre_rdy : std_logic;
signal uncommit_en : std_logic;
signal piso_din_be : unsigned(3 downto 0);
signal piso_din_rdy : std_logic;
signal data_vld : std_logic;
signal piso8_din : unsigned(31 downto 0);
signal piso8_din_be : unsigned(3 downto 0);
signal piso8_din_rdy : std_logic;
signal piso8_din_vld : std_logic;
signal piso_dout : unsigned(7 downto 0);
signal piso_dout_vld : std_logic;
signal piso_10mbps_din_rdy : std_logic;
signal piso8_dout : unsigned(7 downto 0);
signal piso8_dout_vld : std_logic;
signal piso8_dout_en : std_logic;
signal piso4_din_rdy : std_logic;
signal tx_en : std_logic;
subtype inter_frame_gap_cnt_t is natural;
signal inter_frame_gap_cnt : inter_frame_gap_cnt_t;
signal inter_frame_gap_rdy : std_logic;
subtype ifg_cnt_t is natural range 0 to 23; -- 10/100 mbps
-- subtype ifg_cnt_t is natural range 0 to 11; -- 1000 mbps
signal ifg_cnt : ifg_cnt_t;
signal ifg_idle : std_logic;
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_wait, xfer_active, xfer_uncommit, xfer_free);
type xfer_state_t is (xfer_init, xfer_idle, xfer_setup, xfer_arm, xfer_active, xfer_uncommit, xfer_free);
signal xfer_s, xfer_sn : xfer_state_t;
type stream_state_t is (stream_init, stream_idle, stream_start, stream_preamble0, stream_preamble1, stream_active, stream_crc, stream_stop, stream_finish);
signal stream_s, stream_sn : stream_state_t;
type piso_byte_mask_array_t is array (0 to 3) of unsigned (3 downto 0);
constant piso_byte_mask_rom : piso_byte_mask_array_t :=
(
@@ -87,17 +91,28 @@ ARCHITECTURE behavior OF pkt_gen IS
"1110"
);
signal preamble_en : std_logic;
signal preamble_addr : natural range 0 to 1;
type preamble_t is array (0 to 1) of unsigned(31 downto 0);
constant preamble : preamble_t :=
(
X"55555555",
X"555555D5"
);
begin
mii_tx_er <= '0';
piso_din_be <= mii_fifo_dout(35 downto 32);
mii_fifo_re <= piso_din_rdy;
data_vld <= not mii_fifo_empty;
mii_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(xfer_remain)) when xfer_remain_en = '1' else "1111";
piso8_din <= preamble(preamble_addr) when preamble_en = '1' else mii_fifo_dout(31 downto 0);
piso8_din_be <= "1111" when preamble_en = '1' else mii_fifo_dout(35 downto 32);
mii_fifo_we <= xfer_bsy;
xfer_cnt_en <= xfer_bsy and not mii_fifo_full;
mii_fifo_din(35 downto 32) <= piso_byte_mask_rom(to_integer(pkt_nbytes(1 downto 0))) when xfer_pre_rdy = '1' else "1111";
mii_fifo_din(31 downto 0) <= pkt_data;
------------------------------------------------------------------
-- Transfer stuff
@@ -115,16 +130,12 @@ xfer_state_next:
end process;
xfer_state:
process(xfer_s, xfer_odd, xfer_rdy, inter_frame_gap_rdy, mii_fifo_full)
process(xfer_s, xfer_bsy, xfer_sync)
begin
xfer_cnt_set <= '0';
xfer_cnt_adv <= '0';
xfer_ptr_set <= '0';
xfer_ptr_adv <= '0';
xfer_remain_en <= '0';
mii_fifo_we <= '0';
commit_en <= '0';
uncommit_en <= '0';
xfer_set <= '0';
xfer_en <= '0';
xfer_sn <= xfer_s;
@@ -134,40 +145,28 @@ xfer_state:
xfer_sn <= xfer_idle;
when xfer_idle =>
xfer_ptr_set <= '1';
xfer_cnt_set <= '1';
xfer_sn <= xfer_wait;
xfer_sn <= xfer_setup;
when xfer_wait =>
if inter_frame_gap_rdy = '1' then
xfer_sn <= xfer_setup;
xfer_cnt_adv <= '1';
end if;
when xfer_setup =>
xfer_cnt_adv <= '1';
xfer_ptr_adv <= '1';
xfer_set <= '1';
xfer_sn <= xfer_arm;
when xfer_arm =>
xfer_en <= '1';
xfer_sn <= xfer_active;
when xfer_active =>
mii_fifo_we <= '1';
xfer_cnt_adv <= not mii_fifo_full;
xfer_ptr_adv <= not mii_fifo_full;
if xfer_rdy = '1' then
xfer_remain_en <= xfer_odd;
xfer_cnt_adv <= '0';
xfer_ptr_adv <= '0';
if mii_fifo_full = '0' then
xfer_sn <= xfer_uncommit;
end if;
xfer_en <= '1';
if xfer_bsy = '0' then
xfer_sn <= xfer_uncommit;
end if;
when xfer_uncommit =>
commit_en <= '1';
uncommit_en <= '1';
xfer_sn <= xfer_free;
when xfer_free =>
if inter_frame_gap_rdy = '0' then
if xfer_sync(1) = '1' then
xfer_sn <= xfer_idle;
end if;
@@ -177,6 +176,33 @@ xfer_state:
end process;
------------------------------------------------------------------
interframe_gap_ready:
process(clk)
begin
if rising_edge(clk) then
xfer_sync(1) <= xfer_sync(0);
xfer_sync(0) <= mii_fifo_empty;
end if;
end process;
------------------------------------------------------------------
interframe_gap_counter:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
ifg_idle <= '0';
if rst = '1' or piso8_dout_vld = '1' then
ifg_cnt <= ifg_cnt_t'high;
ifg_idle <= '1';
elsif ifg_cnt /= 0 then
ifg_cnt <= ifg_cnt - 1;
else
ifg_idle <= '1';
end if;
end if;
end process;
------------------------------------------------------------------
pkt_params:
process(clk)
@@ -195,7 +221,7 @@ pkt_params:
seed2 := 12586901;
tx_packets <= 0;
tx_bytes <= 0;
elsif commit_en = '1' then
elsif uncommit_en = '1' then
uniform(seed1, seed2, krand);
size := to_unsigned(PKT_SIZE_MIN + natural(real(PKT_SIZE_MAX-PKT_SIZE_MIN)*krand), word_ptr_t'length);
delay := natural(1.0E6*f_sysclk*(PKT_DLY_MIN + (PKT_DLY_MAX-PKT_DLY_MIN)*krand));
@@ -212,54 +238,28 @@ pkt_params:
end if;
end process;
------------------------------------------------------------------
interframe_gap_counter:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
if rst = '1' then
inter_frame_gap_rdy <= '1';
elsif tx_en = '1' then
inter_frame_gap_rdy <= '0';
inter_frame_gap_cnt <= pkt_delay;
elsif inter_frame_gap_cnt /= 0 then
inter_frame_gap_cnt <= inter_frame_gap_cnt - 1;
else
inter_frame_gap_rdy <= '1';
end if;
end if;
end process;
------------------------------------------------------------------
xfer_counter:
process(clk)
begin
if rising_edge(clk) then
if xfer_cnt_set = '1' then
xfer_size <= (others => '0');
xfer_rdy <= '0';
if xfer_set = '1' then
xfer_cnt <= pkt_nwords;
elsif xfer_cnt_adv = '1' then
if xfer_cnt /= 0 then
xfer_cnt <= xfer_cnt - 1;
xfer_size <= xfer_size + 1;
else
xfer_rdy <= '1';
end if;
end if;
end if;
end process;
xfer_pointer:
process(clk)
begin
if rising_edge(clk) then
if xfer_ptr_set = '1' then
xfer_remain <= pkt_nbytes(1 downto 0);
xfer_odd <= '0';
if xfer_tag(3 downto 2) /= "00" then
xfer_odd <= '1';
xfer_size <= (others => '0');
xfer_bsy <= '0';
xfer_pre_rdy <= '0';
elsif xfer_en = '1' then
xfer_bsy <= '1';
if xfer_cnt_en = '1' or xfer_bsy = '0' then
if xfer_cnt /= 1 then
xfer_cnt <= xfer_cnt - 1;
xfer_size <= xfer_size + 1;
else
xfer_pre_rdy <= '1';
end if;
if xfer_pre_rdy = '1' then
xfer_bsy <= '0';
end if;
end if;
end if;
end if;
@@ -272,9 +272,9 @@ pkt_data_gen:
variable data : unsigned(7 downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
if xfer_set = '1' then
data := (others => '0');
elsif xfer_cnt_adv = '1' then
elsif xfer_cnt_en = '1' or xfer_bsy = '0' then
pkt_data(7 downto 0) <= data;
data := data + 1;
pkt_data(15 downto 8) <= data;
@@ -288,6 +288,87 @@ pkt_data_gen:
end process;
------------------------------------------------------------------
stream_state_next:
process(mii_tx_clk)
begin
if rising_edge(mii_tx_clk) then
if rst = '1' then
stream_s <= stream_init;
else
stream_s <= stream_sn;
end if;
end if;
end process;
stream_state:
process(stream_s, ifg_idle, mii_fifo_empty, piso8_din_rdy, piso8_dout_vld)
begin
piso8_din_vld <= '0';
mii_fifo_re <= '0';
preamble_en <= '0';
preamble_addr <= 0;
stream_sn <= stream_s;
case stream_s is
when stream_init =>
if mii_fifo_empty = '1' then
stream_sn <= stream_idle;
end if;
when stream_idle =>
if mii_fifo_empty = '0' and piso8_din_rdy = '1' then
stream_sn <= stream_start;
end if;
when stream_start =>
stream_sn <= stream_preamble0;
when stream_preamble0 =>
preamble_addr <= 0;
preamble_en <= '1';
piso8_din_vld <= '1';
if piso8_din_rdy = '1' then
stream_sn <= stream_preamble1;
end if;
when stream_preamble1 =>
preamble_addr <= 1;
preamble_en <= '1';
piso8_din_vld <= '1';
if piso8_din_rdy = '1' then
stream_sn <= stream_active;
end if;
when stream_active =>
piso8_din_vld <= not mii_fifo_empty;
mii_fifo_re <= piso8_din_rdy;
if mii_fifo_empty = '1' then
stream_sn <= stream_crc;
end if;
when stream_crc =>
stream_sn <= stream_stop;
when stream_stop =>
if piso8_dout_vld = '0' then
stream_sn <= stream_finish;
end if;
when stream_finish =>
if ifg_idle = '0' then
stream_sn <= stream_idle;
end if;
when others =>
stream_sn <= stream_idle;
end case;
end process;
------------------------------------------------------------------
-- Instantiate synchronous FIFO
inst_mii_fifo: entity work.fifo_async
@@ -323,16 +404,18 @@ inst_piso : entity work.piso
(
rst => rst,
clk => mii_tx_clk,
din_vld => data_vld,
din_rdy => piso_din_rdy,
din_be => piso_din_be,
din => mii_fifo_dout(31 downto 0),
dout_vld => piso_dout_vld,
dout_en => piso_10mbps_din_rdy,
dout => piso_dout
din_vld => piso8_din_vld,
din_rdy => piso8_din_rdy,
din_be => piso8_din_be,
din => piso8_din,
dout_vld => piso8_dout_vld,
dout_en => piso8_dout_en,
dout => piso8_dout
);
piso8_dout_en <= piso4_din_rdy and ifg_idle;
inst_piso_10mbps : entity work.piso
GENERIC MAP
(
@@ -344,10 +427,10 @@ inst_piso_10mbps : entity work.piso
(
rst => rst,
clk => mii_tx_clk,
din_vld => piso_dout_vld,
din_rdy => piso_10mbps_din_rdy,
din_vld => piso8_dout_vld,
din_rdy => piso4_din_rdy,
din_be => "11",
din => piso_dout,
din => piso8_dout,
dout_vld => tx_en,
dout_en => '1',
dout => mii_tx(3 downto 0)