- TX-params are set via ctrl_in directly from regsiter interface.

No parameter set via din anymore
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git-svn-id: http://moon:8086/svn/vhdl/trunk@820 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
2010-03-25 19:56:53 +00:00
parent 832c1c8a33
commit e8b6c8efdb
3 changed files with 15 additions and 32 deletions
+8 -12
View File
@@ -62,7 +62,7 @@ ARCHITECTURE behavior OF emac_top_jb IS
signal if_rdy : std_logic;
begin
SRDY_O <= CYC_I and if_rdy;
SRDY_O <= CYC_I;
INT_O <= irq_rx or irq_tx;
mii_gtx_clk <= '0';
@@ -71,16 +71,15 @@ registers_write:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if_rdy <= '1';
tx_ctrl_in.data_vld <= '0';
tx_ctrl_in.tx_size_vld <= '0';
tx_ctrl_in.tx_req_en <= '0';
rx_ctrl_in.uncommit <= '0';
if RST_I = '1' then
rx_int_en <= '0';
tx_int_en <= '0';
tx_ctrl_in.tx_er <= '0';
elsif (STB_I and CYC_I and WE_I) = '1' then
tx_ctrl_in.tx_size <= (others => '0');
elsif (STB_I and CYC_I and WE_I) = '1' then
case ADDR_I(5 downto 2) is
when "0000" =>
@@ -91,9 +90,7 @@ registers_write:
rx_int_en <= DAT_I(4);
when "0001" =>
if_rdy <= '0'; -- allow request size to propagate inside TX module
tx_ctrl_in.tx_size_vld <= '1';
tx_din <= X"0000" & DAT_I(31 downto 16);
tx_ctrl_in.tx_size <= DAT_I(31 downto 16);
when "0010" =>
tx_ctrl_in.data_vld <= '1';
@@ -111,13 +108,12 @@ registers_read:
if rising_edge(CLK_I) then
rx_ctrl_in.data_read <= '0';
ACK_O <= '0';
if CYC_I = '1' then
ACK_O <= STB_I and not WE_I;
if (STB_I and CYC_I) = '1' then
ACK_O <= not WE_I;
DAT_O <= (others => '0');
case ADDR_I(5 downto 2) is
when "0000" =>
DAT_O <= (others => '0');
DAT_O <= (others => '0');
DAT_O(31) <= tx_ctrl_in.tx_er;
DAT_O(30) <= mii_rx_er;
DAT_O(29) <= mii_col;
@@ -130,7 +126,7 @@ registers_read:
DAT_O <= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size;
when "0010" =>
rx_ctrl_in.data_read <= STB_I and not WE_I;
rx_ctrl_in.data_read <= not WE_I;
ACK_O <= rx_ctrl_out.data_vld;
DAT_O <= rx_dout;
+5 -18
View File
@@ -49,8 +49,6 @@ ARCHITECTURE behavior OF emac_tx IS
signal flush_en : std_logic;
signal alloc_req_size : unsigned(15 downto 0);
signal fill_base : word_ptr_t;
signal fill_size : word_ptr_t;
signal fill_cnt : word_ptr_t;
@@ -233,17 +231,6 @@ host_state:
------------------------------------------------------------------
-- Allocation stuff
------------------------------------------------------------------
alloc_req_size_register:
process(clk)
begin
if rising_edge(clk) then
if ctrl_in.tx_size_vld = '1' then
alloc_req_size <= din(15 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------
alloc_request_logic:
process(clk)
@@ -253,12 +240,12 @@ alloc_request_logic:
alloc_req <= '0';
elsif ctrl_in.tx_req_en = '1' and alloc_req = '0' then
alloc_req <= '1';
fill_remain <= alloc_req_size(1 downto 0);
fill_size <= alloc_req_size(word_ptr_t'left+2 downto 2);
if din(1 downto 0) /= "00" then
fill_size <= alloc_req_size(word_ptr_t'left+2 downto 2) + 1;
fill_remain <= ctrl_in.tx_size(1 downto 0);
fill_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2);
if ctrl_in.tx_size(1 downto 0) /= "00" then
fill_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1;
end if;
ctrl_out.tx_size <= resize(alloc_req_size(word_ptr_t'left downto 0), 16);
ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
elsif alloc_ack = '1' then
alloc_req <= '0';
+2 -2
View File
@@ -16,9 +16,9 @@ package emac_types is
-- Types
type tx_ctrl_in_t is record
tx_er : std_logic;
tx_size_vld : std_logic;
data_vld : std_logic;
tx_size : unsigned(15 downto 0);
tx_req_en : std_logic;
data_vld : std_logic;
end record;
type tx_ctrl_out_t is record