- TX-params are set via ctrl_in directly from regsiter interface.
No parameter set via din anymore Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@820 cc03376c-175c-47c8-b038-4cd826a8556b
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@@ -62,7 +62,7 @@ ARCHITECTURE behavior OF emac_top_jb IS
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signal if_rdy : std_logic;
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signal if_rdy : std_logic;
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begin
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begin
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SRDY_O <= CYC_I and if_rdy;
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SRDY_O <= CYC_I;
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INT_O <= irq_rx or irq_tx;
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INT_O <= irq_rx or irq_tx;
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mii_gtx_clk <= '0';
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mii_gtx_clk <= '0';
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@@ -71,15 +71,14 @@ registers_write:
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process(CLK_I)
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process(CLK_I)
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begin
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begin
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if rising_edge(CLK_I) then
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if rising_edge(CLK_I) then
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if_rdy <= '1';
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tx_ctrl_in.data_vld <= '0';
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tx_ctrl_in.data_vld <= '0';
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tx_ctrl_in.tx_size_vld <= '0';
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tx_ctrl_in.tx_req_en <= '0';
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tx_ctrl_in.tx_req_en <= '0';
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rx_ctrl_in.uncommit <= '0';
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rx_ctrl_in.uncommit <= '0';
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if RST_I = '1' then
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if RST_I = '1' then
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rx_int_en <= '0';
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rx_int_en <= '0';
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tx_int_en <= '0';
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tx_int_en <= '0';
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tx_ctrl_in.tx_er <= '0';
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tx_ctrl_in.tx_er <= '0';
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tx_ctrl_in.tx_size <= (others => '0');
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elsif (STB_I and CYC_I and WE_I) = '1' then
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elsif (STB_I and CYC_I and WE_I) = '1' then
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case ADDR_I(5 downto 2) is
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case ADDR_I(5 downto 2) is
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@@ -91,9 +90,7 @@ registers_write:
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rx_int_en <= DAT_I(4);
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rx_int_en <= DAT_I(4);
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when "0001" =>
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when "0001" =>
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if_rdy <= '0'; -- allow request size to propagate inside TX module
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tx_ctrl_in.tx_size <= DAT_I(31 downto 16);
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tx_ctrl_in.tx_size_vld <= '1';
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tx_din <= X"0000" & DAT_I(31 downto 16);
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when "0010" =>
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when "0010" =>
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tx_ctrl_in.data_vld <= '1';
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tx_ctrl_in.data_vld <= '1';
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@@ -111,13 +108,12 @@ registers_read:
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if rising_edge(CLK_I) then
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if rising_edge(CLK_I) then
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rx_ctrl_in.data_read <= '0';
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rx_ctrl_in.data_read <= '0';
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ACK_O <= '0';
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ACK_O <= '0';
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if CYC_I = '1' then
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if (STB_I and CYC_I) = '1' then
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ACK_O <= STB_I and not WE_I;
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ACK_O <= not WE_I;
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DAT_O <= (others => '0');
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case ADDR_I(5 downto 2) is
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case ADDR_I(5 downto 2) is
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when "0000" =>
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when "0000" =>
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DAT_O <= (others => '0');
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DAT_O <= (others => '0');
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DAT_O(31) <= tx_ctrl_in.tx_er;
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DAT_O(31) <= tx_ctrl_in.tx_er;
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DAT_O(30) <= mii_rx_er;
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DAT_O(30) <= mii_rx_er;
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DAT_O(29) <= mii_col;
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DAT_O(29) <= mii_col;
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@@ -130,7 +126,7 @@ registers_read:
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DAT_O <= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size;
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DAT_O <= tx_ctrl_out.tx_size & rx_ctrl_out.rx_size;
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when "0010" =>
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when "0010" =>
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rx_ctrl_in.data_read <= STB_I and not WE_I;
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rx_ctrl_in.data_read <= not WE_I;
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ACK_O <= rx_ctrl_out.data_vld;
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ACK_O <= rx_ctrl_out.data_vld;
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DAT_O <= rx_dout;
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DAT_O <= rx_dout;
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@@ -49,8 +49,6 @@ ARCHITECTURE behavior OF emac_tx IS
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signal flush_en : std_logic;
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signal flush_en : std_logic;
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signal alloc_req_size : unsigned(15 downto 0);
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signal fill_base : word_ptr_t;
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signal fill_base : word_ptr_t;
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signal fill_size : word_ptr_t;
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signal fill_size : word_ptr_t;
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signal fill_cnt : word_ptr_t;
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signal fill_cnt : word_ptr_t;
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@@ -233,17 +231,6 @@ host_state:
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------------------------------------------------------------------
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------------------------------------------------------------------
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-- Allocation stuff
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-- Allocation stuff
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------------------------------------------------------------------
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alloc_req_size_register:
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process(clk)
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begin
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if rising_edge(clk) then
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if ctrl_in.tx_size_vld = '1' then
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alloc_req_size <= din(15 downto 0);
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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------------------------------------------------------------------
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alloc_request_logic:
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alloc_request_logic:
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process(clk)
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process(clk)
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@@ -253,12 +240,12 @@ alloc_request_logic:
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alloc_req <= '0';
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alloc_req <= '0';
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elsif ctrl_in.tx_req_en = '1' and alloc_req = '0' then
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elsif ctrl_in.tx_req_en = '1' and alloc_req = '0' then
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alloc_req <= '1';
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alloc_req <= '1';
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fill_remain <= alloc_req_size(1 downto 0);
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fill_remain <= ctrl_in.tx_size(1 downto 0);
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fill_size <= alloc_req_size(word_ptr_t'left+2 downto 2);
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fill_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2);
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if din(1 downto 0) /= "00" then
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if ctrl_in.tx_size(1 downto 0) /= "00" then
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fill_size <= alloc_req_size(word_ptr_t'left+2 downto 2) + 1;
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fill_size <= ctrl_in.tx_size(word_ptr_t'left+2 downto 2) + 1;
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end if;
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end if;
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ctrl_out.tx_size <= resize(alloc_req_size(word_ptr_t'left downto 0), 16);
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ctrl_out.tx_size <= resize(ctrl_in.tx_size(word_ptr_t'left downto 0), 16);
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elsif alloc_ack = '1' then
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elsif alloc_ack = '1' then
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alloc_req <= '0';
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alloc_req <= '0';
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@@ -16,9 +16,9 @@ package emac_types is
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-- Types
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-- Types
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type tx_ctrl_in_t is record
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type tx_ctrl_in_t is record
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tx_er : std_logic;
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tx_er : std_logic;
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tx_size_vld : std_logic;
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tx_size : unsigned(15 downto 0);
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data_vld : std_logic;
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tx_req_en : std_logic;
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tx_req_en : std_logic;
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data_vld : std_logic;
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end record;
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end record;
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type tx_ctrl_out_t is record
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type tx_ctrl_out_t is record
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