diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_clk_cycloneive.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/clock/altera/sdr_clk_cycloneive.vhd
similarity index 100%
rename from lib/SDRAM/ddr_sdr_v1_5/src/sdr_clk_cycloneive.vhd
rename to lib/SDRAM/ddr_sdr_v1_5/src/clock/altera/sdr_clk_cycloneive.vhd
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/clock/xilinx/ddr_clk_virtex4.vhd
similarity index 100%
rename from lib/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
rename to lib/SDRAM/ddr_sdr_v1_5/src/clock/xilinx/ddr_clk_virtex4.vhd
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/phy/altera/sdr_phy_de0nano.vhd
similarity index 100%
rename from lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_de0nano.vhd
rename to lib/SDRAM/ddr_sdr_v1_5/src/phy/altera/sdr_phy_de0nano.vhd
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/phy/xilinx/ddr_phy_virtex4.vhd
similarity index 100%
rename from lib/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
rename to lib/SDRAM/ddr_sdr_v1_5/src/phy/xilinx/ddr_phy_virtex4.vhd
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/phy/xilinx/sdr_phy_virtex4.vhd
similarity index 100%
rename from lib/SDRAM/ddr_sdr_v1_5/src/sdr_phy_virtex4.vhd
rename to lib/SDRAM/ddr_sdr_v1_5/src/phy/xilinx/sdr_phy_virtex4.vhd