diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index 1a09d8e..cce6fdb 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -800,6 +800,7 @@ proc_stage_MEM_except:
 	begin
 		MEM_stage.events				<= MEM_stage.events_in;
 		MEM_stage.events.Int			<= c0_ctrl_in.int;
+		MEM_stage.events.NMI			<= c0_ctrl_in.NMI;
 	end process;
 
 	MEM_stage.exc	<= event_is_active(MEM_stage.events);
diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd
index ba57a1d..1ebee86 100644
--- a/lib/CPUs/MIPS/src/core/mips_top.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_top.vhd
@@ -40,6 +40,7 @@ entity mips_top is
 	(
 		debug		: out unsigned(1 downto 0);
 		eb			: in  STD_LOGIC;
+		nmi			: in  STD_LOGIC;
 		RST_I		: in  STD_LOGIC;
 		CLK_I		: in  STD_LOGIC;
 		ACK_I		: in  STD_LOGIC;
@@ -129,6 +130,7 @@ architecture rtl of mips_top is
 	(
 		rst			: in  STD_LOGIC;
 		clk			: in  STD_LOGIC;
+		nmi			: in  STD_LOGIC;
 		eb			: in  STD_LOGIC;
 		int			: in  unsigned (5 downto 0);
 		ir_en		: in  STD_LOGIC;
@@ -251,6 +253,7 @@ inst_cop: cop
 	(
 		rst			=> cpu_rst,
 		clk			=> CLK_I,
+		nmi			=> nmi,
 		eb			=> eb,
 		int			=> INT,
 		ir_en		=> pipe_cop_ir_en,
diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd
index b4565a5..d820a21 100644
--- a/lib/CPUs/MIPS/src/core/mips_types.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_types.vhd
@@ -213,6 +213,7 @@ package mips_types is
 	end record;
 
 	type event_t is record
+		NMI				: STD_LOGIC;
 		Int				: STD_LOGIC;
 		data_load_err	: STD_LOGIC;
 		data_store_err	: STD_LOGIC;
@@ -270,6 +271,7 @@ package mips_types is
 		exc_pending		: STD_LOGIC;
 		exc_exit		: STD_LOGIC;
 		user_mode		: STD_LOGIC;
+		NMI				: STD_LOGIC;
 		int				: STD_LOGIC;
 		exc_vec			: word_t;
 		icache			: cache_ctrl_t;
@@ -592,6 +594,7 @@ package body mips_types is
 	function events_clr return event_t is
 	variable result : event_t;
 	begin
+		result.NMI				:= '0';
 		result.Int				:= '0';
 		result.data_load_err	:= '0';
 		result.data_store_err	:= '0';
@@ -613,6 +616,7 @@ package body mips_types is
 	begin
 		result := '0';
 		
+		result	:= result or e.NMI;
 		result	:= result or e.Int;
 		result	:= result or e.data_load_err;
 		result	:= result or e.data_store_err;
@@ -632,6 +636,7 @@ package body mips_types is
 	function "or" (a, b : event_t) return event_t is
 	variable result : event_t;
 	begin
+		result.NMI				:= a.NMI or b.NMI;
 		result.Int				:= a.Int or b.Int;
 		result.data_load_err	:= a.data_load_err or b.data_load_err;
 		result.data_store_err	:= a.data_store_err or b.data_store_err;
diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd
index 4b28f69..4392be5 100644
--- a/lib/CPUs/MIPS/src/tb_mips_top.vhd
+++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd
@@ -44,6 +44,7 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	signal debug		: unsigned(1 downto 0);
 
 	-- Master 
+	signal nmi			: STD_LOGIC := '0';
 	signal rst			: STD_LOGIC := '1';
 	signal clk			: STD_LOGIC := '0';
 	signal eb			: STD_LOGIC := '1';
@@ -214,7 +215,8 @@ uut: entity work.mips_top
 		CYC_O	=> CYC_O,
 		STB_O	=> STB_O,
 		MRDY_O	=> MRDY_O,
-		INT		=> INT
+		INT		=> INT,
+		nmi		=> nmi
 	);
 	INT(1)	<= int_uart;
 	INT(5)	<= int_timer;
@@ -430,12 +432,12 @@ STIMULUS: process
 		wait for 3*CLK_PERIOD;
 		wait until rising_edge(clk);
 		rst <= '0';
-		wait for 50000*CLK_PERIOD;
+		wait for 250000*CLK_PERIOD;
 		wait until rising_edge(clk);
-		rst <= '0';
-		wait for 3*CLK_PERIOD;
+		nmi <= '1';
+		wait for 3000*CLK_PERIOD;
 		wait until rising_edge(clk);
-		rst <= '0';
+		nmi <= '0';
 
 		wait; 
 	
diff --git a/projects/mips_sys/src/mips_sys.vhd b/projects/mips_sys/src/mips_sys.vhd
index 76e7bc8..1e34f82 100644
--- a/projects/mips_sys/src/mips_sys.vhd
+++ b/projects/mips_sys/src/mips_sys.vhd
@@ -128,6 +128,7 @@ ARCHITECTURE behavior OF mips_sys IS
 	(
 		debug		: out unsigned(1 downto 0);
 		eb			: in  STD_LOGIC;
+		nmi			: in  STD_LOGIC;
 		RST_I		: in  STD_LOGIC;
 		CLK_I		: in  STD_LOGIC;
 		ACK_I		: in  STD_LOGIC;
@@ -303,6 +304,7 @@ ARCHITECTURE behavior OF mips_sys IS
 	);
 	END COMPONENT;
 
+	signal nmi			: std_logic;
 	signal rst			: std_logic;
 	signal clk			: std_logic;
 	signal eb			: std_logic;
@@ -436,7 +438,8 @@ BEGIN
 	gpi1(7 downto 0)	<= sys_dip;
 	sys_led				<= gpo0(8 downto 0);
 	sys_error			<= debug;
-	rst_in 				<= not sys_rst_n_in;
+	nmi					<= not sys_rst_n_in;
+	rst_in 				<= not sys_rst_n_in and sys_btn(0) and sys_btn(2);
 	rst					<= not locked;
 	sys_usb_rstn		<= not gpo1(0);
 	sys_flash_byten		<= '1';
@@ -588,6 +591,7 @@ inst_mips_top: mips_top
 	(
 		debug			=> debug,
 		eb				=> eb,
+		nmi				=> nmi,
 		RST_I			=> rst,
 		CLK_I			=> clk,
 		ACK_I			=> ACK_I_cpu,