[J-MIPS]

- I/D-Cache added input registers for data fetch


git-svn-id: http://moon:8086/svn/vhdl/trunk@1381 cc03376c-175c-47c8-b038-4cd826a8556b

lib/CPUs/MIPS/src/core/mips_dcache.vhd

@@ -178,6 +178,9 @@ END COMPONENT;
 	signal	instant_raw			: std_logic;
 	signal  hit_cache_index		: unsigned(cache_index_width-1 downto 0);
 
+	signal  DAT_I_r				: word_t;
+	signal  ACK_I_r				: std_logic;
+	
 	alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
 	alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
 	alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
@@ -197,12 +200,23 @@ begin
 
 	cpu_hit_we	<= cpu_we2 and cache_hit;
 	
+data_in_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			ACK_I_r	<= ACK_I;
+			if ACK_I = '1' then
+				DAT_I_r <= DAT_I;
+			end if;
+		end if;
+	end process;	
+	
 fill_address_register:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
 			if fill_count_en = '1' then
-				if ACK_I = '1' then
+				if ACK_I_r = '1' then
 					fill_word_index	<= fill_word_index + 1;
 				end if;	
 			elsif cache_busy = '0' then
@@ -304,7 +318,7 @@ gen_data_ram:
 			addr_a	=> ctrl_data_ram_addr,
 			addr_b	=> cpu_data_ram_addr,
 			din_a	=> cpu_data_reg(8*(i+1)-1 downto 8*i),
-			din_b	=> DAT_I(8*(i+1)-1 downto 8*i),
+			din_b	=> DAT_I_r(8*(i+1)-1 downto 8*i),
 			dout_a	=> open,
 			dout_b	=> cpu_data_ram_dout(8*(i+1)-1 downto 8*i)
 		);
@@ -358,7 +372,7 @@ cache_state_next:
 	
 	cpu_data_ram_addr	<= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and instant_raw = '0' and fill_count_en = '0') else (fill_cache_index & fill_word_index);
 	ctrl_data_ram_addr	<= fill_cache_index & fill_word_index;
-	ctrl_data_ram_we	<= (others => fill_count_en and ACK_I);
+	ctrl_data_ram_we	<= (others => fill_count_en and ACK_I_r);
 	cpu_data_ram_we		<= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
 	
 cache_state:
@@ -513,7 +527,7 @@ fill_counter:
 				fill_count_rdy	<= '0';
 				fill_count		<= 2**word_index_width-1;
 			else	
-				if ACK_I = '1' then
+				if ACK_I_r = '1' then
 					if fill_count /= 0 then
 						fill_count 	<= fill_count - 1;
 					else

lib/CPUs/MIPS/src/core/mips_icache.vhd

@@ -186,6 +186,9 @@ END COMPONENT;
 	signal  invalidate_en		: std_logic;
 	signal  invalidate_req		: std_logic;
 
+	signal  DAT_I_r				: word_t;
+	signal  ACK_I_r				: std_logic;
+	
 	alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
 	alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
 	alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
@@ -204,12 +207,23 @@ begin
 	tag_inv			<= ctrl.inv_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
 
 	
+data_in_register:
+	process(CLK_I)
+	begin
+		if rising_edge(CLK_I) then
+			ACK_I_r	<= ACK_I;
+			if ACK_I = '1' then
+				DAT_I_r <= DAT_I;
+			end if;
+		end if;
+	end process;	
+	
 fill_address_register:
 	process(CLK_I)
 	begin
 		if rising_edge(CLK_I) then
 			if fill_count_en = '1' then
-				if ACK_I = '1' then
+				if ACK_I_r = '1' then
 					fill_word_index	<= fill_word_index + 1;
 				end if;	
 			elsif cache_busy = '0' then
@@ -334,8 +348,8 @@ cache_state_next:
 	tag_ram_addr_rd		<= cpu_cache_index when was_miss = '0' else fill_cache_index;
 	data_ram_addr_rd	<= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (fill_cache_index & fill_word_index);
 	data_ram_addr_wr	<= fill_cache_index & fill_word_index;
-	data_ram_data_wr	<= DAT_I;
+	data_ram_data_wr	<= DAT_I_r;
-	data_ram_we			<= fill_count_en and ACK_I;
+	data_ram_we			<= fill_count_en and ACK_I_r;
 	data_ram_re		<= (cpu_en or was_miss) and not data_ram_we;
 --	tag_ram_re		<= (cpu_en or was_miss) and not data_ram_we;
 
@@ -488,7 +502,7 @@ fill_counter:
 				fill_count_rdy	<= '0';
 				fill_count		<= 2**word_index_width-1;
 			else	
-				if ACK_I = '1' then
+				if ACK_I_r = '1' then
 					if fill_count /= 0 then
 						fill_count 	<= fill_count - 1;
 					else