diff --git a/lib/CPUs/MIPS/sim/tb_mips_biu.fdo b/lib/CPUs/MIPS/sim/tb_mips_biu.fdo
new file mode 100644
index 0000000..9e2923f
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_biu.fdo
@@ -0,0 +1,48 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+# Packages
+vcom -explicit  -93 "../src/core/TLB/mips_util_pkg.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_types.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../JBUS/src/busmaster_types.vhd"
+
+# RAMS
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../../misc/ram_sim.vhd"
+vcom -explicit  -93 "../../../misc/ram_wb.vhd"
+vcom -explicit  -93 "../../../misc/rom_sim.vhd"
+vcom -explicit  -93 "../../../misc/rom_wb.vhd"
+
+
+# FIFOS
+vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
+
+# MIPS Cache
+vcom -explicit  -93 "../src/core/TLB/mips_icache.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_dcache.vhd"
+
+# MIPS TLB
+vcom -explicit  -93 "../src/core/TLB/mips_tlb_block.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_tlb.vhd"
+
+# Busmaster
+vcom -explicit  -93 "../../../JBUS/src/busmaster_async.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_biu.vhd"
+vcom -explicit  -93 "../src/tb_mips_biu_tlb.vhd"
+
+vsim -t 1ps   -lib work tb_biu_tlb
+do {tb_mips_biu_tlb.wdo}
+view wave
+view structure
+view signals
+run 10us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_biu.wdo b/lib/CPUs/MIPS/sim/tb_mips_biu.wdo
new file mode 100644
index 0000000..ed4cb3e
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_biu.wdo
@@ -0,0 +1,164 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_biu_tlb/clk
+add wave -noupdate -format Logic /tb_biu_tlb/rst
+add wave -noupdate -format Logic /tb_biu_tlb/int_o
+add wave -noupdate -format Logic /tb_biu_tlb/cyc_o
+add wave -noupdate -format Logic /tb_biu_tlb/stb_o
+add wave -noupdate -format Logic /tb_biu_tlb/we_o
+add wave -noupdate -format Literal /tb_biu_tlb/sel_o
+add wave -noupdate -format Logic /tb_biu_tlb/ack_i
+add wave -noupdate -format Logic /tb_biu_tlb/mrdy_o
+add wave -noupdate -format Logic /tb_biu_tlb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/mdat_o
+add wave -noupdate -format Literal /tb_biu_tlb/index_in
+add wave -noupdate -format Logic /tb_biu_tlb/entry_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/entry_lo_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/entry_hi_in
+add wave -noupdate -format Literal /tb_biu_tlb/index_out
+add wave -noupdate -format Logic /tb_biu_tlb/entry_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/entry_lo_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/entry_hi_out
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_imem_err
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_imem_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/cpu_imem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/cpu_imem_dout
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_imem_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_dmem_err
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_dmem_en
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_dmem_we
+add wave -noupdate -format Literal /tb_biu_tlb/cpu_dmem_addr
+add wave -noupdate -format Literal /tb_biu_tlb/cpu_dmem_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/cpu_dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/cpu_dmem_dout
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_dmem_rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/ctrl_out
+add wave -noupdate -divider BIU
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/clk_i
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_imem_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/cpu_imem_din_reg
+add wave -noupdate -format Logic /tb_biu_tlb/cpu_dmem_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/cpu_dmem_din_reg
+add wave -noupdate -format Literal /tb_biu_tlb/op_descr
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/imem_err
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/imem_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/imem_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/imem_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/imem_dout
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/dmem_err
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/dmem_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/dmem_en
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/dmem_we
+add wave -noupdate -format Literal /tb_biu_tlb/inst_biu/dmem_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/dmem_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/dmem_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/dmem_addr
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/rst_i
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/clk_i
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/srdy_i
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/stb_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/mdat_i
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/ack_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/mdat_o
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/we_o
+add wave -noupdate -format Literal /tb_biu_tlb/inst_biu/sel_o
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/cyc_o
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/mrdy_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/ctrl_out
+add wave -noupdate -format Literal /tb_biu_tlb/inst_biu/s
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_idle
+add wave -noupdate -format Literal /tb_biu_tlb/inst_biu/bus_timeout_cnt
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_timeout
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/rst
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/bus_din
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_din_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_din_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/bus_dout
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_dout_vld
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_dout_re
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_cmd_cycle_en
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_cmd_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_cmd_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/bus_cmd
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/bus_cyc_complete
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/i_bus_din_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/i_bus_cmd_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/i_bus_cmd_we
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/i_bus_cmd_cycle_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/i_bus_cmd
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/i_tlb_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/i_tlb_out
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/d_bus_din_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/d_bus_cmd_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/d_bus_cmd_we
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/d_bus_cmd_cycle_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/d_bus_cmd
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/d_tlb_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/d_tlb_out
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/icache_bus_gnt
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/dcache_bus_gnt
+add wave -noupdate -divider BUS-Master
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/clk
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/rst
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_cycle_finished
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_cycle_en
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/inst_busmaster/cmd_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/inst_busmaster/din
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/din_rdy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/din_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/inst_busmaster/dout
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/dout_vld
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/dout_re
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/ack_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/inst_busmaster/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/inst_busmaster/mdat_o
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/srdy_i
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/stb_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/inst_busmaster/addr_o
+add wave -noupdate -format Literal /tb_biu_tlb/inst_biu/inst_busmaster/sel_o
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/we_o
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cyc_o
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/mrdy_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/inst_busmaster/cmd_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_biu_tlb/inst_biu/inst_busmaster/cmd_fifo_dout
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_fifo_re
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_fifo_we
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_fifo_full
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/read_fifo_re
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/read_fifo_we
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/read_fifo_full
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/read_fifo_empty
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/write_fifo_re
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/write_fifo_we
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/write_fifo_full
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/write_fifo_empty
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cycle_busy
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_en
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/cmd_read_en
+add wave -noupdate -format Literal /tb_biu_tlb/inst_biu/inst_busmaster/read_cnt
+add wave -noupdate -format Logic /tb_biu_tlb/inst_biu/inst_busmaster/write
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {2188429 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {9563964 ps} {10022950 ps}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_cam.fdo b/lib/CPUs/MIPS/sim/tb_mips_cam.fdo
new file mode 100644
index 0000000..93eb44f
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_cam.fdo
@@ -0,0 +1,24 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+# RAMS
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
+
+
+# FIFOS
+
+# MIPS
+vcom -explicit  -93 "../src/core/TLB/mips_types.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_cam.vhd"
+
+vcom -explicit  -93 "../src/tb_mips_cam.vhd"
+vsim -t 1ps   -lib work tb_cam
+do {tb_mips_cam.wdo}
+view wave
+view structure
+view signals
+run 20us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_cam.wdo b/lib/CPUs/MIPS/sim/tb_mips_cam.wdo
new file mode 100644
index 0000000..5e1a43f
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_cam.wdo
@@ -0,0 +1,69 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_cam/clk_o
+add wave -noupdate -format Logic /tb_cam/rst_o
+add wave -noupdate -format Logic /tb_cam/cam_rdy
+add wave -noupdate -format Logic /tb_cam/cam_vld
+add wave -noupdate -format Logic /tb_cam/cam_we
+add wave -noupdate -format Logic /tb_cam/cam_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/cam_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/cam_data
+add wave -noupdate -format Literal /tb_cam/cam_hit
+add wave -noupdate -format Logic /tb_cam/cam_hit_vld
+add wave -noupdate -divider CAM
+add wave -noupdate -format Literal /tb_cam/inst_cam/state
+add wave -noupdate -format Literal /tb_cam/inst_cam/debug
+add wave -noupdate -format Literal /tb_cam/inst_cam/num_entries
+add wave -noupdate -format Literal /tb_cam/inst_cam/data_width
+add wave -noupdate -format Logic /tb_cam/inst_cam/rst
+add wave -noupdate -format Logic /tb_cam/inst_cam/clk
+add wave -noupdate -format Logic /tb_cam/inst_cam/rdy
+add wave -noupdate -format Logic /tb_cam/inst_cam/re
+add wave -noupdate -format Logic /tb_cam/inst_cam/we
+add wave -noupdate -format Logic /tb_cam/inst_cam/vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/din
+add wave -noupdate -format Literal /tb_cam/inst_cam/hit
+add wave -noupdate -format Logic /tb_cam/inst_cam/cam_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/cam_ram_addr_wr
+add wave -noupdate -format Literal /tb_cam/inst_cam/cam_ram_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/cam_ram_addr_rd
+add wave -noupdate -format Literal -expand /tb_cam/inst_cam/cam_ram_dout
+add wave -noupdate -format Literal /tb_cam/inst_cam/cam_ram_result
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/clear_addr
+add wave -noupdate -format Logic /tb_cam/inst_cam/clear_count_en
+add wave -noupdate -format Logic /tb_cam/inst_cam/clear_count_rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/clear_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/clear_data
+add wave -noupdate -format Literal /tb_cam/inst_cam/vld_cam
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/pipe0
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/pipe1
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/pipe2
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/pipe3
+add wave -noupdate -divider Track-RAM
+add wave -noupdate -format Logic /tb_cam/inst_cam/over_write
+add wave -noupdate -format Logic /tb_cam/inst_cam/track_ram_re
+add wave -noupdate -format Logic /tb_cam/inst_cam/track_ram_we
+add wave -noupdate -format Logic /tb_cam/inst_cam/rdy
+add wave -noupdate -format Logic /tb_cam/inst_cam/we
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/track_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/track_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/track_ram_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_cam/inst_cam/track_ram_dout
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cam/inst_cam/inst_track_ram/ram
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {Cursor {19917510 ps} 0}
+configure wave -namecolwidth 137
+configure wave -valuecolwidth 214
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 100
+configure wave -griddelta 40
+configure wave -timeline 1
+update
+WaveRestoreZoom {19867492 ps} {20006975 ps}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_dcache.fdo b/lib/CPUs/MIPS/sim/tb_mips_dcache.fdo
new file mode 100644
index 0000000..6a14901
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_dcache.fdo
@@ -0,0 +1,45 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+vcom -explicit  -93 "../src/core/TLB/mips_util_pkg.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_types.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../JBUS/src/busmaster_types.vhd"
+
+# RAMS
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../../misc/ram_sim.vhd"
+vcom -explicit  -93 "../../../misc/ram_wb.vhd"
+vcom -explicit  -93 "../../../misc/rom_sim.vhd"
+vcom -explicit  -93 "../../../misc/rom_wb.vhd"
+
+
+# FIFOS
+vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
+
+# MIPS Cache
+vcom -explicit  -93 "../src/core/TLB/mips_dcache.vhd"
+
+# MIPS TLB
+vcom -explicit  -93 "../src/core/TLB/mips_tlb_block.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_tlb.vhd"
+
+# Busmaster
+vcom -explicit  -93 "../../../JBUS/src/busmaster_sync.vhd"
+vcom -explicit  -93 "../src/tb_mips_dcache_tlb.vhd"
+
+vsim -t 1ps   -lib work tb_dcache_tlb
+do {tb_mips_dcache_tlb.wdo}
+view wave
+view structure
+view signals
+run 10us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_dcache.wdo b/lib/CPUs/MIPS/sim/tb_mips_dcache.wdo
new file mode 100644
index 0000000..0953254
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_dcache.wdo
@@ -0,0 +1,263 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_dcache_tlb/clk
+add wave -noupdate -format Logic /tb_dcache_tlb/rst
+add wave -noupdate -format Logic /tb_dcache_tlb/int_o
+add wave -noupdate -format Logic /tb_dcache_tlb/cyc_o
+add wave -noupdate -format Logic /tb_dcache_tlb/stb_o
+add wave -noupdate -format Logic /tb_dcache_tlb/we_o
+add wave -noupdate -format Literal /tb_dcache_tlb/sel_o
+add wave -noupdate -format Logic /tb_dcache_tlb/ack_i
+add wave -noupdate -format Logic /tb_dcache_tlb/mrdy_o
+add wave -noupdate -format Logic /tb_dcache_tlb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/mdat_o
+add wave -noupdate -format Logic /tb_dcache_tlb/ce
+add wave -noupdate -format Literal /tb_dcache_tlb/index_in
+add wave -noupdate -format Logic /tb_dcache_tlb/entry_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/entry_lo_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/entry_hi_in
+add wave -noupdate -format Literal /tb_dcache_tlb/index_out
+add wave -noupdate -format Logic /tb_dcache_tlb/entry_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/entry_lo_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/entry_hi_out
+add wave -noupdate -format Literal /tb_dcache_tlb/tlb_index_hit
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/tlb_pa
+add wave -noupdate -format Literal -expand /tb_dcache_tlb/tlb_flags
+add wave -noupdate -format Logic /tb_dcache_tlb/tlb_hit
+add wave -noupdate -format Logic /tb_dcache_tlb/cpu_en
+add wave -noupdate -format Logic /tb_dcache_tlb/cpu_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/cpu_addr
+add wave -noupdate -format Literal /tb_dcache_tlb/cpu_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/cpu_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/cpu_dout
+add wave -noupdate -format Logic /tb_dcache_tlb/cpu_rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/dcache_ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/bus_din
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_din_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/bus_dout
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_dout_vld
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_dout_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_cmd_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_cmd_we
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_cmd_cycle_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/bus_cmd
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_cyc_complete
+add wave -noupdate -divider TLB
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_tlb/rst
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_tlb/clk
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_tlb/ce
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_tlb/index_in
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_tlb/entry_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_tlb/entry_lo_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_tlb/entry_hi_in
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_tlb/index_out
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_tlb/entry_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_tlb/entry_lo_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_tlb/entry_hi_out
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_tlb/tlb_blk_entry_we
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_tlb/tlb_blk_hit
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_tlb/tlb_blk_flags
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_tlb/tlb_blk_pfn
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_tlb/tlb_blk_entry_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_tlb/tlb_blk_entry_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_tlb/pa
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_tlb/hit
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_tlb/flags
+add wave -noupdate -divider D-Cache
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/rst
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/clk
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_dcache_tlb/inst_dcache/debug
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/cache_busy_state
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/cache_ctrl_state
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/cpu_din_reg
+add wave -noupdate -format Logic /tb_dcache_tlb/cpu_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/request_va
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/request_pa
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/cache_req_rd
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/cache_req_wr
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/single_read_en
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/single_read_set
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/single_read_reg_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/din
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/en
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/we
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/be
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/addr
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/tlb_exc
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/tlb_exc_type
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/cache_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/read_rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/dout
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/cache_hit
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/write_hit
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/cache_req_rd
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/cache_req_wr
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/we_reg
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/instant_raw
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/tag_match
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_dcache_tlb/inst_dcache/ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/bus_din
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/bus_din_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/bus_din_vld
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/bus_cmd_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/bus_cmd_we
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/bus_cmd_cycle_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/bus_cmd_out
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/bus_cyc_complete
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/cache_hit_inv
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/tag_match_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/cache_index_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/tag_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/tag_reg_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/cache_entry_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/cache_entry_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/cache_entry_out_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/data_ram_addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/data_ram_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/data_reg
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/be_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/ctrl_data_ram_addr
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/ctrl_data_ram_we
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/data_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/tag_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/tag_ram_dout
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/tag_ram_dout_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/tag_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/tag_ram_din
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/tag_ram_we
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/fill_count
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/fill_count_en
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/fill_count_rdy
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/flush_count
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/flush_count_rst
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/flush_count_en
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/flush_count_rdy
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_dcache/request_count
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/request_count_en
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/request_count_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/was_miss
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/invalidate_all
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/invalidate_ack
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/invalidate_en
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/invalidate_req
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/hit_cache_index
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/req_word_index
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/fill_word_index
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/inst_tag_ram/ram
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/write_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_dcache/write_fifo_dout
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/write_fifo_re
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/write_fifo_we
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/write_fifo_full
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/write_fifo_empty
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/write_data_avail
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/read_write_buffer
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_dcache/write_through_en
+add wave -noupdate -divider Bus-Master
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/clk
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/rst
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_cycle_finished
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_cycle_en
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_busmaster_sync/cmd_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_busmaster_sync/din
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/din_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/din_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_busmaster_sync/dout
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/dout_vld
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/dout_re
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/ack_i
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_busmaster_sync/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_busmaster_sync/mdat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_busmaster_sync/addr_o
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_busmaster_sync/sel_o
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/we_o
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cyc_o
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/stb_o
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/mrdy_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_busmaster_sync/cmd_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/inst_busmaster_sync/cmd_fifo_dout
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_fifo_re
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_fifo_we
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_fifo_full
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/read_fifo_re
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/read_fifo_we
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/read_fifo_full
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/read_fifo_empty
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/write_fifo_re
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/write_fifo_we
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/write_fifo_full
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/write_fifo_empty
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cycle_busy
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_en
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/cmd_read_en
+add wave -noupdate -format Literal /tb_dcache_tlb/inst_busmaster_sync/read_cnt
+add wave -noupdate -format Logic /tb_dcache_tlb/inst_busmaster_sync/write
+add wave -noupdate -format Logic /tb_dcache_tlb/clk
+add wave -noupdate -format Logic /tb_dcache_tlb/rst
+add wave -noupdate -format Logic /tb_dcache_tlb/int_o
+add wave -noupdate -format Logic /tb_dcache_tlb/cyc_o
+add wave -noupdate -format Logic /tb_dcache_tlb/stb_o
+add wave -noupdate -format Logic /tb_dcache_tlb/we_o
+add wave -noupdate -format Literal /tb_dcache_tlb/sel_o
+add wave -noupdate -format Logic /tb_dcache_tlb/ack_i
+add wave -noupdate -format Logic /tb_dcache_tlb/mrdy_o
+add wave -noupdate -format Logic /tb_dcache_tlb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/mdat_o
+add wave -noupdate -format Logic /tb_dcache_tlb/ce
+add wave -noupdate -format Literal /tb_dcache_tlb/index_in
+add wave -noupdate -format Logic /tb_dcache_tlb/entry_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/entry_lo_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/entry_hi_in
+add wave -noupdate -format Literal /tb_dcache_tlb/index_out
+add wave -noupdate -format Logic /tb_dcache_tlb/entry_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/entry_lo_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/entry_hi_out
+add wave -noupdate -format Literal /tb_dcache_tlb/tlb_index_hit
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/tlb_pa
+add wave -noupdate -format Literal -expand /tb_dcache_tlb/tlb_flags
+add wave -noupdate -format Logic /tb_dcache_tlb/tlb_hit
+add wave -noupdate -format Logic /tb_dcache_tlb/cpu_en
+add wave -noupdate -format Logic /tb_dcache_tlb/cpu_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/cpu_addr
+add wave -noupdate -format Literal /tb_dcache_tlb/cpu_be
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/cpu_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/cpu_dout
+add wave -noupdate -format Logic /tb_dcache_tlb/cpu_rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/dcache_ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/bus_din
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_din_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/bus_dout
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_dout_vld
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_dout_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_cmd_rdy
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_cmd_we
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_cmd_cycle_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_dcache_tlb/bus_cmd
+add wave -noupdate -format Logic /tb_dcache_tlb/bus_cyc_complete
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {743514 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {3533088 ps}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_icache.fdo b/lib/CPUs/MIPS/sim/tb_mips_icache.fdo
new file mode 100644
index 0000000..0c55ed6
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_icache.fdo
@@ -0,0 +1,45 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+vcom -explicit  -93 "../src/core/TLB/mips_util_pkg.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_types.vhd"
+vcom -explicit  -93 "../../../misc/utils_pkg.vhd"
+vcom -explicit  -93 "../../../JBUS/src/busmaster_types.vhd"
+
+# RAMS
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../../misc/ram_sim.vhd"
+vcom -explicit  -93 "../../../misc/ram_wb.vhd"
+vcom -explicit  -93 "../../../misc/rom_sim.vhd"
+vcom -explicit  -93 "../../../misc/rom_wb.vhd"
+
+
+# FIFOS
+vcom -explicit  -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd"
+vcom -explicit  -93 "../../../FIFO/src/gray_counter.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_sync.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async_ctrl.vhd"
+vcom -explicit  -93 "../../../FIFO/src/fifo_async.vhd"
+
+# MIPS Cache
+vcom -explicit  -93 "../src/core/TLB/mips_icache.vhd"
+
+# MIPS TLB
+vcom -explicit  -93 "../src/core/TLB/mips_tlb_block.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_tlb.vhd"
+
+# Busmaster
+vcom -explicit  -93 "../../../JBUS/src/busmaster_sync.vhd"
+vcom -explicit  -93 "../src/tb_mips_icache_tlb.vhd"
+
+vsim -t 1ps   -lib work tb_icache_tlb
+do {tb_mips_icache_tlb.wdo}
+view wave
+view structure
+view signals
+run 10us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_icache.wdo b/lib/CPUs/MIPS/sim/tb_mips_icache.wdo
new file mode 100644
index 0000000..5a607bf
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_icache.wdo
@@ -0,0 +1,162 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_icache_tlb/clk
+add wave -noupdate -format Logic /tb_icache_tlb/rst
+add wave -noupdate -format Logic /tb_icache_tlb/int_o
+add wave -noupdate -format Logic /tb_icache_tlb/cyc_o
+add wave -noupdate -format Logic /tb_icache_tlb/stb_o
+add wave -noupdate -format Logic /tb_icache_tlb/we_o
+add wave -noupdate -format Literal /tb_icache_tlb/sel_o
+add wave -noupdate -format Logic /tb_icache_tlb/ack_i
+add wave -noupdate -format Logic /tb_icache_tlb/mrdy_o
+add wave -noupdate -format Logic /tb_icache_tlb/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/addr_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/mdat_o
+add wave -noupdate -divider TLB
+add wave -noupdate -format Logic /tb_icache_tlb/inst_tlb/rst
+add wave -noupdate -format Logic /tb_icache_tlb/inst_tlb/clk
+add wave -noupdate -format Logic /tb_icache_tlb/inst_tlb/ce
+add wave -noupdate -format Literal /tb_icache_tlb/inst_tlb/index_in
+add wave -noupdate -format Logic /tb_icache_tlb/inst_tlb/entry_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_tlb/entry_lo_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_tlb/entry_hi_in
+add wave -noupdate -format Literal /tb_icache_tlb/inst_tlb/index_out
+add wave -noupdate -format Logic /tb_icache_tlb/inst_tlb/entry_re
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_tlb/entry_lo_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_tlb/entry_hi_out
+add wave -noupdate -format Literal /tb_icache_tlb/inst_tlb/tlb_blk_entry_we
+add wave -noupdate -format Literal /tb_icache_tlb/inst_tlb/tlb_blk_hit
+add wave -noupdate -format Literal /tb_icache_tlb/inst_tlb/tlb_blk_flags
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_tlb/tlb_blk_pfn
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_tlb/tlb_blk_entry_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_tlb/tlb_blk_entry_hi
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_tlb/pa
+add wave -noupdate -format Logic /tb_icache_tlb/inst_tlb/hit
+add wave -noupdate -format Literal /tb_icache_tlb/inst_tlb/flags
+add wave -noupdate -divider I-Cache
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/rst
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/clk
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/cpu_din_reg
+add wave -noupdate -format Logic /tb_icache_tlb/cpu_din_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/request_va
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/request_pa
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/cache_req_rd
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/cache_hit
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/en
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/read_rdy
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/dout
+add wave -noupdate -format Literal /tb_icache_tlb/inst_icache/cache_busy_state
+add wave -noupdate -format Literal /tb_icache_tlb/inst_icache/cache_ctrl_state
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/single_read_reg_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/single_read_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/ctrl_in
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/tag_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/cache_entry_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/cache_entry_out
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/bus_din
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/bus_din_rdy
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/bus_din_vld
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/bus_cmd_rdy
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/bus_cmd_we
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/bus_cmd_cycle_en
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/bus_cmd_out
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/bus_cyc_complete
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/cache_rdy
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/tag_match
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/tag_match_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/cache_index_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/tag_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/tag_reg_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/cache_entry_out_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/data_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/data_ram_data_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/data_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/data_ram_data_wr
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/data_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/tag_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/tag_ram_data_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/tag_ram_data_rd_inv
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/tag_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/tag_ram_data_wr
+add wave -noupdate -format Literal /tb_icache_tlb/inst_icache/fill_count
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/fill_count_en
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/fill_count_rdy
+add wave -noupdate -format Literal /tb_icache_tlb/inst_icache/flush_count
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/flush_count_rst
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/flush_count_en
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/flush_count_rdy
+add wave -noupdate -format Literal /tb_icache_tlb/inst_icache/request_count
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/request_count_en
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/request_count_rdy
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/ram_read_en
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/was_miss
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/invalidate_all
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/invalidate_ack
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/invalidate_en
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/invalidate_req
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/req_word_index
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_icache/fill_word_index
+add wave -noupdate -format Logic /tb_icache_tlb/inst_icache/tlb_exc
+add wave -noupdate -format Literal /tb_icache_tlb/inst_icache/tlb_exc_type
+add wave -noupdate -divider Busmaster
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/clk
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/rst
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_cycle_finished
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_cycle_en
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_rdy
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_busmaster_sync/cmd_in
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_busmaster_sync/din
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/din_rdy
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/din_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_busmaster_sync/dout
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/dout_vld
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/dout_re
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/ack_i
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/srdy_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_busmaster_sync/mdat_i
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_busmaster_sync/mdat_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_busmaster_sync/addr_o
+add wave -noupdate -format Literal /tb_icache_tlb/inst_busmaster_sync/sel_o
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/we_o
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cyc_o
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/stb_o
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/mrdy_o
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_busmaster_sync/cmd_fifo_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_icache_tlb/inst_busmaster_sync/cmd_fifo_dout
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_fifo_re
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_fifo_we
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_fifo_full
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_fifo_empty
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/read_fifo_re
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/read_fifo_we
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/read_fifo_full
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/read_fifo_empty
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/write_fifo_re
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/write_fifo_we
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/write_fifo_full
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/write_fifo_empty
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cycle_busy
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_en
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/cmd_read_en
+add wave -noupdate -format Literal /tb_icache_tlb/inst_busmaster_sync/read_cnt
+add wave -noupdate -format Logic /tb_icache_tlb/inst_busmaster_sync/write
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1549212 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {1322906 ps} {1804473 ps}
diff --git a/lib/CPUs/MIPS/sim/tb_mips_tlb.fdo b/lib/CPUs/MIPS/sim/tb_mips_tlb.fdo
new file mode 100644
index 0000000..9373009
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_tlb.fdo
@@ -0,0 +1,29 @@
+## NOTE:  Do not edit this file.
+##
+vlib work
+
+# RAMS
+vcom -explicit  -93 "../../../rams/dpram_1w1r1wc_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ra_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_2w2r2c_ro_sim.vhd"
+vcom -explicit  -93 "../../../rams/dpram_1w1r2c_ro_sim.vhd"
+
+
+# FIFOS
+
+# MIPS
+vcom -explicit  -93 "../src/core/TLB/mips_types.vhd"
+vcom -explicit  -93 "../src/core/mips_reg.vhd"
+#vcom -explicit  -93 "../src/core/TLB/mips_tlb_block.vhd"
+#vcom -explicit  -93 "../src/core/TLB/mips_tlb_20130811.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_cam2.vhd"
+vcom -explicit  -93 "../src/core/TLB/mips_tlb.vhd"
+
+vcom -explicit  -93 "../src/tb_mips_tlb.vhd"
+vsim -t 1ps   -lib work tb_tlb
+do {tb_mips_tlb.wdo}
+view wave
+view structure
+view signals
+run 200us
diff --git a/lib/CPUs/MIPS/sim/tb_mips_tlb.wdo b/lib/CPUs/MIPS/sim/tb_mips_tlb.wdo
new file mode 100644
index 0000000..a5e53b8
--- /dev/null
+++ b/lib/CPUs/MIPS/sim/tb_mips_tlb.wdo
@@ -0,0 +1,74 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -format Logic /tb_tlb/clk_o
+add wave -noupdate -format Logic /tb_tlb/rst_o
+add wave -noupdate -format Logic /tb_tlb/ce
+add wave -noupdate -format Logic /tb_tlb/tlb_rdy
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/tlb_ctrl_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_tlb/tlb_ctrl_out
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_tlb/tlb_query_in
+add wave -noupdate -format Literal -radix hexadecimal -expand /tb_tlb/tlb_query_out
+add wave -noupdate -divider TLB
+add wave -noupdate -format Literal /tb_tlb/inst_uut/hit_idx
+add wave -noupdate -format Literal /tb_tlb/inst_uut/num_entries
+add wave -noupdate -format Logic /tb_tlb/inst_uut/rst
+add wave -noupdate -format Logic /tb_tlb/inst_uut/clk
+add wave -noupdate -format Literal /tb_tlb/inst_uut/blk_hit
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/blk_entry_lo
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/qry_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/stat_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/pa
+add wave -noupdate -format Logic /tb_tlb/inst_uut/cam_hit_vld
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/vaddr_reg
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/entry_lo_res
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/entry_lo_umc
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/entry_lo_umuc
+add wave -noupdate -divider REG:LO
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_reg_entry_lo/dout_b
+add wave -noupdate -divider CAM
+add wave -noupdate -format Logic /tb_tlb/inst_uut/clk
+add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/state
+add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/state_next
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/tag_wr
+add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/addr
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/tag_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe0
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe1
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe2
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe3
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe0_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe1_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe2_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/pipe3_rd
+add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/busy
+add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/cam_ram_re
+add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/cam_ram_we
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/cam_ram_addr_wr
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/cam_ram_addr_rd
+add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/track_ram_re
+add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/track_ram_we
+add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/track_ram_addr_wr
+add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/track_ram_addr_rd
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/track_ram_din
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/track_ram_dout
+add wave -noupdate -format Literal /tb_tlb/inst_uut/inst_cam_va/clear_addr
+add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/clear_count_en
+add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/clear_count_rdy
+add wave -noupdate -format Logic /tb_tlb/inst_uut/inst_cam_va/over_write
+add wave -noupdate -format Literal -radix hexadecimal /tb_tlb/inst_uut/inst_cam_va/inst_track_ram/ram
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3385000 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 111
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+update
+WaveRestoreZoom {0 ps} {10940666 ps}
diff --git a/lib/CPUs/MIPS/src/bootloader_flash.ROM.vhd b/lib/CPUs/MIPS/src/bootloader_flash.ROM.vhd
new file mode 100644
index 0000000..f616d56
--- /dev/null
+++ b/lib/CPUs/MIPS/src/bootloader_flash.ROM.vhd
@@ -0,0 +1,2082 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY rom IS
+	Port
+	(
+		clk		: in  STD_LOGIC;
+		ce		: in  STD_LOGIC;
+		addr		: in  unsigned(31 downto 0);
+		dout		: out unsigned(31 downto 0)
+	);
+END rom;
+
+ARCHITECTURE data OF rom IS
+
+	subtype word_t is unsigned(31 downto 0);
+	type word_array_t is array (0 to 2047) of word_t;
+	constant word_array : word_array_t :=
+	(
+
+		X"3C1D8400", -- 00000000
+		X"27BDEFF0", -- 00000004
+		X"3C1A1040", -- 00000008
+		X"375A000A", -- 0000000C
+		X"409A6000", -- 00000010
+		X"241A0000", -- 00000014
+		X"409A6800", -- 00000018
+		X"401A7800", -- 0000001C
+		X"00000000", -- 00000020
+		X"409AF800", -- 00000024
+		X"42000020", -- 00000028
+		X"42000022", -- 0000002C
+		X"3C1A9FC0", -- 00000030
+		X"275A005C", -- 00000034
+		X"0340F809", -- 00000038
+		X"00000000", -- 0000003C
+		X"3C1A9FC0", -- 00000040
+		X"275A1150", -- 00000044
+		X"0340F809", -- 00000048
+		X"00000000", -- 0000004C
+		X"00000000", -- 00000050
+		X"0BF00014", -- 00000054
+		X"00000000", -- 00000058
+		X"3C1AAC01", -- 0000005C
+		X"275A0008", -- 00000060
+		X"241B000D", -- 00000064
+		X"AF5B0000", -- 00000068
+		X"03E00008", -- 0000006C
+		X"00000000", -- 00000070
+		X"00000000", -- 00000074
+		X"00000000", -- 00000078
+		X"00000000", -- 0000007C
+		X"00000000", -- 00000080
+		X"00000000", -- 00000084
+		X"00000000", -- 00000088
+		X"00000000", -- 0000008C
+		X"00000000", -- 00000090
+		X"00000000", -- 00000094
+		X"00000000", -- 00000098
+		X"00000000", -- 0000009C
+		X"00000000", -- 000000A0
+		X"00000000", -- 000000A4
+		X"00000000", -- 000000A8
+		X"00000000", -- 000000AC
+		X"00000000", -- 000000B0
+		X"00000000", -- 000000B4
+		X"00000000", -- 000000B8
+		X"00000000", -- 000000BC
+		X"00000000", -- 000000C0
+		X"00000000", -- 000000C4
+		X"00000000", -- 000000C8
+		X"00000000", -- 000000CC
+		X"00000000", -- 000000D0
+		X"00000000", -- 000000D4
+		X"00000000", -- 000000D8
+		X"00000000", -- 000000DC
+		X"00000000", -- 000000E0
+		X"00000000", -- 000000E4
+		X"00000000", -- 000000E8
+		X"00000000", -- 000000EC
+		X"00000000", -- 000000F0
+		X"00000000", -- 000000F4
+		X"00000000", -- 000000F8
+		X"00000000", -- 000000FC
+		X"00000000", -- 00000100
+		X"00000000", -- 00000104
+		X"00000000", -- 00000108
+		X"00000000", -- 0000010C
+		X"00000000", -- 00000110
+		X"00000000", -- 00000114
+		X"00000000", -- 00000118
+		X"00000000", -- 0000011C
+		X"00000000", -- 00000120
+		X"00000000", -- 00000124
+		X"00000000", -- 00000128
+		X"00000000", -- 0000012C
+		X"00000000", -- 00000130
+		X"00000000", -- 00000134
+		X"00000000", -- 00000138
+		X"00000000", -- 0000013C
+		X"00000000", -- 00000140
+		X"00000000", -- 00000144
+		X"00000000", -- 00000148
+		X"00000000", -- 0000014C
+		X"00000000", -- 00000150
+		X"00000000", -- 00000154
+		X"00000000", -- 00000158
+		X"00000000", -- 0000015C
+		X"00000000", -- 00000160
+		X"00000000", -- 00000164
+		X"00000000", -- 00000168
+		X"00000000", -- 0000016C
+		X"00000000", -- 00000170
+		X"00000000", -- 00000174
+		X"00000000", -- 00000178
+		X"00000000", -- 0000017C
+		X"401A6800", -- 00000180
+		X"3C1BC000", -- 00000184
+		X"001AD082", -- 00000188
+		X"335A000F", -- 0000018C
+		X"035BD025", -- 00000190
+		X"3C1BAC00", -- 00000194
+		X"277B0000", -- 00000198
+		X"AF7A0000", -- 0000019C
+		X"401A6800", -- 000001A0
+		X"00000000", -- 000001A4
+		X"001AD202", -- 000001A8
+		X"335A00FF", -- 000001AC
+		X"1740FFFB", -- 000001B0
+		X"00000000", -- 000001B4
+		X"401A7000", -- 000001B8
+		X"00000000", -- 000001BC
+		X"03400008", -- 000001C0
+		X"42000010", -- 000001C4
+		X"40026000", -- 000001C8
+		X"03E00008", -- 000001CC
+		X"00000000", -- 000001D0
+		X"40846000", -- 000001D4
+		X"03E00008", -- 000001D8
+		X"00000000", -- 000001DC
+		X"40026800", -- 000001E0
+		X"03E00008", -- 000001E4
+		X"00000000", -- 000001E8
+		X"40846800", -- 000001EC
+		X"03E00008", -- 000001F0
+		X"00000000", -- 000001F4
+		X"40027800", -- 000001F8
+		X"03E00008", -- 000001FC
+		X"00000000", -- 00000200
+		X"3C02AC01", -- 00000204
+		X"34430004", -- 00000208
+		X"8C620000", -- 0000020C
+		X"00000000", -- 00000210
+		X"30420010", -- 00000214
+		X"1040FFFC", -- 00000218
+		X"3C02AC01", -- 0000021C
+		X"8C420000", -- 00000220
+		X"00000000", -- 00000224
+		X"00021600", -- 00000228
+		X"03E00008", -- 0000022C
+		X"00021603", -- 00000230
+		X"00042600", -- 00000234
+		X"3C02AC01", -- 00000238
+		X"00042603", -- 0000023C
+		X"34430004", -- 00000240
+		X"8C620000", -- 00000244
+		X"00000000", -- 00000248
+		X"30420002", -- 0000024C
+		X"1440FFFC", -- 00000250
+		X"3C02AC01", -- 00000254
+		X"AC440000", -- 00000258
+		X"03E00008", -- 0000025C
+		X"00000000", -- 00000260
+		X"00042600", -- 00000264
+		X"00042603", -- 00000268
+		X"2402000A", -- 0000026C
+		X"1482000A", -- 00000270
+		X"3C02AC01", -- 00000274
+		X"34430004", -- 00000278
+		X"8C620000", -- 0000027C
+		X"00000000", -- 00000280
+		X"30420002", -- 00000284
+		X"1440FFFC", -- 00000288
+		X"3C02AC01", -- 0000028C
+		X"2403000D", -- 00000290
+		X"AC430000", -- 00000294
+		X"3C02AC01", -- 00000298
+		X"34430004", -- 0000029C
+		X"8C620000", -- 000002A0
+		X"00000000", -- 000002A4
+		X"30420002", -- 000002A8
+		X"1440FFFC", -- 000002AC
+		X"3C02AC01", -- 000002B0
+		X"AC440000", -- 000002B4
+		X"03E00008", -- 000002B8
+		X"00000000", -- 000002BC
+		X"3C02AC01", -- 000002C0
+		X"34470004", -- 000002C4
+		X"00802821", -- 000002C8
+		X"2409000A", -- 000002CC
+		X"3C06AC01", -- 000002D0
+		X"0BF000C6", -- 000002D4
+		X"2408000D", -- 000002D8
+		X"14690007", -- 000002DC
+		X"00000000", -- 000002E0
+		X"8CE20000", -- 000002E4
+		X"00000000", -- 000002E8
+		X"30420002", -- 000002EC
+		X"1440FFFC", -- 000002F0
+		X"00000000", -- 000002F4
+		X"ACC80000", -- 000002F8
+		X"8CE20000", -- 000002FC
+		X"00000000", -- 00000300
+		X"30420002", -- 00000304
+		X"1440FFFC", -- 00000308
+		X"00000000", -- 0000030C
+		X"ACC30000", -- 00000310
+		X"24A50001", -- 00000314
+		X"80A30000", -- 00000318
+		X"00000000", -- 0000031C
+		X"1460FFEE", -- 00000320
+		X"00A41023", -- 00000324
+		X"03E00008", -- 00000328
+		X"00000000", -- 0000032C
+		X"00042600", -- 00000330
+		X"3C02AC01", -- 00000334
+		X"00042603", -- 00000338
+		X"344A0004", -- 0000033C
+		X"00003821", -- 00000340
+		X"3C09AC01", -- 00000344
+		X"24080002", -- 00000348
+		X"308200FF", -- 0000034C
+		X"00022902", -- 00000350
+		X"00041100", -- 00000354
+		X"00022600", -- 00000358
+		X"2CA3000A", -- 0000035C
+		X"00042603", -- 00000360
+		X"14600002", -- 00000364
+		X"24A60030", -- 00000368
+		X"24A60037", -- 0000036C
+		X"8D420000", -- 00000370
+		X"00000000", -- 00000374
+		X"30420002", -- 00000378
+		X"1440FFFC", -- 0000037C
+		X"00061600", -- 00000380
+		X"00021603", -- 00000384
+		X"24E70001", -- 00000388
+		X"AD220000", -- 0000038C
+		X"14E8FFEF", -- 00000390
+		X"308200FF", -- 00000394
+		X"03E00008", -- 00000398
+		X"00000000", -- 0000039C
+		X"27BDFFE0", -- 000003A0
+		X"AFB20018", -- 000003A4
+		X"AFB10014", -- 000003A8
+		X"AFB00010", -- 000003AC
+		X"AFBF001C", -- 000003B0
+		X"00808821", -- 000003B4
+		X"00008021", -- 000003B8
+		X"24120004", -- 000003BC
+		X"00112603", -- 000003C0
+		X"0FF000CC", -- 000003C4
+		X"26100001", -- 000003C8
+		X"1612FFFC", -- 000003CC
+		X"00118A00", -- 000003D0
+		X"8FBF001C", -- 000003D4
+		X"8FB20018", -- 000003D8
+		X"8FB10014", -- 000003DC
+		X"8FB00010", -- 000003E0
+		X"03E00008", -- 000003E4
+		X"27BD0020", -- 000003E8
+		X"27BDFFC8", -- 000003EC
+		X"AFB60028", -- 000003F0
+		X"AFBF0034", -- 000003F4
+		X"AFBE0030", -- 000003F8
+		X"AFB7002C", -- 000003FC
+		X"AFB50024", -- 00000400
+		X"AFB40020", -- 00000404
+		X"AFB3001C", -- 00000408
+		X"AFB20018", -- 0000040C
+		X"AFB10014", -- 00000410
+		X"AFB00010", -- 00000414
+		X"00801021", -- 00000418
+		X"10A00002", -- 0000041C
+		X"00C0B021", -- 00000420
+		X"00002021", -- 00000424
+		X"00409821", -- 00000428
+		X"3C02AC01", -- 0000042C
+		X"00E09021", -- 00000430
+		X"0080A821", -- 00000434
+		X"345E0004", -- 00000438
+		X"00E0A021", -- 0000043C
+		X"3C17AC01", -- 00000440
+		X"0FF000E8", -- 00000444
+		X"02A02021", -- 00000448
+		X"3C049FC0", -- 0000044C
+		X"0FF000B0", -- 00000450
+		X"248416A0", -- 00000454
+		X"02608821", -- 00000458
+		X"0BF00128", -- 0000045C
+		X"00008021", -- 00000460
+		X"12400009", -- 00000464
+		X"00000000", -- 00000468
+		X"82240000", -- 0000046C
+		X"0FF000CC", -- 00000470
+		X"2652FFFF", -- 00000474
+		X"3C049FC0", -- 00000478
+		X"0FF000B0", -- 0000047C
+		X"24841778", -- 00000480
+		X"0BF00128", -- 00000484
+		X"26310001", -- 00000488
+		X"3C049FC0", -- 0000048C
+		X"0FF000B0", -- 00000490
+		X"248416A4", -- 00000494
+		X"0BF0012C", -- 00000498
+		X"3C049FC0", -- 0000049C
+		X"0216102A", -- 000004A0
+		X"1440FFEF", -- 000004A4
+		X"26100001", -- 000004A8
+		X"3C049FC0", -- 000004AC
+		X"0FF000B0", -- 000004B0
+		X"248416A4", -- 000004B4
+		X"02602821", -- 000004B8
+		X"0BF00155", -- 000004BC
+		X"00002021", -- 000004C0
+		X"1280001E", -- 000004C4
+		X"00000000", -- 000004C8
+		X"90A30000", -- 000004CC
+		X"00000000", -- 000004D0
+		X"2462FFE0", -- 000004D4
+		X"304200FF", -- 000004D8
+		X"2C420060", -- 000004DC
+		X"14400003", -- 000004E0
+		X"00031E00", -- 000004E4
+		X"2403002E", -- 000004E8
+		X"00031E00", -- 000004EC
+		X"00031E03", -- 000004F0
+		X"2402000A", -- 000004F4
+		X"14620007", -- 000004F8
+		X"00000000", -- 000004FC
+		X"8FC20000", -- 00000500
+		X"00000000", -- 00000504
+		X"30420002", -- 00000508
+		X"1440FFFC", -- 0000050C
+		X"2402000D", -- 00000510
+		X"AEE20000", -- 00000514
+		X"8FC20000", -- 00000518
+		X"00000000", -- 0000051C
+		X"30420002", -- 00000520
+		X"1440FFFC", -- 00000524
+		X"00000000", -- 00000528
+		X"AEE30000", -- 0000052C
+		X"2694FFFF", -- 00000530
+		X"24840001", -- 00000534
+		X"0BF00155", -- 00000538
+		X"24A50001", -- 0000053C
+		X"3C049FC0", -- 00000540
+		X"0FF000B0", -- 00000544
+		X"24841778", -- 00000548
+		X"0BF00159", -- 0000054C
+		X"3C049FC0", -- 00000550
+		X"0096102A", -- 00000554
+		X"1440FFDA", -- 00000558
+		X"00000000", -- 0000055C
+		X"3C049FC0", -- 00000560
+		X"0FF000B0", -- 00000564
+		X"248416CC", -- 00000568
+		X"02B6A821", -- 0000056C
+		X"1640FFB4", -- 00000570
+		X"02769821", -- 00000574
+		X"8FBF0034", -- 00000578
+		X"8FBE0030", -- 0000057C
+		X"8FB7002C", -- 00000580
+		X"8FB60028", -- 00000584
+		X"8FB50024", -- 00000588
+		X"8FB40020", -- 0000058C
+		X"8FB3001C", -- 00000590
+		X"8FB20018", -- 00000594
+		X"8FB10014", -- 00000598
+		X"8FB00010", -- 0000059C
+		X"03E00008", -- 000005A0
+		X"27BD0038", -- 000005A4
+		X"00C03821", -- 000005A8
+		X"00A03021", -- 000005AC
+		X"0BF000FB", -- 000005B0
+		X"24050001", -- 000005B4
+		X"8C840000", -- 000005B8
+		X"3C020070", -- 000005BC
+		X"34420070", -- 000005C0
+		X"3C0300FF", -- 000005C4
+		X"AC820000", -- 000005C8
+		X"346300FF", -- 000005CC
+		X"8C820000", -- 000005D0
+		X"AC830000", -- 000005D4
+		X"03E00008", -- 000005D8
+		X"00000000", -- 000005DC
+		X"27BDFFF8", -- 000005E0
+		X"AC850000", -- 000005E4
+		X"24820008", -- 000005E8
+		X"0BF0017F", -- 000005EC
+		X"24830020", -- 000005F0
+		X"A0400000", -- 000005F4
+		X"24420001", -- 000005F8
+		X"1443FFFD", -- 000005FC
+		X"00000000", -- 00000600
+		X"24020001", -- 00000604
+		X"AC820004", -- 00000608
+		X"03E00008", -- 0000060C
+		X"27BD0008", -- 00000610
+		X"8C870000", -- 00000614
+		X"3C020098", -- 00000618
+		X"34420098", -- 0000061C
+		X"ACE20000", -- 00000620
+		X"3C0200FF", -- 00000624
+		X"344200FF", -- 00000628
+		X"ACE20000", -- 0000062C
+		X"3C020090", -- 00000630
+		X"34420090", -- 00000634
+		X"ACE20000", -- 00000638
+		X"00804021", -- 0000063C
+		X"94E4009C", -- 00000640
+		X"24030002", -- 00000644
+		X"24020020", -- 00000648
+		X"AD030008", -- 0000064C
+		X"AD03001C", -- 00000650
+		X"AD020018", -- 00000654
+		X"3084FFFF", -- 00000658
+		X"0BF0019D", -- 0000065C
+		X"00001821", -- 00000660
+		X"8D020008", -- 00000664
+		X"00000000", -- 00000668
+		X"00021040", -- 0000066C
+		X"AD020008", -- 00000670
+		X"0064102B", -- 00000674
+		X"1440FFFA", -- 00000678
+		X"24630001", -- 0000067C
+		X"94E200AC", -- 00000680
+		X"94E300A8", -- 00000684
+		X"3042FFFF", -- 00000688
+		X"8D04001C", -- 0000068C
+		X"3063FFFF", -- 00000690
+		X"00021200", -- 00000694
+		X"00432825", -- 00000698
+		X"AD040014", -- 0000069C
+		X"0BF001AE", -- 000006A0
+		X"00001821", -- 000006A4
+		X"8D020014", -- 000006A8
+		X"00000000", -- 000006AC
+		X"00021040", -- 000006B0
+		X"AD020014", -- 000006B4
+		X"0065102B", -- 000006B8
+		X"1440FFFA", -- 000006BC
+		X"24630001", -- 000006C0
+		X"94E300B8", -- 000006C4
+		X"94E600B4", -- 000006C8
+		X"94E200C0", -- 000006CC
+		X"94E400BC", -- 000006D0
+		X"8D05001C", -- 000006D4
+		X"3042FFFF", -- 000006D8
+		X"3084FFFF", -- 000006DC
+		X"00021200", -- 000006E0
+		X"00441025", -- 000006E4
+		X"00052A00", -- 000006E8
+		X"00A20018", -- 000006EC
+		X"3063FFFF", -- 000006F0
+		X"30C6FFFF", -- 000006F4
+		X"00031A00", -- 000006F8
+		X"00661825", -- 000006FC
+		X"24630001", -- 00000700
+		X"AD030010", -- 00000704
+		X"3C0300FF", -- 00000708
+		X"346300FF", -- 0000070C
+		X"00001021", -- 00000710
+		X"00002812", -- 00000714
+		X"AD05000C", -- 00000718
+		X"ACE30000", -- 0000071C
+		X"03E00008", -- 00000720
+		X"00000000", -- 00000724
+		X"8C820008", -- 00000728
+		X"8C860000", -- 0000072C
+		X"00021082", -- 00000730
+		X"00A2102B", -- 00000734
+		X"14400004", -- 00000738
+		X"3C030090", -- 0000073C
+		X"3C028010", -- 00000740
+		X"03E00008", -- 00000744
+		X"34420002", -- 00000748
+		X"8C820010", -- 0000074C
+		X"00000000", -- 00000750
+		X"2442FFFF", -- 00000754
+		X"00021400", -- 00000758
+		X"00A21024", -- 0000075C
+		X"24420002", -- 00000760
+		X"34630090", -- 00000764
+		X"00021080", -- 00000768
+		X"ACC30000", -- 0000076C
+		X"00C21021", -- 00000770
+		X"8C430000", -- 00000774
+		X"3C020001", -- 00000778
+		X"34420001", -- 0000077C
+		X"00621824", -- 00000780
+		X"3C0200FF", -- 00000784
+		X"344200FF", -- 00000788
+		X"ACC20000", -- 0000078C
+		X"03E00008", -- 00000790
+		X"0003102B", -- 00000794
+		X"8C820008", -- 00000798
+		X"00A01821", -- 0000079C
+		X"00021082", -- 000007A0
+		X"00A2102B", -- 000007A4
+		X"8C850000", -- 000007A8
+		X"14400003", -- 000007AC
+		X"3C028010", -- 000007B0
+		X"0BF0020C", -- 000007B4
+		X"34430002", -- 000007B8
+		X"8C820010", -- 000007BC
+		X"00000000", -- 000007C0
+		X"2442FFFF", -- 000007C4
+		X"00021400", -- 000007C8
+		X"00621024", -- 000007CC
+		X"00021080", -- 000007D0
+		X"00A22021", -- 000007D4
+		X"3C020020", -- 000007D8
+		X"34420020", -- 000007DC
+		X"AC820000", -- 000007E0
+		X"3C0200D0", -- 000007E4
+		X"344200D0", -- 000007E8
+		X"AC820000", -- 000007EC
+		X"3C020080", -- 000007F0
+		X"34430080", -- 000007F4
+		X"8C860000", -- 000007F8
+		X"00000000", -- 000007FC
+		X"00C31024", -- 00000800
+		X"1443FFFC", -- 00000804
+		X"3C02002A", -- 00000808
+		X"3442002A", -- 0000080C
+		X"00C21024", -- 00000810
+		X"10400003", -- 00000814
+		X"00001821", -- 00000818
+		X"3C029010", -- 0000081C
+		X"00C21825", -- 00000820
+		X"3C0200FF", -- 00000824
+		X"344200FF", -- 00000828
+		X"AC820000", -- 0000082C
+		X"03E00008", -- 00000830
+		X"00601021", -- 00000834
+		X"8C820008", -- 00000838
+		X"00A01821", -- 0000083C
+		X"00021082", -- 00000840
+		X"00A2102B", -- 00000844
+		X"8C850000", -- 00000848
+		X"14400003", -- 0000084C
+		X"3C028010", -- 00000850
+		X"0BF00234", -- 00000854
+		X"34430002", -- 00000858
+		X"8C820010", -- 0000085C
+		X"00000000", -- 00000860
+		X"2442FFFF", -- 00000864
+		X"00021400", -- 00000868
+		X"00621024", -- 0000086C
+		X"00021080", -- 00000870
+		X"00A22021", -- 00000874
+		X"3C020060", -- 00000878
+		X"34420060", -- 0000087C
+		X"AC820000", -- 00000880
+		X"3C020001", -- 00000884
+		X"34420001", -- 00000888
+		X"AC820000", -- 0000088C
+		X"3C020080", -- 00000890
+		X"34430080", -- 00000894
+		X"8C860000", -- 00000898
+		X"00000000", -- 0000089C
+		X"00C31024", -- 000008A0
+		X"1443FFFC", -- 000008A4
+		X"3C020038", -- 000008A8
+		X"34420038", -- 000008AC
+		X"00C21024", -- 000008B0
+		X"10400003", -- 000008B4
+		X"00001821", -- 000008B8
+		X"3C029010", -- 000008BC
+		X"00C21825", -- 000008C0
+		X"3C0200FF", -- 000008C4
+		X"344200FF", -- 000008C8
+		X"AC820000", -- 000008CC
+		X"03E00008", -- 000008D0
+		X"00601021", -- 000008D4
+		X"8C820008", -- 000008D8
+		X"00A01821", -- 000008DC
+		X"00021082", -- 000008E0
+		X"00A2102B", -- 000008E4
+		X"8C850000", -- 000008E8
+		X"14400003", -- 000008EC
+		X"3C028010", -- 000008F0
+		X"0BF0025C", -- 000008F4
+		X"34430002", -- 000008F8
+		X"8C820010", -- 000008FC
+		X"00000000", -- 00000900
+		X"2442FFFF", -- 00000904
+		X"00021400", -- 00000908
+		X"00621024", -- 0000090C
+		X"00021080", -- 00000910
+		X"00A22021", -- 00000914
+		X"3C020060", -- 00000918
+		X"34420060", -- 0000091C
+		X"AC820000", -- 00000920
+		X"3C0200D0", -- 00000924
+		X"344200D0", -- 00000928
+		X"AC820000", -- 0000092C
+		X"3C020080", -- 00000930
+		X"34430080", -- 00000934
+		X"8C860000", -- 00000938
+		X"00000000", -- 0000093C
+		X"00C31024", -- 00000940
+		X"1443FFFC", -- 00000944
+		X"3C020038", -- 00000948
+		X"34420038", -- 0000094C
+		X"00C21024", -- 00000950
+		X"10400003", -- 00000954
+		X"00001821", -- 00000958
+		X"3C029010", -- 0000095C
+		X"00C21825", -- 00000960
+		X"3C0200FF", -- 00000964
+		X"344200FF", -- 00000968
+		X"AC820000", -- 0000096C
+		X"03E00008", -- 00000970
+		X"00601021", -- 00000974
+		X"8C820008", -- 00000978
+		X"8C840000", -- 0000097C
+		X"00021082", -- 00000980
+		X"00A2102B", -- 00000984
+		X"14400003", -- 00000988
+		X"3C028010", -- 0000098C
+		X"0BF0027C", -- 00000990
+		X"34430002", -- 00000994
+		X"00051080", -- 00000998
+		X"00822021", -- 0000099C
+		X"3C020040", -- 000009A0
+		X"34420040", -- 000009A4
+		X"AC820000", -- 000009A8
+		X"3C020080", -- 000009AC
+		X"AC860000", -- 000009B0
+		X"34430080", -- 000009B4
+		X"8C860000", -- 000009B8
+		X"00000000", -- 000009BC
+		X"00C31024", -- 000009C0
+		X"1443FFFC", -- 000009C4
+		X"3C02001A", -- 000009C8
+		X"3442001A", -- 000009CC
+		X"00C21024", -- 000009D0
+		X"10400003", -- 000009D4
+		X"00001821", -- 000009D8
+		X"3C029010", -- 000009DC
+		X"00C21825", -- 000009E0
+		X"3C0200FF", -- 000009E4
+		X"344200FF", -- 000009E8
+		X"AC820000", -- 000009EC
+		X"03E00008", -- 000009F0
+		X"00601021", -- 000009F4
+		X"8C820008", -- 000009F8
+		X"27BDFFE8", -- 000009FC
+		X"00021082", -- 00000A00
+		X"00A2102B", -- 00000A04
+		X"AFB40014", -- 00000A08
+		X"AFB30010", -- 00000A0C
+		X"AFB2000C", -- 00000A10
+		X"AFB10008", -- 00000A14
+		X"AFB00004", -- 00000A18
+		X"0080C021", -- 00000A1C
+		X"8C8E0000", -- 00000A20
+		X"14400004", -- 00000A24
+		X"00C0A021", -- 00000A28
+		X"3C028010", -- 00000A2C
+		X"0BF002E3", -- 00000A30
+		X"34440002", -- 00000A34
+		X"8C820010", -- 00000A38
+		X"00006821", -- 00000A3C
+		X"2442FFFF", -- 00000A40
+		X"0002CC00", -- 00000A44
+		X"3C0200E8", -- 00000A48
+		X"345300E8", -- 00000A4C
+		X"3C020080", -- 00000A50
+		X"344F0080", -- 00000A54
+		X"3C02001A", -- 00000A58
+		X"3446001A", -- 00000A5C
+		X"3C0200D0", -- 00000A60
+		X"345200D0", -- 00000A64
+		X"3C0200FF", -- 00000A68
+		X"345100FF", -- 00000A6C
+		X"0BF002E1", -- 00000A70
+		X"3C100001", -- 00000A74
+		X"01851023", -- 00000A78
+		X"00505021", -- 00000A7C
+		X"00EA102B", -- 00000A80
+		X"10400002", -- 00000A84
+		X"000C1080", -- 00000A88
+		X"00E05021", -- 00000A8C
+		X"0BF002D7", -- 00000A90
+		X"01C25821", -- 00000A94
+		X"AD730000", -- 00000A98
+		X"8D630000", -- 00000A9C
+		X"00000000", -- 00000AA0
+		X"006F1024", -- 00000AA4
+		X"144FFFFC", -- 00000AA8
+		X"00661024", -- 00000AAC
+		X"14400026", -- 00000AB0
+		X"3C029010", -- 00000AB4
+		X"8F020014", -- 00000AB8
+		X"00000000", -- 00000ABC
+		X"00021882", -- 00000AC0
+		X"006A102B", -- 00000AC4
+		X"10400002", -- 00000AC8
+		X"01404021", -- 00000ACC
+		X"00604021", -- 00000AD0
+		X"2503FFFF", -- 00000AD4
+		X"00031400", -- 00000AD8
+		X"00431025", -- 00000ADC
+		X"00052080", -- 00000AE0
+		X"000D1880", -- 00000AE4
+		X"02834821", -- 00000AE8
+		X"AD620000", -- 00000AEC
+		X"01C42021", -- 00000AF0
+		X"0BF002C3", -- 00000AF4
+		X"00001821", -- 00000AF8
+		X"8D220000", -- 00000AFC
+		X"25290004", -- 00000B00
+		X"AC820000", -- 00000B04
+		X"24840004", -- 00000B08
+		X"0068102B", -- 00000B0C
+		X"1440FFFA", -- 00000B10
+		X"24630001", -- 00000B14
+		X"01A86821", -- 00000B18
+		X"00A82821", -- 00000B1C
+		X"00E83823", -- 00000B20
+		X"AD720000", -- 00000B24
+		X"8D630000", -- 00000B28
+		X"00000000", -- 00000B2C
+		X"006F1024", -- 00000B30
+		X"144FFFFC", -- 00000B34
+		X"00661024", -- 00000B38
+		X"10400005", -- 00000B3C
+		X"01485023", -- 00000B40
+		X"01485021", -- 00000B44
+		X"3C029010", -- 00000B48
+		X"0BF002D9", -- 00000B4C
+		X"00622025", -- 00000B50
+		X"AD710000", -- 00000B54
+		X"00002021", -- 00000B58
+		X"1540FFCE", -- 00000B5C
+		X"00000000", -- 00000B60
+		X"04810007", -- 00000B64
+		X"000C1880", -- 00000B68
+		X"3C0200FF", -- 00000B6C
+		X"01C31821", -- 00000B70
+		X"344200FF", -- 00000B74
+		X"AC620000", -- 00000B78
+		X"0BF002E4", -- 00000B7C
+		X"00801021", -- 00000B80
+		X"14E0FFBC", -- 00000B84
+		X"00B96024", -- 00000B88
+		X"00801021", -- 00000B8C
+		X"8FB40014", -- 00000B90
+		X"8FB30010", -- 00000B94
+		X"8FB2000C", -- 00000B98
+		X"8FB10008", -- 00000B9C
+		X"8FB00004", -- 00000BA0
+		X"03E00008", -- 00000BA4
+		X"27BD0018", -- 00000BA8
+		X"27BDFFE0", -- 00000BAC
+		X"AFBF001C", -- 00000BB0
+		X"AC850000", -- 00000BB4
+		X"24820008", -- 00000BB8
+		X"0BF002F3", -- 00000BBC
+		X"24830020", -- 00000BC0
+		X"A0400000", -- 00000BC4
+		X"24420001", -- 00000BC8
+		X"1443FFFD", -- 00000BCC
+		X"00000000", -- 00000BD0
+		X"3C021234", -- 00000BD4
+		X"34425678", -- 00000BD8
+		X"00021E02", -- 00000BDC
+		X"AFA20010", -- 00000BE0
+		X"24020012", -- 00000BE4
+		X"14620003", -- 00000BE8
+		X"AC800004", -- 00000BEC
+		X"24020001", -- 00000BF0
+		X"AC820004", -- 00000BF4
+		X"0FF00185", -- 00000BF8
+		X"00000000", -- 00000BFC
+		X"8FBF001C", -- 00000C00
+		X"00000000", -- 00000C04
+		X"03E00008", -- 00000C08
+		X"27BD0020", -- 00000C0C
+		X"27BDFFD8", -- 00000C10
+		X"30C20003", -- 00000C14
+		X"AFB2001C", -- 00000C18
+		X"AFBF0024", -- 00000C1C
+		X"AFB30020", -- 00000C20
+		X"AFB10018", -- 00000C24
+		X"AFB00014", -- 00000C28
+		X"10400004", -- 00000C2C
+		X"00809021", -- 00000C30
+		X"00061082", -- 00000C34
+		X"24420001", -- 00000C38
+		X"00023080", -- 00000C3C
+		X"00C59821", -- 00000C40
+		X"0BF00324", -- 00000C44
+		X"00A08821", -- 00000C48
+		X"0FF001CA", -- 00000C4C
+		X"00000000", -- 00000C50
+		X"02402021", -- 00000C54
+		X"10400005", -- 00000C58
+		X"02002821", -- 00000C5C
+		X"0FF00236", -- 00000C60
+		X"00000000", -- 00000C64
+		X"04400011", -- 00000C68
+		X"00401821", -- 00000C6C
+		X"02002821", -- 00000C70
+		X"0FF001E6", -- 00000C74
+		X"02402021", -- 00000C78
+		X"0440000C", -- 00000C7C
+		X"00401821", -- 00000C80
+		X"8E42000C", -- 00000C84
+		X"00000000", -- 00000C88
+		X"02228821", -- 00000C8C
+		X"001117C3", -- 00000C90
+		X"00021782", -- 00000C94
+		X"00511021", -- 00000C98
+		X"00028083", -- 00000C9C
+		X"0233102B", -- 00000CA0
+		X"02402021", -- 00000CA4
+		X"1440FFE8", -- 00000CA8
+		X"02002821", -- 00000CAC
+		X"8FBF0024", -- 00000CB0
+		X"00601021", -- 00000CB4
+		X"8FB30020", -- 00000CB8
+		X"8FB2001C", -- 00000CBC
+		X"8FB10018", -- 00000CC0
+		X"8FB00014", -- 00000CC4
+		X"03E00008", -- 00000CC8
+		X"27BD0028", -- 00000CCC
+		X"30E20003", -- 00000CD0
+		X"10400003", -- 00000CD4
+		X"00071082", -- 00000CD8
+		X"24420001", -- 00000CDC
+		X"00023880", -- 00000CE0
+		X"00052882", -- 00000CE4
+		X"0BF0027E", -- 00000CE8
+		X"00073882", -- 00000CEC
+		X"8C820000", -- 00000CF0
+		X"00002021", -- 00000CF4
+		X"0BF00347", -- 00000CF8
+		X"00454021", -- 00000CFC
+		X"90630000", -- 00000D00
+		X"90A20000", -- 00000D04
+		X"00000000", -- 00000D08
+		X"10620003", -- 00000D0C
+		X"3C028010", -- 00000D10
+		X"03E00008", -- 00000D14
+		X"34420003", -- 00000D18
+		X"0087102B", -- 00000D1C
+		X"01041821", -- 00000D20
+		X"00C42821", -- 00000D24
+		X"1440FFF5", -- 00000D28
+		X"24840001", -- 00000D2C
+		X"03E00008", -- 00000D30
+		X"00000000", -- 00000D34
+		X"8C82000C", -- 00000D38
+		X"00000000", -- 00000D3C
+		X"14400002", -- 00000D40
+		X"00A2001B", -- 00000D44
+		X"0007000D", -- 00000D48
+		X"00001010", -- 00000D4C
+		X"0002102B", -- 00000D50
+		X"00002812", -- 00000D54
+		X"03E00008", -- 00000D58
+		X"00A21021", -- 00000D5C
+		X"8C830010", -- 00000D60
+		X"00000000", -- 00000D64
+		X"00A3102B", -- 00000D68
+		X"14400002", -- 00000D6C
+		X"00000000", -- 00000D70
+		X"2465FFFF", -- 00000D74
+		X"8C82000C", -- 00000D78
+		X"00000000", -- 00000D7C
+		X"00A20018", -- 00000D80
+		X"00001012", -- 00000D84
+		X"03E00008", -- 00000D88
+		X"00000000", -- 00000D8C
+		X"27BDFFE8", -- 00000D90
+		X"AFBF0014", -- 00000D94
+		X"AFB00010", -- 00000D98
+		X"0FF0034E", -- 00000D9C
+		X"00808021", -- 00000DA0
+		X"8E03000C", -- 00000DA4
+		X"8FBF0014", -- 00000DA8
+		X"00430018", -- 00000DAC
+		X"8FB00010", -- 00000DB0
+		X"00001012", -- 00000DB4
+		X"03E00008", -- 00000DB8
+		X"27BD0018", -- 00000DBC
+		X"90830000", -- 00000DC0
+		X"00000000", -- 00000DC4
+		X"2C620041", -- 00000DC8
+		X"14400002", -- 00000DCC
+		X"2462FFD0", -- 00000DD0
+		X"2462FFC9", -- 00000DD4
+		X"90840001", -- 00000DD8
+		X"304200FF", -- 00000DDC
+		X"304300FF", -- 00000DE0
+		X"2C820041", -- 00000DE4
+		X"14400003", -- 00000DE8
+		X"00000000", -- 00000DEC
+		X"0BF0037F", -- 00000DF0
+		X"2482FFC9", -- 00000DF4
+		X"2482FFD0", -- 00000DF8
+		X"304400FF", -- 00000DFC
+		X"00031100", -- 00000E00
+		X"00821025", -- 00000E04
+		X"03E00008", -- 00000E08
+		X"304200FF", -- 00000E0C
+		X"10C00094", -- 00000E10
+		X"00805021", -- 00000E14
+		X"24020003", -- 00000E18
+		X"AC820008", -- 00000E1C
+		X"90A40001", -- 00000E20
+		X"00000000", -- 00000E24
+		X"2482FFCF", -- 00000E28
+		X"304200FF", -- 00000E2C
+		X"2C420003", -- 00000E30
+		X"10400005", -- 00000E34
+		X"2482FFC9", -- 00000E38
+		X"24020002", -- 00000E3C
+		X"AD420008", -- 00000E40
+		X"0BF003A1", -- 00000E44
+		X"2489FFD1", -- 00000E48
+		X"304200FF", -- 00000E4C
+		X"2C420003", -- 00000E50
+		X"10400006", -- 00000E54
+		X"24020030", -- 00000E58
+		X"2402003B", -- 00000E5C
+		X"00444823", -- 00000E60
+		X"24020004", -- 00000E64
+		X"0BF003A1", -- 00000E68
+		X"AD420008", -- 00000E6C
+		X"14820004", -- 00000E70
+		X"00004821", -- 00000E74
+		X"24020001", -- 00000E78
+		X"AD420008", -- 00000E7C
+		X"24090002", -- 00000E80
+		X"90A30002", -- 00000E84
+		X"00000000", -- 00000E88
+		X"2C620041", -- 00000E8C
+		X"10400003", -- 00000E90
+		X"24A40002", -- 00000E94
+		X"0BF003A9", -- 00000E98
+		X"2462FFD0", -- 00000E9C
+		X"2462FFC9", -- 00000EA0
+		X"90830001", -- 00000EA4
+		X"304200FF", -- 00000EA8
+		X"304400FF", -- 00000EAC
+		X"2C620041", -- 00000EB0
+		X"10400002", -- 00000EB4
+		X"2462FFC9", -- 00000EB8
+		X"2462FFD0", -- 00000EBC
+		X"304300FF", -- 00000EC0
+		X"00041100", -- 00000EC4
+		X"00621025", -- 00000EC8
+		X"304200FF", -- 00000ECC
+		X"AD420004", -- 00000ED0
+		X"AD400000", -- 00000ED4
+		X"00405821", -- 00000ED8
+		X"00A03021", -- 00000EDC
+		X"0BF003D5", -- 00000EE0
+		X"00003821", -- 00000EE4
+		X"90C20004", -- 00000EE8
+		X"00000000", -- 00000EEC
+		X"2443FFC9", -- 00000EF0
+		X"2444FFD0", -- 00000EF4
+		X"2C420041", -- 00000EF8
+		X"10400002", -- 00000EFC
+		X"306300FF", -- 00000F00
+		X"308300FF", -- 00000F04
+		X"90C20005", -- 00000F08
+		X"306800FF", -- 00000F0C
+		X"2444FFC9", -- 00000F10
+		X"2443FFD0", -- 00000F14
+		X"2C420041", -- 00000F18
+		X"10400002", -- 00000F1C
+		X"308400FF", -- 00000F20
+		X"306400FF", -- 00000F24
+		X"8D430000", -- 00000F28
+		X"00081100", -- 00000F2C
+		X"00821025", -- 00000F30
+		X"304200FF", -- 00000F34
+		X"00031A00", -- 00000F38
+		X"004B2021", -- 00000F3C
+		X"00431025", -- 00000F40
+		X"AD420000", -- 00000F44
+		X"308B00FF", -- 00000F48
+		X"24E70001", -- 00000F4C
+		X"24C60002", -- 00000F50
+		X"00E9102A", -- 00000F54
+		X"1440FFE3", -- 00000F58
+		X"25220002", -- 00000F5C
+		X"8D440004", -- 00000F60
+		X"00021040", -- 00000F64
+		X"00091827", -- 00000F68
+		X"00832021", -- 00000F6C
+		X"00A21021", -- 00000F70
+		X"AD440004", -- 00000F74
+		X"AD42000C", -- 00000F78
+		X"0BF003F9", -- 00000F7C
+		X"00003021", -- 00000F80
+		X"90E20000", -- 00000F84
+		X"00000000", -- 00000F88
+		X"2444FFC9", -- 00000F8C
+		X"2445FFD0", -- 00000F90
+		X"2C420041", -- 00000F94
+		X"10400002", -- 00000F98
+		X"308400FF", -- 00000F9C
+		X"30A400FF", -- 00000FA0
+		X"90E20001", -- 00000FA4
+		X"308700FF", -- 00000FA8
+		X"2445FFC9", -- 00000FAC
+		X"2444FFD0", -- 00000FB0
+		X"2C420041", -- 00000FB4
+		X"14400002", -- 00000FB8
+		X"308400FF", -- 00000FBC
+		X"30A400FF", -- 00000FC0
+		X"00071100", -- 00000FC4
+		X"00821025", -- 00000FC8
+		X"304200FF", -- 00000FCC
+		X"00661821", -- 00000FD0
+		X"004B2021", -- 00000FD4
+		X"A0620000", -- 00000FD8
+		X"308B00FF", -- 00000FDC
+		X"24C60001", -- 00000FE0
+		X"8D420004", -- 00000FE4
+		X"8D43000C", -- 00000FE8
+		X"00062040", -- 00000FEC
+		X"00C2102A", -- 00000FF0
+		X"1440FFE3", -- 00000FF4
+		X"00643821", -- 00000FF8
+		X"90E40000", -- 00000FFC
+		X"00000000", -- 00001000
+		X"2C820041", -- 00001004
+		X"10400003", -- 00001008
+		X"00E01821", -- 0000100C
+		X"0BF00407", -- 00001010
+		X"2482FFD0", -- 00001014
+		X"2482FFC9", -- 00001018
+		X"90630001", -- 0000101C
+		X"304200FF", -- 00001020
+		X"304400FF", -- 00001024
+		X"2C620041", -- 00001028
+		X"10400002", -- 0000102C
+		X"2462FFC9", -- 00001030
+		X"2462FFD0", -- 00001034
+		X"304200FF", -- 00001038
+		X"00041900", -- 0000103C
+		X"00431825", -- 00001040
+		X"000B1027", -- 00001044
+		X"304200FF", -- 00001048
+		X"306300FF", -- 0000104C
+		X"14430004", -- 00001050
+		X"00000000", -- 00001054
+		X"8D420008", -- 00001058
+		X"03E00008", -- 0000105C
+		X"00000000", -- 00001060
+		X"03E00008", -- 00001064
+		X"00001021", -- 00001068
+		X"00800008", -- 0000106C
+		X"00000000", -- 00001070
+		X"03E00008", -- 00001074
+		X"00000000", -- 00001078
+		X"3C1A1000", -- 0000107C
+		X"375A000A", -- 00001080
+		X"409A6000", -- 00001084
+		X"00800008", -- 00001088
+		X"42000010", -- 0000108C
+		X"03E00008", -- 00001090
+		X"00000000", -- 00001094
+		X"401A6000", -- 00001098
+		X"3C1BFFBF", -- 0000109C
+		X"377BFFFF", -- 000010A0
+		X"035BD024", -- 000010A4
+		X"3C1B0200", -- 000010A8
+		X"035BD025", -- 000010AC
+		X"409A6000", -- 000010B0
+		X"00800008", -- 000010B4
+		X"42000010", -- 000010B8
+		X"03E00008", -- 000010BC
+		X"00000000", -- 000010C0
+		X"27BDFFD8", -- 000010C4
+		X"AFB30020", -- 000010C8
+		X"AFB10018", -- 000010CC
+		X"AFB00014", -- 000010D0
+		X"AFBF0024", -- 000010D4
+		X"AFB2001C", -- 000010D8
+		X"00809821", -- 000010DC
+		X"24110073", -- 000010E0
+		X"24100053", -- 000010E4
+		X"0FF00081", -- 000010E8
+		X"00000000", -- 000010EC
+		X"14510005", -- 000010F0
+		X"00000000", -- 000010F4
+		X"00008021", -- 000010F8
+		X"2412000A", -- 000010FC
+		X"0BF0044A", -- 00001100
+		X"2411000D", -- 00001104
+		X"1450FFF7", -- 00001108
+		X"00000000", -- 0000110C
+		X"0BF0043F", -- 00001110
+		X"00008021", -- 00001114
+		X"0FF00081", -- 00001118
+		X"A0620000", -- 0000111C
+		X"10510003", -- 00001120
+		X"26100001", -- 00001124
+		X"1452FFFB", -- 00001128
+		X"02701821", -- 0000112C
+		X"8FBF0024", -- 00001130
+		X"02001021", -- 00001134
+		X"8FB30020", -- 00001138
+		X"8FB2001C", -- 0000113C
+		X"8FB10018", -- 00001140
+		X"8FB00014", -- 00001144
+		X"03E00008", -- 00001148
+		X"27BD0028", -- 0000114C
+		X"27BDFD98", -- 00001150
+		X"27A40140", -- 00001154
+		X"00002821", -- 00001158
+		X"24060100", -- 0000115C
+		X"AFB20248", -- 00001160
+		X"AFB10244", -- 00001164
+		X"AFB00240", -- 00001168
+		X"3C11AC00", -- 0000116C
+		X"AFBF0264", -- 00001170
+		X"AFBE0260", -- 00001174
+		X"AFB7025C", -- 00001178
+		X"AFB60258", -- 0000117C
+		X"AFB50254", -- 00001180
+		X"AFB40250", -- 00001184
+		X"0FF0056C", -- 00001188
+		X"AFB3024C", -- 0000118C
+		X"3C036000", -- 00001190
+		X"36220004", -- 00001194
+		X"3463B1FF", -- 00001198
+		X"AC430000", -- 0000119C
+		X"3C022000", -- 000011A0
+		X"27B20020", -- 000011A4
+		X"34421000", -- 000011A8
+		X"AE220000", -- 000011AC
+		X"02402021", -- 000011B0
+		X"3C05A400", -- 000011B4
+		X"8E300000", -- 000011B8
+		X"0FF002EB", -- 000011BC
+		X"00000000", -- 000011C0
+		X"04410004", -- 000011C4
+		X"00102C02", -- 000011C8
+		X"3C049FC0", -- 000011CC
+		X"0BF00494", -- 000011D0
+		X"248416A8", -- 000011D4
+		X"02402021", -- 000011D8
+		X"0FF00358", -- 000011DC
+		X"30A5007F", -- 000011E0
+		X"00409021", -- 000011E4
+		X"8E220000", -- 000011E8
+		X"3C030800", -- 000011EC
+		X"00431024", -- 000011F0
+		X"14400045", -- 000011F4
+		X"3C119FC0", -- 000011F8
+		X"0FF000B0", -- 000011FC
+		X"2624175C", -- 00001200
+		X"3C02A400", -- 00001204
+		X"02428021", -- 00001208
+		X"8E030000", -- 0000120C
+		X"3C023149", -- 00001210
+		X"3442464A", -- 00001214
+		X"10620011", -- 00001218
+		X"3C024A46", -- 0000121C
+		X"34424931", -- 00001220
+		X"1062000E", -- 00001224
+		X"00000000", -- 00001228
+		X"0FF000B0", -- 0000122C
+		X"2624175C", -- 00001230
+		X"3C049FC0", -- 00001234
+		X"0FF000B0", -- 00001238
+		X"248416D0", -- 0000123C
+		X"0FF000E8", -- 00001240
+		X"02402021", -- 00001244
+		X"3C049FC0", -- 00001248
+		X"248416E8", -- 0000124C
+		X"0FF000B0", -- 00001250
+		X"00000000", -- 00001254
+		X"0BF00560", -- 00001258
+		X"24020001", -- 0000125C
+		X"3C049FC0", -- 00001260
+		X"0FF000B0", -- 00001264
+		X"248416F4", -- 00001268
+		X"0FF000E8", -- 0000126C
+		X"02402021", -- 00001270
+		X"3C049FC0", -- 00001274
+		X"0FF000B0", -- 00001278
+		X"24841718", -- 0000127C
+		X"8E02000C", -- 00001280
+		X"8E110004", -- 00001284
+		X"00024082", -- 00001288
+		X"8E070008", -- 0000128C
+		X"00002021", -- 00001290
+		X"0BF004AA", -- 00001294
+		X"00001821", -- 00001298
+		X"8CC20000", -- 0000129C
+		X"00000000", -- 000012A0
+		X"ACA20000", -- 000012A4
+		X"0088102B", -- 000012A8
+		X"00673021", -- 000012AC
+		X"00712821", -- 000012B0
+		X"24840001", -- 000012B4
+		X"1440FFF8", -- 000012B8
+		X"24630004", -- 000012BC
+		X"3C049FC0", -- 000012C0
+		X"0FF000B0", -- 000012C4
+		X"24841720", -- 000012C8
+		X"3C049FC0", -- 000012CC
+		X"0FF000B0", -- 000012D0
+		X"24841728", -- 000012D4
+		X"8E040004", -- 000012D8
+		X"0FF000E8", -- 000012DC
+		X"00000000", -- 000012E0
+		X"3C049FC0", -- 000012E4
+		X"0FF000B0", -- 000012E8
+		X"2484175C", -- 000012EC
+		X"3C1A1000", -- 000012F0
+		X"375A000A", -- 000012F4
+		X"409A6000", -- 000012F8
+		X"02200008", -- 000012FC
+		X"42000010", -- 00001300
+		X"0BF00560", -- 00001304
+		X"00001021", -- 00001308
+		X"0FF000B0", -- 0000130C
+		X"2624175C", -- 00001310
+		X"3C049FC0", -- 00001314
+		X"0FF000B0", -- 00001318
+		X"24841734", -- 0000131C
+		X"3C028000", -- 00001320
+		X"3C038010", -- 00001324
+		X"AC400000", -- 00001328
+		X"24420004", -- 0000132C
+		X"1443FFFD", -- 00001330
+		X"00009821", -- 00001334
+		X"3C029FC0", -- 00001338
+		X"245516CC", -- 0000133C
+		X"3C029FC0", -- 00001340
+		X"24561720", -- 00001344
+		X"3C029FC0", -- 00001348
+		X"245E17D4", -- 0000134C
+		X"3C029FC0", -- 00001350
+		X"245717F4", -- 00001354
+		X"3C049FC0", -- 00001358
+		X"0FF000B0", -- 0000135C
+		X"24841754", -- 00001360
+		X"3C149FC0", -- 00001364
+		X"27B00040", -- 00001368
+		X"0FF00431", -- 0000136C
+		X"02002021", -- 00001370
+		X"00403021", -- 00001374
+		X"02002821", -- 00001378
+		X"27A40010", -- 0000137C
+		X"0FF00384", -- 00001380
+		X"00408821", -- 00001384
+		X"00401821", -- 00001388
+		X"24020002", -- 0000138C
+		X"10620005", -- 00001390
+		X"24020004", -- 00001394
+		X"1462FFEF", -- 00001398
+		X"00000000", -- 0000139C
+		X"0BF004FF", -- 000013A0
+		X"3C049FC0", -- 000013A4
+		X"8FA50010", -- 000013A8
+		X"8FA60014", -- 000013AC
+		X"0BF004F4", -- 000013B0
+		X"00001821", -- 000013B4
+		X"8FA2001C", -- 000013B8
+		X"00000000", -- 000013BC
+		X"00431021", -- 000013C0
+		X"90420000", -- 000013C4
+		X"24630001", -- 000013C8
+		X"A0820000", -- 000013CC
+		X"8FA20014", -- 000013D0
+		X"00000000", -- 000013D4
+		X"0062102B", -- 000013D8
+		X"1440FFF6", -- 000013DC
+		X"00652021", -- 000013E0
+		X"00C51821", -- 000013E4
+		X"0263102B", -- 000013E8
+		X"10400060", -- 000013EC
+		X"02208021", -- 000013F0
+		X"0BF0055C", -- 000013F4
+		X"00609821", -- 000013F8
+		X"0FF000B0", -- 000013FC
+		X"24841758", -- 00001400
+		X"8FA60010", -- 00001404
+		X"26470100", -- 00001408
+		X"02661823", -- 0000140C
+		X"27B10020", -- 00001410
+		X"3C024A46", -- 00001414
+		X"00E32821", -- 00001418
+		X"02202021", -- 0000141C
+		X"34424931", -- 00001420
+		X"AFA60144", -- 00001424
+		X"AFA3014C", -- 00001428
+		X"AFA70148", -- 0000142C
+		X"0FF00364", -- 00001430
+		X"AFA20140", -- 00001434
+		X"3C049FC0", -- 00001438
+		X"24841760", -- 0000143C
+		X"0FF000B0", -- 00001440
+		X"AFA20150", -- 00001444
+		X"8FA4014C", -- 00001448
+		X"0FF000E8", -- 0000144C
+		X"00000000", -- 00001450
+		X"0FF000B0", -- 00001454
+		X"02A02021", -- 00001458
+		X"3C049FC0", -- 0000145C
+		X"0FF000B0", -- 00001460
+		X"2484177C", -- 00001464
+		X"0FF000E8", -- 00001468
+		X"02402021", -- 0000146C
+		X"0FF000B0", -- 00001470
+		X"02A02021", -- 00001474
+		X"3C049FC0", -- 00001478
+		X"0FF000B0", -- 0000147C
+		X"24841798", -- 00001480
+		X"8FA40150", -- 00001484
+		X"0FF000E8", -- 00001488
+		X"00000000", -- 0000148C
+		X"0FF000B0", -- 00001490
+		X"02A02021", -- 00001494
+		X"3C049FC0", -- 00001498
+		X"0FF000B0", -- 0000149C
+		X"248417B4", -- 000014A0
+		X"8FA6014C", -- 000014A4
+		X"02202021", -- 000014A8
+		X"24C60100", -- 000014AC
+		X"0FF00304", -- 000014B0
+		X"02402821", -- 000014B4
+		X"0440001F", -- 000014B8
+		X"00408021", -- 000014BC
+		X"0FF000B0", -- 000014C0
+		X"02C02021", -- 000014C4
+		X"0FF000B0", -- 000014C8
+		X"03C02021", -- 000014CC
+		X"02202021", -- 000014D0
+		X"02402821", -- 000014D4
+		X"27A60140", -- 000014D8
+		X"0FF00334", -- 000014DC
+		X"24070100", -- 000014E0
+		X"04400014", -- 000014E4
+		X"00408021", -- 000014E8
+		X"8FA50148", -- 000014EC
+		X"8FA60144", -- 000014F0
+		X"8FA7014C", -- 000014F4
+		X"0FF00334", -- 000014F8
+		X"02202021", -- 000014FC
+		X"0440000D", -- 00001500
+		X"00408021", -- 00001504
+		X"0FF000B0", -- 00001508
+		X"02C02021", -- 0000150C
+		X"3C049FC0", -- 00001510
+		X"0FF000B0", -- 00001514
+		X"248417E4", -- 00001518
+		X"8FA50148", -- 0000151C
+		X"8FA60144", -- 00001520
+		X"8FA7014C", -- 00001524
+		X"0FF0033C", -- 00001528
+		X"02202021", -- 0000152C
+		X"0441000A", -- 00001530
+		X"00408021", -- 00001534
+		X"0FF000B0", -- 00001538
+		X"268417C4", -- 0000153C
+		X"0FF000E8", -- 00001540
+		X"02002021", -- 00001544
+		X"3C049FC0", -- 00001548
+		X"0FF000B0", -- 0000154C
+		X"248417D0", -- 00001550
+		X"0BF0055C", -- 00001554
+		X"00000000", -- 00001558
+		X"0FF000B0", -- 0000155C
+		X"02E02021", -- 00001560
+		X"3C02BFC0", -- 00001564
+		X"00400008", -- 00001568
+		X"00000000", -- 0000156C
+		X"0601FF7E", -- 00001570
+		X"27B00040", -- 00001574
+		X"0BF004D7", -- 00001578
+		X"3C049FC0", -- 0000157C
+		X"8FBF0264", -- 00001580
+		X"8FBE0260", -- 00001584
+		X"8FB7025C", -- 00001588
+		X"8FB60258", -- 0000158C
+		X"8FB50254", -- 00001590
+		X"8FB40250", -- 00001594
+		X"8FB3024C", -- 00001598
+		X"8FB20248", -- 0000159C
+		X"8FB10244", -- 000015A0
+		X"8FB00240", -- 000015A4
+		X"03E00008", -- 000015A8
+		X"27BD0268", -- 000015AC
+		X"2CC20010", -- 000015B0
+		X"00804821", -- 000015B4
+		X"1440002D", -- 000015B8
+		X"00804021", -- 000015BC
+		X"30870003", -- 000015C0
+		X"10E0000E", -- 000015C4
+		X"24820004", -- 000015C8
+		X"00052600", -- 000015CC
+		X"00471023", -- 000015D0
+		X"00042603", -- 000015D4
+		X"01201821", -- 000015D8
+		X"A0640000", -- 000015DC
+		X"24630001", -- 000015E0
+		X"1462FFFD", -- 000015E4
+		X"00000000", -- 000015E8
+		X"00071027", -- 000015EC
+		X"24C3FFFB", -- 000015F0
+		X"24440005", -- 000015F4
+		X"00623023", -- 000015F8
+		X"01244021", -- 000015FC
+		X"30A500FF", -- 00001600
+		X"01003821", -- 00001604
+		X"10A00005", -- 00001608
+		X"00A01821", -- 0000160C
+		X"00051200", -- 00001610
+		X"00451025", -- 00001614
+		X"00021C00", -- 00001618
+		X"00621825", -- 0000161C
+		X"000610C2", -- 00001620
+		X"1040001C", -- 00001624
+		X"30C60007", -- 00001628
+		X"01002021", -- 0000162C
+		X"00403821", -- 00001630
+		X"24E7FFFF", -- 00001634
+		X"AC830000", -- 00001638
+		X"AC830004", -- 0000163C
+		X"14E0FFFC", -- 00001640
+		X"24840008", -- 00001644
+		X"000210C0", -- 00001648
+		X"01023821", -- 0000164C
+		X"00E02021", -- 00001650
+		X"2CC20004", -- 00001654
+		X"14400005", -- 00001658
+		X"00804021", -- 0000165C
+		X"ACE30000", -- 00001660
+		X"24E40004", -- 00001664
+		X"24C6FFFC", -- 00001668
+		X"00804021", -- 0000166C
+		X"10C00007", -- 00001670
+		X"00000000", -- 00001674
+		X"00051600", -- 00001678
+		X"00021603", -- 0000167C
+		X"24C6FFFF", -- 00001680
+		X"A1020000", -- 00001684
+		X"14C0FFFD", -- 00001688
+		X"25080001", -- 0000168C
+		X"03E00008", -- 00001690
+		X"01201021", -- 00001694
+		X"0BF00595", -- 00001698
+		X"01002021", -- 0000169C
+		X"3A200000", -- 000016A0
+		X"20202000", -- 000016A4
+		X"43616E6E", -- 000016A8
+		X"6F742066", -- 000016AC
+		X"696E6420", -- 000016B0
+		X"666C6173", -- 000016B4
+		X"68206465", -- 000016B8
+		X"76696365", -- 000016BC
+		X"2E204578", -- 000016C0
+		X"6974206E", -- 000016C4
+		X"6F77210A", -- 000016C8
+		X"0A000000", -- 000016CC
+		X"496E7661", -- 000016D0
+		X"6C696420", -- 000016D4
+		X"696D6167", -- 000016D8
+		X"6520666F", -- 000016DC
+		X"756E6420", -- 000016E0
+		X"61742000", -- 000016E4
+		X"2E204162", -- 000016E8
+		X"6F72742E", -- 000016EC
+		X"0A000000", -- 000016F0
+		X"426F6F74", -- 000016F4
+		X"696E6720", -- 000016F8
+		X"6170706C", -- 000016FC
+		X"69636174", -- 00001700
+		X"696F6E20", -- 00001704
+		X"66726F6D", -- 00001708
+		X"20666C61", -- 0000170C
+		X"73682028", -- 00001710
+		X"00000000", -- 00001714
+		X"292E2E2E", -- 00001718
+		X"00000000", -- 0000171C
+		X"646F6E65", -- 00001720
+		X"0A000000", -- 00001724
+		X"45786563", -- 00001728
+		X"75746520", -- 0000172C
+		X"61742000", -- 00001730
+		X"52656164", -- 00001734
+		X"696E6720", -- 00001738
+		X"4845582D", -- 0000173C
+		X"5265636F", -- 00001740
+		X"72642066", -- 00001744
+		X"726F6D20", -- 00001748
+		X"55415254", -- 0000174C
+		X"2E2E0000", -- 00001750
+		X"2E000000", -- 00001754
+		X"646F6E65", -- 00001758
+		X"0A0A0000", -- 0000175C
+		X"53697A65", -- 00001760
+		X"206F6620", -- 00001764
+		X"6170706C", -- 00001768
+		X"69636174", -- 0000176C
+		X"696F6E20", -- 00001770
+		X"2020203A", -- 00001774
+		X"20000000", -- 00001778
+		X"50726F67", -- 0000177C
+		X"72616D6D", -- 00001780
+		X"696E6720", -- 00001784
+		X"666C6173", -- 00001788
+		X"68206174", -- 0000178C
+		X"2020203A", -- 00001790
+		X"20000000", -- 00001794
+		X"4E657874", -- 00001798
+		X"20667265", -- 0000179C
+		X"6520666C", -- 000017A0
+		X"61736820", -- 000017A4
+		X"6F666673", -- 000017A8
+		X"6574203A", -- 000017AC
+		X"20000000", -- 000017B0
+		X"466C6173", -- 000017B4
+		X"68206572", -- 000017B8
+		X"6173652E", -- 000017BC
+		X"2E2E0000", -- 000017C0
+		X"6661696C", -- 000017C4
+		X"65642028", -- 000017C8
+		X"00000000", -- 000017CC
+		X"290A0000", -- 000017D0
+		X"466C6173", -- 000017D4
+		X"68207772", -- 000017D8
+		X"6974652E", -- 000017DC
+		X"2E2E0000", -- 000017E0
+		X"466C6173", -- 000017E4
+		X"68207665", -- 000017E8
+		X"72696679", -- 000017EC
+		X"2E2E2E00", -- 000017F0
+		X"70617373", -- 000017F4
+		X"65640A00", -- 000017F8
+		X"00000000", -- 000017FC
+		X"00000000", -- 00001800
+		X"00000000", -- 00001804
+		X"00000000", -- 00001808
+		X"00000000", -- 0000180C
+		X"00000000", -- 00001810
+		X"00000000", -- 00001814
+		X"00000000", -- 00001818
+		X"00000000", -- 0000181C
+		X"00000000", -- 00001820
+		X"00000000", -- 00001824
+		X"00000000", -- 00001828
+		X"00000000", -- 0000182C
+		X"00000000", -- 00001830
+		X"00000000", -- 00001834
+		X"00000000", -- 00001838
+		X"00000000", -- 0000183C
+		X"00000000", -- 00001840
+		X"00000000", -- 00001844
+		X"00000000", -- 00001848
+		X"00000000", -- 0000184C
+		X"00000000", -- 00001850
+		X"00000000", -- 00001854
+		X"00000000", -- 00001858
+		X"00000000", -- 0000185C
+		X"00000000", -- 00001860
+		X"00000000", -- 00001864
+		X"00000000", -- 00001868
+		X"00000000", -- 0000186C
+		X"00000000", -- 00001870
+		X"00000000", -- 00001874
+		X"00000000", -- 00001878
+		X"00000000", -- 0000187C
+		X"00000000", -- 00001880
+		X"00000000", -- 00001884
+		X"00000000", -- 00001888
+		X"00000000", -- 0000188C
+		X"00000000", -- 00001890
+		X"00000000", -- 00001894
+		X"00000000", -- 00001898
+		X"00000000", -- 0000189C
+		X"00000000", -- 000018A0
+		X"00000000", -- 000018A4
+		X"00000000", -- 000018A8
+		X"00000000", -- 000018AC
+		X"00000000", -- 000018B0
+		X"00000000", -- 000018B4
+		X"00000000", -- 000018B8
+		X"00000000", -- 000018BC
+		X"00000000", -- 000018C0
+		X"00000000", -- 000018C4
+		X"00000000", -- 000018C8
+		X"00000000", -- 000018CC
+		X"00000000", -- 000018D0
+		X"00000000", -- 000018D4
+		X"00000000", -- 000018D8
+		X"00000000", -- 000018DC
+		X"00000000", -- 000018E0
+		X"00000000", -- 000018E4
+		X"00000000", -- 000018E8
+		X"00000000", -- 000018EC
+		X"00000000", -- 000018F0
+		X"00000000", -- 000018F4
+		X"00000000", -- 000018F8
+		X"00000000", -- 000018FC
+		X"00000000", -- 00001900
+		X"00000000", -- 00001904
+		X"00000000", -- 00001908
+		X"00000000", -- 0000190C
+		X"00000000", -- 00001910
+		X"00000000", -- 00001914
+		X"00000000", -- 00001918
+		X"00000000", -- 0000191C
+		X"00000000", -- 00001920
+		X"00000000", -- 00001924
+		X"00000000", -- 00001928
+		X"00000000", -- 0000192C
+		X"00000000", -- 00001930
+		X"00000000", -- 00001934
+		X"00000000", -- 00001938
+		X"00000000", -- 0000193C
+		X"00000000", -- 00001940
+		X"00000000", -- 00001944
+		X"00000000", -- 00001948
+		X"00000000", -- 0000194C
+		X"00000000", -- 00001950
+		X"00000000", -- 00001954
+		X"00000000", -- 00001958
+		X"00000000", -- 0000195C
+		X"00000000", -- 00001960
+		X"00000000", -- 00001964
+		X"00000000", -- 00001968
+		X"00000000", -- 0000196C
+		X"00000000", -- 00001970
+		X"00000000", -- 00001974
+		X"00000000", -- 00001978
+		X"00000000", -- 0000197C
+		X"00000000", -- 00001980
+		X"00000000", -- 00001984
+		X"00000000", -- 00001988
+		X"00000000", -- 0000198C
+		X"00000000", -- 00001990
+		X"00000000", -- 00001994
+		X"00000000", -- 00001998
+		X"00000000", -- 0000199C
+		X"00000000", -- 000019A0
+		X"00000000", -- 000019A4
+		X"00000000", -- 000019A8
+		X"00000000", -- 000019AC
+		X"00000000", -- 000019B0
+		X"00000000", -- 000019B4
+		X"00000000", -- 000019B8
+		X"00000000", -- 000019BC
+		X"00000000", -- 000019C0
+		X"00000000", -- 000019C4
+		X"00000000", -- 000019C8
+		X"00000000", -- 000019CC
+		X"00000000", -- 000019D0
+		X"00000000", -- 000019D4
+		X"00000000", -- 000019D8
+		X"00000000", -- 000019DC
+		X"00000000", -- 000019E0
+		X"00000000", -- 000019E4
+		X"00000000", -- 000019E8
+		X"00000000", -- 000019EC
+		X"00000000", -- 000019F0
+		X"00000000", -- 000019F4
+		X"00000000", -- 000019F8
+		X"00000000", -- 000019FC
+		X"00000000", -- 00001A00
+		X"00000000", -- 00001A04
+		X"00000000", -- 00001A08
+		X"00000000", -- 00001A0C
+		X"00000000", -- 00001A10
+		X"00000000", -- 00001A14
+		X"00000000", -- 00001A18
+		X"00000000", -- 00001A1C
+		X"00000000", -- 00001A20
+		X"00000000", -- 00001A24
+		X"00000000", -- 00001A28
+		X"00000000", -- 00001A2C
+		X"00000000", -- 00001A30
+		X"00000000", -- 00001A34
+		X"00000000", -- 00001A38
+		X"00000000", -- 00001A3C
+		X"00000000", -- 00001A40
+		X"00000000", -- 00001A44
+		X"00000000", -- 00001A48
+		X"00000000", -- 00001A4C
+		X"00000000", -- 00001A50
+		X"00000000", -- 00001A54
+		X"00000000", -- 00001A58
+		X"00000000", -- 00001A5C
+		X"00000000", -- 00001A60
+		X"00000000", -- 00001A64
+		X"00000000", -- 00001A68
+		X"00000000", -- 00001A6C
+		X"00000000", -- 00001A70
+		X"00000000", -- 00001A74
+		X"00000000", -- 00001A78
+		X"00000000", -- 00001A7C
+		X"00000000", -- 00001A80
+		X"00000000", -- 00001A84
+		X"00000000", -- 00001A88
+		X"00000000", -- 00001A8C
+		X"00000000", -- 00001A90
+		X"00000000", -- 00001A94
+		X"00000000", -- 00001A98
+		X"00000000", -- 00001A9C
+		X"00000000", -- 00001AA0
+		X"00000000", -- 00001AA4
+		X"00000000", -- 00001AA8
+		X"00000000", -- 00001AAC
+		X"00000000", -- 00001AB0
+		X"00000000", -- 00001AB4
+		X"00000000", -- 00001AB8
+		X"00000000", -- 00001ABC
+		X"00000000", -- 00001AC0
+		X"00000000", -- 00001AC4
+		X"00000000", -- 00001AC8
+		X"00000000", -- 00001ACC
+		X"00000000", -- 00001AD0
+		X"00000000", -- 00001AD4
+		X"00000000", -- 00001AD8
+		X"00000000", -- 00001ADC
+		X"00000000", -- 00001AE0
+		X"00000000", -- 00001AE4
+		X"00000000", -- 00001AE8
+		X"00000000", -- 00001AEC
+		X"00000000", -- 00001AF0
+		X"00000000", -- 00001AF4
+		X"00000000", -- 00001AF8
+		X"00000000", -- 00001AFC
+		X"00000000", -- 00001B00
+		X"00000000", -- 00001B04
+		X"00000000", -- 00001B08
+		X"00000000", -- 00001B0C
+		X"00000000", -- 00001B10
+		X"00000000", -- 00001B14
+		X"00000000", -- 00001B18
+		X"00000000", -- 00001B1C
+		X"00000000", -- 00001B20
+		X"00000000", -- 00001B24
+		X"00000000", -- 00001B28
+		X"00000000", -- 00001B2C
+		X"00000000", -- 00001B30
+		X"00000000", -- 00001B34
+		X"00000000", -- 00001B38
+		X"00000000", -- 00001B3C
+		X"00000000", -- 00001B40
+		X"00000000", -- 00001B44
+		X"00000000", -- 00001B48
+		X"00000000", -- 00001B4C
+		X"00000000", -- 00001B50
+		X"00000000", -- 00001B54
+		X"00000000", -- 00001B58
+		X"00000000", -- 00001B5C
+		X"00000000", -- 00001B60
+		X"00000000", -- 00001B64
+		X"00000000", -- 00001B68
+		X"00000000", -- 00001B6C
+		X"00000000", -- 00001B70
+		X"00000000", -- 00001B74
+		X"00000000", -- 00001B78
+		X"00000000", -- 00001B7C
+		X"00000000", -- 00001B80
+		X"00000000", -- 00001B84
+		X"00000000", -- 00001B88
+		X"00000000", -- 00001B8C
+		X"00000000", -- 00001B90
+		X"00000000", -- 00001B94
+		X"00000000", -- 00001B98
+		X"00000000", -- 00001B9C
+		X"00000000", -- 00001BA0
+		X"00000000", -- 00001BA4
+		X"00000000", -- 00001BA8
+		X"00000000", -- 00001BAC
+		X"00000000", -- 00001BB0
+		X"00000000", -- 00001BB4
+		X"00000000", -- 00001BB8
+		X"00000000", -- 00001BBC
+		X"00000000", -- 00001BC0
+		X"00000000", -- 00001BC4
+		X"00000000", -- 00001BC8
+		X"00000000", -- 00001BCC
+		X"00000000", -- 00001BD0
+		X"00000000", -- 00001BD4
+		X"00000000", -- 00001BD8
+		X"00000000", -- 00001BDC
+		X"00000000", -- 00001BE0
+		X"00000000", -- 00001BE4
+		X"00000000", -- 00001BE8
+		X"00000000", -- 00001BEC
+		X"00000000", -- 00001BF0
+		X"00000000", -- 00001BF4
+		X"00000000", -- 00001BF8
+		X"00000000", -- 00001BFC
+		X"00000000", -- 00001C00
+		X"00000000", -- 00001C04
+		X"00000000", -- 00001C08
+		X"00000000", -- 00001C0C
+		X"00000000", -- 00001C10
+		X"00000000", -- 00001C14
+		X"00000000", -- 00001C18
+		X"00000000", -- 00001C1C
+		X"00000000", -- 00001C20
+		X"00000000", -- 00001C24
+		X"00000000", -- 00001C28
+		X"00000000", -- 00001C2C
+		X"00000000", -- 00001C30
+		X"00000000", -- 00001C34
+		X"00000000", -- 00001C38
+		X"00000000", -- 00001C3C
+		X"00000000", -- 00001C40
+		X"00000000", -- 00001C44
+		X"00000000", -- 00001C48
+		X"00000000", -- 00001C4C
+		X"00000000", -- 00001C50
+		X"00000000", -- 00001C54
+		X"00000000", -- 00001C58
+		X"00000000", -- 00001C5C
+		X"00000000", -- 00001C60
+		X"00000000", -- 00001C64
+		X"00000000", -- 00001C68
+		X"00000000", -- 00001C6C
+		X"00000000", -- 00001C70
+		X"00000000", -- 00001C74
+		X"00000000", -- 00001C78
+		X"00000000", -- 00001C7C
+		X"00000000", -- 00001C80
+		X"00000000", -- 00001C84
+		X"00000000", -- 00001C88
+		X"00000000", -- 00001C8C
+		X"00000000", -- 00001C90
+		X"00000000", -- 00001C94
+		X"00000000", -- 00001C98
+		X"00000000", -- 00001C9C
+		X"00000000", -- 00001CA0
+		X"00000000", -- 00001CA4
+		X"00000000", -- 00001CA8
+		X"00000000", -- 00001CAC
+		X"00000000", -- 00001CB0
+		X"00000000", -- 00001CB4
+		X"00000000", -- 00001CB8
+		X"00000000", -- 00001CBC
+		X"00000000", -- 00001CC0
+		X"00000000", -- 00001CC4
+		X"00000000", -- 00001CC8
+		X"00000000", -- 00001CCC
+		X"00000000", -- 00001CD0
+		X"00000000", -- 00001CD4
+		X"00000000", -- 00001CD8
+		X"00000000", -- 00001CDC
+		X"00000000", -- 00001CE0
+		X"00000000", -- 00001CE4
+		X"00000000", -- 00001CE8
+		X"00000000", -- 00001CEC
+		X"00000000", -- 00001CF0
+		X"00000000", -- 00001CF4
+		X"00000000", -- 00001CF8
+		X"00000000", -- 00001CFC
+		X"00000000", -- 00001D00
+		X"00000000", -- 00001D04
+		X"00000000", -- 00001D08
+		X"00000000", -- 00001D0C
+		X"00000000", -- 00001D10
+		X"00000000", -- 00001D14
+		X"00000000", -- 00001D18
+		X"00000000", -- 00001D1C
+		X"00000000", -- 00001D20
+		X"00000000", -- 00001D24
+		X"00000000", -- 00001D28
+		X"00000000", -- 00001D2C
+		X"00000000", -- 00001D30
+		X"00000000", -- 00001D34
+		X"00000000", -- 00001D38
+		X"00000000", -- 00001D3C
+		X"00000000", -- 00001D40
+		X"00000000", -- 00001D44
+		X"00000000", -- 00001D48
+		X"00000000", -- 00001D4C
+		X"00000000", -- 00001D50
+		X"00000000", -- 00001D54
+		X"00000000", -- 00001D58
+		X"00000000", -- 00001D5C
+		X"00000000", -- 00001D60
+		X"00000000", -- 00001D64
+		X"00000000", -- 00001D68
+		X"00000000", -- 00001D6C
+		X"00000000", -- 00001D70
+		X"00000000", -- 00001D74
+		X"00000000", -- 00001D78
+		X"00000000", -- 00001D7C
+		X"00000000", -- 00001D80
+		X"00000000", -- 00001D84
+		X"00000000", -- 00001D88
+		X"00000000", -- 00001D8C
+		X"00000000", -- 00001D90
+		X"00000000", -- 00001D94
+		X"00000000", -- 00001D98
+		X"00000000", -- 00001D9C
+		X"00000000", -- 00001DA0
+		X"00000000", -- 00001DA4
+		X"00000000", -- 00001DA8
+		X"00000000", -- 00001DAC
+		X"00000000", -- 00001DB0
+		X"00000000", -- 00001DB4
+		X"00000000", -- 00001DB8
+		X"00000000", -- 00001DBC
+		X"00000000", -- 00001DC0
+		X"00000000", -- 00001DC4
+		X"00000000", -- 00001DC8
+		X"00000000", -- 00001DCC
+		X"00000000", -- 00001DD0
+		X"00000000", -- 00001DD4
+		X"00000000", -- 00001DD8
+		X"00000000", -- 00001DDC
+		X"00000000", -- 00001DE0
+		X"00000000", -- 00001DE4
+		X"00000000", -- 00001DE8
+		X"00000000", -- 00001DEC
+		X"00000000", -- 00001DF0
+		X"00000000", -- 00001DF4
+		X"00000000", -- 00001DF8
+		X"00000000", -- 00001DFC
+		X"00000000", -- 00001E00
+		X"00000000", -- 00001E04
+		X"00000000", -- 00001E08
+		X"00000000", -- 00001E0C
+		X"00000000", -- 00001E10
+		X"00000000", -- 00001E14
+		X"00000000", -- 00001E18
+		X"00000000", -- 00001E1C
+		X"00000000", -- 00001E20
+		X"00000000", -- 00001E24
+		X"00000000", -- 00001E28
+		X"00000000", -- 00001E2C
+		X"00000000", -- 00001E30
+		X"00000000", -- 00001E34
+		X"00000000", -- 00001E38
+		X"00000000", -- 00001E3C
+		X"00000000", -- 00001E40
+		X"00000000", -- 00001E44
+		X"00000000", -- 00001E48
+		X"00000000", -- 00001E4C
+		X"00000000", -- 00001E50
+		X"00000000", -- 00001E54
+		X"00000000", -- 00001E58
+		X"00000000", -- 00001E5C
+		X"00000000", -- 00001E60
+		X"00000000", -- 00001E64
+		X"00000000", -- 00001E68
+		X"00000000", -- 00001E6C
+		X"00000000", -- 00001E70
+		X"00000000", -- 00001E74
+		X"00000000", -- 00001E78
+		X"00000000", -- 00001E7C
+		X"00000000", -- 00001E80
+		X"00000000", -- 00001E84
+		X"00000000", -- 00001E88
+		X"00000000", -- 00001E8C
+		X"00000000", -- 00001E90
+		X"00000000", -- 00001E94
+		X"00000000", -- 00001E98
+		X"00000000", -- 00001E9C
+		X"00000000", -- 00001EA0
+		X"00000000", -- 00001EA4
+		X"00000000", -- 00001EA8
+		X"00000000", -- 00001EAC
+		X"00000000", -- 00001EB0
+		X"00000000", -- 00001EB4
+		X"00000000", -- 00001EB8
+		X"00000000", -- 00001EBC
+		X"00000000", -- 00001EC0
+		X"00000000", -- 00001EC4
+		X"00000000", -- 00001EC8
+		X"00000000", -- 00001ECC
+		X"00000000", -- 00001ED0
+		X"00000000", -- 00001ED4
+		X"00000000", -- 00001ED8
+		X"00000000", -- 00001EDC
+		X"00000000", -- 00001EE0
+		X"00000000", -- 00001EE4
+		X"00000000", -- 00001EE8
+		X"00000000", -- 00001EEC
+		X"00000000", -- 00001EF0
+		X"00000000", -- 00001EF4
+		X"00000000", -- 00001EF8
+		X"00000000", -- 00001EFC
+		X"00000000", -- 00001F00
+		X"00000000", -- 00001F04
+		X"00000000", -- 00001F08
+		X"00000000", -- 00001F0C
+		X"00000000", -- 00001F10
+		X"00000000", -- 00001F14
+		X"00000000", -- 00001F18
+		X"00000000", -- 00001F1C
+		X"00000000", -- 00001F20
+		X"00000000", -- 00001F24
+		X"00000000", -- 00001F28
+		X"00000000", -- 00001F2C
+		X"00000000", -- 00001F30
+		X"00000000", -- 00001F34
+		X"00000000", -- 00001F38
+		X"00000000", -- 00001F3C
+		X"00000000", -- 00001F40
+		X"00000000", -- 00001F44
+		X"00000000", -- 00001F48
+		X"00000000", -- 00001F4C
+		X"00000000", -- 00001F50
+		X"00000000", -- 00001F54
+		X"00000000", -- 00001F58
+		X"00000000", -- 00001F5C
+		X"00000000", -- 00001F60
+		X"00000000", -- 00001F64
+		X"00000000", -- 00001F68
+		X"00000000", -- 00001F6C
+		X"00000000", -- 00001F70
+		X"00000000", -- 00001F74
+		X"00000000", -- 00001F78
+		X"00000000", -- 00001F7C
+		X"00000000", -- 00001F80
+		X"00000000", -- 00001F84
+		X"00000000", -- 00001F88
+		X"00000000", -- 00001F8C
+		X"00000000", -- 00001F90
+		X"00000000", -- 00001F94
+		X"00000000", -- 00001F98
+		X"00000000", -- 00001F9C
+		X"00000000", -- 00001FA0
+		X"00000000", -- 00001FA4
+		X"00000000", -- 00001FA8
+		X"00000000", -- 00001FAC
+		X"00000000", -- 00001FB0
+		X"00000000", -- 00001FB4
+		X"00000000", -- 00001FB8
+		X"00000000", -- 00001FBC
+		X"00000000", -- 00001FC0
+		X"00000000", -- 00001FC4
+		X"00000000", -- 00001FC8
+		X"00000000", -- 00001FCC
+		X"00000000", -- 00001FD0
+		X"00000000", -- 00001FD4
+		X"00000000", -- 00001FD8
+		X"00000000", -- 00001FDC
+		X"00000000", -- 00001FE0
+		X"00000000", -- 00001FE4
+		X"00000000", -- 00001FE8
+		X"00000000", -- 00001FEC
+		X"00000000", -- 00001FF0
+		X"00000000", -- 00001FF4
+		X"00000000", -- 00001FF8
+		X"00000000"  -- 00001FFC
+	);
+
+begin
+
+PROM_READ:
+	process(clk)
+	begin
+		if rising_edge(clk) and ce = '1' then
+			dout <= word_array(to_integer(addr(12 downto 2)));
+		end if;
+	end process;
+
+end data;
diff --git a/lib/CPUs/MIPS/src/bootloader_flash.dis b/lib/CPUs/MIPS/src/bootloader_flash.dis
new file mode 100644
index 0000000..c46e185
--- /dev/null
+++ b/lib/CPUs/MIPS/src/bootloader_flash.dis
@@ -0,0 +1,1468 @@
+
+bootloader_flash.elf:     file format elf32-bigmips
+
+
+Disassembly of section .init:
+
+9fc00000 <__entry>:
+9fc00000:	3c1d8400 	lui	sp,0x8400
+9fc00004:	27bdeff0 	addiu	sp,sp,-4112
+9fc00008:	3c1a1040 	lui	k0,0x1040
+9fc0000c:	375a000a 	ori	k0,k0,0xa
+9fc00010:	409a6000 	mtc0	k0,c0_sr
+9fc00014:	241a0000 	li	k0,0
+9fc00018:	409a6800 	mtc0	k0,c0_cause
+9fc0001c:	401a7800 	mfc0	k0,c0_prid
+9fc00020:	00000000 	nop
+9fc00024:	409af800 	mtc0	k0,$31
+9fc00028:	42000020 	c0	0x20
+9fc0002c:	42000022 	c0	0x22
+9fc00030:	3c1a9fc0 	lui	k0,0x9fc0
+9fc00034:	275a005c 	addiu	k0,k0,92
+9fc00038:	0340f809 	jalr	k0
+9fc0003c:	00000000 	nop
+9fc00040:	3c1a9fc0 	lui	k0,0x9fc0
+9fc00044:	275a1150 	addiu	k0,k0,4432
+9fc00048:	0340f809 	jalr	k0
+9fc0004c:	00000000 	nop
+
+9fc00050 <_terminate>:
+9fc00050:	00000000 	nop
+9fc00054:	0bf00014 	j	9fc00050 <_terminate>
+9fc00058:	00000000 	nop
+
+9fc0005c <_init>:
+9fc0005c:	3c1aac01 275a0008 241b000d af5b0000     <...'Z..$....[..
+9fc0006c:	03e00008                                ....
+
+Disassembly of section .ktext:
+
+9fc00180 <_exc_handler>:
+9fc00180:	401a6800 	mfc0	k0,c0_cause
+9fc00184:	3c1bc000 	lui	k1,0xc000
+9fc00188:	001ad082 	srl	k0,k0,0x2
+9fc0018c:	335a000f 	andi	k0,k0,0xf
+9fc00190:	035bd025 	or	k0,k0,k1
+9fc00194:	3c1bac00 	lui	k1,0xac00
+9fc00198:	277b0000 	addiu	k1,k1,0
+9fc0019c:	af7a0000 	sw	k0,0(k1)
+9fc001a0:	401a6800 	mfc0	k0,c0_cause
+9fc001a4:	00000000 	nop
+9fc001a8:	001ad202 	srl	k0,k0,0x8
+9fc001ac:	335a00ff 	andi	k0,k0,0xff
+9fc001b0:	1740fffb 	bnez	k0,9fc001a0 <_exc_handler+0x20>
+9fc001b4:	00000000 	nop
+9fc001b8:	401a7000 	mfc0	k0,c0_epc
+9fc001bc:	00000000 	nop
+9fc001c0:	03400008 	jr	k0
+9fc001c4:	42000010 	rfe
+
+Disassembly of section .text:
+
+9fc001c8 <CP0_SR_read>:
+9fc001c8:	40026000 	mfc0	v0,c0_sr
+9fc001cc:	03e00008 	jr	ra
+9fc001d0:	00000000 	nop
+
+9fc001d4 <CP0_SR_write>:
+9fc001d4:	40846000 	mtc0	a0,c0_sr
+9fc001d8:	03e00008 	jr	ra
+9fc001dc:	00000000 	nop
+
+9fc001e0 <CP0_CR_read>:
+9fc001e0:	40026800 	mfc0	v0,c0_cause
+9fc001e4:	03e00008 	jr	ra
+9fc001e8:	00000000 	nop
+
+9fc001ec <CP0_CR_write>:
+9fc001ec:	40846800 	mtc0	a0,c0_cause
+9fc001f0:	03e00008 	jr	ra
+9fc001f4:	00000000 	nop
+
+9fc001f8 <CP0_PRID_read>:
+9fc001f8:	40027800 	mfc0	v0,c0_prid
+9fc001fc:	03e00008 	jr	ra
+9fc00200:	00000000 	nop
+
+9fc00204 <readchar>:
+9fc00204:	3c02ac01 	lui	v0,0xac01
+9fc00208:	34430004 	ori	v1,v0,0x4
+9fc0020c:	8c620000 	lw	v0,0(v1)
+9fc00210:	00000000 	nop
+9fc00214:	30420010 	andi	v0,v0,0x10
+9fc00218:	1040fffc 	beqz	v0,9fc0020c <readchar+0x8>
+9fc0021c:	3c02ac01 	lui	v0,0xac01
+9fc00220:	8c420000 	lw	v0,0(v0)
+9fc00224:	00000000 	nop
+9fc00228:	00021600 	sll	v0,v0,0x18
+9fc0022c:	03e00008 	jr	ra
+9fc00230:	00021603 	sra	v0,v0,0x18
+
+9fc00234 <writechar>:
+9fc00234:	00042600 	sll	a0,a0,0x18
+9fc00238:	3c02ac01 	lui	v0,0xac01
+9fc0023c:	00042603 	sra	a0,a0,0x18
+9fc00240:	34430004 	ori	v1,v0,0x4
+9fc00244:	8c620000 	lw	v0,0(v1)
+9fc00248:	00000000 	nop
+9fc0024c:	30420002 	andi	v0,v0,0x2
+9fc00250:	1440fffc 	bnez	v0,9fc00244 <writechar+0x10>
+9fc00254:	3c02ac01 	lui	v0,0xac01
+9fc00258:	ac440000 	sw	a0,0(v0)
+9fc0025c:	03e00008 	jr	ra
+9fc00260:	00000000 	nop
+
+9fc00264 <_putchar>:
+9fc00264:	00042600 	sll	a0,a0,0x18
+9fc00268:	00042603 	sra	a0,a0,0x18
+9fc0026c:	2402000a 	li	v0,10
+9fc00270:	1482000a 	bne	a0,v0,9fc0029c <_putchar+0x38>
+9fc00274:	3c02ac01 	lui	v0,0xac01
+9fc00278:	34430004 	ori	v1,v0,0x4
+9fc0027c:	8c620000 	lw	v0,0(v1)
+9fc00280:	00000000 	nop
+9fc00284:	30420002 	andi	v0,v0,0x2
+9fc00288:	1440fffc 	bnez	v0,9fc0027c <_putchar+0x18>
+9fc0028c:	3c02ac01 	lui	v0,0xac01
+9fc00290:	2403000d 	li	v1,13
+9fc00294:	ac430000 	sw	v1,0(v0)
+9fc00298:	3c02ac01 	lui	v0,0xac01
+9fc0029c:	34430004 	ori	v1,v0,0x4
+9fc002a0:	8c620000 	lw	v0,0(v1)
+9fc002a4:	00000000 	nop
+9fc002a8:	30420002 	andi	v0,v0,0x2
+9fc002ac:	1440fffc 	bnez	v0,9fc002a0 <_putchar+0x3c>
+9fc002b0:	3c02ac01 	lui	v0,0xac01
+9fc002b4:	ac440000 	sw	a0,0(v0)
+9fc002b8:	03e00008 	jr	ra
+9fc002bc:	00000000 	nop
+
+9fc002c0 <sputs>:
+9fc002c0:	3c02ac01 	lui	v0,0xac01
+9fc002c4:	34470004 	ori	a3,v0,0x4
+9fc002c8:	00802821 	move	a1,a0
+9fc002cc:	2409000a 	li	t1,10
+9fc002d0:	3c06ac01 	lui	a2,0xac01
+9fc002d4:	0bf000c6 	j	9fc00318 <sputs+0x58>
+9fc002d8:	2408000d 	li	t0,13
+9fc002dc:	14690007 	bne	v1,t1,9fc002fc <sputs+0x3c>
+9fc002e0:	00000000 	nop
+9fc002e4:	8ce20000 	lw	v0,0(a3)
+9fc002e8:	00000000 	nop
+9fc002ec:	30420002 	andi	v0,v0,0x2
+9fc002f0:	1440fffc 	bnez	v0,9fc002e4 <sputs+0x24>
+9fc002f4:	00000000 	nop
+9fc002f8:	acc80000 	sw	t0,0(a2)
+9fc002fc:	8ce20000 	lw	v0,0(a3)
+9fc00300:	00000000 	nop
+9fc00304:	30420002 	andi	v0,v0,0x2
+9fc00308:	1440fffc 	bnez	v0,9fc002fc <sputs+0x3c>
+9fc0030c:	00000000 	nop
+9fc00310:	acc30000 	sw	v1,0(a2)
+9fc00314:	24a50001 	addiu	a1,a1,1
+9fc00318:	80a30000 	lb	v1,0(a1)
+9fc0031c:	00000000 	nop
+9fc00320:	1460ffee 	bnez	v1,9fc002dc <sputs+0x1c>
+9fc00324:	00a41023 	subu	v0,a1,a0
+9fc00328:	03e00008 	jr	ra
+9fc0032c:	00000000 	nop
+
+9fc00330 <print_byte>:
+9fc00330:	00042600 	sll	a0,a0,0x18
+9fc00334:	3c02ac01 	lui	v0,0xac01
+9fc00338:	00042603 	sra	a0,a0,0x18
+9fc0033c:	344a0004 	ori	t2,v0,0x4
+9fc00340:	00003821 	move	a3,zero
+9fc00344:	3c09ac01 	lui	t1,0xac01
+9fc00348:	24080002 	li	t0,2
+9fc0034c:	308200ff 	andi	v0,a0,0xff
+9fc00350:	00022902 	srl	a1,v0,0x4
+9fc00354:	00041100 	sll	v0,a0,0x4
+9fc00358:	00022600 	sll	a0,v0,0x18
+9fc0035c:	2ca3000a 	sltiu	v1,a1,10
+9fc00360:	00042603 	sra	a0,a0,0x18
+9fc00364:	14600002 	bnez	v1,9fc00370 <print_byte+0x40>
+9fc00368:	24a60030 	addiu	a2,a1,48
+9fc0036c:	24a60037 	addiu	a2,a1,55
+9fc00370:	8d420000 	lw	v0,0(t2)
+9fc00374:	00000000 	nop
+9fc00378:	30420002 	andi	v0,v0,0x2
+9fc0037c:	1440fffc 	bnez	v0,9fc00370 <print_byte+0x40>
+9fc00380:	00061600 	sll	v0,a2,0x18
+9fc00384:	00021603 	sra	v0,v0,0x18
+9fc00388:	24e70001 	addiu	a3,a3,1
+9fc0038c:	ad220000 	sw	v0,0(t1)
+9fc00390:	14e8ffef 	bne	a3,t0,9fc00350 <print_byte+0x20>
+9fc00394:	308200ff 	andi	v0,a0,0xff
+9fc00398:	03e00008 	jr	ra
+9fc0039c:	00000000 	nop
+
+9fc003a0 <print_word>:
+9fc003a0:	27bdffe0 	addiu	sp,sp,-32
+9fc003a4:	afb20018 	sw	s2,24(sp)
+9fc003a8:	afb10014 	sw	s1,20(sp)
+9fc003ac:	afb00010 	sw	s0,16(sp)
+9fc003b0:	afbf001c 	sw	ra,28(sp)
+9fc003b4:	00808821 	move	s1,a0
+9fc003b8:	00008021 	move	s0,zero
+9fc003bc:	24120004 	li	s2,4
+9fc003c0:	00112603 	sra	a0,s1,0x18
+9fc003c4:	0ff000cc 	jal	9fc00330 <print_byte>
+9fc003c8:	26100001 	addiu	s0,s0,1
+9fc003cc:	1612fffc 	bne	s0,s2,9fc003c0 <print_word+0x20>
+9fc003d0:	00118a00 	sll	s1,s1,0x8
+9fc003d4:	8fbf001c 	lw	ra,28(sp)
+9fc003d8:	8fb20018 	lw	s2,24(sp)
+9fc003dc:	8fb10014 	lw	s1,20(sp)
+9fc003e0:	8fb00010 	lw	s0,16(sp)
+9fc003e4:	03e00008 	jr	ra
+9fc003e8:	27bd0020 	addiu	sp,sp,32
+
+9fc003ec <memdump>:
+9fc003ec:	27bdffc8 	addiu	sp,sp,-56
+9fc003f0:	afb60028 	sw	s6,40(sp)
+9fc003f4:	afbf0034 	sw	ra,52(sp)
+9fc003f8:	afbe0030 	sw	s8,48(sp)
+9fc003fc:	afb7002c 	sw	s7,44(sp)
+9fc00400:	afb50024 	sw	s5,36(sp)
+9fc00404:	afb40020 	sw	s4,32(sp)
+9fc00408:	afb3001c 	sw	s3,28(sp)
+9fc0040c:	afb20018 	sw	s2,24(sp)
+9fc00410:	afb10014 	sw	s1,20(sp)
+9fc00414:	afb00010 	sw	s0,16(sp)
+9fc00418:	00801021 	move	v0,a0
+9fc0041c:	10a00002 	beqz	a1,9fc00428 <memdump+0x3c>
+9fc00420:	00c0b021 	move	s6,a2
+9fc00424:	00002021 	move	a0,zero
+9fc00428:	00409821 	move	s3,v0
+9fc0042c:	3c02ac01 	lui	v0,0xac01
+9fc00430:	00e09021 	move	s2,a3
+9fc00434:	0080a821 	move	s5,a0
+9fc00438:	345e0004 	ori	s8,v0,0x4
+9fc0043c:	00e0a021 	move	s4,a3
+9fc00440:	3c17ac01 	lui	s7,0xac01
+9fc00444:	0ff000e8 	jal	9fc003a0 <print_word>
+9fc00448:	02a02021 	move	a0,s5
+9fc0044c:	3c049fc0 	lui	a0,0x9fc0
+9fc00450:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc00454:	248416a0 	addiu	a0,a0,5792
+9fc00458:	02608821 	move	s1,s3
+9fc0045c:	0bf00128 	j	9fc004a0 <memdump+0xb4>
+9fc00460:	00008021 	move	s0,zero
+9fc00464:	12400009 	beqz	s2,9fc0048c <memdump+0xa0>
+9fc00468:	00000000 	nop
+9fc0046c:	82240000 	lb	a0,0(s1)
+9fc00470:	0ff000cc 	jal	9fc00330 <print_byte>
+9fc00474:	2652ffff 	addiu	s2,s2,-1
+9fc00478:	3c049fc0 	lui	a0,0x9fc0
+9fc0047c:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc00480:	24841778 	addiu	a0,a0,6008
+9fc00484:	0bf00128 	j	9fc004a0 <memdump+0xb4>
+9fc00488:	26310001 	addiu	s1,s1,1
+9fc0048c:	3c049fc0 	lui	a0,0x9fc0
+9fc00490:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc00494:	248416a4 	addiu	a0,a0,5796
+9fc00498:	0bf0012c 	j	9fc004b0 <memdump+0xc4>
+9fc0049c:	3c049fc0 	lui	a0,0x9fc0
+9fc004a0:	0216102a 	slt	v0,s0,s6
+9fc004a4:	1440ffef 	bnez	v0,9fc00464 <memdump+0x78>
+9fc004a8:	26100001 	addiu	s0,s0,1
+9fc004ac:	3c049fc0 	lui	a0,0x9fc0
+9fc004b0:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc004b4:	248416a4 	addiu	a0,a0,5796
+9fc004b8:	02602821 	move	a1,s3
+9fc004bc:	0bf00155 	j	9fc00554 <memdump+0x168>
+9fc004c0:	00002021 	move	a0,zero
+9fc004c4:	1280001e 	beqz	s4,9fc00540 <memdump+0x154>
+9fc004c8:	00000000 	nop
+9fc004cc:	90a30000 	lbu	v1,0(a1)
+9fc004d0:	00000000 	nop
+9fc004d4:	2462ffe0 	addiu	v0,v1,-32
+9fc004d8:	304200ff 	andi	v0,v0,0xff
+9fc004dc:	2c420060 	sltiu	v0,v0,96
+9fc004e0:	14400003 	bnez	v0,9fc004f0 <memdump+0x104>
+9fc004e4:	00031e00 	sll	v1,v1,0x18
+9fc004e8:	2403002e 	li	v1,46
+9fc004ec:	00031e00 	sll	v1,v1,0x18
+9fc004f0:	00031e03 	sra	v1,v1,0x18
+9fc004f4:	2402000a 	li	v0,10
+9fc004f8:	14620007 	bne	v1,v0,9fc00518 <memdump+0x12c>
+9fc004fc:	00000000 	nop
+9fc00500:	8fc20000 	lw	v0,0(s8)
+9fc00504:	00000000 	nop
+9fc00508:	30420002 	andi	v0,v0,0x2
+9fc0050c:	1440fffc 	bnez	v0,9fc00500 <memdump+0x114>
+9fc00510:	2402000d 	li	v0,13
+9fc00514:	aee20000 	sw	v0,0(s7)
+9fc00518:	8fc20000 	lw	v0,0(s8)
+9fc0051c:	00000000 	nop
+9fc00520:	30420002 	andi	v0,v0,0x2
+9fc00524:	1440fffc 	bnez	v0,9fc00518 <memdump+0x12c>
+9fc00528:	00000000 	nop
+9fc0052c:	aee30000 	sw	v1,0(s7)
+9fc00530:	2694ffff 	addiu	s4,s4,-1
+9fc00534:	24840001 	addiu	a0,a0,1
+9fc00538:	0bf00155 	j	9fc00554 <memdump+0x168>
+9fc0053c:	24a50001 	addiu	a1,a1,1
+9fc00540:	3c049fc0 	lui	a0,0x9fc0
+9fc00544:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc00548:	24841778 	addiu	a0,a0,6008
+9fc0054c:	0bf00159 	j	9fc00564 <memdump+0x178>
+9fc00550:	3c049fc0 	lui	a0,0x9fc0
+9fc00554:	0096102a 	slt	v0,a0,s6
+9fc00558:	1440ffda 	bnez	v0,9fc004c4 <memdump+0xd8>
+9fc0055c:	00000000 	nop
+9fc00560:	3c049fc0 	lui	a0,0x9fc0
+9fc00564:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc00568:	248416cc 	addiu	a0,a0,5836
+9fc0056c:	02b6a821 	addu	s5,s5,s6
+9fc00570:	1640ffb4 	bnez	s2,9fc00444 <memdump+0x58>
+9fc00574:	02769821 	addu	s3,s3,s6
+9fc00578:	8fbf0034 	lw	ra,52(sp)
+9fc0057c:	8fbe0030 	lw	s8,48(sp)
+9fc00580:	8fb7002c 	lw	s7,44(sp)
+9fc00584:	8fb60028 	lw	s6,40(sp)
+9fc00588:	8fb50024 	lw	s5,36(sp)
+9fc0058c:	8fb40020 	lw	s4,32(sp)
+9fc00590:	8fb3001c 	lw	s3,28(sp)
+9fc00594:	8fb20018 	lw	s2,24(sp)
+9fc00598:	8fb10014 	lw	s1,20(sp)
+9fc0059c:	8fb00010 	lw	s0,16(sp)
+9fc005a0:	03e00008 	jr	ra
+9fc005a4:	27bd0038 	addiu	sp,sp,56
+
+9fc005a8 <PrintBuffer8>:
+9fc005a8:	00c03821 	move	a3,a2
+9fc005ac:	00a03021 	move	a2,a1
+9fc005b0:	0bf000fb 	j	9fc003ec <memdump>
+9fc005b4:	24050001 	li	a1,1
+
+9fc005b8 <cfi_get_status>:
+9fc005b8:	8c840000 	lw	a0,0(a0)
+9fc005bc:	3c020070 	lui	v0,0x70
+9fc005c0:	34420070 	ori	v0,v0,0x70
+9fc005c4:	3c0300ff 	lui	v1,0xff
+9fc005c8:	ac820000 	sw	v0,0(a0)
+9fc005cc:	346300ff 	ori	v1,v1,0xff
+9fc005d0:	8c820000 	lw	v0,0(a0)
+9fc005d4:	ac830000 	sw	v1,0(a0)
+9fc005d8:	03e00008 	jr	ra
+9fc005dc:	00000000 	nop
+
+9fc005e0 <cfi_init>:
+9fc005e0:	27bdfff8 	addiu	sp,sp,-8
+9fc005e4:	ac850000 	sw	a1,0(a0)
+9fc005e8:	24820008 	addiu	v0,a0,8
+9fc005ec:	0bf0017f 	j	9fc005fc <cfi_init+0x1c>
+9fc005f0:	24830020 	addiu	v1,a0,32
+9fc005f4:	a0400000 	sb	zero,0(v0)
+9fc005f8:	24420001 	addiu	v0,v0,1
+9fc005fc:	1443fffd 	bne	v0,v1,9fc005f4 <cfi_init+0x14>
+9fc00600:	00000000 	nop
+9fc00604:	24020001 	li	v0,1
+9fc00608:	ac820004 	sw	v0,4(a0)
+9fc0060c:	03e00008 	jr	ra
+9fc00610:	27bd0008 	addiu	sp,sp,8
+
+9fc00614 <cfi_find>:
+9fc00614:	8c870000 	lw	a3,0(a0)
+9fc00618:	3c020098 	lui	v0,0x98
+9fc0061c:	34420098 	ori	v0,v0,0x98
+9fc00620:	ace20000 	sw	v0,0(a3)
+9fc00624:	3c0200ff 	lui	v0,0xff
+9fc00628:	344200ff 	ori	v0,v0,0xff
+9fc0062c:	ace20000 	sw	v0,0(a3)
+9fc00630:	3c020090 	lui	v0,0x90
+9fc00634:	34420090 	ori	v0,v0,0x90
+9fc00638:	ace20000 	sw	v0,0(a3)
+9fc0063c:	00804021 	move	t0,a0
+9fc00640:	94e4009c 	lhu	a0,156(a3)
+9fc00644:	24030002 	li	v1,2
+9fc00648:	24020020 	li	v0,32
+9fc0064c:	ad030008 	sw	v1,8(t0)
+9fc00650:	ad03001c 	sw	v1,28(t0)
+9fc00654:	ad020018 	sw	v0,24(t0)
+9fc00658:	3084ffff 	andi	a0,a0,0xffff
+9fc0065c:	0bf0019d 	j	9fc00674 <cfi_find+0x60>
+9fc00660:	00001821 	move	v1,zero
+9fc00664:	8d020008 	lw	v0,8(t0)
+9fc00668:	00000000 	nop
+9fc0066c:	00021040 	sll	v0,v0,0x1
+9fc00670:	ad020008 	sw	v0,8(t0)
+9fc00674:	0064102b 	sltu	v0,v1,a0
+9fc00678:	1440fffa 	bnez	v0,9fc00664 <cfi_find+0x50>
+9fc0067c:	24630001 	addiu	v1,v1,1
+9fc00680:	94e200ac 	lhu	v0,172(a3)
+9fc00684:	94e300a8 	lhu	v1,168(a3)
+9fc00688:	3042ffff 	andi	v0,v0,0xffff
+9fc0068c:	8d04001c 	lw	a0,28(t0)
+9fc00690:	3063ffff 	andi	v1,v1,0xffff
+9fc00694:	00021200 	sll	v0,v0,0x8
+9fc00698:	00432825 	or	a1,v0,v1
+9fc0069c:	ad040014 	sw	a0,20(t0)
+9fc006a0:	0bf001ae 	j	9fc006b8 <cfi_find+0xa4>
+9fc006a4:	00001821 	move	v1,zero
+9fc006a8:	8d020014 	lw	v0,20(t0)
+9fc006ac:	00000000 	nop
+9fc006b0:	00021040 	sll	v0,v0,0x1
+9fc006b4:	ad020014 	sw	v0,20(t0)
+9fc006b8:	0065102b 	sltu	v0,v1,a1
+9fc006bc:	1440fffa 	bnez	v0,9fc006a8 <cfi_find+0x94>
+9fc006c0:	24630001 	addiu	v1,v1,1
+9fc006c4:	94e300b8 	lhu	v1,184(a3)
+9fc006c8:	94e600b4 	lhu	a2,180(a3)
+9fc006cc:	94e200c0 	lhu	v0,192(a3)
+9fc006d0:	94e400bc 	lhu	a0,188(a3)
+9fc006d4:	8d05001c 	lw	a1,28(t0)
+9fc006d8:	3042ffff 	andi	v0,v0,0xffff
+9fc006dc:	3084ffff 	andi	a0,a0,0xffff
+9fc006e0:	00021200 	sll	v0,v0,0x8
+9fc006e4:	00441025 	or	v0,v0,a0
+9fc006e8:	00052a00 	sll	a1,a1,0x8
+9fc006ec:	00a20018 	mult	a1,v0
+9fc006f0:	3063ffff 	andi	v1,v1,0xffff
+9fc006f4:	30c6ffff 	andi	a2,a2,0xffff
+9fc006f8:	00031a00 	sll	v1,v1,0x8
+9fc006fc:	00661825 	or	v1,v1,a2
+9fc00700:	24630001 	addiu	v1,v1,1
+9fc00704:	ad030010 	sw	v1,16(t0)
+9fc00708:	3c0300ff 	lui	v1,0xff
+9fc0070c:	346300ff 	ori	v1,v1,0xff
+9fc00710:	00001021 	move	v0,zero
+9fc00714:	00002812 	mflo	a1
+9fc00718:	ad05000c 	sw	a1,12(t0)
+9fc0071c:	ace30000 	sw	v1,0(a3)
+9fc00720:	03e00008 	jr	ra
+9fc00724:	00000000 	nop
+
+9fc00728 <cfi_block_is_locked>:
+9fc00728:	8c820008 	lw	v0,8(a0)
+9fc0072c:	8c860000 	lw	a2,0(a0)
+9fc00730:	00021082 	srl	v0,v0,0x2
+9fc00734:	00a2102b 	sltu	v0,a1,v0
+9fc00738:	14400004 	bnez	v0,9fc0074c <cfi_block_is_locked+0x24>
+9fc0073c:	3c030090 	lui	v1,0x90
+9fc00740:	3c028010 	lui	v0,0x8010
+9fc00744:	03e00008 	jr	ra
+9fc00748:	34420002 	ori	v0,v0,0x2
+9fc0074c:	8c820010 	lw	v0,16(a0)
+9fc00750:	00000000 	nop
+9fc00754:	2442ffff 	addiu	v0,v0,-1
+9fc00758:	00021400 	sll	v0,v0,0x10
+9fc0075c:	00a21024 	and	v0,a1,v0
+9fc00760:	24420002 	addiu	v0,v0,2
+9fc00764:	34630090 	ori	v1,v1,0x90
+9fc00768:	00021080 	sll	v0,v0,0x2
+9fc0076c:	acc30000 	sw	v1,0(a2)
+9fc00770:	00c21021 	addu	v0,a2,v0
+9fc00774:	8c430000 	lw	v1,0(v0)
+9fc00778:	3c020001 	lui	v0,0x1
+9fc0077c:	34420001 	ori	v0,v0,0x1
+9fc00780:	00621824 	and	v1,v1,v0
+9fc00784:	3c0200ff 	lui	v0,0xff
+9fc00788:	344200ff 	ori	v0,v0,0xff
+9fc0078c:	acc20000 	sw	v0,0(a2)
+9fc00790:	03e00008 	jr	ra
+9fc00794:	0003102b 	sltu	v0,zero,v1
+
+9fc00798 <cfi_block_erase>:
+9fc00798:	8c820008 	lw	v0,8(a0)
+9fc0079c:	00a01821 	move	v1,a1
+9fc007a0:	00021082 	srl	v0,v0,0x2
+9fc007a4:	00a2102b 	sltu	v0,a1,v0
+9fc007a8:	8c850000 	lw	a1,0(a0)
+9fc007ac:	14400003 	bnez	v0,9fc007bc <cfi_block_erase+0x24>
+9fc007b0:	3c028010 	lui	v0,0x8010
+9fc007b4:	0bf0020c 	j	9fc00830 <cfi_block_erase+0x98>
+9fc007b8:	34430002 	ori	v1,v0,0x2
+9fc007bc:	8c820010 	lw	v0,16(a0)
+9fc007c0:	00000000 	nop
+9fc007c4:	2442ffff 	addiu	v0,v0,-1
+9fc007c8:	00021400 	sll	v0,v0,0x10
+9fc007cc:	00621024 	and	v0,v1,v0
+9fc007d0:	00021080 	sll	v0,v0,0x2
+9fc007d4:	00a22021 	addu	a0,a1,v0
+9fc007d8:	3c020020 	lui	v0,0x20
+9fc007dc:	34420020 	ori	v0,v0,0x20
+9fc007e0:	ac820000 	sw	v0,0(a0)
+9fc007e4:	3c0200d0 	lui	v0,0xd0
+9fc007e8:	344200d0 	ori	v0,v0,0xd0
+9fc007ec:	ac820000 	sw	v0,0(a0)
+9fc007f0:	3c020080 	lui	v0,0x80
+9fc007f4:	34430080 	ori	v1,v0,0x80
+9fc007f8:	8c860000 	lw	a2,0(a0)
+9fc007fc:	00000000 	nop
+9fc00800:	00c31024 	and	v0,a2,v1
+9fc00804:	1443fffc 	bne	v0,v1,9fc007f8 <cfi_block_erase+0x60>
+9fc00808:	3c02002a 	lui	v0,0x2a
+9fc0080c:	3442002a 	ori	v0,v0,0x2a
+9fc00810:	00c21024 	and	v0,a2,v0
+9fc00814:	10400003 	beqz	v0,9fc00824 <cfi_block_erase+0x8c>
+9fc00818:	00001821 	move	v1,zero
+9fc0081c:	3c029010 	lui	v0,0x9010
+9fc00820:	00c21825 	or	v1,a2,v0
+9fc00824:	3c0200ff 	lui	v0,0xff
+9fc00828:	344200ff 	ori	v0,v0,0xff
+9fc0082c:	ac820000 	sw	v0,0(a0)
+9fc00830:	03e00008 	jr	ra
+9fc00834:	00601021 	move	v0,v1
+
+9fc00838 <cfi_block_lock>:
+9fc00838:	8c820008 	lw	v0,8(a0)
+9fc0083c:	00a01821 	move	v1,a1
+9fc00840:	00021082 	srl	v0,v0,0x2
+9fc00844:	00a2102b 	sltu	v0,a1,v0
+9fc00848:	8c850000 	lw	a1,0(a0)
+9fc0084c:	14400003 	bnez	v0,9fc0085c <cfi_block_lock+0x24>
+9fc00850:	3c028010 	lui	v0,0x8010
+9fc00854:	0bf00234 	j	9fc008d0 <cfi_block_lock+0x98>
+9fc00858:	34430002 	ori	v1,v0,0x2
+9fc0085c:	8c820010 	lw	v0,16(a0)
+9fc00860:	00000000 	nop
+9fc00864:	2442ffff 	addiu	v0,v0,-1
+9fc00868:	00021400 	sll	v0,v0,0x10
+9fc0086c:	00621024 	and	v0,v1,v0
+9fc00870:	00021080 	sll	v0,v0,0x2
+9fc00874:	00a22021 	addu	a0,a1,v0
+9fc00878:	3c020060 	lui	v0,0x60
+9fc0087c:	34420060 	ori	v0,v0,0x60
+9fc00880:	ac820000 	sw	v0,0(a0)
+9fc00884:	3c020001 	lui	v0,0x1
+9fc00888:	34420001 	ori	v0,v0,0x1
+9fc0088c:	ac820000 	sw	v0,0(a0)
+9fc00890:	3c020080 	lui	v0,0x80
+9fc00894:	34430080 	ori	v1,v0,0x80
+9fc00898:	8c860000 	lw	a2,0(a0)
+9fc0089c:	00000000 	nop
+9fc008a0:	00c31024 	and	v0,a2,v1
+9fc008a4:	1443fffc 	bne	v0,v1,9fc00898 <cfi_block_lock+0x60>
+9fc008a8:	3c020038 	lui	v0,0x38
+9fc008ac:	34420038 	ori	v0,v0,0x38
+9fc008b0:	00c21024 	and	v0,a2,v0
+9fc008b4:	10400003 	beqz	v0,9fc008c4 <cfi_block_lock+0x8c>
+9fc008b8:	00001821 	move	v1,zero
+9fc008bc:	3c029010 	lui	v0,0x9010
+9fc008c0:	00c21825 	or	v1,a2,v0
+9fc008c4:	3c0200ff 	lui	v0,0xff
+9fc008c8:	344200ff 	ori	v0,v0,0xff
+9fc008cc:	ac820000 	sw	v0,0(a0)
+9fc008d0:	03e00008 	jr	ra
+9fc008d4:	00601021 	move	v0,v1
+
+9fc008d8 <cfi_block_unlock>:
+9fc008d8:	8c820008 	lw	v0,8(a0)
+9fc008dc:	00a01821 	move	v1,a1
+9fc008e0:	00021082 	srl	v0,v0,0x2
+9fc008e4:	00a2102b 	sltu	v0,a1,v0
+9fc008e8:	8c850000 	lw	a1,0(a0)
+9fc008ec:	14400003 	bnez	v0,9fc008fc <cfi_block_unlock+0x24>
+9fc008f0:	3c028010 	lui	v0,0x8010
+9fc008f4:	0bf0025c 	j	9fc00970 <cfi_block_unlock+0x98>
+9fc008f8:	34430002 	ori	v1,v0,0x2
+9fc008fc:	8c820010 	lw	v0,16(a0)
+9fc00900:	00000000 	nop
+9fc00904:	2442ffff 	addiu	v0,v0,-1
+9fc00908:	00021400 	sll	v0,v0,0x10
+9fc0090c:	00621024 	and	v0,v1,v0
+9fc00910:	00021080 	sll	v0,v0,0x2
+9fc00914:	00a22021 	addu	a0,a1,v0
+9fc00918:	3c020060 	lui	v0,0x60
+9fc0091c:	34420060 	ori	v0,v0,0x60
+9fc00920:	ac820000 	sw	v0,0(a0)
+9fc00924:	3c0200d0 	lui	v0,0xd0
+9fc00928:	344200d0 	ori	v0,v0,0xd0
+9fc0092c:	ac820000 	sw	v0,0(a0)
+9fc00930:	3c020080 	lui	v0,0x80
+9fc00934:	34430080 	ori	v1,v0,0x80
+9fc00938:	8c860000 	lw	a2,0(a0)
+9fc0093c:	00000000 	nop
+9fc00940:	00c31024 	and	v0,a2,v1
+9fc00944:	1443fffc 	bne	v0,v1,9fc00938 <cfi_block_unlock+0x60>
+9fc00948:	3c020038 	lui	v0,0x38
+9fc0094c:	34420038 	ori	v0,v0,0x38
+9fc00950:	00c21024 	and	v0,a2,v0
+9fc00954:	10400003 	beqz	v0,9fc00964 <cfi_block_unlock+0x8c>
+9fc00958:	00001821 	move	v1,zero
+9fc0095c:	3c029010 	lui	v0,0x9010
+9fc00960:	00c21825 	or	v1,a2,v0
+9fc00964:	3c0200ff 	lui	v0,0xff
+9fc00968:	344200ff 	ori	v0,v0,0xff
+9fc0096c:	ac820000 	sw	v0,0(a0)
+9fc00970:	03e00008 	jr	ra
+9fc00974:	00601021 	move	v0,v1
+
+9fc00978 <cfi_program_single>:
+9fc00978:	8c820008 	lw	v0,8(a0)
+9fc0097c:	8c840000 	lw	a0,0(a0)
+9fc00980:	00021082 	srl	v0,v0,0x2
+9fc00984:	00a2102b 	sltu	v0,a1,v0
+9fc00988:	14400003 	bnez	v0,9fc00998 <cfi_program_single+0x20>
+9fc0098c:	3c028010 	lui	v0,0x8010
+9fc00990:	0bf0027c 	j	9fc009f0 <cfi_program_single+0x78>
+9fc00994:	34430002 	ori	v1,v0,0x2
+9fc00998:	00051080 	sll	v0,a1,0x2
+9fc0099c:	00822021 	addu	a0,a0,v0
+9fc009a0:	3c020040 	lui	v0,0x40
+9fc009a4:	34420040 	ori	v0,v0,0x40
+9fc009a8:	ac820000 	sw	v0,0(a0)
+9fc009ac:	3c020080 	lui	v0,0x80
+9fc009b0:	ac860000 	sw	a2,0(a0)
+9fc009b4:	34430080 	ori	v1,v0,0x80
+9fc009b8:	8c860000 	lw	a2,0(a0)
+9fc009bc:	00000000 	nop
+9fc009c0:	00c31024 	and	v0,a2,v1
+9fc009c4:	1443fffc 	bne	v0,v1,9fc009b8 <cfi_program_single+0x40>
+9fc009c8:	3c02001a 	lui	v0,0x1a
+9fc009cc:	3442001a 	ori	v0,v0,0x1a
+9fc009d0:	00c21024 	and	v0,a2,v0
+9fc009d4:	10400003 	beqz	v0,9fc009e4 <cfi_program_single+0x6c>
+9fc009d8:	00001821 	move	v1,zero
+9fc009dc:	3c029010 	lui	v0,0x9010
+9fc009e0:	00c21825 	or	v1,a2,v0
+9fc009e4:	3c0200ff 	lui	v0,0xff
+9fc009e8:	344200ff 	ori	v0,v0,0xff
+9fc009ec:	ac820000 	sw	v0,0(a0)
+9fc009f0:	03e00008 	jr	ra
+9fc009f4:	00601021 	move	v0,v1
+
+9fc009f8 <cfi_program_multi>:
+9fc009f8:	8c820008 	lw	v0,8(a0)
+9fc009fc:	27bdffe8 	addiu	sp,sp,-24
+9fc00a00:	00021082 	srl	v0,v0,0x2
+9fc00a04:	00a2102b 	sltu	v0,a1,v0
+9fc00a08:	afb40014 	sw	s4,20(sp)
+9fc00a0c:	afb30010 	sw	s3,16(sp)
+9fc00a10:	afb2000c 	sw	s2,12(sp)
+9fc00a14:	afb10008 	sw	s1,8(sp)
+9fc00a18:	afb00004 	sw	s0,4(sp)
+9fc00a1c:	0080c021 	move	t8,a0
+9fc00a20:	8c8e0000 	lw	t6,0(a0)
+9fc00a24:	14400004 	bnez	v0,9fc00a38 <cfi_program_multi+0x40>
+9fc00a28:	00c0a021 	move	s4,a2
+9fc00a2c:	3c028010 	lui	v0,0x8010
+9fc00a30:	0bf002e3 	j	9fc00b8c <cfi_program_multi+0x194>
+9fc00a34:	34440002 	ori	a0,v0,0x2
+9fc00a38:	8c820010 	lw	v0,16(a0)
+9fc00a3c:	00006821 	move	t5,zero
+9fc00a40:	2442ffff 	addiu	v0,v0,-1
+9fc00a44:	0002cc00 	sll	t9,v0,0x10
+9fc00a48:	3c0200e8 	lui	v0,0xe8
+9fc00a4c:	345300e8 	ori	s3,v0,0xe8
+9fc00a50:	3c020080 	lui	v0,0x80
+9fc00a54:	344f0080 	ori	t7,v0,0x80
+9fc00a58:	3c02001a 	lui	v0,0x1a
+9fc00a5c:	3446001a 	ori	a2,v0,0x1a
+9fc00a60:	3c0200d0 	lui	v0,0xd0
+9fc00a64:	345200d0 	ori	s2,v0,0xd0
+9fc00a68:	3c0200ff 	lui	v0,0xff
+9fc00a6c:	345100ff 	ori	s1,v0,0xff
+9fc00a70:	0bf002e1 	j	9fc00b84 <cfi_program_multi+0x18c>
+9fc00a74:	3c100001 	lui	s0,0x1
+9fc00a78:	01851023 	subu	v0,t4,a1
+9fc00a7c:	00505021 	addu	t2,v0,s0
+9fc00a80:	00ea102b 	sltu	v0,a3,t2
+9fc00a84:	10400002 	beqz	v0,9fc00a90 <cfi_program_multi+0x98>
+9fc00a88:	000c1080 	sll	v0,t4,0x2
+9fc00a8c:	00e05021 	move	t2,a3
+9fc00a90:	0bf002d7 	j	9fc00b5c <cfi_program_multi+0x164>
+9fc00a94:	01c25821 	addu	t3,t6,v0
+9fc00a98:	ad730000 	sw	s3,0(t3)
+9fc00a9c:	8d630000 	lw	v1,0(t3)
+9fc00aa0:	00000000 	nop
+9fc00aa4:	006f1024 	and	v0,v1,t7
+9fc00aa8:	144ffffc 	bne	v0,t7,9fc00a9c <cfi_program_multi+0xa4>
+9fc00aac:	00661024 	and	v0,v1,a2
+9fc00ab0:	14400026 	bnez	v0,9fc00b4c <cfi_program_multi+0x154>
+9fc00ab4:	3c029010 	lui	v0,0x9010
+9fc00ab8:	8f020014 	lw	v0,20(t8)
+9fc00abc:	00000000 	nop
+9fc00ac0:	00021882 	srl	v1,v0,0x2
+9fc00ac4:	006a102b 	sltu	v0,v1,t2
+9fc00ac8:	10400002 	beqz	v0,9fc00ad4 <cfi_program_multi+0xdc>
+9fc00acc:	01404021 	move	t0,t2
+9fc00ad0:	00604021 	move	t0,v1
+9fc00ad4:	2503ffff 	addiu	v1,t0,-1
+9fc00ad8:	00031400 	sll	v0,v1,0x10
+9fc00adc:	00431025 	or	v0,v0,v1
+9fc00ae0:	00052080 	sll	a0,a1,0x2
+9fc00ae4:	000d1880 	sll	v1,t5,0x2
+9fc00ae8:	02834821 	addu	t1,s4,v1
+9fc00aec:	ad620000 	sw	v0,0(t3)
+9fc00af0:	01c42021 	addu	a0,t6,a0
+9fc00af4:	0bf002c3 	j	9fc00b0c <cfi_program_multi+0x114>
+9fc00af8:	00001821 	move	v1,zero
+9fc00afc:	8d220000 	lw	v0,0(t1)
+9fc00b00:	25290004 	addiu	t1,t1,4
+9fc00b04:	ac820000 	sw	v0,0(a0)
+9fc00b08:	24840004 	addiu	a0,a0,4
+9fc00b0c:	0068102b 	sltu	v0,v1,t0
+9fc00b10:	1440fffa 	bnez	v0,9fc00afc <cfi_program_multi+0x104>
+9fc00b14:	24630001 	addiu	v1,v1,1
+9fc00b18:	01a86821 	addu	t5,t5,t0
+9fc00b1c:	00a82821 	addu	a1,a1,t0
+9fc00b20:	00e83823 	subu	a3,a3,t0
+9fc00b24:	ad720000 	sw	s2,0(t3)
+9fc00b28:	8d630000 	lw	v1,0(t3)
+9fc00b2c:	00000000 	nop
+9fc00b30:	006f1024 	and	v0,v1,t7
+9fc00b34:	144ffffc 	bne	v0,t7,9fc00b28 <cfi_program_multi+0x130>
+9fc00b38:	00661024 	and	v0,v1,a2
+9fc00b3c:	10400005 	beqz	v0,9fc00b54 <cfi_program_multi+0x15c>
+9fc00b40:	01485023 	subu	t2,t2,t0
+9fc00b44:	01485021 	addu	t2,t2,t0
+9fc00b48:	3c029010 	lui	v0,0x9010
+9fc00b4c:	0bf002d9 	j	9fc00b64 <cfi_program_multi+0x16c>
+9fc00b50:	00622025 	or	a0,v1,v0
+9fc00b54:	ad710000 	sw	s1,0(t3)
+9fc00b58:	00002021 	move	a0,zero
+9fc00b5c:	1540ffce 	bnez	t2,9fc00a98 <cfi_program_multi+0xa0>
+9fc00b60:	00000000 	nop
+9fc00b64:	04810007 	bgez	a0,9fc00b84 <cfi_program_multi+0x18c>
+9fc00b68:	000c1880 	sll	v1,t4,0x2
+9fc00b6c:	3c0200ff 	lui	v0,0xff
+9fc00b70:	01c31821 	addu	v1,t6,v1
+9fc00b74:	344200ff 	ori	v0,v0,0xff
+9fc00b78:	ac620000 	sw	v0,0(v1)
+9fc00b7c:	0bf002e4 	j	9fc00b90 <cfi_program_multi+0x198>
+9fc00b80:	00801021 	move	v0,a0
+9fc00b84:	14e0ffbc 	bnez	a3,9fc00a78 <cfi_program_multi+0x80>
+9fc00b88:	00b96024 	and	t4,a1,t9
+9fc00b8c:	00801021 	move	v0,a0
+9fc00b90:	8fb40014 	lw	s4,20(sp)
+9fc00b94:	8fb30010 	lw	s3,16(sp)
+9fc00b98:	8fb2000c 	lw	s2,12(sp)
+9fc00b9c:	8fb10008 	lw	s1,8(sp)
+9fc00ba0:	8fb00004 	lw	s0,4(sp)
+9fc00ba4:	03e00008 	jr	ra
+9fc00ba8:	27bd0018 	addiu	sp,sp,24
+
+9fc00bac <flash_find>:
+9fc00bac:	27bdffe0 	addiu	sp,sp,-32
+9fc00bb0:	afbf001c 	sw	ra,28(sp)
+9fc00bb4:	ac850000 	sw	a1,0(a0)
+9fc00bb8:	24820008 	addiu	v0,a0,8
+9fc00bbc:	0bf002f3 	j	9fc00bcc <flash_find+0x20>
+9fc00bc0:	24830020 	addiu	v1,a0,32
+9fc00bc4:	a0400000 	sb	zero,0(v0)
+9fc00bc8:	24420001 	addiu	v0,v0,1
+9fc00bcc:	1443fffd 	bne	v0,v1,9fc00bc4 <flash_find+0x18>
+9fc00bd0:	00000000 	nop
+9fc00bd4:	3c021234 	lui	v0,0x1234
+9fc00bd8:	34425678 	ori	v0,v0,0x5678
+9fc00bdc:	00021e02 	srl	v1,v0,0x18
+9fc00be0:	afa20010 	sw	v0,16(sp)
+9fc00be4:	24020012 	li	v0,18
+9fc00be8:	14620003 	bne	v1,v0,9fc00bf8 <flash_find+0x4c>
+9fc00bec:	ac800004 	sw	zero,4(a0)
+9fc00bf0:	24020001 	li	v0,1
+9fc00bf4:	ac820004 	sw	v0,4(a0)
+9fc00bf8:	0ff00185 	jal	9fc00614 <cfi_find>
+9fc00bfc:	00000000 	nop
+9fc00c00:	8fbf001c 	lw	ra,28(sp)
+9fc00c04:	00000000 	nop
+9fc00c08:	03e00008 	jr	ra
+9fc00c0c:	27bd0020 	addiu	sp,sp,32
+
+9fc00c10 <flash_erase>:
+9fc00c10:	27bdffd8 	addiu	sp,sp,-40
+9fc00c14:	30c20003 	andi	v0,a2,0x3
+9fc00c18:	afb2001c 	sw	s2,28(sp)
+9fc00c1c:	afbf0024 	sw	ra,36(sp)
+9fc00c20:	afb30020 	sw	s3,32(sp)
+9fc00c24:	afb10018 	sw	s1,24(sp)
+9fc00c28:	afb00014 	sw	s0,20(sp)
+9fc00c2c:	10400004 	beqz	v0,9fc00c40 <flash_erase+0x30>
+9fc00c30:	00809021 	move	s2,a0
+9fc00c34:	00061082 	srl	v0,a2,0x2
+9fc00c38:	24420001 	addiu	v0,v0,1
+9fc00c3c:	00023080 	sll	a2,v0,0x2
+9fc00c40:	00c59821 	addu	s3,a2,a1
+9fc00c44:	0bf00324 	j	9fc00c90 <flash_erase+0x80>
+9fc00c48:	00a08821 	move	s1,a1
+9fc00c4c:	0ff001ca 	jal	9fc00728 <cfi_block_is_locked>
+9fc00c50:	00000000 	nop
+9fc00c54:	02402021 	move	a0,s2
+9fc00c58:	10400005 	beqz	v0,9fc00c70 <flash_erase+0x60>
+9fc00c5c:	02002821 	move	a1,s0
+9fc00c60:	0ff00236 	jal	9fc008d8 <cfi_block_unlock>
+9fc00c64:	00000000 	nop
+9fc00c68:	04400011 	bltz	v0,9fc00cb0 <flash_erase+0xa0>
+9fc00c6c:	00401821 	move	v1,v0
+9fc00c70:	02002821 	move	a1,s0
+9fc00c74:	0ff001e6 	jal	9fc00798 <cfi_block_erase>
+9fc00c78:	02402021 	move	a0,s2
+9fc00c7c:	0440000c 	bltz	v0,9fc00cb0 <flash_erase+0xa0>
+9fc00c80:	00401821 	move	v1,v0
+9fc00c84:	8e42000c 	lw	v0,12(s2)
+9fc00c88:	00000000 	nop
+9fc00c8c:	02228821 	addu	s1,s1,v0
+9fc00c90:	001117c3 	sra	v0,s1,0x1f
+9fc00c94:	00021782 	srl	v0,v0,0x1e
+9fc00c98:	00511021 	addu	v0,v0,s1
+9fc00c9c:	00028083 	sra	s0,v0,0x2
+9fc00ca0:	0233102b 	sltu	v0,s1,s3
+9fc00ca4:	02402021 	move	a0,s2
+9fc00ca8:	1440ffe8 	bnez	v0,9fc00c4c <flash_erase+0x3c>
+9fc00cac:	02002821 	move	a1,s0
+9fc00cb0:	8fbf0024 	lw	ra,36(sp)
+9fc00cb4:	00601021 	move	v0,v1
+9fc00cb8:	8fb30020 	lw	s3,32(sp)
+9fc00cbc:	8fb2001c 	lw	s2,28(sp)
+9fc00cc0:	8fb10018 	lw	s1,24(sp)
+9fc00cc4:	8fb00014 	lw	s0,20(sp)
+9fc00cc8:	03e00008 	jr	ra
+9fc00ccc:	27bd0028 	addiu	sp,sp,40
+
+9fc00cd0 <flash_program>:
+9fc00cd0:	30e20003 	andi	v0,a3,0x3
+9fc00cd4:	10400003 	beqz	v0,9fc00ce4 <flash_program+0x14>
+9fc00cd8:	00071082 	srl	v0,a3,0x2
+9fc00cdc:	24420001 	addiu	v0,v0,1
+9fc00ce0:	00023880 	sll	a3,v0,0x2
+9fc00ce4:	00052882 	srl	a1,a1,0x2
+9fc00ce8:	0bf0027e 	j	9fc009f8 <cfi_program_multi>
+9fc00cec:	00073882 	srl	a3,a3,0x2
+
+9fc00cf0 <flash_verify>:
+9fc00cf0:	8c820000 	lw	v0,0(a0)
+9fc00cf4:	00002021 	move	a0,zero
+9fc00cf8:	0bf00347 	j	9fc00d1c <flash_verify+0x2c>
+9fc00cfc:	00454021 	addu	t0,v0,a1
+9fc00d00:	90630000 	lbu	v1,0(v1)
+9fc00d04:	90a20000 	lbu	v0,0(a1)
+9fc00d08:	00000000 	nop
+9fc00d0c:	10620003 	beq	v1,v0,9fc00d1c <flash_verify+0x2c>
+9fc00d10:	3c028010 	lui	v0,0x8010
+9fc00d14:	03e00008 	jr	ra
+9fc00d18:	34420003 	ori	v0,v0,0x3
+9fc00d1c:	0087102b 	sltu	v0,a0,a3
+9fc00d20:	01041821 	addu	v1,t0,a0
+9fc00d24:	00c42821 	addu	a1,a2,a0
+9fc00d28:	1440fff5 	bnez	v0,9fc00d00 <flash_verify+0x10>
+9fc00d2c:	24840001 	addiu	a0,a0,1
+9fc00d30:	03e00008 	jr	ra
+9fc00d34:	00000000 	nop
+
+9fc00d38 <flash_get_blocknum_by_offset>:
+9fc00d38:	8c82000c 	lw	v0,12(a0)
+9fc00d3c:	00000000 	nop
+9fc00d40:	14400002 	bnez	v0,9fc00d4c <flash_get_blocknum_by_offset+0x14>
+9fc00d44:	00a2001b 	divu	zero,a1,v0
+9fc00d48:	0007000d 	break	0x7
+9fc00d4c:	00001010 	mfhi	v0
+9fc00d50:	0002102b 	sltu	v0,zero,v0
+9fc00d54:	00002812 	mflo	a1
+9fc00d58:	03e00008 	jr	ra
+9fc00d5c:	00a21021 	addu	v0,a1,v0
+
+9fc00d60 <flash_get_offset_by_blocknum>:
+9fc00d60:	8c830010 	lw	v1,16(a0)
+9fc00d64:	00000000 	nop
+9fc00d68:	00a3102b 	sltu	v0,a1,v1
+9fc00d6c:	14400002 	bnez	v0,9fc00d78 <flash_get_offset_by_blocknum+0x18>
+9fc00d70:	00000000 	nop
+9fc00d74:	2465ffff 	addiu	a1,v1,-1
+9fc00d78:	8c82000c 	lw	v0,12(a0)
+9fc00d7c:	00000000 	nop
+9fc00d80:	00a20018 	mult	a1,v0
+9fc00d84:	00001012 	mflo	v0
+9fc00d88:	03e00008 	jr	ra
+9fc00d8c:	00000000 	nop
+
+9fc00d90 <flash_get_offset_blockaligned>:
+9fc00d90:	27bdffe8 	addiu	sp,sp,-24
+9fc00d94:	afbf0014 	sw	ra,20(sp)
+9fc00d98:	afb00010 	sw	s0,16(sp)
+9fc00d9c:	0ff0034e 	jal	9fc00d38 <flash_get_blocknum_by_offset>
+9fc00da0:	00808021 	move	s0,a0
+9fc00da4:	8e03000c 	lw	v1,12(s0)
+9fc00da8:	8fbf0014 	lw	ra,20(sp)
+9fc00dac:	00430018 	mult	v0,v1
+9fc00db0:	8fb00010 	lw	s0,16(sp)
+9fc00db4:	00001012 	mflo	v0
+9fc00db8:	03e00008 	jr	ra
+9fc00dbc:	27bd0018 	addiu	sp,sp,24
+
+9fc00dc0 <h2i>:
+9fc00dc0:	90830000 	lbu	v1,0(a0)
+9fc00dc4:	00000000 	nop
+9fc00dc8:	2c620041 	sltiu	v0,v1,65
+9fc00dcc:	14400002 	bnez	v0,9fc00dd8 <h2i+0x18>
+9fc00dd0:	2462ffd0 	addiu	v0,v1,-48
+9fc00dd4:	2462ffc9 	addiu	v0,v1,-55
+9fc00dd8:	90840001 	lbu	a0,1(a0)
+9fc00ddc:	304200ff 	andi	v0,v0,0xff
+9fc00de0:	304300ff 	andi	v1,v0,0xff
+9fc00de4:	2c820041 	sltiu	v0,a0,65
+9fc00de8:	14400003 	bnez	v0,9fc00df8 <h2i+0x38>
+9fc00dec:	00000000 	nop
+9fc00df0:	0bf0037f 	j	9fc00dfc <h2i+0x3c>
+9fc00df4:	2482ffc9 	addiu	v0,a0,-55
+9fc00df8:	2482ffd0 	addiu	v0,a0,-48
+9fc00dfc:	304400ff 	andi	a0,v0,0xff
+9fc00e00:	00031100 	sll	v0,v1,0x4
+9fc00e04:	00821025 	or	v0,a0,v0
+9fc00e08:	03e00008 	jr	ra
+9fc00e0c:	304200ff 	andi	v0,v0,0xff
+
+9fc00e10 <decode_srec>:
+9fc00e10:	10c00094 	beqz	a2,9fc01064 <decode_srec+0x254>
+9fc00e14:	00805021 	move	t2,a0
+9fc00e18:	24020003 	li	v0,3
+9fc00e1c:	ac820008 	sw	v0,8(a0)
+9fc00e20:	90a40001 	lbu	a0,1(a1)
+9fc00e24:	00000000 	nop
+9fc00e28:	2482ffcf 	addiu	v0,a0,-49
+9fc00e2c:	304200ff 	andi	v0,v0,0xff
+9fc00e30:	2c420003 	sltiu	v0,v0,3
+9fc00e34:	10400005 	beqz	v0,9fc00e4c <decode_srec+0x3c>
+9fc00e38:	2482ffc9 	addiu	v0,a0,-55
+9fc00e3c:	24020002 	li	v0,2
+9fc00e40:	ad420008 	sw	v0,8(t2)
+9fc00e44:	0bf003a1 	j	9fc00e84 <decode_srec+0x74>
+9fc00e48:	2489ffd1 	addiu	t1,a0,-47
+9fc00e4c:	304200ff 	andi	v0,v0,0xff
+9fc00e50:	2c420003 	sltiu	v0,v0,3
+9fc00e54:	10400006 	beqz	v0,9fc00e70 <decode_srec+0x60>
+9fc00e58:	24020030 	li	v0,48
+9fc00e5c:	2402003b 	li	v0,59
+9fc00e60:	00444823 	subu	t1,v0,a0
+9fc00e64:	24020004 	li	v0,4
+9fc00e68:	0bf003a1 	j	9fc00e84 <decode_srec+0x74>
+9fc00e6c:	ad420008 	sw	v0,8(t2)
+9fc00e70:	14820004 	bne	a0,v0,9fc00e84 <decode_srec+0x74>
+9fc00e74:	00004821 	move	t1,zero
+9fc00e78:	24020001 	li	v0,1
+9fc00e7c:	ad420008 	sw	v0,8(t2)
+9fc00e80:	24090002 	li	t1,2
+9fc00e84:	90a30002 	lbu	v1,2(a1)
+9fc00e88:	00000000 	nop
+9fc00e8c:	2c620041 	sltiu	v0,v1,65
+9fc00e90:	10400003 	beqz	v0,9fc00ea0 <decode_srec+0x90>
+9fc00e94:	24a40002 	addiu	a0,a1,2
+9fc00e98:	0bf003a9 	j	9fc00ea4 <decode_srec+0x94>
+9fc00e9c:	2462ffd0 	addiu	v0,v1,-48
+9fc00ea0:	2462ffc9 	addiu	v0,v1,-55
+9fc00ea4:	90830001 	lbu	v1,1(a0)
+9fc00ea8:	304200ff 	andi	v0,v0,0xff
+9fc00eac:	304400ff 	andi	a0,v0,0xff
+9fc00eb0:	2c620041 	sltiu	v0,v1,65
+9fc00eb4:	10400002 	beqz	v0,9fc00ec0 <decode_srec+0xb0>
+9fc00eb8:	2462ffc9 	addiu	v0,v1,-55
+9fc00ebc:	2462ffd0 	addiu	v0,v1,-48
+9fc00ec0:	304300ff 	andi	v1,v0,0xff
+9fc00ec4:	00041100 	sll	v0,a0,0x4
+9fc00ec8:	00621025 	or	v0,v1,v0
+9fc00ecc:	304200ff 	andi	v0,v0,0xff
+9fc00ed0:	ad420004 	sw	v0,4(t2)
+9fc00ed4:	ad400000 	sw	zero,0(t2)
+9fc00ed8:	00405821 	move	t3,v0
+9fc00edc:	00a03021 	move	a2,a1
+9fc00ee0:	0bf003d5 	j	9fc00f54 <decode_srec+0x144>
+9fc00ee4:	00003821 	move	a3,zero
+9fc00ee8:	90c20004 	lbu	v0,4(a2)
+9fc00eec:	00000000 	nop
+9fc00ef0:	2443ffc9 	addiu	v1,v0,-55
+9fc00ef4:	2444ffd0 	addiu	a0,v0,-48
+9fc00ef8:	2c420041 	sltiu	v0,v0,65
+9fc00efc:	10400002 	beqz	v0,9fc00f08 <decode_srec+0xf8>
+9fc00f00:	306300ff 	andi	v1,v1,0xff
+9fc00f04:	308300ff 	andi	v1,a0,0xff
+9fc00f08:	90c20005 	lbu	v0,5(a2)
+9fc00f0c:	306800ff 	andi	t0,v1,0xff
+9fc00f10:	2444ffc9 	addiu	a0,v0,-55
+9fc00f14:	2443ffd0 	addiu	v1,v0,-48
+9fc00f18:	2c420041 	sltiu	v0,v0,65
+9fc00f1c:	10400002 	beqz	v0,9fc00f28 <decode_srec+0x118>
+9fc00f20:	308400ff 	andi	a0,a0,0xff
+9fc00f24:	306400ff 	andi	a0,v1,0xff
+9fc00f28:	8d430000 	lw	v1,0(t2)
+9fc00f2c:	00081100 	sll	v0,t0,0x4
+9fc00f30:	00821025 	or	v0,a0,v0
+9fc00f34:	304200ff 	andi	v0,v0,0xff
+9fc00f38:	00031a00 	sll	v1,v1,0x8
+9fc00f3c:	004b2021 	addu	a0,v0,t3
+9fc00f40:	00431025 	or	v0,v0,v1
+9fc00f44:	ad420000 	sw	v0,0(t2)
+9fc00f48:	308b00ff 	andi	t3,a0,0xff
+9fc00f4c:	24e70001 	addiu	a3,a3,1
+9fc00f50:	24c60002 	addiu	a2,a2,2
+9fc00f54:	00e9102a 	slt	v0,a3,t1
+9fc00f58:	1440ffe3 	bnez	v0,9fc00ee8 <decode_srec+0xd8>
+9fc00f5c:	25220002 	addiu	v0,t1,2
+9fc00f60:	8d440004 	lw	a0,4(t2)
+9fc00f64:	00021040 	sll	v0,v0,0x1
+9fc00f68:	00091827 	nor	v1,zero,t1
+9fc00f6c:	00832021 	addu	a0,a0,v1
+9fc00f70:	00a21021 	addu	v0,a1,v0
+9fc00f74:	ad440004 	sw	a0,4(t2)
+9fc00f78:	ad42000c 	sw	v0,12(t2)
+9fc00f7c:	0bf003f9 	j	9fc00fe4 <decode_srec+0x1d4>
+9fc00f80:	00003021 	move	a2,zero
+9fc00f84:	90e20000 	lbu	v0,0(a3)
+9fc00f88:	00000000 	nop
+9fc00f8c:	2444ffc9 	addiu	a0,v0,-55
+9fc00f90:	2445ffd0 	addiu	a1,v0,-48
+9fc00f94:	2c420041 	sltiu	v0,v0,65
+9fc00f98:	10400002 	beqz	v0,9fc00fa4 <decode_srec+0x194>
+9fc00f9c:	308400ff 	andi	a0,a0,0xff
+9fc00fa0:	30a400ff 	andi	a0,a1,0xff
+9fc00fa4:	90e20001 	lbu	v0,1(a3)
+9fc00fa8:	308700ff 	andi	a3,a0,0xff
+9fc00fac:	2445ffc9 	addiu	a1,v0,-55
+9fc00fb0:	2444ffd0 	addiu	a0,v0,-48
+9fc00fb4:	2c420041 	sltiu	v0,v0,65
+9fc00fb8:	14400002 	bnez	v0,9fc00fc4 <decode_srec+0x1b4>
+9fc00fbc:	308400ff 	andi	a0,a0,0xff
+9fc00fc0:	30a400ff 	andi	a0,a1,0xff
+9fc00fc4:	00071100 	sll	v0,a3,0x4
+9fc00fc8:	00821025 	or	v0,a0,v0
+9fc00fcc:	304200ff 	andi	v0,v0,0xff
+9fc00fd0:	00661821 	addu	v1,v1,a2
+9fc00fd4:	004b2021 	addu	a0,v0,t3
+9fc00fd8:	a0620000 	sb	v0,0(v1)
+9fc00fdc:	308b00ff 	andi	t3,a0,0xff
+9fc00fe0:	24c60001 	addiu	a2,a2,1
+9fc00fe4:	8d420004 	lw	v0,4(t2)
+9fc00fe8:	8d43000c 	lw	v1,12(t2)
+9fc00fec:	00062040 	sll	a0,a2,0x1
+9fc00ff0:	00c2102a 	slt	v0,a2,v0
+9fc00ff4:	1440ffe3 	bnez	v0,9fc00f84 <decode_srec+0x174>
+9fc00ff8:	00643821 	addu	a3,v1,a0
+9fc00ffc:	90e40000 	lbu	a0,0(a3)
+9fc01000:	00000000 	nop
+9fc01004:	2c820041 	sltiu	v0,a0,65
+9fc01008:	10400003 	beqz	v0,9fc01018 <decode_srec+0x208>
+9fc0100c:	00e01821 	move	v1,a3
+9fc01010:	0bf00407 	j	9fc0101c <decode_srec+0x20c>
+9fc01014:	2482ffd0 	addiu	v0,a0,-48
+9fc01018:	2482ffc9 	addiu	v0,a0,-55
+9fc0101c:	90630001 	lbu	v1,1(v1)
+9fc01020:	304200ff 	andi	v0,v0,0xff
+9fc01024:	304400ff 	andi	a0,v0,0xff
+9fc01028:	2c620041 	sltiu	v0,v1,65
+9fc0102c:	10400002 	beqz	v0,9fc01038 <decode_srec+0x228>
+9fc01030:	2462ffc9 	addiu	v0,v1,-55
+9fc01034:	2462ffd0 	addiu	v0,v1,-48
+9fc01038:	304200ff 	andi	v0,v0,0xff
+9fc0103c:	00041900 	sll	v1,a0,0x4
+9fc01040:	00431825 	or	v1,v0,v1
+9fc01044:	000b1027 	nor	v0,zero,t3
+9fc01048:	304200ff 	andi	v0,v0,0xff
+9fc0104c:	306300ff 	andi	v1,v1,0xff
+9fc01050:	14430004 	bne	v0,v1,9fc01064 <decode_srec+0x254>
+9fc01054:	00000000 	nop
+9fc01058:	8d420008 	lw	v0,8(t2)
+9fc0105c:	03e00008 	jr	ra
+9fc01060:	00000000 	nop
+9fc01064:	03e00008 	jr	ra
+9fc01068:	00001021 	move	v0,zero
+
+9fc0106c <Jump_to>:
+9fc0106c:	00800008 	jr	a0
+9fc01070:	00000000 	nop
+9fc01074:	03e00008 	jr	ra
+9fc01078:	00000000 	nop
+
+9fc0107c <Exec_at>:
+9fc0107c:	3c1a1000 	lui	k0,0x1000
+9fc01080:	375a000a 	ori	k0,k0,0xa
+9fc01084:	409a6000 	mtc0	k0,c0_sr
+9fc01088:	00800008 	jr	a0
+9fc0108c:	42000010 	rfe
+9fc01090:	03e00008 	jr	ra
+9fc01094:	00000000 	nop
+
+9fc01098 <Exec_RE_at>:
+9fc01098:	401a6000 	mfc0	k0,c0_sr
+9fc0109c:	3c1bffbf 	lui	k1,0xffbf
+9fc010a0:	377bffff 	ori	k1,k1,0xffff
+9fc010a4:	035bd024 	and	k0,k0,k1
+9fc010a8:	3c1b0200 	lui	k1,0x200
+9fc010ac:	035bd025 	or	k0,k0,k1
+9fc010b0:	409a6000 	mtc0	k0,c0_sr
+9fc010b4:	00800008 	jr	a0
+9fc010b8:	42000010 	rfe
+9fc010bc:	03e00008 	jr	ra
+9fc010c0:	00000000 	nop
+
+9fc010c4 <srec_getline>:
+9fc010c4:	27bdffd8 	addiu	sp,sp,-40
+9fc010c8:	afb30020 	sw	s3,32(sp)
+9fc010cc:	afb10018 	sw	s1,24(sp)
+9fc010d0:	afb00014 	sw	s0,20(sp)
+9fc010d4:	afbf0024 	sw	ra,36(sp)
+9fc010d8:	afb2001c 	sw	s2,28(sp)
+9fc010dc:	00809821 	move	s3,a0
+9fc010e0:	24110073 	li	s1,115
+9fc010e4:	24100053 	li	s0,83
+9fc010e8:	0ff00081 	jal	9fc00204 <readchar>
+9fc010ec:	00000000 	nop
+9fc010f0:	14510005 	bne	v0,s1,9fc01108 <srec_getline+0x44>
+9fc010f4:	00000000 	nop
+9fc010f8:	00008021 	move	s0,zero
+9fc010fc:	2412000a 	li	s2,10
+9fc01100:	0bf0044a 	j	9fc01128 <srec_getline+0x64>
+9fc01104:	2411000d 	li	s1,13
+9fc01108:	1450fff7 	bne	v0,s0,9fc010e8 <srec_getline+0x24>
+9fc0110c:	00000000 	nop
+9fc01110:	0bf0043f 	j	9fc010fc <srec_getline+0x38>
+9fc01114:	00008021 	move	s0,zero
+9fc01118:	0ff00081 	jal	9fc00204 <readchar>
+9fc0111c:	a0620000 	sb	v0,0(v1)
+9fc01120:	10510003 	beq	v0,s1,9fc01130 <srec_getline+0x6c>
+9fc01124:	26100001 	addiu	s0,s0,1
+9fc01128:	1452fffb 	bne	v0,s2,9fc01118 <srec_getline+0x54>
+9fc0112c:	02701821 	addu	v1,s3,s0
+9fc01130:	8fbf0024 	lw	ra,36(sp)
+9fc01134:	02001021 	move	v0,s0
+9fc01138:	8fb30020 	lw	s3,32(sp)
+9fc0113c:	8fb2001c 	lw	s2,28(sp)
+9fc01140:	8fb10018 	lw	s1,24(sp)
+9fc01144:	8fb00014 	lw	s0,20(sp)
+9fc01148:	03e00008 	jr	ra
+9fc0114c:	27bd0028 	addiu	sp,sp,40
+
+9fc01150 <main>:
+9fc01150:	27bdfd98 	addiu	sp,sp,-616
+9fc01154:	27a40140 	addiu	a0,sp,320
+9fc01158:	00002821 	move	a1,zero
+9fc0115c:	24060100 	li	a2,256
+9fc01160:	afb20248 	sw	s2,584(sp)
+9fc01164:	afb10244 	sw	s1,580(sp)
+9fc01168:	afb00240 	sw	s0,576(sp)
+9fc0116c:	3c11ac00 	lui	s1,0xac00
+9fc01170:	afbf0264 	sw	ra,612(sp)
+9fc01174:	afbe0260 	sw	s8,608(sp)
+9fc01178:	afb7025c 	sw	s7,604(sp)
+9fc0117c:	afb60258 	sw	s6,600(sp)
+9fc01180:	afb50254 	sw	s5,596(sp)
+9fc01184:	afb40250 	sw	s4,592(sp)
+9fc01188:	0ff0056c 	jal	9fc015b0 <memset>
+9fc0118c:	afb3024c 	sw	s3,588(sp)
+9fc01190:	3c036000 	lui	v1,0x6000
+9fc01194:	36220004 	ori	v0,s1,0x4
+9fc01198:	3463b1ff 	ori	v1,v1,0xb1ff
+9fc0119c:	ac430000 	sw	v1,0(v0)
+9fc011a0:	3c022000 	lui	v0,0x2000
+9fc011a4:	27b20020 	addiu	s2,sp,32
+9fc011a8:	34421000 	ori	v0,v0,0x1000
+9fc011ac:	ae220000 	sw	v0,0(s1)
+9fc011b0:	02402021 	move	a0,s2
+9fc011b4:	3c05a400 	lui	a1,0xa400
+9fc011b8:	8e300000 	lw	s0,0(s1)
+9fc011bc:	0ff002eb 	jal	9fc00bac <flash_find>
+9fc011c0:	00000000 	nop
+9fc011c4:	04410004 	bgez	v0,9fc011d8 <main+0x88>
+9fc011c8:	00102c02 	srl	a1,s0,0x10
+9fc011cc:	3c049fc0 	lui	a0,0x9fc0
+9fc011d0:	0bf00494 	j	9fc01250 <main+0x100>
+9fc011d4:	248416a8 	addiu	a0,a0,5800
+9fc011d8:	02402021 	move	a0,s2
+9fc011dc:	0ff00358 	jal	9fc00d60 <flash_get_offset_by_blocknum>
+9fc011e0:	30a5007f 	andi	a1,a1,0x7f
+9fc011e4:	00409021 	move	s2,v0
+9fc011e8:	8e220000 	lw	v0,0(s1)
+9fc011ec:	3c030800 	lui	v1,0x800
+9fc011f0:	00431024 	and	v0,v0,v1
+9fc011f4:	14400045 	bnez	v0,9fc0130c <main+0x1bc>
+9fc011f8:	3c119fc0 	lui	s1,0x9fc0
+9fc011fc:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01200:	2624175c 	addiu	a0,s1,5980
+9fc01204:	3c02a400 	lui	v0,0xa400
+9fc01208:	02428021 	addu	s0,s2,v0
+9fc0120c:	8e030000 	lw	v1,0(s0)
+9fc01210:	3c023149 	lui	v0,0x3149
+9fc01214:	3442464a 	ori	v0,v0,0x464a
+9fc01218:	10620011 	beq	v1,v0,9fc01260 <main+0x110>
+9fc0121c:	3c024a46 	lui	v0,0x4a46
+9fc01220:	34424931 	ori	v0,v0,0x4931
+9fc01224:	1062000e 	beq	v1,v0,9fc01260 <main+0x110>
+9fc01228:	00000000 	nop
+9fc0122c:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01230:	2624175c 	addiu	a0,s1,5980
+9fc01234:	3c049fc0 	lui	a0,0x9fc0
+9fc01238:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc0123c:	248416d0 	addiu	a0,a0,5840
+9fc01240:	0ff000e8 	jal	9fc003a0 <print_word>
+9fc01244:	02402021 	move	a0,s2
+9fc01248:	3c049fc0 	lui	a0,0x9fc0
+9fc0124c:	248416e8 	addiu	a0,a0,5864
+9fc01250:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01254:	00000000 	nop
+9fc01258:	0bf00560 	j	9fc01580 <main+0x430>
+9fc0125c:	24020001 	li	v0,1
+9fc01260:	3c049fc0 	lui	a0,0x9fc0
+9fc01264:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01268:	248416f4 	addiu	a0,a0,5876
+9fc0126c:	0ff000e8 	jal	9fc003a0 <print_word>
+9fc01270:	02402021 	move	a0,s2
+9fc01274:	3c049fc0 	lui	a0,0x9fc0
+9fc01278:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc0127c:	24841718 	addiu	a0,a0,5912
+9fc01280:	8e02000c 	lw	v0,12(s0)
+9fc01284:	8e110004 	lw	s1,4(s0)
+9fc01288:	00024082 	srl	t0,v0,0x2
+9fc0128c:	8e070008 	lw	a3,8(s0)
+9fc01290:	00002021 	move	a0,zero
+9fc01294:	0bf004aa 	j	9fc012a8 <main+0x158>
+9fc01298:	00001821 	move	v1,zero
+9fc0129c:	8cc20000 	lw	v0,0(a2)
+9fc012a0:	00000000 	nop
+9fc012a4:	aca20000 	sw	v0,0(a1)
+9fc012a8:	0088102b 	sltu	v0,a0,t0
+9fc012ac:	00673021 	addu	a2,v1,a3
+9fc012b0:	00712821 	addu	a1,v1,s1
+9fc012b4:	24840001 	addiu	a0,a0,1
+9fc012b8:	1440fff8 	bnez	v0,9fc0129c <main+0x14c>
+9fc012bc:	24630004 	addiu	v1,v1,4
+9fc012c0:	3c049fc0 	lui	a0,0x9fc0
+9fc012c4:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc012c8:	24841720 	addiu	a0,a0,5920
+9fc012cc:	3c049fc0 	lui	a0,0x9fc0
+9fc012d0:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc012d4:	24841728 	addiu	a0,a0,5928
+9fc012d8:	8e040004 	lw	a0,4(s0)
+9fc012dc:	0ff000e8 	jal	9fc003a0 <print_word>
+9fc012e0:	00000000 	nop
+9fc012e4:	3c049fc0 	lui	a0,0x9fc0
+9fc012e8:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc012ec:	2484175c 	addiu	a0,a0,5980
+9fc012f0:	3c1a1000 	lui	k0,0x1000
+9fc012f4:	375a000a 	ori	k0,k0,0xa
+9fc012f8:	409a6000 	mtc0	k0,c0_sr
+9fc012fc:	02200008 	jr	s1
+9fc01300:	42000010 	rfe
+9fc01304:	0bf00560 	j	9fc01580 <main+0x430>
+9fc01308:	00001021 	move	v0,zero
+9fc0130c:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01310:	2624175c 	addiu	a0,s1,5980
+9fc01314:	3c049fc0 	lui	a0,0x9fc0
+9fc01318:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc0131c:	24841734 	addiu	a0,a0,5940
+9fc01320:	3c028000 	lui	v0,0x8000
+9fc01324:	3c038010 	lui	v1,0x8010
+9fc01328:	ac400000 	sw	zero,0(v0)
+9fc0132c:	24420004 	addiu	v0,v0,4
+9fc01330:	1443fffd 	bne	v0,v1,9fc01328 <main+0x1d8>
+9fc01334:	00009821 	move	s3,zero
+9fc01338:	3c029fc0 	lui	v0,0x9fc0
+9fc0133c:	245516cc 	addiu	s5,v0,5836
+9fc01340:	3c029fc0 	lui	v0,0x9fc0
+9fc01344:	24561720 	addiu	s6,v0,5920
+9fc01348:	3c029fc0 	lui	v0,0x9fc0
+9fc0134c:	245e17d4 	addiu	s8,v0,6100
+9fc01350:	3c029fc0 	lui	v0,0x9fc0
+9fc01354:	245717f4 	addiu	s7,v0,6132
+9fc01358:	3c049fc0 	lui	a0,0x9fc0
+9fc0135c:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01360:	24841754 	addiu	a0,a0,5972
+9fc01364:	3c149fc0 	lui	s4,0x9fc0
+9fc01368:	27b00040 	addiu	s0,sp,64
+9fc0136c:	0ff00431 	jal	9fc010c4 <srec_getline>
+9fc01370:	02002021 	move	a0,s0
+9fc01374:	00403021 	move	a2,v0
+9fc01378:	02002821 	move	a1,s0
+9fc0137c:	27a40010 	addiu	a0,sp,16
+9fc01380:	0ff00384 	jal	9fc00e10 <decode_srec>
+9fc01384:	00408821 	move	s1,v0
+9fc01388:	00401821 	move	v1,v0
+9fc0138c:	24020002 	li	v0,2
+9fc01390:	10620005 	beq	v1,v0,9fc013a8 <main+0x258>
+9fc01394:	24020004 	li	v0,4
+9fc01398:	1462ffef 	bne	v1,v0,9fc01358 <main+0x208>
+9fc0139c:	00000000 	nop
+9fc013a0:	0bf004ff 	j	9fc013fc <main+0x2ac>
+9fc013a4:	3c049fc0 	lui	a0,0x9fc0
+9fc013a8:	8fa50010 	lw	a1,16(sp)
+9fc013ac:	8fa60014 	lw	a2,20(sp)
+9fc013b0:	0bf004f4 	j	9fc013d0 <main+0x280>
+9fc013b4:	00001821 	move	v1,zero
+9fc013b8:	8fa2001c 	lw	v0,28(sp)
+9fc013bc:	00000000 	nop
+9fc013c0:	00431021 	addu	v0,v0,v1
+9fc013c4:	90420000 	lbu	v0,0(v0)
+9fc013c8:	24630001 	addiu	v1,v1,1
+9fc013cc:	a0820000 	sb	v0,0(a0)
+9fc013d0:	8fa20014 	lw	v0,20(sp)
+9fc013d4:	00000000 	nop
+9fc013d8:	0062102b 	sltu	v0,v1,v0
+9fc013dc:	1440fff6 	bnez	v0,9fc013b8 <main+0x268>
+9fc013e0:	00652021 	addu	a0,v1,a1
+9fc013e4:	00c51821 	addu	v1,a2,a1
+9fc013e8:	0263102b 	sltu	v0,s3,v1
+9fc013ec:	10400060 	beqz	v0,9fc01570 <main+0x420>
+9fc013f0:	02208021 	move	s0,s1
+9fc013f4:	0bf0055c 	j	9fc01570 <main+0x420>
+9fc013f8:	00609821 	move	s3,v1
+9fc013fc:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01400:	24841758 	addiu	a0,a0,5976
+9fc01404:	8fa60010 	lw	a2,16(sp)
+9fc01408:	26470100 	addiu	a3,s2,256
+9fc0140c:	02661823 	subu	v1,s3,a2
+9fc01410:	27b10020 	addiu	s1,sp,32
+9fc01414:	3c024a46 	lui	v0,0x4a46
+9fc01418:	00e32821 	addu	a1,a3,v1
+9fc0141c:	02202021 	move	a0,s1
+9fc01420:	34424931 	ori	v0,v0,0x4931
+9fc01424:	afa60144 	sw	a2,324(sp)
+9fc01428:	afa3014c 	sw	v1,332(sp)
+9fc0142c:	afa70148 	sw	a3,328(sp)
+9fc01430:	0ff00364 	jal	9fc00d90 <flash_get_offset_blockaligned>
+9fc01434:	afa20140 	sw	v0,320(sp)
+9fc01438:	3c049fc0 	lui	a0,0x9fc0
+9fc0143c:	24841760 	addiu	a0,a0,5984
+9fc01440:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01444:	afa20150 	sw	v0,336(sp)
+9fc01448:	8fa4014c 	lw	a0,332(sp)
+9fc0144c:	0ff000e8 	jal	9fc003a0 <print_word>
+9fc01450:	00000000 	nop
+9fc01454:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01458:	02a02021 	move	a0,s5
+9fc0145c:	3c049fc0 	lui	a0,0x9fc0
+9fc01460:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01464:	2484177c 	addiu	a0,a0,6012
+9fc01468:	0ff000e8 	jal	9fc003a0 <print_word>
+9fc0146c:	02402021 	move	a0,s2
+9fc01470:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01474:	02a02021 	move	a0,s5
+9fc01478:	3c049fc0 	lui	a0,0x9fc0
+9fc0147c:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01480:	24841798 	addiu	a0,a0,6040
+9fc01484:	8fa40150 	lw	a0,336(sp)
+9fc01488:	0ff000e8 	jal	9fc003a0 <print_word>
+9fc0148c:	00000000 	nop
+9fc01490:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01494:	02a02021 	move	a0,s5
+9fc01498:	3c049fc0 	lui	a0,0x9fc0
+9fc0149c:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc014a0:	248417b4 	addiu	a0,a0,6068
+9fc014a4:	8fa6014c 	lw	a2,332(sp)
+9fc014a8:	02202021 	move	a0,s1
+9fc014ac:	24c60100 	addiu	a2,a2,256
+9fc014b0:	0ff00304 	jal	9fc00c10 <flash_erase>
+9fc014b4:	02402821 	move	a1,s2
+9fc014b8:	0440001f 	bltz	v0,9fc01538 <main+0x3e8>
+9fc014bc:	00408021 	move	s0,v0
+9fc014c0:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc014c4:	02c02021 	move	a0,s6
+9fc014c8:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc014cc:	03c02021 	move	a0,s8
+9fc014d0:	02202021 	move	a0,s1
+9fc014d4:	02402821 	move	a1,s2
+9fc014d8:	27a60140 	addiu	a2,sp,320
+9fc014dc:	0ff00334 	jal	9fc00cd0 <flash_program>
+9fc014e0:	24070100 	li	a3,256
+9fc014e4:	04400014 	bltz	v0,9fc01538 <main+0x3e8>
+9fc014e8:	00408021 	move	s0,v0
+9fc014ec:	8fa50148 	lw	a1,328(sp)
+9fc014f0:	8fa60144 	lw	a2,324(sp)
+9fc014f4:	8fa7014c 	lw	a3,332(sp)
+9fc014f8:	0ff00334 	jal	9fc00cd0 <flash_program>
+9fc014fc:	02202021 	move	a0,s1
+9fc01500:	0440000d 	bltz	v0,9fc01538 <main+0x3e8>
+9fc01504:	00408021 	move	s0,v0
+9fc01508:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc0150c:	02c02021 	move	a0,s6
+9fc01510:	3c049fc0 	lui	a0,0x9fc0
+9fc01514:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01518:	248417e4 	addiu	a0,a0,6116
+9fc0151c:	8fa50148 	lw	a1,328(sp)
+9fc01520:	8fa60144 	lw	a2,324(sp)
+9fc01524:	8fa7014c 	lw	a3,332(sp)
+9fc01528:	0ff0033c 	jal	9fc00cf0 <flash_verify>
+9fc0152c:	02202021 	move	a0,s1
+9fc01530:	0441000a 	bgez	v0,9fc0155c <main+0x40c>
+9fc01534:	00408021 	move	s0,v0
+9fc01538:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc0153c:	268417c4 	addiu	a0,s4,6084
+9fc01540:	0ff000e8 	jal	9fc003a0 <print_word>
+9fc01544:	02002021 	move	a0,s0
+9fc01548:	3c049fc0 	lui	a0,0x9fc0
+9fc0154c:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01550:	248417d0 	addiu	a0,a0,6096
+9fc01554:	0bf0055c 	j	9fc01570 <main+0x420>
+9fc01558:	00000000 	nop
+9fc0155c:	0ff000b0 	jal	9fc002c0 <sputs>
+9fc01560:	02e02021 	move	a0,s7
+9fc01564:	3c02bfc0 	lui	v0,0xbfc0
+9fc01568:	00400008 	jr	v0
+9fc0156c:	00000000 	nop
+9fc01570:	0601ff7e 	bgez	s0,9fc0136c <main+0x21c>
+9fc01574:	27b00040 	addiu	s0,sp,64
+9fc01578:	0bf004d7 	j	9fc0135c <main+0x20c>
+9fc0157c:	3c049fc0 	lui	a0,0x9fc0
+9fc01580:	8fbf0264 	lw	ra,612(sp)
+9fc01584:	8fbe0260 	lw	s8,608(sp)
+9fc01588:	8fb7025c 	lw	s7,604(sp)
+9fc0158c:	8fb60258 	lw	s6,600(sp)
+9fc01590:	8fb50254 	lw	s5,596(sp)
+9fc01594:	8fb40250 	lw	s4,592(sp)
+9fc01598:	8fb3024c 	lw	s3,588(sp)
+9fc0159c:	8fb20248 	lw	s2,584(sp)
+9fc015a0:	8fb10244 	lw	s1,580(sp)
+9fc015a4:	8fb00240 	lw	s0,576(sp)
+9fc015a8:	03e00008 	jr	ra
+9fc015ac:	27bd0268 	addiu	sp,sp,616
+
+9fc015b0 <memset>:
+9fc015b0:	2cc20010 	sltiu	v0,a2,16
+9fc015b4:	00804821 	move	t1,a0
+9fc015b8:	1440002d 	bnez	v0,9fc01670 <memset+0xc0>
+9fc015bc:	00804021 	move	t0,a0
+9fc015c0:	30870003 	andi	a3,a0,0x3
+9fc015c4:	10e0000e 	beqz	a3,9fc01600 <memset+0x50>
+9fc015c8:	24820004 	addiu	v0,a0,4
+9fc015cc:	00052600 	sll	a0,a1,0x18
+9fc015d0:	00471023 	subu	v0,v0,a3
+9fc015d4:	00042603 	sra	a0,a0,0x18
+9fc015d8:	01201821 	move	v1,t1
+9fc015dc:	a0640000 	sb	a0,0(v1)
+9fc015e0:	24630001 	addiu	v1,v1,1
+9fc015e4:	1462fffd 	bne	v1,v0,9fc015dc <memset+0x2c>
+9fc015e8:	00000000 	nop
+9fc015ec:	00071027 	nor	v0,zero,a3
+9fc015f0:	24c3fffb 	addiu	v1,a2,-5
+9fc015f4:	24440005 	addiu	a0,v0,5
+9fc015f8:	00623023 	subu	a2,v1,v0
+9fc015fc:	01244021 	addu	t0,t1,a0
+9fc01600:	30a500ff 	andi	a1,a1,0xff
+9fc01604:	01003821 	move	a3,t0
+9fc01608:	10a00005 	beqz	a1,9fc01620 <memset+0x70>
+9fc0160c:	00a01821 	move	v1,a1
+9fc01610:	00051200 	sll	v0,a1,0x8
+9fc01614:	00451025 	or	v0,v0,a1
+9fc01618:	00021c00 	sll	v1,v0,0x10
+9fc0161c:	00621825 	or	v1,v1,v0
+9fc01620:	000610c2 	srl	v0,a2,0x3
+9fc01624:	1040001c 	beqz	v0,9fc01698 <memset+0xe8>
+9fc01628:	30c60007 	andi	a2,a2,0x7
+9fc0162c:	01002021 	move	a0,t0
+9fc01630:	00403821 	move	a3,v0
+9fc01634:	24e7ffff 	addiu	a3,a3,-1
+9fc01638:	ac830000 	sw	v1,0(a0)
+9fc0163c:	ac830004 	sw	v1,4(a0)
+9fc01640:	14e0fffc 	bnez	a3,9fc01634 <memset+0x84>
+9fc01644:	24840008 	addiu	a0,a0,8
+9fc01648:	000210c0 	sll	v0,v0,0x3
+9fc0164c:	01023821 	addu	a3,t0,v0
+9fc01650:	00e02021 	move	a0,a3
+9fc01654:	2cc20004 	sltiu	v0,a2,4
+9fc01658:	14400005 	bnez	v0,9fc01670 <memset+0xc0>
+9fc0165c:	00804021 	move	t0,a0
+9fc01660:	ace30000 	sw	v1,0(a3)
+9fc01664:	24e40004 	addiu	a0,a3,4
+9fc01668:	24c6fffc 	addiu	a2,a2,-4
+9fc0166c:	00804021 	move	t0,a0
+9fc01670:	10c00007 	beqz	a2,9fc01690 <memset+0xe0>
+9fc01674:	00000000 	nop
+9fc01678:	00051600 	sll	v0,a1,0x18
+9fc0167c:	00021603 	sra	v0,v0,0x18
+9fc01680:	24c6ffff 	addiu	a2,a2,-1
+9fc01684:	a1020000 	sb	v0,0(t0)
+9fc01688:	14c0fffd 	bnez	a2,9fc01680 <memset+0xd0>
+9fc0168c:	25080001 	addiu	t0,t0,1
+9fc01690:	03e00008 	jr	ra
+9fc01694:	01201021 	move	v0,t1
+9fc01698:	0bf00595 	j	9fc01654 <memset+0xa4>
+9fc0169c:	01002021 	move	a0,t0
diff --git a/lib/CPUs/MIPS/src/tb_mips_biu.vhd b/lib/CPUs/MIPS/src/tb_mips_biu.vhd
new file mode 100644
index 0000000..4fcae5c
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_biu.vhd
@@ -0,0 +1,408 @@
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_util_pkg.all;
+use work.busmaster_types.all;
+
+ENTITY tb_biu_tlb IS
+END tb_biu_tlb;
+
+ARCHITECTURE behavior OF tb_biu_tlb IS 
+
+	constant DATA_WIDTH			: integer := 32;
+	constant CLK_PERIOD			: time := 10 ns;
+
+	signal CLK				: std_logic := '1';
+	signal RST				: std_logic := '1';
+	signal INT_O			: std_logic;
+	signal CYC_O			: std_logic;
+	signal STB_O			: std_logic;
+	signal WE_O				: std_logic;
+	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I			: std_logic := '0';
+	signal MRDY_O			: std_logic := '1';
+	signal SRDY_I			: std_logic := '0';
+	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_O			: unsigned(31 downto 0) := (others => '-');
+
+	signal index_in			: unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
+	signal entry_we			: STD_LOGIC := '0';
+	signal entry_lo_in		: tlb_entry_lo_t;
+	signal entry_hi_in		: tlb_entry_hi_t;
+	
+	signal index_out		: unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
+	signal entry_re			: STD_LOGIC := '0';
+	signal entry_lo_out		: tlb_entry_lo_t;
+	signal entry_hi_out		: tlb_entry_hi_t;
+		
+	-- CPU control/data
+	signal cpu_imem_err					: STD_LOGIC := '0';
+	signal cpu_imem_en					: STD_LOGIC := '0';
+	signal cpu_imem_addr				: word_t := (others => '-');
+	signal cpu_imem_dout				: word_t;
+	signal cpu_imem_rdy					: STD_LOGIC;
+
+	signal cpu_dmem_err					: STD_LOGIC := '0';
+	signal cpu_dmem_en					: STD_LOGIC := '0';
+	signal cpu_dmem_we					: STD_LOGIC := '0';
+	signal cpu_dmem_addr				: word_t := (others => '-');
+	signal cpu_dmem_be					: unsigned(3 downto 0) := (others => '1');
+	signal cpu_dmem_din					: word_t := X"BFC0_BABE";
+	signal cpu_dmem_dout				: word_t;
+	signal cpu_dmem_rdy					: STD_LOGIC;
+
+	-- BIU control
+	signal ctrl_in						: biu_ctrl_in_t;
+	signal ctrl_out						: biu_ctrl_out_t;
+
+	type op_descr_t is (op_idle, op_entry_i_write, op_entry_d_write, op_cpu_i_read, op_cpu_d_read, op_cpu_d_write);
+	signal op_descr						: op_descr_t := op_idle;
+
+	signal cpu_imem_din_reg				: word_t;
+	signal cpu_imem_din_vld				: STD_LOGIC;
+	signal cpu_dmem_din_reg				: word_t;
+	signal cpu_dmem_din_vld				: STD_LOGIC;
+
+BEGIN
+
+inst_biu: entity work.biu
+	GENERIC MAP
+	(
+		icache_size	=>	1024,	-- words
+		icache_line	=>	8,		-- words
+		dcache_size	=>	1024,	-- words
+		dcache_line	=>	8		-- words
+	)
+	PORT MAP
+	(
+		clk			=>	CLK,
+
+		imem_err	=>	cpu_imem_err,
+		imem_rdy	=>	cpu_imem_rdy,
+		imem_en		=>	cpu_imem_en,
+		imem_addr	=>	cpu_imem_addr,
+		imem_dout	=>	cpu_imem_dout,
+		dmem_err	=>	cpu_dmem_err,
+		dmem_rdy	=>	cpu_dmem_rdy,
+		dmem_en		=>	cpu_dmem_en,
+		dmem_we		=>	cpu_dmem_we,
+		dmem_be		=>	cpu_dmem_be,
+		dmem_dout	=>	cpu_dmem_dout,
+		dmem_din	=>	cpu_dmem_din,
+		dmem_addr	=>	cpu_dmem_addr,
+
+		RST_I		=>	RST,
+		CLK_I		=>	CLK,
+		ACK_I		=>	ACK_I,
+		SRDY_I		=>	SRDY_I,
+		ADDR_O		=>	ADDR_O,
+		MDAT_I		=>	MDAT_I,
+		MDAT_O		=>	MDAT_O,
+		WE_O		=>	WE_O,
+		SEL_O		=>	SEL_O,
+		CYC_O		=>	CYC_O,
+		STB_O		=>	STB_O,
+		MRDY_O		=>	MRDY_O,
+		
+		ctrl_in		=>	ctrl_in,
+		ctrl_out	=>	ctrl_out
+		
+	);
+
+
+inst_rom_wb: entity work.rom_wb
+--	GENERIC MAP 
+--	(
+--		NUM_WORDS	=>	256
+--	)
+	PORT MAP
+	(
+		CLK_I		=>	CLK,
+		RST_I		=>	RST,
+		CYC_I		=>	CYC_O,
+		STB_I		=>	STB_O,
+--		SEL_I		=>	SEL_O,
+		WE_I		=>	WE_O,
+		ACK_O		=>	ACK_I,
+		SRDY_O		=>	SRDY_I,
+		MRDY_I		=>	MRDY_O,
+		ADDR_I		=>	ADDR_O,
+--		DAT_I		=>	MDAT_O,
+		DAT_O		=>	MDAT_I
+	);
+
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK <= not CLK;
+	end process;
+
+cpu_imem_din_register:
+	process(clk)
+	variable en2: std_logic;
+	begin
+		if rising_edge(clk) then
+			cpu_imem_din_vld	<= '0';
+			if en2 = '1' and cpu_imem_rdy = '1' then
+				cpu_imem_din_reg	<= cpu_imem_dout;
+				cpu_imem_din_vld	<= '1';
+			end if;
+			en2	:= cpu_imem_en;
+		end if;
+	end process;	
+
+cpu_dmem_din_register:
+	process(clk)
+	variable en2: std_logic;
+	begin
+		if rising_edge(clk) then
+			cpu_dmem_din_vld	<= '0';
+			if en2 = '1' and cpu_dmem_rdy = '1' then
+				cpu_dmem_din_reg	<= cpu_dmem_dout;
+				cpu_dmem_din_vld	<= '1';
+			end if;
+			en2	:= cpu_dmem_en;
+		end if;
+	end process;	
+
+
+	ctrl_in.icache.inv_addr			<= X"BEEF_BABE";
+	ctrl_in.icache.inv_at			<= '0';
+	ctrl_in.icache.inv_all			<= '0';
+
+	ctrl_in.dcache.inv_addr			<= X"BEEF_BABE";
+	ctrl_in.dcache.inv_at			<= '0';
+	ctrl_in.dcache.inv_all			<= '0';
+
+STIMULUS: process
+
+	variable result : unsigned(31 downto 0);
+
+	procedure cmd_entry_i_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
+	begin
+	
+		op_descr <= op_entry_i_write;
+		
+		ctrl_in.itlb.entry_wr_idx		<= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
+
+		ctrl_in.itlb.entry_hi.vpn	<= vpn;
+		ctrl_in.itlb.entry_hi.asid	<= asid;
+		ctrl_in.itlb.entry_hi.g		<= g;
+
+		ctrl_in.itlb.entry_lo.pfn	<= pfn;	
+		ctrl_in.itlb.entry_lo.n		<= n;	
+		ctrl_in.itlb.entry_lo.d		<= d;	
+		ctrl_in.itlb.entry_lo.v		<= v;	
+
+		ctrl_in.itlb.entry_we			<= '1';
+		wait until rising_edge(CLK);
+		ctrl_in.itlb.entry_we			<= '0';
+	
+	end procedure cmd_entry_i_write;
+
+	procedure cmd_entry_d_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
+	begin
+	
+		op_descr <= op_entry_d_write;
+		ctrl_in.dtlb.entry_wr_idx		<= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
+
+		ctrl_in.dtlb.entry_hi.vpn	<= vpn;
+		ctrl_in.dtlb.entry_hi.asid	<= asid;
+		ctrl_in.dtlb.entry_hi.g		<= g;
+
+		ctrl_in.dtlb.entry_lo.pfn	<= pfn;	
+		ctrl_in.dtlb.entry_lo.n		<= n;	
+		ctrl_in.dtlb.entry_lo.d		<= d;	
+		ctrl_in.dtlb.entry_lo.v		<= v;	
+
+		ctrl_in.dtlb.entry_we			<= '1';
+		wait until rising_edge(CLK);
+		ctrl_in.dtlb.entry_we			<= '0';
+	
+	end procedure cmd_entry_d_write;
+
+	procedure cpu_i_read(addr : unsigned) is
+	begin
+
+		op_descr <= op_cpu_i_read;
+		cpu_imem_addr	<= addr;
+		cpu_imem_en		<= '1';
+		wait until rising_edge(CLK) and cpu_imem_rdy = '1';
+		cpu_imem_en		<= '0';
+
+	end procedure cpu_i_read;
+
+	procedure cpu_d_read(addr : unsigned) is
+	begin
+
+		op_descr <= op_cpu_d_read;
+		cpu_dmem_addr	<= addr;
+		cpu_dmem_en		<= '1';
+		wait until rising_edge(CLK) and cpu_dmem_rdy = '1';
+		cpu_dmem_en		<= '0';
+
+	end procedure cpu_d_read;
+
+	procedure cpu_d_write(addr, data : unsigned) is
+	begin
+
+		op_descr <= op_cpu_d_write;
+		cpu_dmem_we		<= '1';
+		cpu_dmem_addr	<= addr;
+		cpu_dmem_din	<= data;
+		cpu_dmem_en		<= '1';
+		wait until rising_edge(CLK) and cpu_dmem_rdy = '1';
+		cpu_dmem_en		<= '0';
+
+	end procedure cpu_d_write;
+
+	begin
+
+		wait for 6*CLK_PERIOD;
+		RST <= '0';
+		wait for 60*CLK_PERIOD;
+		wait until rising_edge(CLK) and cpu_imem_rdy = '1' and cpu_dmem_rdy = '1';
+
+		cmd_entry_i_write(0, "110000", X"0000_0", X"00DE_C", '0', '0', '0', '1');
+		cmd_entry_i_write(1, "110000", X"0000_1", X"11DE_C", '0', '0', '0', '1');
+		cmd_entry_i_write(2, "110000", X"0000_2", X"22DE_C", '0', '0', '0', '1');
+		cmd_entry_i_write(3, "110000", X"0000_3", X"33DE_C", '0', '0', '0', '1');
+		cmd_entry_i_write(4, "110000", X"0000_4", X"44DE_C", '0', '0', '0', '1');
+		cmd_entry_i_write(5, "110000", X"0000_5", X"55DE_C", '0', '0', '0', '1');
+		cmd_entry_i_write(6, "110000", X"0000_6", X"66DE_C", '0', '0', '0', '1');
+		cmd_entry_i_write(7, "110000", X"0000_7", X"77DE_C", '0', '0', '0', '1');
+		
+		cmd_entry_d_write(0, "110000", X"0000_0", X"00DE_C", '0', '0', '0', '1');
+		cmd_entry_d_write(1, "110000", X"0000_1", X"11DE_C", '0', '0', '0', '1');
+		cmd_entry_d_write(2, "110000", X"0000_2", X"22DE_C", '0', '0', '0', '1');
+		cmd_entry_d_write(3, "110000", X"0000_3", X"33DE_C", '0', '0', '0', '1');
+		cmd_entry_d_write(4, "110000", X"0000_4", X"44DE_C", '0', '0', '0', '1');
+		cmd_entry_d_write(5, "110000", X"0000_5", X"55DE_C", '0', '0', '0', '1');
+		cmd_entry_d_write(6, "110000", X"0000_6", X"66DE_C", '0', '0', '0', '1');
+		cmd_entry_d_write(7, "110000", X"0000_7", X"77DE_C", '0', '0', '0', '1');
+
+		cpu_i_read(X"BFC0_0200");
+		cpu_i_read(X"BFC0_0180");
+		cpu_d_read(X"BFC0_0200");
+
+		cpu_i_read(X"8000_0204");
+		cpu_i_read(X"8000_0300");
+		cpu_i_read(X"8000_0304");
+		cpu_i_read(X"8000_0308");
+		
+		cpu_i_read(X"9000_0208");
+		cpu_i_read(X"9000_030C");
+		cpu_i_read(X"9100_0310");
+		cpu_i_read(X"9200_0314");
+
+		cpu_i_read(X"A000_020C");
+		cpu_i_read(X"A000_0318");
+		cpu_i_read(X"A100_031C");
+		cpu_i_read(X"A200_0320");
+		
+		cpu_i_read(X"B000_0210");
+		cpu_i_read(X"B000_0324");
+		cpu_i_read(X"B000_0328");
+		cpu_i_read(X"B000_032C");
+
+		cpu_i_read(X"0000_0400");
+		cpu_i_read(X"0000_1420");
+		cpu_i_read(X"0000_2440");
+		cpu_i_read(X"0000_3460");
+		cpu_i_read(X"0000_4480");
+		cpu_i_read(X"0000_54A0");
+		cpu_i_read(X"0000_64C0");
+		cpu_i_read(X"0000_74E0");
+		cpu_i_read(X"0000_8500");
+		cpu_i_read(X"0000_9520");
+		
+		cpu_i_read(X"0000_0400");
+		cpu_i_read(X"0000_1420");
+		cpu_i_read(X"0000_2440");
+		cpu_i_read(X"0000_3460");
+		cpu_i_read(X"0000_4480");
+		cpu_i_read(X"0000_54A0");
+		cpu_i_read(X"0000_64C0");
+		cpu_i_read(X"0000_74E0");
+
+
+		cpu_i_read(X"0000_0400");
+
+		cpu_i_read(X"0000_0410");
+		cpu_i_read(X"0000_0404");
+		cpu_i_read(X"0000_0408");
+		cpu_i_read(X"0000_0404");
+		cpu_i_read(X"0000_0434");
+		cpu_i_read(X"0000_0400");
+
+
+		---------------------------------------------
+		cpu_d_read(X"BFC0_0200");
+		cpu_d_read(X"BFC0_0180");
+
+		cpu_d_read(X"8000_0204");
+		cpu_d_read(X"8000_0300");
+		cpu_d_read(X"8000_0304");
+		cpu_d_read(X"8000_0308");
+		
+		cpu_d_read(X"9000_0208");
+		cpu_d_read(X"9000_030C");
+		cpu_d_read(X"9100_0310");
+		cpu_d_read(X"9200_0314");
+
+		cpu_d_read(X"A000_020C");
+		cpu_d_read(X"A000_0318");
+		cpu_d_read(X"A100_031C");
+		cpu_d_read(X"A200_0320");
+		
+		cpu_d_read(X"B000_0210");
+		cpu_d_read(X"B000_0324");
+		cpu_d_read(X"B000_0328");
+		cpu_d_read(X"B000_032C");
+
+		cpu_d_read(X"0000_0400");
+		cpu_d_read(X"0000_1420");
+		cpu_d_read(X"0000_2440");
+		cpu_d_read(X"0000_3460");
+		cpu_d_read(X"0000_4480");
+		cpu_d_read(X"0000_54A0");
+		cpu_d_read(X"0000_64C0");
+		cpu_d_read(X"0000_74E0");
+		cpu_d_read(X"0000_8500");
+		cpu_d_read(X"0000_9520");
+		
+		cpu_d_read(X"0000_0400");
+		cpu_d_read(X"0000_1420");
+		cpu_d_read(X"0000_2440");
+		cpu_d_read(X"0000_3460");
+		cpu_d_read(X"0000_4480");
+		cpu_d_read(X"0000_54A0");
+		cpu_d_read(X"0000_64C0");
+		cpu_d_read(X"0000_74E0");
+		cpu_d_write(X"0000_0400", X"AAAA_AAAA");
+
+		cpu_d_read(X"0000_0400");
+
+		cpu_d_read(X"0000_0410");
+		cpu_d_read(X"0000_0404");
+		cpu_d_read(X"0000_0408");
+		cpu_d_write(X"0000_0404", X"5555_5555");
+		cpu_d_read(X"0000_0404");
+		cpu_d_write(X"0000_0404", X"6666_6666");
+		cpu_d_read(X"0000_0434");
+		cpu_d_write(X"0000_0400", X"1111_1111");
+		cpu_d_write(X"0000_0404", X"2222_2222");
+		cpu_d_write(X"0000_0408", X"3333_3333");
+		cpu_d_write(X"0000_040C", X"4444_4444");
+		cpu_d_read(X"0000_0400");
+
+	wait;
+	
+	end process;
+	
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_cam.vhd b/lib/CPUs/MIPS/src/tb_mips_cam.vhd
new file mode 100644
index 0000000..9783c09
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_cam.vhd
@@ -0,0 +1,161 @@
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_util_pkg.all;
+
+ENTITY tb_cam IS
+END tb_cam;
+
+ARCHITECTURE behavior OF tb_cam IS 
+
+	constant CLK_PERIOD			: time := 10 ns;
+	constant DATA_WIDTH			: integer := 20;
+	constant CAM_NUM_ENTRIES	: integer := 32;
+
+	signal CLK_O				: std_logic := '1';
+	signal RST_O				: std_logic := '1';
+	signal cam_we				: std_logic := '0';
+	signal cam_re				: std_logic := '0';
+	signal cam_vld				: std_logic := '0';
+	signal cam_rdy				: std_logic := '-';
+
+	signal cam_addr				: unsigned(lg2(CAM_NUM_ENTRIES)-1 downto 0) := (others => '0');
+	signal cam_data				: unsigned(DATA_WIDTH-1 downto 0) := (others => '0');
+
+	signal cam_hit				: unsigned (CAM_NUM_ENTRIES-1 downto 0);
+	signal cam_hit_vld			: std_logic := '-';
+
+
+BEGIN
+
+inst_cam: entity work.cam
+	GENERIC MAP
+	(
+		NUM_ENTRIES			=>	CAM_NUM_ENTRIES,
+		DATA_WIDTH			=>	DATA_WIDTH,
+		CAM_RAM_MAX_WIDTH	=>	15
+	)
+	PORT MAP
+	(
+		rst		=>	RST_O,
+		clk		=>	CLK_O,
+		
+		rdy		=>	cam_rdy,
+		
+		re		=>	cam_re,
+		we		=>	cam_we,
+		vld		=>	cam_vld,
+		addr	=>	cam_addr,
+		din		=>	cam_data,
+
+		hit		=>	cam_hit,
+		hit_vld	=>	cam_hit_vld
+
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+
+STIMULUS: process
+
+	variable result : unsigned(31 downto 0);
+
+	procedure cam_entry_write(index : integer; data : unsigned; valid : std_logic) is
+	begin
+	
+	cam_data			<= data;
+	cam_addr			<= to_unsigned(index, lg2(CAM_NUM_ENTRIES));
+	cam_vld				<= valid;
+	cam_we				<= '1';
+	wait until rising_edge(CLK_O) and cam_rdy = '1';
+	cam_we				<= '0';
+	
+	end procedure cam_entry_write;
+
+	procedure cam_lookup(data : unsigned) is
+	begin
+	
+	cam_data			<= data;
+	cam_re				<= '1';
+	wait until rising_edge(CLK_O) and cam_rdy = '1';
+	cam_re				<= '0';
+
+	end procedure cam_lookup;
+	
+
+	begin
+
+		wait for 6*CLK_PERIOD;
+		RST_O <= '0';
+		wait for 60*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+
+
+		cam_entry_write(1, X"CAFE_1", '1');
+		cam_entry_write(2, X"CAFE_2", '1');
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+		
+		cam_lookup(X"CAFE_1");
+		cam_lookup(X"CAFE_2");
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+		
+		-- overwrite
+		cam_entry_write(2, X"BEEF_2", '1');
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+		
+		-- overwrite entry
+		cam_entry_write(2, X"CAFE_2", '1');
+		-- new entry
+		cam_entry_write(3, X"CAFE_3", '1');
+		cam_entry_write(4, X"CAFE_4", '1');
+
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+		cam_entry_write(1, X"CAFE_1", '0');
+		cam_entry_write(2, X"CAFE_2", '0');
+		cam_entry_write(3, X"CAFE_3", '0');
+		cam_entry_write(4, X"CAFE_4", '0');
+
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+		cam_lookup(X"BEEF_2");
+		cam_lookup(X"CAFE_1");
+		cam_lookup(X"CAFE_2");
+		cam_lookup(X"CAFE_3");
+		cam_lookup(X"CAFE_4");
+		
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+		cam_entry_write(1, X"CAFE_1", '1');
+		cam_entry_write(2, X"CAFE_2", '1');
+		cam_entry_write(3, X"CAFE_3", '1');
+		cam_entry_write(4, X"CAFE_4", '1');
+
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+		cam_lookup(X"CAFE_1");
+		cam_lookup(X"CAFE_2");
+		cam_lookup(X"CAFE_3");
+		cam_lookup(X"CAFE_4");
+
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+		cam_entry_write(7, X"CAFE_7", '0');
+
+		wait for 8*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and cam_rdy = '1';
+	wait;
+	
+	end process;
+	
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_dcache.vhd b/lib/CPUs/MIPS/src/tb_mips_dcache.vhd
new file mode 100644
index 0000000..74beb4f
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_dcache.vhd
@@ -0,0 +1,389 @@
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_util_pkg.all;
+use work.busmaster_types.all;
+
+ENTITY tb_dcache_tlb IS
+END tb_dcache_tlb;
+
+ARCHITECTURE behavior OF tb_dcache_tlb IS 
+
+	constant DATA_WIDTH			: integer := 32;
+	constant CLK_PERIOD			: time := 10 ns;
+	constant TLB_NUM_ENTRIES	: integer := 8;
+
+	signal CLK				: std_logic := '1';
+	signal RST				: std_logic := '1';
+	signal INT_O			: std_logic;
+	signal CYC_O			: std_logic;
+	signal STB_O			: std_logic;
+	signal WE_O				: std_logic;
+	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I			: std_logic := '0';
+	signal MRDY_O			: std_logic := '1';
+	signal SRDY_I			: std_logic := '0';
+	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_O			: unsigned(31 downto 0) := (others => '-');
+
+	signal ce				: std_logic := '1';
+
+	signal index_in			: unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
+	signal entry_we			: STD_LOGIC := '0';
+	signal entry_lo_in		: tlb_entry_lo_t;
+	signal entry_hi_in		: tlb_entry_hi_t;
+	
+	signal index_out		: unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
+	signal entry_re			: STD_LOGIC := '0';
+	signal entry_lo_out		: tlb_entry_lo_t;
+	signal entry_hi_out		: tlb_entry_hi_t;
+		
+	signal tlb_in			: tlb_query_in_t;
+	signal tlb_out			: tlb_query_out_t;
+
+	signal tlb_index_hit	: unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0);
+	signal tlb_va			: word_t := (others => '-');
+
+	signal tlb_pa			: word_t;
+	signal tlb_flags		: tlb_flags_t;
+	signal tlb_hit			: STD_LOGIC;
+
+	-- CPU control/data
+	signal cpu_en						: STD_LOGIC := '0';
+	signal cpu_we						: STD_LOGIC := '0';
+	signal cpu_addr						: word_t := (others => '-');
+	signal cpu_be						: unsigned(3 downto 0) := (others => '1');
+	signal cpu_din						: word_t := X"BFC0_BABE";
+	signal cpu_dout						: word_t;
+	signal cpu_rdy						: STD_LOGIC;
+
+	-- Cache control
+	signal dcache_ctrl_in				: cache_ctrl_t;
+
+	-- busmaster data
+	signal bus_din						: word_t := (others => '-');
+	signal bus_din_rdy					: std_logic := '0';
+	signal bus_din_vld					: std_logic := '0';
+
+	signal bus_dout						: word_t := (others => '-');
+	signal bus_dout_vld					: std_logic := '0';
+	signal bus_dout_rdy					: std_logic := '0';
+
+	-- busmaster command
+	signal bus_cmd_rdy					: std_logic := '0';
+	signal bus_cmd_we					: std_logic := '0';
+	signal bus_cmd_cycle_en				: std_logic := '0';
+	signal bus_cmd						: bm_cmd_t;
+	signal bus_cyc_complete				: std_logic := '0';
+
+	signal cpu_din_reg					: word_t;
+	signal cpu_din_vld					: STD_LOGIC;
+
+BEGIN
+
+inst_tlb : entity work.tlb
+	GENERIC MAP
+	(
+		NUM_ENTRIES			=> TLB_NUM_ENTRIES
+	)
+	PORT MAP
+	(
+		-- System signals
+		rst					=> RST,
+		clk					=> CLK,
+		ce					=> ce,
+
+		index_in			=> index_in,
+		entry_we			=> entry_we,
+		entry_lo_in			=> entry_lo_in,
+		entry_hi_in			=> entry_hi_in,
+		
+		index_out			=> index_out,
+		entry_re			=> entry_re,
+		entry_lo_out		=> entry_lo_out,
+		entry_hi_out		=> entry_hi_out,
+
+		tlb_query_in		=> tlb_in,
+		tlb_query_out		=> tlb_out
+	);
+
+	dcache_ctrl_in.inv_addr			<= X"BEEF_BABE";
+	dcache_ctrl_in.inv_at			<= '0';
+	dcache_ctrl_in.inv_all			<= '0';
+	
+inst_dcache: entity work.dcache
+	GENERIC MAP
+	(
+		cache_size			=>	1024,
+		line_size			=>	8
+	)
+	PORT MAP
+	(
+		rst					=>	RST,
+		clk					=>	CLK,
+
+		-- CPU control/data
+		en					=>	cpu_en,
+		we					=>	cpu_we,
+		addr				=>	cpu_addr,
+		be					=>	cpu_be,
+		din					=>	cpu_din,
+		dout				=>	cpu_dout,
+		rdy					=>	cpu_rdy,
+
+		-- Cache control
+		ctrl_in				=>	dcache_ctrl_in,
+		tlb_query_in		=>  tlb_out,
+		tlb_query_out		=>  tlb_in,
+
+		-- busmaster data
+		bus_din				=>	bus_din,
+		bus_din_rdy			=>	bus_din_rdy,
+		bus_din_vld			=>	bus_din_vld,
+
+		bus_dout			=>	bus_dout,
+		bus_dout_vld		=>	bus_dout_vld,
+		bus_dout_rdy		=>	bus_dout_rdy,
+
+		-- busmaster command
+		bus_cmd_rdy			=>	bus_cmd_rdy,
+		bus_cmd_we			=>	bus_cmd_we,
+		bus_cmd_cycle_en	=>	bus_cmd_cycle_en,
+		bus_cmd_out			=>	bus_cmd,
+		bus_cyc_complete	=>	bus_cyc_complete
+	);
+
+
+inst_busmaster_sync : entity work.busmaster_sync
+	GENERIC MAP
+	(
+		DATA_WIDTH					=> DATA_WIDTH,
+		FIFO_DEPTH					=> 4
+	)
+	PORT MAP
+	(
+		-- System signals
+		rst					=> RST,
+		clk					=> CLK,
+
+		cmd_cycle_finished	=> bus_cyc_complete,
+		cmd_cycle_en		=> bus_cmd_cycle_en,
+		
+		cmd_rdy				=> bus_cmd_rdy,
+		cmd_we				=> bus_cmd_we,
+		cmd_in				=> bus_cmd,
+		
+		din_rdy				=> bus_dout_rdy,
+		din_we				=> bus_dout_vld,
+		din					=> bus_dout,
+
+		dout				=> bus_din,
+		dout_vld			=> bus_din_vld,
+		dout_re				=> bus_din_rdy,
+
+		-- JBUS Master signals
+		CYC_O				=> CYC_O,
+		STB_O				=> STB_O,
+		WE_O				=> WE_O,
+		SEL_O				=> SEL_O,
+		ACK_I				=> ACK_I,
+		SRDY_I				=> SRDY_I,
+		MRDY_O				=> MRDY_O,
+		ADDR_O				=> ADDR_O,
+		MDAT_I				=> MDAT_I,
+		MDAT_O				=> MDAT_O
+	);
+
+inst_rom_wb: entity work.rom_wb
+--	GENERIC MAP 
+--	(
+--		NUM_WORDS	=>	256
+--	)
+	PORT MAP
+	(
+		CLK_I		=>	CLK,
+		RST_I		=>	RST,
+		CYC_I		=>	CYC_O,
+		STB_I		=>	STB_O,
+--		SEL_I		=>	SEL_O,
+		WE_I		=>	WE_O,
+		ACK_O		=>	ACK_I,
+		SRDY_O		=>	SRDY_I,
+		MRDY_I		=>	MRDY_O,
+		ADDR_I		=>	ADDR_O,
+--		DAT_I		=>	MDAT_O,
+		DAT_O		=>	MDAT_I
+	);
+
+
+cpu_din_register:
+	process(clk)
+	variable en2: std_logic;
+	begin
+		if rising_edge(clk) then
+			cpu_din_vld	<= '0';
+			if en2 = '1' and cpu_rdy = '1' then
+				cpu_din_reg	<= cpu_dout;
+				cpu_din_vld	<= '1';
+			end if;
+			en2	:= cpu_en;
+		end if;
+	end process;	
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK <= not CLK;
+	end process;
+
+
+STIMULUS: process
+
+	variable result : unsigned(31 downto 0);
+
+	procedure cmd_entry_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
+	begin
+	
+		index_in			<= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
+
+		entry_hi_in.vpn		<= vpn;
+		entry_hi_in.asid	<= asid;
+		entry_hi_in.g		<= g;
+
+		entry_lo_in.pfn		<= pfn;	
+		entry_lo_in.n		<= n;	
+		entry_lo_in.d		<= d;	
+		entry_lo_in.v		<= v;	
+
+		entry_we			<= '1';
+		wait until rising_edge(CLK);
+		entry_we			<= '0';
+	
+	end procedure cmd_entry_write;
+
+	procedure cpu_read(addr : unsigned) is
+	begin
+
+		cpu_we		<= '0';
+		cpu_addr	<= addr;
+		cpu_en		<= '1';
+		wait until rising_edge(CLK) and cpu_rdy = '1';
+		cpu_en		<= '0';
+
+	end procedure cpu_read;
+
+	procedure cpu_write(addr, data : unsigned) is
+	begin
+
+		cpu_we		<= '1';
+		cpu_addr	<= addr;
+		cpu_din		<= data;
+		cpu_en		<= '1';
+		wait until rising_edge(CLK) and cpu_rdy = '1';
+		cpu_en		<= '0';
+
+	end procedure cpu_write;
+
+	begin
+
+		wait for 6*CLK_PERIOD;
+		RST <= '0';
+		wait for 60*CLK_PERIOD;
+		wait until rising_edge(CLK) and cpu_rdy = '1';
+
+		cmd_entry_write(0, "110000", X"0000_0", X"00DE_C", '0', '0', '0', '1');
+		cmd_entry_write(1, "110000", X"0000_1", X"11DE_C", '0', '0', '0', '1');
+		cmd_entry_write(2, "110000", X"0000_2", X"22DE_C", '0', '0', '0', '1');
+		cmd_entry_write(3, "110000", X"0000_3", X"33DE_C", '0', '0', '0', '1');
+		cmd_entry_write(4, "110000", X"0000_4", X"44DE_C", '0', '0', '0', '1');
+		cmd_entry_write(5, "110000", X"0000_5", X"55DE_C", '0', '0', '0', '1');
+		cmd_entry_write(6, "110000", X"0000_6", X"66DE_C", '0', '0', '0', '1');
+		cmd_entry_write(7, "110000", X"0000_7", X"77DE_C", '0', '0', '0', '1');
+		
+
+		cpu_read(X"BFC0_0200");
+		cpu_read(X"BFC0_0180");
+
+		cpu_read(X"8000_0204");
+		cpu_read(X"8000_0300");
+		cpu_read(X"8000_0304");
+		cpu_read(X"8000_0308");
+		
+		cpu_read(X"9000_0208");
+		cpu_read(X"9000_030C");
+		cpu_read(X"9100_0310");
+		cpu_read(X"9200_0314");
+
+		cpu_read(X"A000_020C");
+		cpu_read(X"A000_0318");
+		cpu_read(X"A100_031C");
+		cpu_read(X"A200_0320");
+		
+		cpu_read(X"B000_0210");
+		cpu_read(X"B000_0324");
+		cpu_read(X"B000_0328");
+		cpu_read(X"B000_032C");
+
+		cpu_read(X"0000_0400");
+		cpu_read(X"0000_1420");
+		cpu_read(X"0000_2440");
+		cpu_read(X"0000_3460");
+		cpu_read(X"0000_4480");
+		cpu_read(X"0000_54A0");
+		cpu_read(X"0000_64C0");
+		cpu_read(X"0000_74E0");
+		cpu_read(X"0000_8500");
+		cpu_read(X"0000_9520");
+		
+		cpu_read(X"0000_0400");
+		cpu_read(X"0000_1420");
+		cpu_read(X"0000_2440");
+		cpu_read(X"0000_3460");
+		cpu_read(X"0000_4480");
+		cpu_read(X"0000_54A0");
+		cpu_read(X"0000_64C0");
+		cpu_read(X"0000_74E0");
+		cpu_write(X"0000_0400", X"AAAA_AAAA");
+
+--		cmd_entry_write(0, "110000", X"0000_0", X"40DE_F", '0', '0', '1', '1');
+
+		cpu_read(X"0000_0400");
+
+		cpu_read(X"0000_0410");
+		cpu_read(X"0000_0404");
+		cpu_read(X"0000_0408");
+		cpu_write(X"0000_0404", X"5555_5555");
+		cpu_read(X"0000_0404");
+		cpu_write(X"0000_0404", X"6666_6666");
+		cpu_read(X"0000_0434");
+		cpu_write(X"0000_0400", X"1111_1111");
+		cpu_write(X"0000_0404", X"2222_2222");
+		cpu_write(X"0000_0408", X"3333_3333");
+		cpu_write(X"0000_040C", X"4444_4444");
+		cpu_write(X"0000_0400", X"1111_1111");
+		cpu_write(X"0000_0404", X"2222_2222");
+		cpu_write(X"0000_0408", X"3333_3333");
+		cpu_write(X"0000_040C", X"4444_4444");
+		cpu_write(X"0000_0400", X"1111_1111");
+		cpu_write(X"0000_0404", X"2222_2222");
+		cpu_write(X"0000_0408", X"3333_3333");
+		cpu_write(X"0000_040C", X"4444_4444");
+		cpu_write(X"0000_0400", X"1111_1111");
+		cpu_write(X"0000_0404", X"2222_2222");
+		cpu_write(X"0000_0408", X"3333_3333");
+		cpu_write(X"0000_040C", X"4444_4444");
+		cpu_write(X"0000_0400", X"1111_1111");
+		cpu_write(X"0000_0404", X"2222_2222");
+		cpu_write(X"0000_0408", X"3333_3333");
+		cpu_write(X"0000_040C", X"4444_4444");
+		cpu_read(X"0000_0400");
+
+	wait;
+	
+	end process;
+	
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_icache.vhd b/lib/CPUs/MIPS/src/tb_mips_icache.vhd
new file mode 100644
index 0000000..3342ba8
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_icache.vhd
@@ -0,0 +1,363 @@
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_util_pkg.all;
+use work.busmaster_types.all;
+
+ENTITY tb_icache_tlb IS
+END tb_icache_tlb;
+
+ARCHITECTURE behavior OF tb_icache_tlb IS 
+
+	constant DATA_WIDTH			: integer := 32;
+	constant CLK_PERIOD			: time := 10 ns;
+	constant TLB_NUM_ENTRIES	: integer := 8;
+
+	signal CLK				: std_logic := '1';
+	signal RST				: std_logic := '1';
+	signal INT_O			: std_logic;
+	signal CYC_O			: std_logic;
+	signal STB_O			: std_logic;
+	signal WE_O				: std_logic;
+	signal SEL_O			: unsigned(3 downto 0) := (others => '1');
+	signal ACK_I			: std_logic := '0';
+	signal MRDY_O			: std_logic := '1';
+	signal SRDY_I			: std_logic := '0';
+	signal ADDR_O			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_I			: unsigned(31 downto 0) := (others => '-');
+	signal MDAT_O			: unsigned(31 downto 0) := (others => '-');
+
+	signal ce				: std_logic := '1';
+
+	signal index_in			: unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
+	signal entry_we			: STD_LOGIC := '0';
+	signal entry_lo_in		: tlb_entry_lo_t;
+	signal entry_hi_in		: tlb_entry_hi_t;
+	
+	signal index_out		: unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0) := (others => '0');
+	signal entry_re			: STD_LOGIC := '0';
+	signal entry_lo_out		: tlb_entry_lo_t;
+	signal entry_hi_out		: tlb_entry_hi_t;
+		
+	signal tlb_in			: tlb_query_in_t;
+	signal tlb_out			: tlb_query_out_t;
+
+	signal tlb_index_hit	: unsigned(lg2(TLB_NUM_ENTRIES)-1 downto 0);
+	signal tlb_va			: word_t := (others => '-');
+
+	signal tlb_pa			: word_t;
+	signal tlb_flags		: tlb_flags_t;
+	signal tlb_hit			: STD_LOGIC;
+
+	-- CPU control/data
+	signal cpu_en						: STD_LOGIC := '0';
+	signal cpu_we						: STD_LOGIC := '0';
+	signal cpu_be						: unsigned(3 downto 0) := (others => '1');
+	signal cpu_addr						: word_t := (others => '-');
+	signal cpu_dout						: word_t;
+	signal cpu_din						: word_t := X"BFC0_BABE";
+	signal cpu_rdy						: STD_LOGIC;
+
+	-- Cache control
+	signal icache_ctrl_in				: cache_ctrl_t;
+
+	-- busmaster data
+	signal bus_din						: word_t := (others => '-');
+	signal bus_din_rdy					: std_logic := '0';
+	signal bus_din_vld					: std_logic := '0';
+
+	signal bus_dout						: word_t := (others => '-');
+	signal bus_dout_vld					: std_logic := '0';
+	signal bus_dout_rdy					: std_logic := '0';
+
+	-- busmaster command
+	signal bus_cmd_rdy					: std_logic := '0';
+	signal bus_cmd_we					: std_logic := '0';
+	signal bus_cmd_cycle_en				: std_logic := '0';
+	signal bus_cmd						: bm_cmd_t;
+	signal bus_cyc_complete				: std_logic := '0';
+
+	signal cpu_din_reg					: word_t;
+	signal cpu_din_vld					: STD_LOGIC;
+
+BEGIN
+
+inst_tlb : entity work.tlb
+	GENERIC MAP
+	(
+		NUM_ENTRIES			=> TLB_NUM_ENTRIES
+	)
+	PORT MAP
+	(
+		-- System signals
+		rst					=> RST,
+		clk					=> CLK,
+		ce					=> ce,
+
+		index_in			=> index_in,
+		entry_we			=> entry_we,
+		entry_lo_in			=> entry_lo_in,
+		entry_hi_in			=> entry_hi_in,
+		
+		index_out			=> index_out,
+		entry_re			=> entry_re,
+		entry_lo_out		=> entry_lo_out,
+		entry_hi_out		=> entry_hi_out,
+
+		tlb_query_in		=> tlb_in,
+		tlb_query_out		=> tlb_out
+	);
+
+	icache_ctrl_in.inv_addr			<= X"BEEF_BABE";
+	icache_ctrl_in.inv_at			<= '0';
+	icache_ctrl_in.inv_all			<= '0';
+	
+inst_icache: entity work.icache
+	GENERIC MAP
+	(
+		cache_size			=>	1024,
+		line_size			=>	8
+	)
+	PORT MAP
+	(
+		rst					=>	RST,
+		clk					=>	CLK,
+
+		-- CPU control/data
+		en					=>	cpu_en,
+		addr				=>	cpu_addr,
+		dout				=>	cpu_dout,
+		rdy					=>	cpu_rdy,
+
+		-- Cache control
+		ctrl_in				=>	icache_ctrl_in,
+		tlb_query_in		=>  tlb_out,
+		tlb_query_out		=>  tlb_in,
+		
+		-- busmaster data
+		bus_din				=>	bus_din,
+		bus_din_rdy			=>	bus_din_rdy,
+		bus_din_vld			=>	bus_din_vld,
+
+		-- busmaster command
+		bus_cmd_rdy			=>	bus_cmd_rdy,
+		bus_cmd_we			=>	bus_cmd_we,
+		bus_cmd_cycle_en	=>	bus_cmd_cycle_en,
+		bus_cmd_out			=>	bus_cmd,
+		bus_cyc_complete	=>	bus_cyc_complete
+	);
+
+
+inst_busmaster_sync : entity work.busmaster_sync
+	GENERIC MAP
+	(
+		DATA_WIDTH					=> DATA_WIDTH,
+		FIFO_DEPTH					=> 4
+	)
+	PORT MAP
+	(
+		-- System signals
+		rst					=> RST,
+		clk					=> CLK,
+
+		cmd_cycle_finished	=> bus_cyc_complete,
+		cmd_cycle_en		=> bus_cmd_cycle_en,
+		
+		cmd_rdy				=> bus_cmd_rdy,
+		cmd_we				=> bus_cmd_we,
+		cmd_in				=> bus_cmd,
+		
+		din_rdy				=> bus_dout_rdy,
+		din_we				=> bus_dout_vld,
+		din					=> bus_dout,
+
+		dout				=> bus_din,
+		dout_vld			=> bus_din_vld,
+		dout_re				=> bus_din_rdy,
+
+		-- JBUS Master signals
+		CYC_O				=> CYC_O,
+		STB_O				=> STB_O,
+		WE_O				=> WE_O,
+		SEL_O				=> SEL_O,
+		ACK_I				=> ACK_I,
+		SRDY_I				=> SRDY_I,
+		MRDY_O				=> MRDY_O,
+		ADDR_O				=> ADDR_O,
+		MDAT_I				=> MDAT_I,
+		MDAT_O				=> MDAT_O
+	);
+
+inst_rom_wb: entity work.rom_wb
+--	GENERIC MAP 
+--	(
+--		NUM_WORDS	=>	256
+--	)
+	PORT MAP
+	(
+		CLK_I		=>	CLK,
+		RST_I		=>	RST,
+		CYC_I		=>	CYC_O,
+		STB_I		=>	STB_O,
+--		SEL_I		=>	SEL_O,
+		WE_I		=>	WE_O,
+		ACK_O		=>	ACK_I,
+		SRDY_O		=>	SRDY_I,
+		MRDY_I		=>	MRDY_O,
+		ADDR_I		=>	ADDR_O,
+--		DAT_I		=>	MDAT_O,
+		DAT_O		=>	MDAT_I
+	);
+
+
+cpu_din_register:
+	process(clk)
+	variable en2: std_logic;
+	begin
+		if rising_edge(clk) then
+			cpu_din_vld	<= '0';
+			if en2 = '1' and cpu_rdy = '1' then
+				cpu_din_reg	<= cpu_dout;
+				cpu_din_vld	<= '1';
+			end if;
+			en2	:= cpu_en;
+		end if;
+	end process;	
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK <= not CLK;
+	end process;
+
+
+STIMULUS: process
+
+	variable result : unsigned(31 downto 0);
+
+	procedure cmd_entry_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
+	begin
+	
+		index_in			<= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
+
+		entry_hi_in.vpn		<= vpn;
+		entry_hi_in.asid	<= asid;
+		entry_hi_in.g		<= g;
+
+		entry_lo_in.pfn		<= pfn;	
+		entry_lo_in.n		<= n;	
+		entry_lo_in.d		<= d;	
+		entry_lo_in.v		<= v;	
+
+		entry_we			<= '1';
+		wait until rising_edge(CLK);
+		entry_we			<= '0';
+	
+	end procedure cmd_entry_write;
+
+	procedure cpu_read(addr : unsigned) is
+	begin
+
+		cpu_we		<= '0';
+		cpu_addr	<= addr;
+		cpu_en		<= '1';
+		wait until rising_edge(CLK) and cpu_rdy = '1';
+		cpu_en		<= '0';
+		wait for 60*CLK_PERIOD;
+		wait until rising_edge(CLK);
+
+	end procedure cpu_read;
+
+	procedure cpu_write(addr, data : unsigned) is
+	begin
+
+		cpu_we		<= '1';
+		cpu_addr	<= addr;
+		cpu_din		<= data;
+		cpu_en		<= '1';
+		wait until rising_edge(CLK) and cpu_rdy = '1';
+		cpu_en		<= '0';
+		wait for 60*CLK_PERIOD;
+		wait until rising_edge(CLK);
+		
+	end procedure cpu_write;
+
+	begin
+
+		wait for 6*CLK_PERIOD;
+		RST <= '0';
+		wait for 60*CLK_PERIOD;
+		wait until rising_edge(CLK) and cpu_rdy = '1';
+
+		cmd_entry_write(0, "110000", X"0000_0", X"00DE_F", '0', '0', '0', '1');
+		cmd_entry_write(1, "110000", X"0000_1", X"11DE_F", '0', '0', '0', '1');
+		cmd_entry_write(2, "110000", X"0000_2", X"22DE_F", '0', '0', '0', '1');
+		cmd_entry_write(3, "110000", X"0000_3", X"33DE_F", '0', '0', '0', '1');
+		cmd_entry_write(4, "110000", X"0000_4", X"44DE_F", '0', '0', '0', '1');
+		cmd_entry_write(5, "110000", X"0000_5", X"55DE_F", '0', '0', '0', '1');
+		cmd_entry_write(6, "110000", X"0000_6", X"66DE_F", '0', '0', '0', '1');
+		cmd_entry_write(7, "110000", X"0000_7", X"77DE_F", '0', '0', '0', '1');
+		
+		cpu_read(X"BFC0_0200");
+		cpu_read(X"BFC0_0180");
+
+		cpu_read(X"8000_0204");
+		cpu_read(X"8000_0300");
+		cpu_read(X"8000_0304");
+		cpu_read(X"8000_0308");
+		
+		cpu_read(X"9000_0208");
+		cpu_read(X"9000_030C");
+		cpu_read(X"9100_0310");
+		cpu_read(X"9200_0314");
+
+		cpu_read(X"A000_020C");
+		cpu_read(X"A000_0318");
+		cpu_read(X"A100_031C");
+		cpu_read(X"A200_0320");
+		
+		cpu_read(X"B000_0210");
+		cpu_read(X"B000_0324");
+		cpu_read(X"B000_0328");
+		cpu_read(X"B000_032C");
+
+		cpu_read(X"0000_0400");
+		cpu_read(X"0000_1420");
+		cpu_read(X"0000_2440");
+		cpu_read(X"0000_3460");
+		cpu_read(X"0000_4480");
+		cpu_read(X"0000_54A0");
+		cpu_read(X"0000_64C0");
+		cpu_read(X"0000_74E0");
+		cpu_read(X"0000_8500");
+		cpu_read(X"0000_9520");
+		
+		cpu_read(X"0000_0400");
+		cpu_read(X"0000_1420");
+		cpu_read(X"0000_2440");
+		cpu_read(X"0000_3460");
+		cpu_read(X"0000_4480");
+		cpu_read(X"0000_54A0");
+		cpu_read(X"0000_64C0");
+		cpu_read(X"0000_74E0");
+		cpu_write(X"0000_0400", X"AAAA_AAAA");
+
+--		cmd_entry_write(0, "110000", X"0000_0", X"40DE_F", '0', '0', '1', '1');
+
+		cpu_read(X"0000_0400");
+
+		cpu_read(X"0000_0410");
+		cpu_read(X"0000_0404");
+		cpu_read(X"0000_0408");
+		cpu_write(X"0000_0404", X"5555_5555");
+		cpu_read(X"0000_0404");
+		cpu_read(X"0000_0400");
+
+	wait;
+	
+	end process;
+	
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_tlb.vhd b/lib/CPUs/MIPS/src/tb_mips_tlb.vhd
new file mode 100644
index 0000000..22dc78b
--- /dev/null
+++ b/lib/CPUs/MIPS/src/tb_mips_tlb.vhd
@@ -0,0 +1,211 @@
+LIBRARY ieee;
+use IEEE.STD_LOGIC_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+library work;
+use work.mips_types.all;
+use work.mips_util_pkg.all;
+
+ENTITY tb_tlb IS
+END tb_tlb;
+
+ARCHITECTURE behavior OF tb_tlb IS 
+
+	constant DATA_WIDTH			: integer := 32;
+	constant CLK_PERIOD			: time := 10 ns;
+
+	signal CLK_O			: std_logic := '1';
+	signal RST_O			: std_logic := '1';
+	signal ce				: std_logic := '1';
+
+	signal tlb_rdy				: std_logic;
+	
+	signal tlb_ctrl_in		: tlb_ctrl_in_t;
+	signal tlb_ctrl_out		: tlb_ctrl_out_t;
+	signal tlb_query_in		: tlb_query_in_t;
+	signal tlb_query_out	: tlb_query_out_t;
+
+
+BEGIN
+
+inst_uut : entity work.tlb
+	GENERIC MAP
+	(
+		NUM_ENTRIES			=> TLB_NUM_ENTRIES,
+		CACHE_KSEG1			=> false,
+		USE_TLB				=> true
+	)
+	PORT MAP
+	(
+		-- System signals
+		rst					=> RST_O,
+		clk					=> CLK_O,
+		ce					=> ce,
+
+		rdy					=> tlb_rdy,
+		
+		ctrl_in				=> tlb_ctrl_in,
+		ctrl_out			=> tlb_ctrl_out,
+
+		query_in			=> tlb_query_in,
+		query_out			=> tlb_query_out
+
+	);
+
+CLK_GEN: process
+	begin
+		wait for CLK_PERIOD/2;
+		CLK_O <= not CLK_O;
+	end process;
+
+STIMULUS: process
+
+	variable result : unsigned(31 downto 0);
+
+	procedure cmd_entry_write(index : integer; asid, vpn, pfn : unsigned; g, n, d, v : std_logic) is
+	begin
+	
+	tlb_ctrl_in.entry_wr_idx	<= to_unsigned(index, lg2(TLB_NUM_ENTRIES));
+	
+	tlb_ctrl_in.entry_hi.vpn	<= vpn;
+	tlb_ctrl_in.entry_hi.asid	<= asid;
+
+	tlb_ctrl_in.entry_lo.pfn	<= pfn;	
+	tlb_ctrl_in.entry_lo.g		<= g;
+	tlb_ctrl_in.entry_lo.n		<= n;	
+	tlb_ctrl_in.entry_lo.d		<= d;	
+	tlb_ctrl_in.entry_lo.v		<= v;	
+	
+	tlb_ctrl_in.entry_we		<= '1';
+	wait until rising_edge(CLK_O) and tlb_rdy = '1';
+	tlb_ctrl_in.entry_we		<= '0';
+	
+	end procedure cmd_entry_write;
+
+	procedure cmd_read_single(addr : unsigned) is
+	begin
+	
+	end procedure cmd_read_single;
+
+	begin
+
+		tlb_ctrl_in.entry_we	<= '0';
+		tlb_ctrl_in.entry_re	<= '0';
+		tlb_query_in.vld		<= '0';
+		tlb_query_in.write		<= '0';
+		tlb_query_in.vaddr		<= X"BFC0_CAFE";
+		
+		wait for 6*CLK_PERIOD;
+		RST_O <= '0';
+		wait for 60*CLK_PERIOD;
+		wait until rising_edge(CLK_O) and tlb_rdy = '1';
+
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '1';
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '0';
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '1';
+		tlb_query_in.vaddr <= X"9FC0_CAFE";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '0';
+
+		cmd_entry_write(0, "110000", X"0000_0", X"00DE_F", '0', '0', '0', '1');
+		cmd_entry_write(1, "110000", X"0000_1", X"01DE_F", '0', '0', '0', '1');
+		cmd_entry_write(2, "110000", X"0000_2", X"02DE_F", '0', '0', '0', '0');
+		cmd_entry_write(3, "110000", X"0000_3", X"43DE_F", '0', '0', '0', '1');
+		cmd_entry_write(4, "100000", X"0000_4", X"44DE_F", '0', '0', '0', '1');
+		cmd_entry_write(5, "110000", X"0000_5", X"65DE_F", '0', '0', '0', '1');
+		cmd_entry_write(6, "100000", X"0000_6", X"66DE_F", '1', '0', '0', '1');
+		cmd_entry_write(7, "110000", X"0000_7", X"67DE_F", '0', '0', '0', '1');
+		
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '1';
+
+		tlb_query_in.vaddr <= X"8000_BABE";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"8000_1234";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"8100_1234";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"8200_1234";
+		
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"9000_BABE";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"9000_1234";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"9100_1234";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"9200_1234";
+
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"A000_BABE";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"A000_1234";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"A100_1234";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"A200_1234";
+		
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"B000_BABE";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"B000_1234";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"B100_1234";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"B200_1234";
+
+
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= X"0000_0CAF";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vaddr <= tlb_query_in.vaddr + X"1000";
+
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '0';
+
+		cmd_entry_write(0, "110000", X"0000_0", X"40DE_F", '0', '0', '1', '1');
+
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '1';
+		tlb_query_in.vaddr <= X"0000_0CAF";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '0';
+
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '1';
+		tlb_query_in.write	<= '1';
+		tlb_query_in.vaddr <= X"0008_0CAF";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '0';
+
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '1';
+		tlb_query_in.write	<= '1';
+		tlb_query_in.vaddr <= X"0000_0CAF";
+		wait until rising_edge(CLK_O);
+		tlb_query_in.vld	<= '0';
+
+	wait;
+	
+	end process;
+	
+END;
diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd
index c044a61..1cfc94a 100644
--- a/lib/CPUs/MIPS/src/tb_mips_top.vhd
+++ b/lib/CPUs/MIPS/src/tb_mips_top.vhd
@@ -25,6 +25,7 @@
 LIBRARY ieee;
 use IEEE.STD_LOGIC_1164.ALL;
 USE ieee.numeric_std.ALL;
+USE std.textio.ALL;
 
 library work;
 use work.mips_types.all;
@@ -41,8 +42,10 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	constant CLK_PERIOD 			: time := 10 ns;
 	constant SRAM_ADDR_WIDTH		: integer := 17;		-- bits
 	constant FLASH_ADDR_WIDTH		: integer := 17;		-- bits
-	
-	signal debug				: chip_debug_t;
+	constant WITH_TLB				: boolean := true;
+	constant KSEG_01_TRANSLATED		: boolean := true;
+	signal debug					: chip_debug_t;
+	signal tb_fin					: STD_LOGIC := '0';
 
 	-- Master 
 	signal nmi					: STD_LOGIC := '0';
@@ -115,7 +118,43 @@ ARCHITECTURE behavior OF tb_mips_top IS
 	type word_array_t is array (natural range <>) of unsigned(31 downto 0);
 	signal sram_data : word_array_t(0 to 2**SRAM_ADDR_WIDTH-1);
 	signal flash_data : word_array_t(0 to 2**FLASH_ADDR_WIDTH-1);
+
+	subtype nibble_t is unsigned (3 downto 0);
 	
+	function to_character(x : nibble_t) return character is
+	type cnv_tbl_t is array (0 to 15) of character;
+	variable cnv_tbl : cnv_tbl_t := "0123456789ABCDEF";
+	variable result : character;
+	begin 
+		for i in nibble_t'low to nibble_t'high loop
+			result := '0';
+			if x(i) /= '0' and x(i) /= '1' then
+				result := 'X';
+			end if;			
+		end loop;
+
+		if result = '0' then
+			result := cnv_tbl(to_integer(x));
+		end if;
+
+		return result;
+	end to_character;
+	
+	
+	function to_string(x : word_t ) return string is
+	variable result : string (1 to 8);
+	variable j : integer := 32;
+	variable nibble : nibble_t;
+	begin
+		for i in 1 to 8 loop
+			nibble := x(j-1 downto j-4);
+			j := j - 4;
+			result(i) := to_character(nibble);
+		end loop;
+		return result;
+		
+	end to_string;
+
 BEGIN
 
 ------------------------------------------------------------------
@@ -128,6 +167,46 @@ CLK_GEN: process
 ------------------------------------------------------------------
 -- Memory mux
 ------------------------------------------------------------------
+--  rom_u        : Virtual = 0xBFC00000, Physical = 0x1FC00000
+--  rom_c        : Virtual = 0x9FC00000, Physical = 0x1FC00000
+
+--  ram_u        : Virtual = 0xA0000000, Physical = 0x00000000
+--  ram_c        : Virtual = 0x80000000, Physical = 0x00000000
+--  flash_u      : Virtual = 0xA4000000, Physical = 0x04000000
+--  flash_c      : Virtual = 0x88000000, Physical = 0x08000000
+--  io_u         : Virtual = 0xA8000000, Physical = 0x0C000000
+--  io_c         : Virtual = 0x88000000, Physical = 0x0C000000
+
+gen_mem_mux_translate:
+if KSEG_01_TRANSLATED = true generate
+mem_mux:
+	process(ADDR_O)
+	begin
+		mem_area			<= mem_dead;
+		flash_page_mode_en	<= '0';
+		if ADDR_O(31 downto 28) = X"0" then
+			if    ADDR_O(27 downto 26) = "00" then
+				mem_area	<= mem_sram;
+			elsif ADDR_O(27 downto 26) = "01" then
+				mem_area			<= mem_flash;
+			elsif ADDR_O(27 downto 26) = "10" then
+				mem_area			<= mem_flash;
+				flash_page_mode_en	<= '1';
+			elsif ADDR_O(27 downto 26) =  "11" then
+				if ADDR_O(18 downto 16) = "000" then
+					mem_area	<= mem_gpio;
+				elsif ADDR_O(18 downto 16) = "001" then
+					mem_area	<= mem_uart;
+				end if;	
+			end if;
+		elsif (ADDR_O(31 downto 28) = X"1" and ADDR_O(15) = '0') then
+			mem_area	<= mem_rom;
+		end if;
+	end process;	
+end generate;
+
+gen_mem_mux_non_translate:
+if KSEG_01_TRANSLATED = false generate
 mem_mux:
 	process(ADDR_O)
 	begin
@@ -152,6 +231,7 @@ mem_mux:
 			mem_area	<= mem_sram;
 		end if;
 	end process;	
+end generate;
 
 signal_mux:
 	process(mem_area, CYC_O)
@@ -199,8 +279,9 @@ signal_mux:
 uut: entity work.mips_top
 	GENERIC MAP
 	(
-		icache_size		=> 1024,	-- words
-		dcache_size		=> 1024		-- words
+		icache_size		=> 256,		-- words
+		dcache_size		=> 256,		-- words
+		WITH_TLB		=> WITH_TLB
 	)
 	PORT MAP
 	(
@@ -394,14 +475,16 @@ SRAM_WRITE:
 			end if;	
 		end if;	
 	end process;
-
+	
 ------------------------------------------------------------------
 FLASH_READ:
 	process(rst, flash_cs_n, flash_oe_n, flash_a)
 	type file_t is file of integer;
---	file load_flash : file_t open read_mode is "ucb.elf.flash.bin";
-	file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
---	file load_flash : file_t open read_mode is "test_dcache.flash.bin";
+	file load_flash : file_t open read_mode is "test_tlb_sim.elf.flash.bin";
+--	file load_flash : file_t open read_mode is "test_exception_sim.elf.flash.bin";
+--	file load_flash : file_t open read_mode is "test_timer.elf.flash.bin";
+--	file load_flash : file_t open read_mode is "test_dcache_sim.elf.flash.bin";
+--	file load_flash : file_t open read_mode is "dhry.flash.bin";
 	variable instr : integer;
 	variable index : natural;
 	variable temp : signed(31 downto 0);
@@ -437,6 +520,62 @@ FLASH_READ:
 		end if;	
 	end process;
 
+------------------------------------------------------------------
+icache_trace_write:
+	process(clk)
+	type file_t is file of string;
+	file f : file_t open write_mode is "icache_trace.dat";
+	variable file_opened : std_logic;
+	variable saddr : string(1 to 8);
+	variable sdata : string(1 to 8);
+	begin
+		
+		if rising_edge(clk) then
+			if rst = '1' then
+				file_opened := '1';
+			elsif file_opened = '1' then
+				if debug.imem_din_vld = '1' then
+					saddr := to_string(debug.imem_addr_reg);
+					sdata := to_string(debug.imem_din_reg);
+					write(f, saddr & " : " & sdata & CR);
+				end if;
+			else
+				file_close(f);
+				file_opened := '0';
+			end if;
+		end if;
+	end process;
+
+------------------------------------------------------------------
+dcache_trace_write:
+	process(clk)
+	type file_t is file of string;
+	file f : file_t open write_mode is "dcache_trace.dat";
+	variable file_opened : std_logic;
+	variable saddr : string(1 to 8);
+	variable sdata : string(1 to 8);
+	begin
+		
+		if rising_edge(clk) then
+			if rst = '1' then
+				file_opened := '1';
+			elsif file_opened = '1' then
+				if debug.dmem_din_vld = '1' then
+					saddr := to_string(debug.dmem_addr_reg);
+					sdata := to_string(debug.dmem_din_reg);
+					write(f, saddr & " : " & sdata & " R" & CR);
+				elsif debug.dmem_dout_vld = '1' then
+					saddr := to_string(debug.dmem_addr_reg);
+					sdata := to_string(debug.dmem_dout_reg);
+					write(f, saddr & " : " & sdata & " W" & CR);
+				end if;
+			else
+				file_close(f);
+				file_opened := '0';
+			end if;
+		end if;
+	end process;
+
 ------------------------------------------------------------------
 STIMULUS: process
 
@@ -446,12 +585,13 @@ STIMULUS: process
 		wait for 3*CLK_PERIOD;
 		wait until rising_edge(clk);
 		rst <= '0';
-		wait for 778254*CLK_PERIOD;
+
+		wait for 1200000*CLK_PERIOD;
+
 		wait until rising_edge(clk);
-		nmi <= '0';
-		wait for 3000*CLK_PERIOD;
+		tb_fin	<= '1';
 		wait until rising_edge(clk);
-		nmi <= '0';
+		tb_fin	<= '0';
 
 		wait;