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[JUART]

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- renamed ports

git-svn-id: http://moon:8086/svn/vhdl/trunk@1352 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2016-12-20 19:14:21 +00:00
parent 82a500a99b
commit e4da80768a
2 changed files with 27 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/uart/sim/tb_juart_tx_rx.wdo
+6 -6
View File
@@ -3,13 +3,13 @@ quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /tb_juart_tx_rx/rst
add wave -noupdate -format Logic /tb_juart_tx_rx/clk
add wave -noupdate -format Logic /tb_juart_tx_rx/en_16_x_baud
add wave -noupdate -format Logic /tb_juart_tx_rx/send_character
add wave -noupdate -format Logic /tb_juart_tx_rx/serial_out
add wave -noupdate -format Logic /tb_juart_tx_rx/tx_we
add wave -noupdate -format Logic /tb_juart_tx_rx/ser_out
add wave -noupdate -format Logic /tb_juart_tx_rx/tx_complete
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_in
add wave -noupdate -format Logic /tb_juart_tx_rx/serial_in
add wave -noupdate -format Logic /tb_juart_tx_rx/data_strobe
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_out
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/tx_din
add wave -noupdate -format Logic /tb_juart_tx_rx/ser_in
add wave -noupdate -format Logic /tb_juart_tx_rx/rx_dout_vld
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/rx_dout
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_rx
add wave -noupdate -format Literal -radix hexadecimal /tb_juart_tx_rx/data_tx
TreeUpdate [SetDefaultTree]
lib/uart/tb_juart_tx_rx.vhd
+21 -21
View File
@@ -40,15 +40,15 @@ architecture behave of tb_juart_tx_rx is
signal en_16_x_baud : std_logic := '1';
-- TX
signal send_character : std_logic := '0';
signal serial_out : std_logic;
signal tx_we : std_logic := '0';
signal ser_out : std_logic;
signal Tx_complete : std_logic;
signal data_in : unsigned(7 downto 0) := (others => '0');
signal tx_din : unsigned(7 downto 0) := (others => '0');
-- RX
signal serial_in : std_logic := '1';
signal data_strobe : std_logic;
signal data_out : unsigned(7 downto 0);
signal ser_in : std_logic := '1';
signal rx_dout_vld : std_logic;
signal rx_dout : unsigned(7 downto 0);
-- Others
signal baud_count : unsigned(15 downto 0);
@@ -58,18 +58,18 @@ architecture behave of tb_juart_tx_rx is
begin
serial_in <= serial_out;
ser_in <= ser_out;
inst_juart_tx : entity work.juart_tx
PORT MAP
(
rst => rst,
clk => clk,
we => tx_we,
din => tx_din,
en_16_x_baud => en_16_x_baud,
send_character => send_character,
Tx_complete => Tx_complete,
data_in => data_in,
serial_out => serial_out
ser_out => ser_out
);
inst_juart_rx : entity work.juart_rx
@@ -78,9 +78,9 @@ inst_juart_rx : entity work.juart_rx
rst => rst,
clk => clk,
en_16_x_baud => en_16_x_baud,
data_strobe => data_strobe,
data_out => data_out,
serial_in => serial_in
dout_vld => rx_dout_vld,
dout => rx_dout,
ser_in => ser_in
);
CLK_GEN: process
@@ -91,15 +91,15 @@ CLK_GEN: process
PROC_DATAREG_RX: process
begin
wait until rising_edge(clk) and data_strobe = '1';
data_rx <= data_out;
assert data_out = data_tx report "Data mismatch" severity failure;
wait until rising_edge(clk) and rx_dout_vld = '1';
data_rx <= rx_dout;
assert rx_dout = data_tx report "Data mismatch" severity failure;
end process;
PROC_DATAREG_TX: process
begin
wait until rising_edge(clk) and send_character = '1';
data_tx <= data_in;
wait until rising_edge(clk) and tx_we = '1';
data_tx <= tx_din;
end process;
baud_timer:
@@ -132,10 +132,10 @@ STIMULUS: process
for i in 0 to 255 loop
wait until rising_edge(clk) and Tx_complete = '1';
data_in <= to_unsigned(i, 8);
send_character <= '1';
tx_din <= to_unsigned(i, 8);
tx_we <= '1';
wait until rising_edge(clk) and Tx_complete = '0';
send_character <= '0';
tx_we <= '0';
end loop;
wait;