diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
index 940d559..8b42cfc 100644
--- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
+++ b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd
@@ -82,16 +82,6 @@ architecture Behavioral of pipeline is
 	);
 	END COMPONENT;
 
---------------------------------------------------------------------------
-	COMPONENT idecode_rom is
-	Port 
-	(
-		nop			: in  std_logic;
-		inst_in		: in  word_t;
-		ctrl_out	: out ctrl_lines_t
-	);
-	END COMPONENT;
-
 --------------------------------------------------------------------------
 	COMPONENT shifter is
 	Generic 
@@ -167,7 +157,6 @@ architecture Behavioral of pipeline is
 	signal sdu				: sdu_t;
 	signal reg_a			: word_t;
 	signal reg_b			: word_t;
-	signal ctrl_lines		: ctrl_lines_t;
 	signal branch_ce		: STD_LOGIC;
 	signal cpu_run			: STD_LOGIC;
 	signal alu_result		: word_t;
@@ -182,6 +171,7 @@ architecture Behavioral of pipeline is
 	signal bcu_op_b			: word_t;
 	signal bcu_flags		: bcu_flags_t;
 	signal vaddr			: word_t;
+	signal dmem_src			: word_t;
 	
 	attribute ram_style : string;
 	
@@ -226,7 +216,8 @@ begin
 	c0_ctrl_out.events		<= MEM_stage.events;
 	cop_ir					<= ID_stage.IR;
 	cop_ir_en				<= ID_stage.ctrl.cop_instr_en;
-	
+	cop_dout				<= MEM_stage.data;
+
 --------------------------------------------------------------------------
 -- Muldiv
 --------------------------------------------------------------------------
@@ -345,7 +336,7 @@ proc_stage_branch:
 	ID_stage.shamt				<= extract_shamt(ID_stage.IR);
 	ID_stage.reg_a_rptr			<= extract_rs(ID_stage.IR);
 	ID_stage.reg_b_rptr			<= extract_rt(ID_stage.IR);
-	ID_stage.ctrl				<= ctrl_lines;
+	ID_stage.ctrl				<= opcode_ctrl_lines(ID_stage.IR) when sdu.ID_nop = '0' else ctrl_lines_default;
 	ID_stage.reg_write			<= ID_stage.ctrl.reg_write;
 	ID_stage.cop_read			<= cop_reg_rd;
 	ID_stage.epc				<= pc.last;
@@ -443,14 +434,6 @@ proc_imm_mux:
 	end process;
 
 --------------------------------------------------------------------------
-inst_idecode_rom: idecode_rom
-	PORT MAP
-	(
-		nop			=> sdu.ID_nop,
-		inst_in		=> ID_stage.IR,
-		ctrl_out	=> ctrl_lines
-	);
-
 inst_reg_dual: reg_dual
 	GENERIC MAP
 	(
@@ -580,11 +563,11 @@ proc_stage_DMEM_ADDR:
 			end if;
 		end if;
 	end process;
+	dmem_src	<= cop_din when EX_stage.ctrl.cop_instr_en = '1' else EX_stage.reg_b;
 	dmem_be		<= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_en, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.shift_byp) after 1 ns;
 	dmem_we		<= EX_stage.ctrl.dmem_we;
-	dmem_dout	<= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
+	dmem_dout	<= store_shift(dmem_src, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns;
 	dmem_addr	<= EX_stage.va;
-	cop_dout	<= EX_stage.reg_b;
 	EX_stage.events			<= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in;
 	EX_stage.exc			<= event_is_active(EX_stage.events);
 	
@@ -753,13 +736,13 @@ proc_stage_MEM_n:
 				MEM_stage.pa_off		<= EX_stage.pa_off;
 				MEM_stage.reg_wptr		<= EX_stage.reg_wptr;
 				MEM_stage.nop			<= sdu.MEM_nop;
-				if EX_stage.ctrl.dmem_en = '1' then
-					MEM_stage.ex_result		<= EX_stage.reg_b;
-				else
-					MEM_stage.ex_result		<= EX_stage.result;
+				MEM_stage.ex_result		<= EX_stage.reg_b;
+				if EX_stage.ctrl.cop_instr_en = '1' then
 					if EX_stage.cop_read = '1' then
 						MEM_stage.ex_result	<= cop_din;
 					end if;	
+				elsif EX_stage.ctrl.dmem_en = '0' then
+					MEM_stage.ex_result		<= EX_stage.result;
 				end if;	
 				if sdu.MEM_nop = '1' then
 					MEM_stage.op		<= NOP;