From e2da4a51083174ceb6a61163c440eb635c4d7d7a Mon Sep 17 00:00:00 2001 From: Jens Ahrensfeld Date: Sat, 8 Aug 2009 12:38:22 +0000 Subject: [PATCH] update Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@482 cc03376c-175c-47c8-b038-4cd826a8556b --- lib/CPUs/MIPS/dist/tmpl/notes.txt | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/lib/CPUs/MIPS/dist/tmpl/notes.txt b/lib/CPUs/MIPS/dist/tmpl/notes.txt index 7174aac..e059343 100644 --- a/lib/CPUs/MIPS/dist/tmpl/notes.txt +++ b/lib/CPUs/MIPS/dist/tmpl/notes.txt @@ -1,3 +1,34 @@ +----------------------------------------------------------------- +Changes in release 12 +----------------------------------------------------------------- +- reworked GCC-toolchain: Valid mips*-elf-binaries are now compiled and linked + using a single mips*-elf-gcc command. + To use: Copy $THIS_REALEASE/bsp/toolchain/specs to $MIPS_GCC_PREFIX/lib/gcc/mipsel-elf/$GCC_VERSION/, + and see bsp/examples/Makefile gcc usage + GCC-provided crt*-functions are now called without problems. + In summary: The toolchain is now more compliant to the intentional use of GCC. +- mips_biu.vhd: Addresses 0xA0000000..0xBFFFFFFF are now un-dcached for memory-mapped I/O, + which is now compliant to literature. +- gpio_wb.vhd: Timer reset is now removed. This helps to keep current time in case of CPU reset. +- new bsp-example source: gunzip +- updated drawing 'mips_jbus_timing.pdf' +- added drawing 'memory_map.pdf' +- moved COP0 from mips_pipeline.vhd to mips_top.vhd. Created new cop-interface for later COPz connection. +- added I/D-cache info (size and linesize) to upper 16 bits of PrID-Register. + Example of reading cache info is done in bsp/examples/testbench::PrintCPUinfo() +- simplified instruction decoder in mips_instr.vhd. Now there are less warnings during synthesis. + Removed idecode_rom.vhd from project as consequence. +- added cop0 instructions to invalidate I-cache and D-Cache +- added copz instructions lwcz and swcz +- gpio_wb.vhd: added 32 bit timer with interrupt and auto reload +- added debugger in libsys. New files are mipsdis.c/h and dbg.c/h +- exception handlers can now be registered to any exception type +- bugfix: cop0 registers were not written during exception commit. Cop registers now behave like general registers. +- added pin 'eb' to mips_top.vhd to select CPU-endianess at reset time (eb = 0 : little-endian, eb = 1 : big-endian) +- Status register bit 'RE'= 1 (bit 25) reverses endianess in user-mode +- Status register bit 'TS' (TLB Shutdown, bit 21) is tied high to indicate the absence of a MMU. +- uart_wb.vhd: added interrupt enable + ----------------------------------------------------------------- Changes in release 11 -----------------------------------------------------------------