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- added bus input FIFO

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git-svn-id: http://moon:8086/svn/vhdl/trunk@917 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2010-05-17 08:33:50 +00:00
parent ec301f5710
commit e28d864e40
1 changed files with 92 additions and 52 deletions
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lib/VGA_ctrl/src/vga_frontend64.vhd
+92 -52
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@@ -236,25 +236,35 @@ architecture Behavioral of vga_frontend64 is
signal odd_pixel : unsigned(NextExpBaseTwo(tsvga.ts_h.ncyc_scan)-1 downto 0);
-- Bus FIFO
signal bus_fifo_din : unsigned(104 downto 0);
signal bus_fifo_dout : unsigned(104 downto 0);
signal bus_fifo_re : std_logic;
signal bus_fifo_we : std_logic;
signal bus_fifo_full : std_logic;
signal bus_fifo_empty : std_logic;
signal bus_fifo_rdy : std_logic;
-- Bus output FIFO
signal busout_fifo_din : unsigned(104 downto 0);
signal busout_fifo_dout : unsigned(104 downto 0);
signal busout_fifo_re : std_logic;
signal busout_fifo_we : std_logic;
signal busout_fifo_full : std_logic;
signal busout_fifo_empty : std_logic;
signal busout_fifo_rdy : std_logic;
alias bus_fifo_addr_in is bus_fifo_din(31 downto 0);
alias bus_fifo_data_in is bus_fifo_din(95 downto 32);
alias bus_fifo_sel_in is bus_fifo_din(103 downto 96);
alias bus_fifo_we_in is bus_fifo_din(104);
alias busout_fifo_addr_in is busout_fifo_din(31 downto 0);
alias busout_fifo_data_in is busout_fifo_din(95 downto 32);
alias busout_fifo_sel_in is busout_fifo_din(103 downto 96);
alias busout_fifo_we_in is busout_fifo_din(104);
alias bus_fifo_addr_out is bus_fifo_dout(31 downto 0);
alias bus_fifo_data_out is bus_fifo_dout(95 downto 32);
alias bus_fifo_sel_out is bus_fifo_dout(103 downto 96);
alias bus_fifo_we_out is bus_fifo_dout(104);
alias busout_fifo_addr_out is busout_fifo_dout(31 downto 0);
alias busout_fifo_data_out is busout_fifo_dout(95 downto 32);
alias busout_fifo_sel_out is busout_fifo_dout(103 downto 96);
alias busout_fifo_we_out is busout_fifo_dout(104);
-- Bus input FIFO
signal busin_fifo_din : unsigned(63 downto 0);
signal busin_fifo_dout : unsigned(63 downto 0);
signal busin_fifo_re : std_logic;
signal busin_fifo_we : std_logic;
signal busin_fifo_full : std_logic;
signal busin_fifo_empty : std_logic;
signal busin_fifo_rdy : std_logic;
signal busin_fifo_dout_vld : std_logic;
type vm_state_t is (init, rdy, scan_bus_request, scan_bus_read, blit_src_bus_request, blit_src_bus_read, blit_dst_prime_pipe, blit_dst_bus_request, bus_fin);
signal s, sn : vm_state_t;
@@ -357,12 +367,12 @@ inst_vga_backend : entity work.vga_backend
);
SRDY_O <= CYC_I; -- and cg_rdy;
MRDY_O <= not fifo_full;
STB_O <= not bus_fifo_empty;
ADDR_O <= bus_fifo_addr_out;
MDAT_O <= bus_fifo_data_out;
SEL_O <= bus_fifo_sel_out;
WE_O <= bus_fifo_we_out;
MRDY_O <= busin_fifo_rdy; --not fifo_full;
STB_O <= not busout_fifo_empty;
ADDR_O <= busout_fifo_addr_out;
MDAT_O <= busout_fifo_data_out;
SEL_O <= busout_fifo_sel_out;
WE_O <= busout_fifo_we_out;
odd_pixel <= to_unsigned(stat_hpos, odd_pixel'length);
ctrl_scan_en <= '1';
@@ -397,42 +407,71 @@ inst_linefifo: entity work.fifo_async
);
fifo_color_in <= MDAT_I;
fifo_color_in <= busin_fifo_dout;
fifo_color_re <= stat_scan and odd_pixel(0);
fifo_color_we <= ACK_I and CYC_O_scan; -- TODO:
fifo_color_we <= busin_fifo_dout_vld and CYC_O_scan; -- TODO:
-- Instantiate synchronous FIFO
inst_bus_fifo: entity work.fifo_sync
-- Bus input FIFO
inst_busin_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 2,
data_width => 105,
data_width => busin_fifo_din'length,
do_last_read_update => true
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => busin_fifo_we,
re => busin_fifo_re,
fifo_full => busin_fifo_full,
fifo_empty => busin_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => busin_fifo_din,
data_r => busin_fifo_dout
);
busin_fifo_rdy <= not busin_fifo_full;
busin_fifo_din <= MDAT_I;
busin_fifo_we <= ACK_I and bus_cycle_en and bus_read_en;
busin_fifo_dout_vld <= not busin_fifo_empty;
busin_fifo_re <= not fifo_full when CYC_O_scan = '1' else blit_src_we;
-- Bus output FIFO
inst_busout_fifo: entity work.fifo_sync
GENERIC MAP
(
addr_width => 2,
data_width => busout_fifo_din'length,
do_last_read_update => false
)
PORT MAP
(
rst => RST_I,
clk => CLK_I,
we => bus_fifo_we,
re => bus_fifo_re,
fifo_full => bus_fifo_full,
fifo_empty => bus_fifo_empty,
we => busout_fifo_we,
re => busout_fifo_re,
fifo_full => busout_fifo_full,
fifo_empty => busout_fifo_empty,
fifo_afull => open,
fifo_aempty => open,
data_w => bus_fifo_din,
data_r => bus_fifo_dout
data_w => busout_fifo_din,
data_r => busout_fifo_dout
);
bus_fifo_rdy <= not bus_fifo_full;
bus_fifo_re <= not bus_fifo_empty and SRDY_I;
bus_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst);
bus_fifo_data_in <= blit_dst_reg;
bus_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
busout_fifo_rdy <= not busout_fifo_full;
busout_fifo_re <= not busout_fifo_empty and SRDY_I;
busout_fifo_we <= bus_cycle_en and (STB_O_scan or STB_O_blit_src or STB_O_blit_dst);
busout_fifo_data_in <= blit_dst_reg;
busout_fifo_addr_in <= ADDR_O_blit_src when CYC_O_blit_src = '1' else
ADDR_O_blit_dst when CYC_O_blit_dst = '1' else
ADDR_O_scan;
bus_fifo_sel_in <= blit_dst_be when CYC_O_blit_dst = '1' else (others => '1');
bus_fifo_we_in <= CYC_O_blit_dst;
busout_fifo_sel_in <= blit_dst_be when CYC_O_blit_dst = '1' else (others => '1');
busout_fifo_we_in <= CYC_O_blit_dst;
CYC_O <= bus_cycle_en;
------------------------------------------------------------------------------------
-- VGA master FSM
vga_master_next:
process(CLK_I)
begin
@@ -446,7 +485,7 @@ vga_master_next:
end process;
vga_master:
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, SRDY_I, ACK_I, bus_read_fin, bus_fifo_rdy, bus_fifo_empty, blit_chunk_cnt, blitfifo_src_empty, blit_dst_vld, blit_src_finish, blit_dst_finish, blit_const_color_en, blitfifo_src_full)
process(s, stat_vga_rdy, vga_scan_dma_en2, fifo_almost_empty, fifo_almost_full, bus_read_fin, busout_fifo_rdy, busout_fifo_empty, blit_chunk_cnt, blitfifo_src_empty, blit_dst_vld, blit_src_finish, blit_const_color_en)
begin
CYC_O_scan <= '0';
@@ -540,7 +579,7 @@ vga_master:
when bus_fin =>
bus_cycle_en <= '1';
if bus_fifo_empty = '1' then
if busout_fifo_empty = '1' then
sn <= rdy;
end if;
@@ -550,13 +589,14 @@ vga_master:
end case;
end process;
------------------------------------------------------------------------------------
proc_bus_request_counter:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
request_cnt <= (others => '0');
elsif request_en = '1' and bus_fifo_rdy = '1' then
elsif request_en = '1' and busout_fifo_rdy = '1' then
request_cnt <= request_cnt + 1;
end if;
end if;
@@ -568,7 +608,7 @@ proc_bus_read_counter:
if rising_edge(CLK_I) then
if request_cnt_rst = '1' then
read_cnt <= (others => '0');
elsif bus_read_en = '1' and ACK_I = '1' then
elsif busin_fifo_dout_vld = '1' then
read_cnt <= read_cnt + 1;
end if;
end if;
@@ -591,7 +631,7 @@ proc_blit_chunk_counter:
if rising_edge(CLK_I) then
if blit_chunk_cnt_rst = '1' then
blit_chunk_cnt <= BLIT_CHUNK_SIZE-1;
elsif blit_chunk_cnt_en = '1' and bus_fifo_rdy = '1' then
elsif blit_chunk_cnt_en = '1' and busout_fifo_rdy = '1' then
if blit_chunk_cnt /= 0 then
blit_chunk_cnt <= blit_chunk_cnt - 1;
end if;
@@ -612,7 +652,7 @@ proc_scan_addr:
if vga_scan_dma_en2 = '0' then
pixel_cnt <= 0;
front <= host_fb_front;
elsif STB_O_scan = '1' and bus_fifo_rdy = '1' then
elsif STB_O_scan = '1' and busout_fifo_rdy = '1' then
if pixel_cnt /= MAX_REQUEST_CNT/2-1 then
pixel_cnt <= pixel_cnt + 1;
else
@@ -641,14 +681,14 @@ inst_align_src : entity work.align
eb => '1',
offset => blit_src_addr,
din_vld => blit_src_we,
din => MDAT_I,
din => busin_fifo_dout,
dout_vld => blit_src_reg_vld,
dout => blit_src_reg,
byte_en => open
);
blit_src_we <= ACK_I and CYC_O_blit_src; -- TODO:
blit_src_we <= busin_fifo_dout_vld and CYC_O_blit_src; -- TODO:
blit_src_re <= not blitfifo_src_full; -- TODO:
proc_blit_src_counter:
@@ -728,7 +768,7 @@ proc_blit_addr_src:
if blit_src_addr (2 downto 0) /= "000" then
blit_src_do_extra <= not blit_const_color_en;
end if;
elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and bus_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then
elsif blit_src_finish = '0' and ((STB_O_blit_src = '1' and busout_fifo_rdy = '1') or (blit_const_color_en = '1' and blitfifo_src_full = '0')) then
blit_src_offset <= blit_src_offset + 8;
if blit_src_cnt_x /= blit_nx then
blit_src_cnt_x <= blit_src_cnt_x + 1;
@@ -779,7 +819,7 @@ inst_align_dst : entity work.align
blit_dst_we <= not blitfifo_src_empty;
blit_dst_re <= CYC_O_blit_dst and bus_fifo_rdy and not blit_dst_last;
blit_dst_re <= CYC_O_blit_dst and busout_fifo_rdy and not blit_dst_last;
blit_dst_vld <= blit_dst_reg_vld or blit_dst_last;
---------------------------------------------------------------------------------
@@ -803,7 +843,7 @@ proc_blit_addr_dst:
blit_dst_unaligned <= '1';
blit_dst_do_extra <= '1';
end if;
elsif blit_dst_finish = '0' and (STB_O_blit_dst = '1' and bus_fifo_rdy = '1') then
elsif blit_dst_finish = '0' and (STB_O_blit_dst = '1' and busout_fifo_rdy = '1') then
blit_dst_first <= blit_dst_last;
blit_dst_last <= '0';
blit_dst_offset <= blit_dst_offset + 8;