diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd
index ae7c360..ab4aabb 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb32.vhd
@@ -35,7 +35,8 @@ entity ctrl_ddr_wb32 is
 		BURST_LEN		: natural	:= 2;
 		F_SYSCLK		: real		:= 100.0;
 		F_SDRCLK	 	: real		:= 100.0;
-		FIFO_DEPTH		: integer	:= 4
+		FIFO_DEPTH		: integer	:= 4;
+		TPD_BOARD_SIM	: time		:= 0 ns
 	);
 	Port
 	(
@@ -120,7 +121,8 @@ begin
 	inst_sdram_phy : entity work.sdram_phy
 	Generic map
 	(
-		F_SDRCLK		=> F_SDRCLK
+		F_SDRCLK		=> F_SDRCLK,
+		TPD_BOARD_SIM	=> TPD_BOARD_SIM
 	)
 	Port map
 	(
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd
index c772380..3c9c227 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb32.vhd
@@ -34,6 +34,7 @@ end;
 architecture struct of tb_ctrl_ddr_wb32 is
 
 	constant CLK_PERIOD		: time := 10 ns;
+	constant TPD_BOARD_SIM	: time := 1 ns;
 	constant SDCLK_PERIOD	: time := 7.5 ns;
 	constant BURST_LEN		: natural := 2;
 
@@ -106,7 +107,7 @@ begin
 		end if;
 	end process;
 	
-	sdclk_fb	<= part_clk_p after 1 ns;
+	sdclk_fb	<= part_clk_p after TPD_BOARD_SIM;
 	
 	-- DDR SDRAM Controller Core
 	uut : entity work.ctrl_ddr_wb32
@@ -115,7 +116,8 @@ begin
 		BURST_LEN		=> BURST_LEN,
 		F_SYSCLK	 	=> 100.000,
 		F_SDRCLK	 	=> 133.333,
-		FIFO_DEPTH		=> 4
+		FIFO_DEPTH		=> 4,
+		TPD_BOARD_SIM	=> TPD_BOARD_SIM
 	)
 	PORT MAP
 	(
diff --git a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
index 2fa2271..c3b1ef9 100644
--- a/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
+++ b/lib/SDRAM/ddr_sdr_v1_5/src/tb_ctrl_ddr_wb64.vhd
@@ -110,7 +110,7 @@ begin
 		end if;
 	end process;
 	
-	sdclk_fb	<= part_clk_p;
+	sdclk_fb	<= part_clk_p after TPD_BOARD_SIM;
 
 	DAT_O	<= X"DEADBEEF" & sddat;
 	SEL_O	<= "0000" & sdsel;