- initial version
git-svn-id: http://moon:8086/svn/vhdl/trunk@1073 cc03376c-175c-47c8-b038-4cd826a8556b
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-- --------------------------------------------------------------------
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--
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-- Title : std_logic_1164 multi-value logic system
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-- Library : This package shall be compiled into a library
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-- : symbolically named IEEE.
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-- :
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-- Developers: IEEE model standards group (par 1164)
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-- Purpose : This packages defines a standard for designers
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-- : to use in describing the interconnection data types
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-- : used in vhdl modeling.
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-- :
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-- Limitation: The logic system defined in this package may
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-- : be insufficient for modeling switched transistors,
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-- : since such a requirement is out of the scope of this
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-- : effort. Furthermore, mathematics, primitives,
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-- : timing standards, etc. are considered orthogonal
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-- : issues as it relates to this package and are therefore
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-- : beyond the scope of this effort.
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-- :
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-- Note : No declarations or definitions shall be included in,
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-- : or excluded from this package. The "package declaration"
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-- : defines the types, subtypes and declarations of
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-- : std_logic_1164. The std_logic_1164 package body shall be
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-- : considered the formal definition of the semantics of
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-- : this package. Tool developers may choose to implement
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-- : the package body in the most efficient manner available
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-- : to them.
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-- :
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-- --------------------------------------------------------------------
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-- modification history :
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-- --------------------------------------------------------------------
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-- version | mod. date:|
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-- v4.200 | 01/02/92 |
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-- --------------------------------------------------------------------
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PACKAGE std_logic_1164 IS
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-------------------------------------------------------------------
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-- logic state system (unresolved)
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-------------------------------------------------------------------
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TYPE std_ulogic IS ( 'U', -- Uninitialized
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'X', -- Forcing Unknown
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'0', -- Forcing 0
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'1', -- Forcing 1
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'Z', -- High Impedance
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'W', -- Weak Unknown
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'L', -- Weak 0
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'H', -- Weak 1
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'-' -- Don't care
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);
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-------------------------------------------------------------------
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-- unconstrained array of std_ulogic for use with the resolution function
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-------------------------------------------------------------------
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TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic;
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-------------------------------------------------------------------
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-- resolution function
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-------------------------------------------------------------------
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FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic;
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-------------------------------------------------------------------
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-- *** industry standard logic type ***
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-------------------------------------------------------------------
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SUBTYPE std_logic IS resolved std_ulogic;
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-------------------------------------------------------------------
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-- unconstrained array of std_logic for use in declaring signal arrays
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-------------------------------------------------------------------
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TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic;
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-------------------------------------------------------------------
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-- common subtypes
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-------------------------------------------------------------------
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SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1')
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SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z')
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SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')
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SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')
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-------------------------------------------------------------------
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-- overloaded logical operators
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-------------------------------------------------------------------
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FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
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FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
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FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
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FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
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FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01;
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function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01;
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FUNCTION "not" ( l : std_ulogic ) RETURN UX01;
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-------------------------------------------------------------------
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-- vectorized overloaded logical operators
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-------------------------------------------------------------------
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FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
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FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
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FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
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FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
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FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector;
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-- -----------------------------------------------------------------------
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-- Note : The declaration and implementation of the "xnor" function is
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-- specifically commented until at which time the VHDL language has been
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-- officially adopted as containing such a function. At such a point,
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-- the following comments may be removed along with this notice without
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-- further "official" ballotting of this std_logic_1164 package. It is
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-- the intent of this effort to provide such a function once it becomes
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-- available in the VHDL standard.
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-- -----------------------------------------------------------------------
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function "xnor" ( l, r : std_logic_vector ) return std_logic_vector;
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function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector;
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FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;
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-------------------------------------------------------------------
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-- conversion functions
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-------------------------------------------------------------------
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FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0')
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RETURN BIT;
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FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0')
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RETURN BIT_VECTOR;
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FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0')
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RETURN BIT_VECTOR;
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FUNCTION To_StdULogic (b : BIT ) RETURN std_ulogic;
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FUNCTION To_StdLogicVector (b : BIT_VECTOR ) RETURN std_logic_vector;
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FUNCTION To_StdLogicVector (s : std_ulogic_vector) RETURN std_logic_vector;
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FUNCTION To_StdULogicVector(b : BIT_VECTOR ) RETURN std_ulogic_vector;
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FUNCTION To_StdULogicVector(s : std_logic_vector) RETURN std_ulogic_vector;
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-------------------------------------------------------------------
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-- strength strippers and type convertors
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-------------------------------------------------------------------
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FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
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FUNCTION To_X01 ( s : std_ulogic ) RETURN X01;
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FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
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FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
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FUNCTION To_X01 ( b : BIT ) RETURN X01;
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FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
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FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z;
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FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector;
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FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
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FUNCTION To_X01Z ( b : BIT ) RETURN X01Z;
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FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector;
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FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector;
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FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01;
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FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector;
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FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector;
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FUNCTION To_UX01 ( b : BIT ) RETURN UX01;
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-------------------------------------------------------------------
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-- edge detection
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-------------------------------------------------------------------
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FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
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FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;
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-------------------------------------------------------------------
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-- object contains an unknown
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-------------------------------------------------------------------
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FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN;
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FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN;
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FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN;
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END std_logic_1164;
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