jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

- m�nor changes

Browse Source 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@973 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2013-05-27 21:31:22 +00:00
parent 6147fe66e3
commit e138bc1259
4 changed files with 17 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/JBUS/src/dma.vhd
+4 -4
View File
@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dma.vhd,v 1.1 2013-05-27 11:15:58 jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/dma.vhd,v 1.2 2013-05-27 21:31:15 jens Exp $
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
@@ -34,7 +34,7 @@ entity dma is
req_complete_ack : in std_logic;
-- busmaster control
bus_source_en : out std_logic;
bus_din_re : out std_logic;
bus_cyc_complete : in std_logic;
bus_cmd_rdy : in std_logic;
bus_cmd_we : out std_logic;
@@ -100,7 +100,7 @@ state:
chunk_count_rst <= '0';
chunk_count_en <= '0';
master_req <= '0';
bus_source_en <= '0';
bus_din_re <= '0';
sn <= s;
case s is
@@ -133,7 +133,7 @@ state:
bus_cmd_cycle_en <= '1';
req_count_en <= bus_cmd_rdy;
chunk_count_en <= bus_cmd_rdy;
bus_source_en <= '1';
bus_din_re <= '1';
if req_count_rdy = '1' then
sn <= FINISH;
elsif chunk_count_rdy = '1' then
lib/JBUS/src/tb_dma.vhd
+11 -11
View File
@@ -1,5 +1,5 @@
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dma.vhd,v 1.1 2013-05-27 11:15:58 jens Exp $
-- $Header: /tmp/cvsroot/VHDL/lib/JBUS/src/tb_dma.vhd,v 1.2 2013-05-27 21:31:15 jens Exp $
-----------------------------------------------------------------------
LIBRARY ieee;
@@ -49,7 +49,7 @@ ARCHITECTURE behavior OF tb_dma IS
signal dma_req_complete : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_req_complete_ack : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
signal dma_bus_source_en : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_bus_din_re : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_bus_cmd_cycle_finished : unsigned(DMA_NUM_CHANNEL-1 downto 0);
signal dma_bus_cmd_cycle_en : unsigned(DMA_NUM_CHANNEL-1 downto 0) := (others => '0');
signal dma_bus_cmd_rdy : unsigned(DMA_NUM_CHANNEL-1 downto 0);
@@ -60,7 +60,7 @@ ARCHITECTURE behavior OF tb_dma IS
signal arb_idx : natural range 0 to DMA_NUM_CHANNEL-1;
-- BUS Master controller
signal bus_source_en : std_logic;
signal bus_din_re : std_logic;
signal bus_cmd_cycle_finished : std_logic;
signal bus_cmd_cycle_en : std_logic := '0';
signal bus_cmd_rdy : std_logic;
@@ -268,22 +268,22 @@ arbiter_mux:
process(dma_master_gnt, dma_bus_cmd, dma_bus_cmd_we, dma_bus_cmd_cycle_en)
variable v_bus_cmd_we : std_logic;
variable v_bus_cmd_cycle_en : std_logic;
variable v_bus_source_en : std_logic;
variable v_bus_din_re : std_logic;
begin
v_bus_cmd_we := '0';
v_bus_cmd_cycle_en := '0';
v_bus_source_en := '0';
v_bus_din_re := '0';
for i in 0 to DMA_NUM_CHANNEL-1 loop
v_bus_cmd_we := v_bus_cmd_we or dma_bus_cmd_we(i);
v_bus_cmd_cycle_en := v_bus_cmd_cycle_en or dma_bus_cmd_cycle_en(i);
v_bus_source_en := v_bus_source_en or dma_bus_source_en(i);
v_bus_din_re := v_bus_din_re or dma_bus_din_re(i);
if dma_master_gnt(i) = '1' then
bus_cmd <= dma_bus_cmd(i);
end if;
end loop;
bus_cmd_we <= v_bus_cmd_we;
bus_cmd_cycle_en <= v_bus_cmd_cycle_en;
bus_source_en <= v_bus_source_en;
bus_din_re <= v_bus_din_re;
end process;
gen_uut:
@@ -317,7 +317,7 @@ for i in 0 to DMA_NUM_CHANNEL-1 generate
req_complete_ack => dma_req_complete_ack(i),
-- busmaster control
bus_source_en => dma_bus_source_en(i),
bus_din_re => dma_bus_din_re(i),
bus_cyc_complete => dma_bus_cmd_cycle_finished(i),
bus_cmd_rdy => dma_bus_cmd_rdy(i),
@@ -409,10 +409,10 @@ CLK_GEN: process
SRDY_I <= CYC_O;
bus_dout_re <= '1' when dma_write_source = DATA_GEN else not read_fifo_full;
bus_din_vld <= bus_source_en when dma_write_source = DATA_GEN else (bus_source_en and not read_fifo_empty);
bus_din_vld <= bus_din_re when dma_write_source = DATA_GEN else (bus_din_re and not read_fifo_empty);
bus_din <= data_gen_reg when dma_write_source = DATA_GEN else read_fifo_dout;
data_gen_reg_inc <= (bus_din_rdy and bus_source_en) when dma_write_source = DATA_GEN else '0';
read_fifo_re <= (bus_din_rdy and bus_source_en) when dma_write_source = READ_FIFO else '0';
data_gen_reg_inc <= (bus_din_rdy and bus_din_re) when dma_write_source = DATA_GEN else '0';
read_fifo_re <= (bus_din_rdy and bus_din_re) when dma_write_source = READ_FIFO else '0';
read_fifo_we <= bus_dout_vld;
read_fifo_din <= bus_dout;