- added PS2 interface 1

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git-svn-id: http://moon:8086/svn/vhdl/trunk@618 cc03376c-175c-47c8-b038-4cd826a8556b

projects/mips_sys/src/mips_sys.vhd

@@ -123,6 +123,9 @@ PORT
 	sys_ps2_0_clk		: inout std_logic;
 	sys_ps2_0_data		: inout std_logic;
 
+	sys_ps2_1_clk		: inout std_logic;
+	sys_ps2_1_data		: inout std_logic;
+
 	sys_error			: out unsigned(1 downto 0) -- indicates Errors
 	
 );
@@ -339,6 +342,10 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal ps2_0_data_rx		: std_logic;
 	signal ps2_0_clk_tx			: std_logic;
 	signal ps2_0_data_tx		: std_logic;
+	signal ps2_1_clk_rx			: std_logic;
+	signal ps2_1_data_rx		: std_logic;
+	signal ps2_1_clk_tx			: std_logic;
+	signal ps2_1_data_tx		: std_logic;
 
 	-- Arbiter
 	constant ARB_MAX_MASTER		: natural := 2;
@@ -438,6 +445,12 @@ ARCHITECTURE behavior OF mips_sys IS
 	signal SRDY_O_ps2_0			: std_logic;
 	signal SDAT_O_ps2_0			: unsigned(31 downto 0);
 
+	signal INT_O_ps2_1			: std_logic;
+	signal CYC_I_ps2_1			: std_logic;
+	signal ACK_O_ps2_1			: std_logic;
+	signal SRDY_O_ps2_1			: std_logic;
+	signal SDAT_O_ps2_1			: unsigned(31 downto 0);
+
 	signal gpo0					: unsigned(31 downto 0);
 	signal gpo1					: unsigned(31 downto 0);
 	signal gpi0					: unsigned(31 downto 0);
@@ -539,7 +552,7 @@ int_sample:
 	process(CLK_O)
 	begin
 		if rising_edge(CLK_O) then
-			INT <= int_timer & INT_O_ps2_0 & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
+			INT <= int_timer & (INT_O_ps2_0 or INT_O_ps2_1) & (gpo1(2) and INT_O_ac97) & (gpo1(1) and sys_usb_int) & (int_uart0 or int_uart1) & sys_btn(4);
 		end if;
 	end process;
 	
@@ -589,6 +602,7 @@ signal_mux:
 		CYC_I_uart0		<= '0';
 		CYC_I_uart1		<= '0';
 		CYC_I_ps2_0		<= '0';
+		CYC_I_ps2_1		<= '0';
 		CYC_I_gpio		<= '0';
 		CYC_I_flash		<= '0';
 		CYC_I_usb		<= '0';
@@ -611,6 +625,9 @@ signal_mux:
 		when mem_ps2_0 =>
 			CYC_I_ps2_0		<= CYC_O;
 
+		when mem_ps2_1 =>
+			CYC_I_ps2_1		<= CYC_O;
+
 		when mem_flash =>
 			CYC_I_flash		<= CYC_O;
 
@@ -636,8 +653,8 @@ signal_mux:
 	end process;
 
 ------------------------------------------------------------------
- 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_ps2_0 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
+ 	SRDY_I		<=	SRDY_O_flash or SRDY_O_usb or SRDY_O_sdram or SRDY_O_rom or SRDY_O_uart0 or SRDY_O_uart1 or SRDY_O_ps2_0 or SRDY_O_ps2_1 or SRDY_O_gpio or SRDY_O_vga or SRDY_O_ac97;
- 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_ps2_0 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
+ 	ACK_I		<=	ACK_O_flash or ACK_O_usb or ACK_O_sdram or ACK_O_rom or ACK_O_uart0 or ACK_O_uart1 or ACK_O_ps2_0 or ACK_O_ps2_1 or ACK_O_gpio or ACK_O_vga or ACK_O_ac97;
  	MDAT_I		<=	SDAT_O_sdram(31 downto 0) when CYC_I_sdram = '1' else
 					SDAT_O_rom when CYC_I_rom = '1' else
 					SDAT_O_flash when CYC_I_flash = '1' else
@@ -645,6 +662,7 @@ signal_mux:
 					SDAT_O_uart0 when CYC_I_uart0 = '1' else
 					SDAT_O_uart1 when CYC_I_uart1 = '1' else
 					SDAT_O_ps2_0 when CYC_I_ps2_0 = '1' else
+					SDAT_O_ps2_1 when CYC_I_ps2_1 = '1' else
 					SDAT_O_vga when CYC_I_vga = '1' else
 					SDAT_O_ac97 when CYC_I_ac97 = '1' else
 					SDAT_O_gpio when CYC_I_gpio = '1' else X"DEADBEEF";
@@ -1013,5 +1031,44 @@ inst_ps2_phy_0: entity work.ps2_phy
 		tx_data => ps2_0_data_tx
 	);
 
+inst_ps2_wb_1: entity work.ps2_wb
+	GENERIC MAP
+	(
+		f_sys_clk_hz	=> sys_freq
+	)
+	PORT MAP
+	(
+		CLK_I		=> CLK_O,
+		RST_I		=> RST_O,
+		CYC_I		=> CYC_I_ps2_1,
+		STB_I		=> STB_O,
+		SEL_I		=> SEL_O,
+		WE_I		=> WE_O,
+		ACK_O		=> ACK_O_ps2_1,
+		SRDY_O		=> SRDY_O_ps2_1,
+		MRDY_I		=> MRDY_O,
+		ADDR_I		=> ADDR_O,
+		DAT_I		=> MDAT_O,
+		DAT_O		=> SDAT_O_ps2_1,
+		INT_O		=> INT_O_ps2_1,
+		clk_rx		=> ps2_1_clk_rx,
+		data_rx		=> ps2_1_data_rx,
+		clk_tx		=> ps2_1_clk_tx,
+		data_tx		=> ps2_1_data_tx
+	);
+
+inst_ps2_phy_1: entity work.ps2_phy
+	PORT MAP
+	(
+		rst => RST_O,
+		clk => CLK_O,
+		ps2_clk => sys_ps2_1_clk,
+		ps2_data => sys_ps2_1_data,
+		rx_clk => ps2_1_clk_rx,
+		rx_data => ps2_1_data_rx,
+		tx_clk => ps2_1_clk_tx,
+		tx_data => ps2_1_data_tx
+	);
+
 	------------------------------------------------------------------
 END;