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Bug fix: Address and data latch only if ready

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git-svn-id: http://moon:8086/svn/vhdl/trunk@47 cc03376c-175c-47c8-b038-4cd826a8556b
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jens
2008-10-11 20:13:52 +00:00
parent b6309838f1
commit de6bd8f29c
1 changed files with 34 additions and 17 deletions
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lib/misc/async_port_wb.vhd
+29 -12
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@@ -1,5 +1,5 @@
----------------------------------------------------------------------- -----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.1 2008-10-10 21:25:46 Jens Exp $ -- $Header: /tmp/cvsroot/VHDL/lib/misc/async_port_wb.vhd,v 1.2 2008-10-11 20:13:52 Jens Exp $
----------------------------------------------------------------------- -----------------------------------------------------------------------
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
@@ -46,7 +46,7 @@ architecture Behavioral of async_port_wb is
drive_d : std_logic; drive_d : std_logic;
end record; end record;
type async_state_t is (start, reset, rdy, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release); type async_state_t is (start, reset, idle, leadin_rd, read, leadin_wr, write, leadout_rd, leadout_wr, release);
signal s, sn : async_state_t; signal s, sn : async_state_t;
signal as : async_t; signal as : async_t;
@@ -54,10 +54,16 @@ architecture Behavioral of async_port_wb is
signal cc_rst : std_logic; signal cc_rst : std_logic;
signal cycle_cnt : natural range 0 to 15; signal cycle_cnt : natural range 0 to 15;
signal cycle_reload : natural range 0 to 15; signal cycle_reload : natural range 0 to 15;
signal rdy : std_logic;
signal en : std_logic;
signal data_reg : unsigned(data_width-1 downto 0);
------------------------------------------------------------------ ------------------------------------------------------------------
begin begin
SRDY_O <= CYC_I and rdy;
en <= CYC_I and STB_I;
proc_cycle_counter: proc_cycle_counter:
process(CLK_I) process(CLK_I)
begin begin
@@ -84,7 +90,7 @@ architecture Behavioral of async_port_wb is
end process; end process;
proc_state: proc_state:
process(s, cycle_cnt, STB_I, CYC_I, WE_I) process(s, cycle_cnt, en, WE_I)
begin begin
cycle_reload <= async_timespec.ncyc_pulse_rst; cycle_reload <= async_timespec.ncyc_pulse_rst;
@@ -94,8 +100,8 @@ architecture Behavioral of async_port_wb is
as.wr <= '0'; as.wr <= '0';
as.rd <= '0'; as.rd <= '0';
as.drive_d <= '0'; as.drive_d <= '0';
SRDY_O <= '0';
ack <= '0'; ack <= '0';
rdy <= '0';
sn <= s; sn <= s;
case s is case s is
@@ -106,11 +112,11 @@ architecture Behavioral of async_port_wb is
when reset => when reset =>
as.rst <= '1'; as.rst <= '1';
if cycle_cnt = 0 then if cycle_cnt = 0 then
sn <= rdy; sn <= idle;
end if; end if;
when rdy => when idle =>
SRDY_O <= CYC_I; rdy <= '1';
if (STB_I and CYC_I) = '1' then if en = '1' then
as.cs <= '1'; as.cs <= '1';
cc_rst <= '1'; cc_rst <= '1';
cycle_reload <= async_timespec.ncyc_access-1; cycle_reload <= async_timespec.ncyc_access-1;
@@ -184,11 +190,11 @@ architecture Behavioral of async_port_wb is
when release => when release =>
if cycle_cnt = 0 then if cycle_cnt = 0 then
sn <= rdy; sn <= idle;
end if; end if;
when others => when others =>
sn <= rdy; sn <= idle;
end case; end case;
end process; end process;
@@ -223,12 +229,23 @@ architecture Behavioral of async_port_wb is
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
if RST_I = '1' then if RST_I = '1' then
async_a <= (others => '0'); async_a <= (others => '0');
elsif (STB_I and CYC_I) = '1' then elsif en = '1' and rdy = '1' then
async_a <= ADDR_I(addr_width-1 downto 0); async_a <= ADDR_I(addr_width-1 downto 0);
end if; end if;
end if; end if;
end process; end process;
------------------------------------------------------------------
data_register:
process(CLK_I)
begin
if rising_edge(CLK_I) then
if en = '1' and rdy = '1' then
data_reg <= DAT_I(data_width-1 downto 0);
end if;
end if;
end process;
------------------------------------------------------------------ ------------------------------------------------------------------
output_ACK: output_ACK:
process(CLK_I) process(CLK_I)
@@ -249,7 +266,7 @@ architecture Behavioral of async_port_wb is
if rising_edge(CLK_I) then if rising_edge(CLK_I) then
async_d <= (others => 'Z'); async_d <= (others => 'Z');
if as.drive_d = '1' then if as.drive_d = '1' then
async_d <= DAT_I(data_width-1 downto 0); async_d <= data_reg;
end if; end if;
end if; end if;
end process; end process;