diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd index 1494c9b..f5ab332 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd @@ -41,9 +41,11 @@ entity ddr_phy is u_tag_wr : out user_tag_t; read_clk : in STD_LOGIC; phy_ctrl : in phy_ctrl_t; - part_ctrl : in part_ctrl_t; - sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); + part_ctrl : in part_ctrl_t; + sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); + sdr_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0); + sdr_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0); + sdr_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0); sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); sdr_data_vld : out STD_LOGIC; sdr_data_req_w : out STD_LOGIC; @@ -81,6 +83,9 @@ architecture tech of ddr_phy is type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; signal u_tag_pipe : u_tag_array_t; + type dm_out_array_t is array (natural range 0 to 4) of unsigned(SDR_DM_WIDTH-1 downto 0); + signal dm_out_pipe : dm_out_array_t; + begin ------------------------------------------------------------------------------------------------------------------------------------------------ @@ -97,6 +102,19 @@ utag_pipe: end if; end process; +dmout_pipe: + process(sys_rst, sys_clk0) + begin + if rising_edge(sys_clk0) then + for i in dm_out_pipe'length-1 downto 1 loop + dm_out_pipe(i) <= dm_out_pipe(i-1); + end loop; + if phy_ctrl.utag_we = '1' then + dm_out_pipe(0) <= sdr_dm_rd_in; + end if; + end if; + end process; + WE_REGISTER: process(sys_rst, sys_clk0) begin @@ -221,8 +239,8 @@ gen_ddr_dm_out: Q => part_dm(n), -- 1-bit DDR output C => sys_clk270, -- 1-bit clock input CE => '1', -- 1-bit clock enable input - D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm(n), -- 1-bit data input (negative edge) + D1 => sdr_dm_wr_in(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) + D2 => sdr_dm_wr_in(n), -- 1-bit data input (negative edge) R => '0', -- 1-bit reset input S => '0' -- 1-bit set input ); @@ -349,10 +367,11 @@ misc_flags_and_data_out: elsif rising_edge(sys_clk0) then sdr_data_r <= data_reg_r; if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); + u_tag_rd <= u_tag_pipe(4); + sdr_dm_rd_out <= dm_out_pipe(4); end if; if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); + u_tag_wr <= u_tag_pipe(0); end if; sdr_data_req_w <= phy_ctrl.we; sdr_data_req_r <= phy_ctrl.re; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd index 98dea2a..268636e 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd @@ -87,12 +87,15 @@ architecture struct of sdram_ctrl_frontend is signal u_cmd_we : std_logic; signal u_busy : std_logic; signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm : unsigned(SDR_DM_WIDTH-1 downto 0); + signal u_dm_wr_in : unsigned(SDR_DM_WIDTH-1 downto 0); + signal u_dm_rd_in : unsigned(SDR_DM_WIDTH-1 downto 0); + signal u_dm_rd_out : unsigned(SDR_DM_WIDTH-1 downto 0); signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); signal u_data_vld : std_logic; signal u_req_wr : std_logic; + signal rdy : std_logic; - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; + constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH + SDR_DM_WIDTH; signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); signal cat_fifo_re : std_logic; @@ -111,8 +114,8 @@ architecture struct of sdram_ctrl_frontend is -- signal write_fifo_almost_full : std_logic; -- signal write_fifo_almost_empty : std_logic; - signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0); + signal read_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); + signal read_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); signal read_fifo_re : std_logic; signal read_fifo_we : std_logic; signal read_fifo_full : std_logic; @@ -122,14 +125,22 @@ architecture struct of sdram_ctrl_frontend is alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); + alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH); + alias dm_rd_fifo_in is cat_fifo_din(SDR_DM_WIDTH-1 downto 0); alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); + alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto SDR_DM_WIDTH); + alias dm_rd_fifo_out is cat_fifo_dout(SDR_DM_WIDTH-1 downto 0); + alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH); alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0); alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH); alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); + + alias read_fifo_dm_in is read_fifo_din(read_fifo_din'length-1 downto read_fifo_din'length-SDR_DM_WIDTH); + alias read_fifo_data_in is read_fifo_din(read_fifo_din'length-SDR_DM_WIDTH-1 downto 0); + alias read_fifo_dm_out is read_fifo_dout(read_fifo_dout'length-1 downto read_fifo_dout'length-SDR_DM_WIDTH); + alias read_fifo_data_out is read_fifo_dout(read_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); begin @@ -180,7 +191,7 @@ begin GENERIC MAP ( addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH ) PORT MAP ( @@ -227,7 +238,9 @@ begin u_cmd_we => u_cmd_we, u_data_wr => u_data_w, u_data_rd => u_data_r, - u_dm => u_dm, + u_dm_wr_in => u_dm_wr_in, + u_dm_rd_in => u_dm_rd_in, + u_dm_rd_out => u_dm_rd_out, -- SDRAM signals sd_clk_p => sd_clk_p, @@ -248,22 +261,24 @@ begin ------------------------------------------------------------------------------------------ sys_rst_out <= rst_out; sys_clk_out <= clk_out; - - busy <= cat_fifo_full or write_fifo_full or read_fifo_full; - write_fifo_we <= en and not r_wn and not write_fifo_full and not cat_fifo_full and not read_fifo_full; + busy <= not rdy; + rdy <= not (cat_fifo_full or write_fifo_full or read_fifo_full); + write_fifo_we <= en and not r_wn and rdy; write_fifo_data_in <= din; write_fifo_dm_in <= not be; - cat_fifo_we <= en and not cat_fifo_full and not write_fifo_full and not read_fifo_full; + cat_fifo_we <= en and rdy; cmd_fifo_in <= UCMD_WRITE when r_wn = '0' else UCMD_READ; addr_fifo_in <= addr; + dm_rd_fifo_in <= not be; tag_fifo_in <= (others=>'0'); - dout <= read_fifo_dout; + dout <= read_fifo_data_out; dout_vld <= not read_fifo_empty; u_cmd_we <= (not cat_fifo_empty) and (not u_busy); u_cmd <= cmd_fifo_out; u_addr <= addr_fifo_out; - u_dm <= write_fifo_dm_out; + u_dm_rd_in <= dm_rd_fifo_out; + u_dm_wr_in <= write_fifo_dm_out; u_tag_in <= tag_fifo_out; write_fifo_re <= u_req_wr and (not write_fifo_empty); @@ -271,7 +286,8 @@ begin u_data_w <= write_fifo_data_out; read_fifo_re <= (not read_fifo_empty) and dout_re; read_fifo_we <= u_data_vld; - read_fifo_din <= u_data_r; + read_fifo_data_in <= u_data_r; + read_fifo_dm_in <= u_dm_rd_out; end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd index ba9ee71..19768a4 100644 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd +++ b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd @@ -39,8 +39,8 @@ entity sdram_ctrl_top is ( sys_rst_in : in STD_LOGIC; sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; + sys_rst_out : out STD_LOGIC; + sys_clk_out : out STD_LOGIC; sys_clk_fb : in STD_LOGIC; -- User interface @@ -54,8 +54,10 @@ entity sdram_ctrl_top is u_addr : in user_addr_t; u_cmd : in user_cmd_t; u_cmd_we : in STD_LOGIC; - u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); + u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); + u_dm_wr_in : in unsigned(SDR_DM_WIDTH-1 downto 0); + u_dm_rd_in : in unsigned(SDR_DM_WIDTH-1 downto 0); + u_dm_rd_out : out unsigned(SDR_DM_WIDTH-1 downto 0); u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); -- SDRAM signals @@ -68,7 +70,7 @@ entity sdram_ctrl_top is sd_we_n : out STD_LOGIC; sd_addr : out sdr_addr_t; sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); + sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) @@ -264,7 +266,9 @@ begin sdr_data_req_w => u_data_req_w, sdr_data_req_r => u_data_req_r, sdr_data_w => u_data_wr, - sdr_dm => u_dm, + sdr_dm_wr_in => u_dm_wr_in, + sdr_dm_rd_in => u_dm_rd_in, + sdr_dm_rd_out => u_dm_rd_out, sdr_data_r => u_data_rd, sdr_data_vld => u_data_vld, part_clk_p => sd_clk_p,