diff --git a/lib/CPUs/JCpu/asm/dctest.jsm b/lib/CPUs/JCpu/asm/dctest.jsm deleted file mode 100644 index 38d5947..0000000 --- a/lib/CPUs/JCpu/asm/dctest.jsm +++ /dev/null @@ -1,56 +0,0 @@ -; ------------------------------------------------- -; PROJECT "dctest" -; ------------------------------------------------- - -include "../../../jasm/cregs.inc.jsm" - -; ------------------------------------------------- - xmem - org 4 -konst: dc 0x01, 0x12,"A" -gap1: db 16 -mesg: dc "Hallo", 13,0x0A, 0 -name: dc "Jens",0 -msg1: dc "Welcome to JASM CPU",0 -msg2: dc "Ready",0 -msg3: dc "Testing",0 -msg4: dc "Passed",0 -msg5: dc "Error",0 -crlf: dc 0x0D, 0x0A - - org 0x00 -shit: db 4 - - cmem 0 - org 8 -cram1: db 16 -cram2: db 6 -cram3: db 4 - - cmem 1 -cram4: db 8 -cram5: db 8 - org 0x20 -cram6: db 8 -cram7: db 4 - -reg_revision: equ 0x00 -reg_testid: equ 0x01 - -; ------------------------------------------------- - code - org 0x000 -reset: jmp start - -; ------------------------------------------------- - org 0x001 -int_vec: jmp isr - -; ------------------------------------------------- - org 0x010 - -start: jmp start - -; ------------------------------------------------- -isr: reti - diff --git a/lib/CPUs/JCpu/asm/dctest.tcl b/lib/CPUs/JCpu/asm/dctest.tcl deleted file mode 100644 index ca88834..0000000 --- a/lib/CPUs/JCpu/asm/dctest.tcl +++ /dev/null @@ -1,212 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from dctest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010" - -# 0x001: JMP 0x011 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130011" - -# 0x002: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000" - -# 0x003: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000" - -# 0x004: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000" - -# 0x005: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000" - -# 0x007: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000" - -# 0x009: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000" - -# 0x00B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000" - -# 0x00D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000" - -# 0x00F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01030010" - -# 0x011: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0113F000" - -# Assembled from dctest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0401" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0512" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0641" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1748" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1861" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "196C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A6C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B6F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C0D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D0A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F4A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2065" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "216E" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2273" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2457" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2565" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "266C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2763" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "286F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "296D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2A65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2B20" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2C74" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2D6F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2E20" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2F4A" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3041" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3153" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "324D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3320" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3443" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3550" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3655" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3852" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3965" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3A61" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3B64" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3C79" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3E54" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "3F65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4073" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4174" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4269" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "436E" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4467" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4650" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4761" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4873" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4973" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4A65" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4B64" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4D45" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4E72" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "4F72" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "506F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5172" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "5200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "530D" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "540A" - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/itest.jsm b/lib/CPUs/JCpu/asm/itest.jsm deleted file mode 100644 index 9666253..0000000 --- a/lib/CPUs/JCpu/asm/itest.jsm +++ /dev/null @@ -1,858 +0,0 @@ -; ------------------------------------------------- -; PROJECT "itest" -; ------------------------------------------------- - -include "../../../jasm/cregs.inc.jsm" - -; ------------------------------------------------- - xmem -msg: dc "Hallo", 0 -xram: db 256 - - cmem 0 -cram: db 256 - -reg_revision: equ 0x00 -reg_testid: equ 0x01 - -; ------------------------------------------------- - code - org 0x000 -reset: jmp start - -; ------------------------------------------------- - org 0x001 -int_vec: jmp isr - -; ------------------------------------------------- - org 0x010 - -start: call init - cin R0, (cpu_revision) - xout (reg_revision), R0 - - ; Test 0 - call test0 - - ; Test 1 - mov R0, 1 - xout (reg_testid), R0 - call test1 - - ; Test 2 - mov R0, 2 - xout (reg_testid), R0 - call test2 - - ; Test 3 - mov R0, 3 - xout (reg_testid), R0 - call test3 - - ; Test 4 - mov R0, 4 - xout (reg_testid), R0 - call test4 - - ; Test 5 - mov R0, 5 - xout (reg_testid), R0 - call test5 - - ; Test 6 - mov R0, 6 - xout (reg_testid), R0 - call test6 - - ; Test 7 - mov R0, 7 - xout (reg_testid), R0 - call test7 - - ; Test 8 - mov R0, 8 - xout (reg_testid), R0 - call test8 - - ; Test 9 - mov R0, 9 - xout (reg_testid), R0 - call test9 - - ; Test 10 - mov R0, 10 - xout (reg_testid), R0 - call test10 - - ; Test 11 - mov R0, 11 - xout (reg_testid), R0 - call test11 - - ; Test 12 - mov R0, 12 - xout (reg_testid), R0 - call test12 - - ; End of test - mov R0, 0xFF - xout (reg_testid), R0 - - jmp ok - -; ------------------------------------------------- -init: mov R0, 0 - mov R1, 0 - mov R2, 0 - mov R3, 0 - mov R4, 0 - mov R5, 0 - mov R6, 0 - mov R7, 0 - mov R8, 0 - mov R9, 0 - mov R10, 0 - mov R11, 0 - mov R12, 0 - mov R13, 0 - mov R14, 0 - mov R15, 0 - ret - -; ------------------------------------------------- -; MOV|R|K -; MOV|R|R -test0: mov R0, 0x10 - cmp R0, 0x10 - jne error - add R0, 1 - - mov R1, R0 - cmp R1, 0x11 - jne error - add R1, 1 - - mov R2, R1 - cmp R2, 0x12 - jne error - add R2, 1 - - mov R3, R2 - cmp R3, 0x13 - jne error - add R3, 1 - - mov R4, R3 - cmp R4, 0x14 - jne error - add R4, 1 - - mov R5, R4 - cmp R5, 0x15 - jne error - add R5, 1 - - mov R6, R5 - cmp R6, 0x16 - jne error - add R6, 1 - - mov R7, R6 - cmp R7, 0x17 - jne error - add R7, 1 - - mov R8, R7 - cmp R8, 0x18 - jne error - add R8, 1 - - mov R9, R8 - cmp R9, 0x19 - jne error - add R9, 1 - - mov R10, R9 - cmp R10, 0x1A - jne error - add R10, 1 - - mov R11, R10 - cmp R11, 0x1B - jne error - add R11, 1 - - mov R12, R11 - cmp R12, 0x1C - jne error - add R12, 1 - - mov R13, R12 - cmp R13, 0x1D - jne error - add R13, 1 - - mov R14, R13 - cmp R14, 0x1E - jne error - add R14, 1 - - mov R15, R14 - cmp R15, 0x1F - jne error - add R15, 1 - - ret - -; ------------------------------------------------- -; Instruction test -; TST|R -; CMP|R|K -; JNZ|K -; JC|K -; JNE|K -; JLT|K -; JGT|K -; JLE|K -; JGE|K -; JMP|K -test1: mov R0, 0 ; R0 <= 0 - tst R0 - jnz error - jc error - cmp R0, 0 - jne error - jlt error - jgt error - jle t1_ok10 - jmp error - -t1_ok10: jeq t1_ok20 - jmp error - -t1_ok20: jge t1_ok30 - jmp error - -t1_ok30: cmp R0, 0x55 - jeq error - jlt t1_ok40 - jmp error - -t1_ok40: jle t1_ok50 - jmp error - -t1_ok50: jge error - jgt error - - mov R0, 0x55 ; R0 <= 0xAA - tst R0 - jz error - jc error - - cmp R0, 0xAA - jeq error - jne t1_ok60 - jmp error - -t1_ok60: jlt t1_ok70 - jmp error - -t1_ok70: jle t1_ok80 - jmp error - -t1_ok80: jgt error - - cmp R0, 0x55 - jeq t1_ok90 - jmp error - -t1_ok90: jne error - jlt error - - jle t1_ok100 - jmp error - -t1_ok100: jgt error - jge t1_ok110 - jmp error - -t1_ok110: mov R0, 0xAA ; R0 <= 0x55 - tst R0 - jz error - jc error - - cmp R0, 0x55 - jeq error - jne t1_ok120 - jmp error - -t1_ok120: jgt t1_ok130 - jmp error - -t1_ok130: jge t1_ok140 - jmp error - -t1_ok140: jlt error - jle error - - ret - -; ------------------------------------------------- -; ADD|R|K -; ADDC|R|K -; ToDo: ADD|R|R -; ToDo: ADDC|R|R -; CMP|R|R -test2: mov R0, 0 - mov R1, 0 - mov R2, R0 - mov R3, R1 - -t2_loop: add R0, 0x01 - addc R1, 0x00 - add R2, 1 - cmp R2, 0 - jne t2_L1 - add R3, 1 - cmp R3, 0x02 -t2_L1: jne t2_loop - cmp R0, R2 - jne error - cmp R1, R3 - jne error - mov R0, 0 - - ret - -; ------------------------------------------------- -; SUB|R|K -; SUBC|R|K -; ToDo: SUB|R|R -; ToDo: SUBC|R|R -; CMP|R|R -test3: mov R0, 0x00 - mov R1, 0x03 - mov R2, R0 - mov R3, R1 - -t3_loop: sub R0, 0x01 - subc R1, 0x00 - sub R2, 1 - cmp R2, 0xFF - jne t3_L1 - sub R3, 1 - cmp R3, 0x00 -t3_L1: jne t3_loop - cmp R0, R2 - jne error - cmp R1, R3 - jne error - mov R0, 0 - - ret -; ------------------------------------------------- -; SUB|K|R -; SUB|R|R -; SUBC|R|R -; SUBC|K|R -; CMP|R|R -test4: mov R0, 0x03 - mov R1, 0x05 - sub 0x05, R0 - sub R1, 0x03 - cmp R0, R1 - jne error - mov R0, 0x03 - mov R1, 0x05 - sub R0, R1 - subc 0, R0 - cmp R0, 0x01 - jne error - add R0, 0 - subc R1, R0 - cmp R1, 0x04 - jne error - mov R0, 0 - - ret - -; ------------------------------------------------- -; MOVC|R|Ri -; MOVC|R|Ki -; MOVC|Ri|R -; MOVC|Ri|K -; MOVC|Ki|R -test5: mov R0, 1 - movc (cram+0x5A), R0 - dec R0 - movc (cram+0), R0 - movc R1, (cram+0x5A) - movc (R1), 0xA5 - movc R0, (R1) - movc R1, (R1) - add R1, 0xFF-0xA5 - movc R0, (R1) -t5_loop1: movc (R0), R0 - movc R2, (R0) - cmp R2, R0 - jne error - movc (R2), R1 - movc R2, (R2) - cmp R2, R1 - jne error - dec R1 - inc R0 - jnz t5_loop1 - - ret - -; ------------------------------------------------- -; MOVX|R|Ri -; MOVX|R|Ki -; MOVX|Ri|R -; MOVX|Ri|K -; MOVX|Ki|R -test6: mov R0, 1 - movx (xram+0x5A), R0 - dec R0 - movx (xram+0), R0 - movx R1, (xram+0x5A) - movx (R1), 0xA5 - movx R0, (R1) - movx R1, (R1) - add R1, 0xFF-0xA5 - movx R0, (R1) -t6_loop1: movx (R0), R0 - movx R2, (R0) - cmp R2, R0 - jne error - movx (R2), R1 - movx R2, (R2) - cmp R2, R1 - jne error - dec R1 - inc R0 - jnz t6_loop1 - - ret - -; ------------------------------------------------- -; PUSH|R -; POP|R -test7: mov R0, 0xAA - mov R1, 0 -t7_loop1: push R0 - inc R0 - dec R1 - jnz t7_loop1 -t7_loop2: pop R0 - dec R1 - jnz t7_loop2 - cmp R0, 0xAA - jne error - - ret - -; ------------------------------------------------- -; JMP|K -; CALL|K -; RET -test8: mov R0, 0x55 - push R0 - mov R0, 0 - mov R1, 0xFF - call t8_rec - pop R0 - cmp R0, 0x55 - jne error - - ; Stack manipulations 1 - mov R0, return1'high - mov R1, return1'low - cout (cpu_stack_high), R0 - push R1 - - mov R0, init'high - mov R1, init'low - cout (cpu_stack_high), R0 - push R1 - ret - - ; Stack manipulations 2 -return1: mov R0, return2'high - mov R1, return2'low - cout (cpu_stack_high), R0 - push R1 - - mov R0, init'high - mov R1, init'low - cout (cpu_stack_high), R0 - push R1 -return2: ret - -t8_rec: cmp R0, R1 - jeq ex_t8_rec - inc R0 - jmp t8_rstub -ex_t8_rec: dec R0 - dec R1 - ret - -t8_rstub: call t8_rec - jmp ex_t8_rec - -; ------------------------------------------------- -; SWAP|R -; SHL|R -; SHR|R -; ROL|R -; ROR|R -; ROLC|R -; RORC|R -test9: mov R0, 0xA5 ; SWAP test - mov R1, 0x5A - swap R0 - cmp R0, 0x5A - jne error - swap R0 - cmp R0, 0xA5 - jne error - mov R0, 0xD2 - swap R0 - cmp R0, 0x2D - jne error - swap R1 - cmp R0, 0x2D - jne error - cmp R1, 0xA5 - jne error - - mov R0, 0x2D - shl R0 ; SHL test - cmp R0, 0x5A - jne error - shl R0 - cmp R0, 0xB4 - jne error - shl R0 - cmp R0, 0x68 - jne error - shl R0 - cmp R0, 0xD0 - jne error - shl R0 - cmp R0, 0xA0 - jne error - shl R0 - cmp R0, 0x40 - jne error - shl R0 - cmp R0, 0x80 - jne error - shl R0 - cmp R0, 0x00 - jne error - - mov R1, 0x84 - shr R1 ; SHR test - cmp R1, 0x42 - jne error - shr R1 - cmp R1, 0x21 - jne error - shr R1 - cmp R1, 0x10 - jne error - shr R1 - cmp R1, 0x08 - jne error - shr R1 - cmp R1, 0x04 - jne error - shr R1 - cmp R1, 0x02 - jne error - shr R1 - cmp R1, 0x01 - jne error - shr R1 - cmp R1, 0x00 - jne error - - mov R0, 0xC5 ; ROL test - rol R0 - cmp R0, 0x8B - jne error - rol R0 - cmp R0, 0x17 - jne error - rol R0 - cmp R0, 0x2E - jne error - rol R0 - cmp R0, 0x5C - jne error - rol R0 - cmp R0, 0xB8 - jne error - rol R0 - cmp R0, 0x71 - jne error - rol R0 - cmp R0, 0xE2 - jne error - rol R0 - cmp R0, 0xC5 - jne error - - mov R1, 0x63 ; ROR test - ror R1 - cmp R1, 0xB1 - jne error - ror R1 - cmp R1, 0xD8 - jne error - ror R1 - cmp R1, 0x6C - jne error - ror R1 - cmp R1, 0x36 - jne error - ror R1 - cmp R1, 0x1B - jne error - ror R1 - cmp R1, 0x8D - jne error - ror R1 - cmp R1, 0xC6 - jne error - ror R1 - cmp R1, 0x63 - jne error - - - xor R0, R0 ; ROLC generate - mov R0, 0xC5 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - push R0 - rolc R0 - - cmp R0, 0xC5 ; ROLC verify - jne error - pop R0 - cmp R0, 0x62 - jne error - pop R0 - cmp R0, 0xB1 - jne error - pop R0 - cmp R0, 0x58 - jne error - pop R0 - cmp R0, 0xAC - jne error - pop R0 - cmp R0, 0x56 - jne error - pop R0 - cmp R0, 0x2B - jne error - pop R0 - cmp R0, 0x15 - jne error - pop R0 - cmp R0, 0x8A - jne error - - xor R1, R1 ; RORC generate - mov R1, 0x63 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - push R1 - rorc R1 - - cmp R1, 0x63 ; RORC verify - jne error - pop R1 - cmp R1, 0xC6 - jne error - pop R1 - cmp R1, 0x8C - jne error - pop R1 - cmp R1, 0x19 - jne error - pop R1 - cmp R1, 0x33 - jne error - pop R1 - cmp R1, 0x66 - jne error - pop R1 - cmp R1, 0xCC - jne error - pop R1 - cmp R1, 0x98 - jne error - pop R1 - cmp R1, 0x31 - jne error - - ret - -; ------------------------------------------------- -; AND|R|R -; AND|R|K -; OR|R|R -; OR|R|K -; XOR|R|R -; XOR|R|K -test10: mov R0, 0xA5 ; AND - swap R0 - push R0 - and R0, 0x0F - cmp R0, 0x0A - jne error - pop R0 - push R0 - and R0, 0x0F - cmp R0, 0x0A - pop R1 - jne error - swap R1 - mov R2, 0x0F - and R1, R2 - cmp R1, 0x05 - jne error - - mov R0, 0x05 ; OR - mov R2, 0xA0 - swap R0 - or R2, R0 - cmp R2, 0xF0 - jne error - swap R0 - or R0, 0x50 - cmp R0, 0x55 - jne error - - mov R1, 0x01 - mov R0, 0x01 - xor R0, 0x01 - jnz error - xor R0, R1 - cmp R0, 0x01 - jne error - - ret - -; ------------------------------------------------- -test11: - mov R0, 0x03 - cout (cpu_int_ctrl), R0 - - xin R0, (2) - or R0, 1 - xout (2), R0 - nop - nop - nop - nop - nop - nop - xin R0, (2) - and R0, 0xFE - xout (2), R0 - nop - nop - nop - nop - - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - cin R0, (cpu_int_ctrl) - or R0, 0x80 - cout (cpu_int_ctrl), R0 - nop - nop - nop - nop - nop - nop - nop - nop - nop - ret - -; ------------------------------------------------- -; Tests clrc, setc -test12: sub R0, 0 - jc error - setc - jnc error - nop - sub R0, 0 - jc error - - mov R0, 0 - clrc - jc error - setc - jnc error - nop - clrc - jc error - ret - -; ------------------------------------------------- -isr: inc R14 - reti - -; ------------------------------------------------- - org 0x3FF -error: jmp error - -; ------------------------------------------------- - org 0x2FF -ok: jmp ok - -; ------------------------------------------------- - \ No newline at end of file diff --git a/lib/CPUs/JCpu/asm/itest.tcl b/lib/CPUs/JCpu/asm/itest.tcl deleted file mode 100644 index 3724ca6..0000000 --- a/lib/CPUs/JCpu/asm/itest.tcl +++ /dev/null @@ -1,3407 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from itest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x010 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030010" - -# 0x001: JMP 0x288 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00130288" - -# 0x002: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00200000" - -# 0x003: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00300000" - -# 0x004: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00400000" - -# 0x005: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00600000" - -# 0x007: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00800000" - -# 0x009: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A00000" - -# 0x00B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C00000" - -# 0x00D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E00000" - -# 0x00F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: CALL 0x03B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103B03B" - -# 0x011: CIN R00, (0x00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01129000" - -# 0x012: XOUT (0x00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01224000" - -# 0x013: CALL 0x04C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0133B04C" - -# 0x014: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01403010" - -# 0x015: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01524010" - -# 0x016: CALL 0x08D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163B08D" - -# 0x017: MOV R00, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01703020" - -# 0x018: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01824010" - -# 0x019: CALL 0x0C9 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193B0C9" - -# 0x01A: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A03030" - -# 0x01B: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B24010" - -# 0x01C: CALL 0x0DB -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01C3B0DB" - -# 0x01D: MOV R00, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01D03040" - -# 0x01E: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01E24010" - -# 0x01F: CALL 0x0ED -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01F3B0ED" - -# 0x020: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02003050" - -# 0x021: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02124010" - -# 0x022: CALL 0x0FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0223B0FF" - -# 0x023: MOV R00, 0x06 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02303060" - -# 0x024: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02424010" - -# 0x025: CALL 0x115 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0253B115" - -# 0x026: MOV R00, 0x07 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02603070" - -# 0x027: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02724010" - -# 0x028: CALL 0x12B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0283B12B" - -# 0x029: MOV R00, 0x08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02903080" - -# 0x02A: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02A24010" - -# 0x02B: CALL 0x137 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02B3B137" - -# 0x02C: MOV R00, 0x09 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02C03090" - -# 0x02D: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02D24010" - -# 0x02E: CALL 0x15A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02E3B15A" - -# 0x02F: MOV R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "02F030A0" - -# 0x030: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03024010" - -# 0x031: CALL 0x22A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0313B22A" - -# 0x032: MOV R00, 0x0B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "032030B0" - -# 0x033: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03324010" - -# 0x034: CALL 0x24D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0343B24D" - -# 0x035: MOV R00, 0x0C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "035030C0" - -# 0x036: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03624010" - -# 0x037: CALL 0x278 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0373B278" - -# 0x038: MOV R00, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03803FF0" - -# 0x039: XOUT (0x01), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03924010" - -# 0x03A: JMP 0x2FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03A302FF" - -# 0x03B: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03B03000" - -# 0x03C: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03C03001" - -# 0x03D: MOV R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03D03002" - -# 0x03E: MOV R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03E03003" - -# 0x03F: MOV R04, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "03F03004" - -# 0x040: MOV R05, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04003005" - -# 0x041: MOV R06, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04103006" - -# 0x042: MOV R07, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04203007" - -# 0x043: MOV R08, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04303008" - -# 0x044: MOV R09, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04403009" - -# 0x045: MOV R10, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0450300A" - -# 0x046: MOV R11, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0460300B" - -# 0x047: MOV R12, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0470300C" - -# 0x048: MOV R13, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0480300D" - -# 0x049: MOV R14, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0490300E" - -# 0x04A: MOV R15, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04A0300F" - -# 0x04B: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04B3E000" - -# 0x04C: MOV R00, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04C03100" - -# 0x04D: CMP R00, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04D0F100" - -# 0x04E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04E3A3FF" - -# 0x04F: ADD R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "04F11010" - -# 0x050: MOV R01, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05002001" - -# 0x051: CMP R01, 0x11 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0510F111" - -# 0x052: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0523A3FF" - -# 0x053: ADD R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05311011" - -# 0x054: MOV R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05402012" - -# 0x055: CMP R02, 0x12 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0550F122" - -# 0x056: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0563A3FF" - -# 0x057: ADD R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05711012" - -# 0x058: MOV R03, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05802023" - -# 0x059: CMP R03, 0x13 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0590F133" - -# 0x05A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05A3A3FF" - -# 0x05B: ADD R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05B11013" - -# 0x05C: MOV R04, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05C02034" - -# 0x05D: CMP R04, 0x14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05D0F144" - -# 0x05E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05E3A3FF" - -# 0x05F: ADD R04, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "05F11014" - -# 0x060: MOV R05, R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06002045" - -# 0x061: CMP R05, 0x15 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0610F155" - -# 0x062: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0623A3FF" - -# 0x063: ADD R05, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06311015" - -# 0x064: MOV R06, R05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06402056" - -# 0x065: CMP R06, 0x16 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0650F166" - -# 0x066: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0663A3FF" - -# 0x067: ADD R06, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06711016" - -# 0x068: MOV R07, R06 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06802067" - -# 0x069: CMP R07, 0x17 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0690F177" - -# 0x06A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06A3A3FF" - -# 0x06B: ADD R07, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06B11017" - -# 0x06C: MOV R08, R07 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06C02078" - -# 0x06D: CMP R08, 0x18 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06D0F188" - -# 0x06E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06E3A3FF" - -# 0x06F: ADD R08, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "06F11018" - -# 0x070: MOV R09, R08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07002089" - -# 0x071: CMP R09, 0x19 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0710F199" - -# 0x072: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0723A3FF" - -# 0x073: ADD R09, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07311019" - -# 0x074: MOV R10, R09 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0740209A" - -# 0x075: CMP R10, 0x1A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0750F1AA" - -# 0x076: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0763A3FF" - -# 0x077: ADD R10, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0771101A" - -# 0x078: MOV R11, R10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "078020AB" - -# 0x079: CMP R11, 0x1B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0790F1BB" - -# 0x07A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07A3A3FF" - -# 0x07B: ADD R11, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07B1101B" - -# 0x07C: MOV R12, R11 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07C020BC" - -# 0x07D: CMP R12, 0x1C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07D0F1CC" - -# 0x07E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07E3A3FF" - -# 0x07F: ADD R12, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "07F1101C" - -# 0x080: MOV R13, R12 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "080020CD" - -# 0x081: CMP R13, 0x1D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0810F1DD" - -# 0x082: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0823A3FF" - -# 0x083: ADD R13, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0831101D" - -# 0x084: MOV R14, R13 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "084020DE" - -# 0x085: CMP R14, 0x1E -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0850F1EE" - -# 0x086: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0863A3FF" - -# 0x087: ADD R14, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0871101E" - -# 0x088: MOV R15, R14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "088020EF" - -# 0x089: CMP R15, 0x1F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0890F1FF" - -# 0x08A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08A3A3FF" - -# 0x08B: ADD R15, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08B1101F" - -# 0x08C: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08C3E000" - -# 0x08D: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08D03000" - -# 0x08E: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08E0F000" - -# 0x08F: JNZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "08F323FF" - -# 0x090: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "090333FF" - -# 0x091: CMP R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0910F000" - -# 0x092: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0923A3FF" - -# 0x093: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "093353FF" - -# 0x094: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "094363FF" - -# 0x095: JLE 0x097 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09537097" - -# 0x096: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "096303FF" - -# 0x097: JEQ 0x099 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09739099" - -# 0x098: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "098303FF" - -# 0x099: JGE 0x09B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0993809B" - -# 0x09A: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09A303FF" - -# 0x09B: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09B0F550" - -# 0x09C: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09C393FF" - -# 0x09D: JLT 0x09F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09D3509F" - -# 0x09E: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09E303FF" - -# 0x09F: JLE 0x0A1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "09F370A1" - -# 0x0A0: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A0303FF" - -# 0x0A1: JGE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A1383FF" - -# 0x0A2: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A2363FF" - -# 0x0A3: MOV R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A303550" - -# 0x0A4: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A40F000" - -# 0x0A5: JZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A5313FF" - -# 0x0A6: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A6333FF" - -# 0x0A7: CMP R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A70FAA0" - -# 0x0A8: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A8393FF" - -# 0x0A9: JNE 0x0AB -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0A93A0AB" - -# 0x0AA: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AA303FF" - -# 0x0AB: JLT 0x0AD -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AB350AD" - -# 0x0AC: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AC303FF" - -# 0x0AD: JLE 0x0AF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AD370AF" - -# 0x0AE: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AE303FF" - -# 0x0AF: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0AF363FF" - -# 0x0B0: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B00F550" - -# 0x0B1: JEQ 0x0B3 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B1390B3" - -# 0x0B2: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B2303FF" - -# 0x0B3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B33A3FF" - -# 0x0B4: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B4353FF" - -# 0x0B5: JLE 0x0B7 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B5370B7" - -# 0x0B6: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B6303FF" - -# 0x0B7: JGT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B7363FF" - -# 0x0B8: JGE 0x0BA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B8380BA" - -# 0x0B9: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0B9303FF" - -# 0x0BA: MOV R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BA03AA0" - -# 0x0BB: TST R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BB0F000" - -# 0x0BC: JZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BC313FF" - -# 0x0BD: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BD333FF" - -# 0x0BE: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BE0F550" - -# 0x0BF: JEQ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0BF393FF" - -# 0x0C0: JNE 0x0C2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C03A0C2" - -# 0x0C1: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C1303FF" - -# 0x0C2: JGT 0x0C4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C2360C4" - -# 0x0C3: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C3303FF" - -# 0x0C4: JGE 0x0C6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C4380C6" - -# 0x0C5: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C5303FF" - -# 0x0C6: JLT 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C6353FF" - -# 0x0C7: JLE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C7373FF" - -# 0x0C8: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C83E000" - -# 0x0C9: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0C903000" - -# 0x0CA: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CA03001" - -# 0x0CB: MOV R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CB02002" - -# 0x0CC: MOV R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CC02013" - -# 0x0CD: ADD R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CD11010" - -# 0x0CE: ADDC R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CE13001" - -# 0x0CF: ADD R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0CF11012" - -# 0x0D0: CMP R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D00F002" - -# 0x0D1: JNE 0x0D4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D13A0D4" - -# 0x0D2: ADD R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D211013" - -# 0x0D3: CMP R03, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D30F023" - -# 0x0D4: JNE 0x0CD -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D43A0CD" - -# 0x0D5: CMP R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D50E020" - -# 0x0D6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D63A3FF" - -# 0x0D7: CMP R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D70E031" - -# 0x0D8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D83A3FF" - -# 0x0D9: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0D903000" - -# 0x0DA: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DA3E000" - -# 0x0DB: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DB03000" - -# 0x0DC: MOV R01, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DC03031" - -# 0x0DD: MOV R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DD02002" - -# 0x0DE: MOV R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DE02013" - -# 0x0DF: SUB R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0DF15010" - -# 0x0E0: SUBC R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E017001" - -# 0x0E1: SUB R02, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E115012" - -# 0x0E2: CMP R02, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E20FFF2" - -# 0x0E3: JNE 0x0E6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E33A0E6" - -# 0x0E4: SUB R03, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E415013" - -# 0x0E5: CMP R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E50F003" - -# 0x0E6: JNE 0x0DF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E63A0DF" - -# 0x0E7: CMP R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E70E020" - -# 0x0E8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E83A3FF" - -# 0x0E9: CMP R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0E90E031" - -# 0x0EA: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EA3A3FF" - -# 0x0EB: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EB03000" - -# 0x0EC: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EC3E000" - -# 0x0ED: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0ED03030" - -# 0x0EE: MOV R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EE03051" - -# 0x0EF: SUB 0x05, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0EF2E050" - -# 0x0F0: SUB R01, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F015031" - -# 0x0F1: CMP R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F10E010" - -# 0x0F2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F23A3FF" - -# 0x0F3: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F303030" - -# 0x0F4: MOV R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F403051" - -# 0x0F5: SUB R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F514010" - -# 0x0F6: SUBC 0x00, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F62F000" - -# 0x0F7: CMP R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F70F010" - -# 0x0F8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F83A3FF" - -# 0x0F9: ADD R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0F911000" - -# 0x0FA: SUBC R01, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FA16001" - -# 0x0FB: CMP R01, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FB0F041" - -# 0x0FC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FC3A3FF" - -# 0x0FD: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FD03000" - -# 0x0FE: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FE3E000" - -# 0x0FF: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0FF03010" - -# 0x100: MOVC (0x5A), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1000D5A0" - -# 0x101: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10115010" - -# 0x102: MOVC (0x00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1020D000" - -# 0x103: MOVC R01, (0x5A) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1030A5A1" - -# 0x104: MOVC (R01), 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1040CA51" - -# 0x105: MOVC R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10509010" - -# 0x106: MOVC R01, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10609011" - -# 0x107: ADD R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "107115A1" - -# 0x108: MOVC R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10809010" - -# 0x109: MOVC (R00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1090B000" - -# 0x10A: MOVC R02, (R00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10A09002" - -# 0x10B: CMP R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10B0E002" - -# 0x10C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10C3A3FF" - -# 0x10D: MOVC (R01), R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10D0B021" - -# 0x10E: MOVC R02, (R02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10E09022" - -# 0x10F: CMP R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "10F0E012" - -# 0x110: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1103A3FF" - -# 0x111: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11115011" - -# 0x112: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11211010" - -# 0x113: JNZ 0x109 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11332109" - -# 0x114: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1143E000" - -# 0x115: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11503010" - -# 0x116: MOVX (0x60), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11608600" - -# 0x117: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11715010" - -# 0x118: MOVX (0x06), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11808060" - -# 0x119: MOVX R01, (0x60) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11905601" - -# 0x11A: MOVX (R01), 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11A07A51" - -# 0x11B: MOVX R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11B04010" - -# 0x11C: MOVX R01, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11C04011" - -# 0x11D: ADD R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11D115A1" - -# 0x11E: MOVX R00, (R01) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11E04010" - -# 0x11F: MOVX (R00), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "11F06000" - -# 0x120: MOVX R02, (R00) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12004002" - -# 0x121: CMP R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1210E002" - -# 0x122: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1223A3FF" - -# 0x123: MOVX (R01), R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12306021" - -# 0x124: MOVX R02, (R02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12404022" - -# 0x125: CMP R02, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1250E012" - -# 0x126: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1263A3FF" - -# 0x127: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12715011" - -# 0x128: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12811010" - -# 0x129: JNZ 0x11F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1293211F" - -# 0x12A: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12A3E000" - -# 0x12B: MOV R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12B03AA0" - -# 0x12C: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12C03001" - -# 0x12D: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12D3C000" - -# 0x12E: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12E11010" - -# 0x12F: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "12F15011" - -# 0x130: JNZ 0x12D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1303212D" - -# 0x131: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1313D000" - -# 0x132: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13215011" - -# 0x133: JNZ 0x131 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13332131" - -# 0x134: CMP R00, 0xAA -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1340FAA0" - -# 0x135: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1353A3FF" - -# 0x136: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1363E000" - -# 0x137: MOV R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13703550" - -# 0x138: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1383C000" - -# 0x139: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13903000" - -# 0x13A: MOV R01, 0xFF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13A03FF1" - -# 0x13B: CALL 0x151 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13B3B151" - -# 0x13C: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13C3D000" - -# 0x13D: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13D0F550" - -# 0x13E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13E3A3FF" - -# 0x13F: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "13F03010" - -# 0x140: MOV R01, 0x48 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14003481" - -# 0x141: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14126050" - -# 0x142: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1423C001" - -# 0x143: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14303000" - -# 0x144: MOV R01, 0x3B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "144033B1" - -# 0x145: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14526050" - -# 0x146: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1463C001" - -# 0x147: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1473E000" - -# 0x148: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14803010" - -# 0x149: MOV R01, 0x50 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14903501" - -# 0x14A: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14A26050" - -# 0x14B: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14B3C001" - -# 0x14C: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14C03000" - -# 0x14D: MOV R01, 0x3B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14D033B1" - -# 0x14E: COUT (0x05), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14E26050" - -# 0x14F: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "14F3C001" - -# 0x150: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1503E000" - -# 0x151: CMP R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1510E010" - -# 0x152: JEQ 0x155 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15239155" - -# 0x153: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15311010" - -# 0x154: JMP 0x158 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15430158" - -# 0x155: DEC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15515010" - -# 0x156: DEC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15615011" - -# 0x157: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1573E000" - -# 0x158: CALL 0x151 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1583B151" - -# 0x159: JMP 0x155 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15930155" - -# 0x15A: MOV R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15A03A50" - -# 0x15B: MOV R01, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15B035A1" - -# 0x15C: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15C2A000" - -# 0x15D: CMP R00, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15D0F5A0" - -# 0x15E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15E3A3FF" - -# 0x15F: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "15F2A000" - -# 0x160: CMP R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1600FA50" - -# 0x161: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1613A3FF" - -# 0x162: MOV R00, 0xD2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16203D20" - -# 0x163: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1632A000" - -# 0x164: CMP R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1640F2D0" - -# 0x165: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1653A3FF" - -# 0x166: SWAP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1662A001" - -# 0x167: CMP R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1670F2D0" - -# 0x168: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1683A3FF" - -# 0x169: CMP R01, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1690FA51" - -# 0x16A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16A3A3FF" - -# 0x16B: MOV R00, 0x2D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16B032D0" - -# 0x16C: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16C1E000" - -# 0x16D: CMP R00, 0x5A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16D0F5A0" - -# 0x16E: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16E3A3FF" - -# 0x16F: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "16F1E000" - -# 0x170: CMP R00, 0xB4 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1700FB40" - -# 0x171: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1713A3FF" - -# 0x172: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1721E000" - -# 0x173: CMP R00, 0x68 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1730F680" - -# 0x174: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1743A3FF" - -# 0x175: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1751E000" - -# 0x176: CMP R00, 0xD0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1760FD00" - -# 0x177: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1773A3FF" - -# 0x178: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1781E000" - -# 0x179: CMP R00, 0xA0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1790FA00" - -# 0x17A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17A3A3FF" - -# 0x17B: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17B1E000" - -# 0x17C: CMP R00, 0x40 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17C0F400" - -# 0x17D: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17D3A3FF" - -# 0x17E: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17E1E000" - -# 0x17F: CMP R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "17F0F800" - -# 0x180: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1803A3FF" - -# 0x181: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1811E000" - -# 0x182: CMP R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1820F000" - -# 0x183: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1833A3FF" - -# 0x184: MOV R01, 0x84 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18403841" - -# 0x185: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1851F001" - -# 0x186: CMP R01, 0x42 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1860F421" - -# 0x187: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1873A3FF" - -# 0x188: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1881F001" - -# 0x189: CMP R01, 0x21 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1890F211" - -# 0x18A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18A3A3FF" - -# 0x18B: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18B1F001" - -# 0x18C: CMP R01, 0x10 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18C0F101" - -# 0x18D: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18D3A3FF" - -# 0x18E: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18E1F001" - -# 0x18F: CMP R01, 0x08 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "18F0F081" - -# 0x190: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1903A3FF" - -# 0x191: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1911F001" - -# 0x192: CMP R01, 0x04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1920F041" - -# 0x193: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1933A3FF" - -# 0x194: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1941F001" - -# 0x195: CMP R01, 0x02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1950F021" - -# 0x196: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1963A3FF" - -# 0x197: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1971F001" - -# 0x198: CMP R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1980F011" - -# 0x199: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1993A3FF" - -# 0x19A: SHR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19A1F001" - -# 0x19B: CMP R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19B0F001" - -# 0x19C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19C3A3FF" - -# 0x19D: MOV R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19D03C50" - -# 0x19E: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19E20000" - -# 0x19F: CMP R00, 0x8B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "19F0F8B0" - -# 0x1A0: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A03A3FF" - -# 0x1A1: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A120000" - -# 0x1A2: CMP R00, 0x17 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A20F170" - -# 0x1A3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A33A3FF" - -# 0x1A4: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A420000" - -# 0x1A5: CMP R00, 0x2E -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A50F2E0" - -# 0x1A6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A63A3FF" - -# 0x1A7: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A720000" - -# 0x1A8: CMP R00, 0x5C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A80F5C0" - -# 0x1A9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1A93A3FF" - -# 0x1AA: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AA20000" - -# 0x1AB: CMP R00, 0xB8 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AB0FB80" - -# 0x1AC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AC3A3FF" - -# 0x1AD: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AD20000" - -# 0x1AE: CMP R00, 0x71 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AE0F710" - -# 0x1AF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1AF3A3FF" - -# 0x1B0: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B020000" - -# 0x1B1: CMP R00, 0xE2 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B10FE20" - -# 0x1B2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B23A3FF" - -# 0x1B3: ROL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B320000" - -# 0x1B4: CMP R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B40FC50" - -# 0x1B5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B53A3FF" - -# 0x1B6: MOV R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B603631" - -# 0x1B7: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B721001" - -# 0x1B8: CMP R01, 0xB1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B80FB11" - -# 0x1B9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1B93A3FF" - -# 0x1BA: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BA21001" - -# 0x1BB: CMP R01, 0xD8 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BB0FD81" - -# 0x1BC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BC3A3FF" - -# 0x1BD: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BD21001" - -# 0x1BE: CMP R01, 0x6C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BE0F6C1" - -# 0x1BF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1BF3A3FF" - -# 0x1C0: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C021001" - -# 0x1C1: CMP R01, 0x36 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C10F361" - -# 0x1C2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C23A3FF" - -# 0x1C3: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C321001" - -# 0x1C4: CMP R01, 0x1B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C40F1B1" - -# 0x1C5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C53A3FF" - -# 0x1C6: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C621001" - -# 0x1C7: CMP R01, 0x8D -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C70F8D1" - -# 0x1C8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C83A3FF" - -# 0x1C9: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1C921001" - -# 0x1CA: CMP R01, 0xC6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CA0FC61" - -# 0x1CB: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CB3A3FF" - -# 0x1CC: ROR R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CC21001" - -# 0x1CD: CMP R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CD0F631" - -# 0x1CE: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CE3A3FF" - -# 0x1CF: XOR R00, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1CF1C000" - -# 0x1D0: MOV R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D003C50" - -# 0x1D1: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D122000" - -# 0x1D2: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D23C000" - -# 0x1D3: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D322000" - -# 0x1D4: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D43C000" - -# 0x1D5: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D522000" - -# 0x1D6: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D63C000" - -# 0x1D7: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D722000" - -# 0x1D8: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D83C000" - -# 0x1D9: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1D922000" - -# 0x1DA: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DA3C000" - -# 0x1DB: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DB22000" - -# 0x1DC: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DC3C000" - -# 0x1DD: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DD22000" - -# 0x1DE: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DE3C000" - -# 0x1DF: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1DF22000" - -# 0x1E0: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E03C000" - -# 0x1E1: ROLC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E122000" - -# 0x1E2: CMP R00, 0xC5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E20FC50" - -# 0x1E3: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E33A3FF" - -# 0x1E4: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E43D000" - -# 0x1E5: CMP R00, 0x62 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E50F620" - -# 0x1E6: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E63A3FF" - -# 0x1E7: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E73D000" - -# 0x1E8: CMP R00, 0xB1 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E80FB10" - -# 0x1E9: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1E93A3FF" - -# 0x1EA: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EA3D000" - -# 0x1EB: CMP R00, 0x58 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EB0F580" - -# 0x1EC: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EC3A3FF" - -# 0x1ED: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1ED3D000" - -# 0x1EE: CMP R00, 0xAC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EE0FAC0" - -# 0x1EF: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1EF3A3FF" - -# 0x1F0: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F03D000" - -# 0x1F1: CMP R00, 0x56 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F10F560" - -# 0x1F2: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F23A3FF" - -# 0x1F3: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F33D000" - -# 0x1F4: CMP R00, 0x2B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F40F2B0" - -# 0x1F5: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F53A3FF" - -# 0x1F6: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F63D000" - -# 0x1F7: CMP R00, 0x15 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F70F150" - -# 0x1F8: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F83A3FF" - -# 0x1F9: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1F93D000" - -# 0x1FA: CMP R00, 0x8A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FA0F8A0" - -# 0x1FB: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FB3A3FF" - -# 0x1FC: XOR R01, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FC1C011" - -# 0x1FD: MOV R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FD03631" - -# 0x1FE: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FE23001" - -# 0x1FF: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "1FF3C001" - -# 0x200: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20023001" - -# 0x201: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2013C001" - -# 0x202: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20223001" - -# 0x203: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2033C001" - -# 0x204: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20423001" - -# 0x205: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2053C001" - -# 0x206: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20623001" - -# 0x207: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2073C001" - -# 0x208: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20823001" - -# 0x209: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2093C001" - -# 0x20A: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20A23001" - -# 0x20B: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20B3C001" - -# 0x20C: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20C23001" - -# 0x20D: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20D3C001" - -# 0x20E: RORC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20E23001" - -# 0x20F: CMP R01, 0x63 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "20F0F631" - -# 0x210: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2103A3FF" - -# 0x211: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2113D001" - -# 0x212: CMP R01, 0xC6 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2120FC61" - -# 0x213: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2133A3FF" - -# 0x214: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2143D001" - -# 0x215: CMP R01, 0x8C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2150F8C1" - -# 0x216: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2163A3FF" - -# 0x217: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2173D001" - -# 0x218: CMP R01, 0x19 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2180F191" - -# 0x219: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2193A3FF" - -# 0x21A: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21A3D001" - -# 0x21B: CMP R01, 0x33 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21B0F331" - -# 0x21C: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21C3A3FF" - -# 0x21D: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21D3D001" - -# 0x21E: CMP R01, 0x66 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21E0F661" - -# 0x21F: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "21F3A3FF" - -# 0x220: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2203D001" - -# 0x221: CMP R01, 0xCC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2210FCC1" - -# 0x222: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2223A3FF" - -# 0x223: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2233D001" - -# 0x224: CMP R01, 0x98 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2240F981" - -# 0x225: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2253A3FF" - -# 0x226: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2263D001" - -# 0x227: CMP R01, 0x31 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2270F311" - -# 0x228: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2283A3FF" - -# 0x229: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2293E000" - -# 0x22A: MOV R00, 0xA5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22A03A50" - -# 0x22B: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22B2A000" - -# 0x22C: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22C3C000" - -# 0x22D: AND R00, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22D190F0" - -# 0x22E: CMP R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22E0F0A0" - -# 0x22F: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "22F3A3FF" - -# 0x230: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2303D000" - -# 0x231: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2313C000" - -# 0x232: AND R00, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "232190F0" - -# 0x233: CMP R00, 0x0A -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2330F0A0" - -# 0x234: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2343D001" - -# 0x235: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2353A3FF" - -# 0x236: SWAP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2362A001" - -# 0x237: MOV R02, 0x0F -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "237030F2" - -# 0x238: AND R01, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23818021" - -# 0x239: CMP R01, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2390F051" - -# 0x23A: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23A3A3FF" - -# 0x23B: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23B03050" - -# 0x23C: MOV R02, 0xA0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23C03A02" - -# 0x23D: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23D2A000" - -# 0x23E: OR R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23E1A002" - -# 0x23F: CMP R02, 0xF0 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "23F0FF02" - -# 0x240: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2403A3FF" - -# 0x241: SWAP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2412A000" - -# 0x242: OR R00, 0x50 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2421B500" - -# 0x243: CMP R00, 0x55 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2430F550" - -# 0x244: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2443A3FF" - -# 0x245: MOV R01, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24503011" - -# 0x246: MOV R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24603010" - -# 0x247: XOR R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2471D010" - -# 0x248: JNZ 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "248323FF" - -# 0x249: XOR R00, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2491C010" - -# 0x24A: CMP R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24A0F010" - -# 0x24B: JNE 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24B3A3FF" - -# 0x24C: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24C3E000" - -# 0x24D: MOV R00, 0x03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24D03030" - -# 0x24E: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24E26030" - -# 0x24F: XIN R00, (0x02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "24F28020" - -# 0x250: OR R00, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2501B010" - -# 0x251: XOUT (0x02), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25124020" - -# 0x252: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25200000" - -# 0x253: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25300000" - -# 0x254: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25400000" - -# 0x255: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25500000" - -# 0x256: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25600000" - -# 0x257: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25700000" - -# 0x258: XIN R00, (0x02) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25828020" - -# 0x259: AND R00, 0xFE -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25919FE0" - -# 0x25A: XOUT (0x02), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25A24020" - -# 0x25B: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25B00000" - -# 0x25C: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25C00000" - -# 0x25D: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25D00000" - -# 0x25E: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25E00000" - -# 0x25F: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "25F29030" - -# 0x260: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2601B800" - -# 0x261: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26126030" - -# 0x262: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26200000" - -# 0x263: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26329030" - -# 0x264: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2641B800" - -# 0x265: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26526030" - -# 0x266: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26600000" - -# 0x267: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26729030" - -# 0x268: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2681B800" - -# 0x269: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26926030" - -# 0x26A: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26A00000" - -# 0x26B: CIN R00, (0x03) -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26B29030" - -# 0x26C: OR R00, 0x80 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26C1B800" - -# 0x26D: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26D26030" - -# 0x26E: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26E00000" - -# 0x26F: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "26F00000" - -# 0x270: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27000000" - -# 0x271: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27100000" - -# 0x272: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27200000" - -# 0x273: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27300000" - -# 0x274: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27400000" - -# 0x275: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27500000" - -# 0x276: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27600000" - -# 0x277: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2773E000" - -# 0x278: SUB R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27815000" - -# 0x279: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "279333FF" - -# 0x27A: SETC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27A2B000" - -# 0x27B: JNC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27B343FF" - -# 0x27C: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27C00000" - -# 0x27D: SUB R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27D15000" - -# 0x27E: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27E333FF" - -# 0x27F: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "27F03000" - -# 0x280: CLRC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28015000" - -# 0x281: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "281333FF" - -# 0x282: SETC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2822B000" - -# 0x283: JNC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "283343FF" - -# 0x284: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28400000" - -# 0x285: CLRC -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28515000" - -# 0x286: JC 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "286333FF" - -# 0x287: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2873E000" - -# 0x288: INC R14 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2881101E" - -# 0x289: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2893F000" - -# 0x28A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28A00000" - -# 0x28B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28B00000" - -# 0x28C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28C00000" - -# 0x28D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28D00000" - -# 0x28E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28E00000" - -# 0x28F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "28F00000" - -# 0x290: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29000000" - -# 0x291: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29100000" - -# 0x292: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29200000" - -# 0x293: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29300000" - -# 0x294: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29400000" - -# 0x295: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29500000" - -# 0x296: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29600000" - -# 0x297: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29700000" - -# 0x298: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29800000" - -# 0x299: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29900000" - -# 0x29A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29A00000" - -# 0x29B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29B00000" - -# 0x29C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29C00000" - -# 0x29D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29D00000" - -# 0x29E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29E00000" - -# 0x29F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "29F00000" - -# 0x2A0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A000000" - -# 0x2A1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A100000" - -# 0x2A2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A200000" - -# 0x2A3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A300000" - -# 0x2A4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A400000" - -# 0x2A5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A500000" - -# 0x2A6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A600000" - -# 0x2A7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A700000" - -# 0x2A8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A800000" - -# 0x2A9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2A900000" - -# 0x2AA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AA00000" - -# 0x2AB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AB00000" - -# 0x2AC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AC00000" - -# 0x2AD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AD00000" - -# 0x2AE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AE00000" - -# 0x2AF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2AF00000" - -# 0x2B0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B000000" - -# 0x2B1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B100000" - -# 0x2B2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B200000" - -# 0x2B3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B300000" - -# 0x2B4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B400000" - -# 0x2B5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B500000" - -# 0x2B6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B600000" - -# 0x2B7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B700000" - -# 0x2B8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B800000" - -# 0x2B9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2B900000" - -# 0x2BA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BA00000" - -# 0x2BB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BB00000" - -# 0x2BC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BC00000" - -# 0x2BD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BD00000" - -# 0x2BE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BE00000" - -# 0x2BF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2BF00000" - -# 0x2C0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C000000" - -# 0x2C1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C100000" - -# 0x2C2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C200000" - -# 0x2C3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C300000" - -# 0x2C4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C400000" - -# 0x2C5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C500000" - -# 0x2C6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C600000" - -# 0x2C7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C700000" - -# 0x2C8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C800000" - -# 0x2C9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2C900000" - -# 0x2CA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CA00000" - -# 0x2CB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CB00000" - -# 0x2CC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CC00000" - -# 0x2CD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CD00000" - -# 0x2CE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CE00000" - -# 0x2CF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2CF00000" - -# 0x2D0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D000000" - -# 0x2D1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D100000" - -# 0x2D2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D200000" - -# 0x2D3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D300000" - -# 0x2D4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D400000" - -# 0x2D5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D500000" - -# 0x2D6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D600000" - -# 0x2D7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D700000" - -# 0x2D8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D800000" - -# 0x2D9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2D900000" - -# 0x2DA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DA00000" - -# 0x2DB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DB00000" - -# 0x2DC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DC00000" - -# 0x2DD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DD00000" - -# 0x2DE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DE00000" - -# 0x2DF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2DF00000" - -# 0x2E0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E000000" - -# 0x2E1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E100000" - -# 0x2E2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E200000" - -# 0x2E3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E300000" - -# 0x2E4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E400000" - -# 0x2E5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E500000" - -# 0x2E6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E600000" - -# 0x2E7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E700000" - -# 0x2E8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E800000" - -# 0x2E9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2E900000" - -# 0x2EA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EA00000" - -# 0x2EB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EB00000" - -# 0x2EC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EC00000" - -# 0x2ED: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2ED00000" - -# 0x2EE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EE00000" - -# 0x2EF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2EF00000" - -# 0x2F0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F000000" - -# 0x2F1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F100000" - -# 0x2F2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F200000" - -# 0x2F3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F300000" - -# 0x2F4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F400000" - -# 0x2F5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F500000" - -# 0x2F6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F600000" - -# 0x2F7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F700000" - -# 0x2F8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F800000" - -# 0x2F9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2F900000" - -# 0x2FA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FA00000" - -# 0x2FB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FB00000" - -# 0x2FC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FC00000" - -# 0x2FD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FD00000" - -# 0x2FE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FE00000" - -# 0x2FF: JMP 0x2FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "2FF302FF" - -# 0x300: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30000000" - -# 0x301: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30100000" - -# 0x302: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30200000" - -# 0x303: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30300000" - -# 0x304: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30400000" - -# 0x305: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30500000" - -# 0x306: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30600000" - -# 0x307: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30700000" - -# 0x308: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30800000" - -# 0x309: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30900000" - -# 0x30A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30A00000" - -# 0x30B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30B00000" - -# 0x30C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30C00000" - -# 0x30D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30D00000" - -# 0x30E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30E00000" - -# 0x30F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "30F00000" - -# 0x310: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31000000" - -# 0x311: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31100000" - -# 0x312: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31200000" - -# 0x313: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31300000" - -# 0x314: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31400000" - -# 0x315: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31500000" - -# 0x316: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31600000" - -# 0x317: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31700000" - -# 0x318: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31800000" - -# 0x319: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31900000" - -# 0x31A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31A00000" - -# 0x31B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31B00000" - -# 0x31C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31C00000" - -# 0x31D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31D00000" - -# 0x31E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31E00000" - -# 0x31F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "31F00000" - -# 0x320: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32000000" - -# 0x321: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32100000" - -# 0x322: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32200000" - -# 0x323: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32300000" - -# 0x324: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32400000" - -# 0x325: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32500000" - -# 0x326: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32600000" - -# 0x327: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32700000" - -# 0x328: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32800000" - -# 0x329: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32900000" - -# 0x32A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32A00000" - -# 0x32B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32B00000" - -# 0x32C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32C00000" - -# 0x32D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32D00000" - -# 0x32E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32E00000" - -# 0x32F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "32F00000" - -# 0x330: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33000000" - -# 0x331: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33100000" - -# 0x332: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33200000" - -# 0x333: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33300000" - -# 0x334: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33400000" - -# 0x335: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33500000" - -# 0x336: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33600000" - -# 0x337: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33700000" - -# 0x338: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33800000" - -# 0x339: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33900000" - -# 0x33A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33A00000" - -# 0x33B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33B00000" - -# 0x33C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33C00000" - -# 0x33D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33D00000" - -# 0x33E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33E00000" - -# 0x33F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "33F00000" - -# 0x340: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34000000" - -# 0x341: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34100000" - -# 0x342: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34200000" - -# 0x343: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34300000" - -# 0x344: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34400000" - -# 0x345: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34500000" - -# 0x346: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34600000" - -# 0x347: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34700000" - -# 0x348: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34800000" - -# 0x349: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34900000" - -# 0x34A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34A00000" - -# 0x34B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34B00000" - -# 0x34C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34C00000" - -# 0x34D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34D00000" - -# 0x34E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34E00000" - -# 0x34F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "34F00000" - -# 0x350: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35000000" - -# 0x351: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35100000" - -# 0x352: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35200000" - -# 0x353: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35300000" - -# 0x354: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35400000" - -# 0x355: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35500000" - -# 0x356: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35600000" - -# 0x357: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35700000" - -# 0x358: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35800000" - -# 0x359: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35900000" - -# 0x35A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35A00000" - -# 0x35B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35B00000" - -# 0x35C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35C00000" - -# 0x35D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35D00000" - -# 0x35E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35E00000" - -# 0x35F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "35F00000" - -# 0x360: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36000000" - -# 0x361: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36100000" - -# 0x362: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36200000" - -# 0x363: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36300000" - -# 0x364: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36400000" - -# 0x365: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36500000" - -# 0x366: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36600000" - -# 0x367: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36700000" - -# 0x368: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36800000" - -# 0x369: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36900000" - -# 0x36A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36A00000" - -# 0x36B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36B00000" - -# 0x36C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36C00000" - -# 0x36D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36D00000" - -# 0x36E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36E00000" - -# 0x36F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "36F00000" - -# 0x370: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37000000" - -# 0x371: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37100000" - -# 0x372: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37200000" - -# 0x373: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37300000" - -# 0x374: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37400000" - -# 0x375: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37500000" - -# 0x376: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37600000" - -# 0x377: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37700000" - -# 0x378: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37800000" - -# 0x379: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37900000" - -# 0x37A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37A00000" - -# 0x37B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37B00000" - -# 0x37C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37C00000" - -# 0x37D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37D00000" - -# 0x37E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37E00000" - -# 0x37F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "37F00000" - -# 0x380: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38000000" - -# 0x381: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38100000" - -# 0x382: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38200000" - -# 0x383: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38300000" - -# 0x384: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38400000" - -# 0x385: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38500000" - -# 0x386: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38600000" - -# 0x387: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38700000" - -# 0x388: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38800000" - -# 0x389: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38900000" - -# 0x38A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38A00000" - -# 0x38B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38B00000" - -# 0x38C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38C00000" - -# 0x38D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38D00000" - -# 0x38E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38E00000" - -# 0x38F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "38F00000" - -# 0x390: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39000000" - -# 0x391: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39100000" - -# 0x392: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39200000" - -# 0x393: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39300000" - -# 0x394: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39400000" - -# 0x395: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39500000" - -# 0x396: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39600000" - -# 0x397: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39700000" - -# 0x398: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39800000" - -# 0x399: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39900000" - -# 0x39A: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39A00000" - -# 0x39B: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39B00000" - -# 0x39C: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39C00000" - -# 0x39D: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39D00000" - -# 0x39E: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39E00000" - -# 0x39F: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "39F00000" - -# 0x3A0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A000000" - -# 0x3A1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A100000" - -# 0x3A2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A200000" - -# 0x3A3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A300000" - -# 0x3A4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A400000" - -# 0x3A5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A500000" - -# 0x3A6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A600000" - -# 0x3A7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A700000" - -# 0x3A8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A800000" - -# 0x3A9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3A900000" - -# 0x3AA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AA00000" - -# 0x3AB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AB00000" - -# 0x3AC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AC00000" - -# 0x3AD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AD00000" - -# 0x3AE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AE00000" - -# 0x3AF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3AF00000" - -# 0x3B0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B000000" - -# 0x3B1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B100000" - -# 0x3B2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B200000" - -# 0x3B3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B300000" - -# 0x3B4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B400000" - -# 0x3B5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B500000" - -# 0x3B6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B600000" - -# 0x3B7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B700000" - -# 0x3B8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B800000" - -# 0x3B9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3B900000" - -# 0x3BA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BA00000" - -# 0x3BB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BB00000" - -# 0x3BC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BC00000" - -# 0x3BD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BD00000" - -# 0x3BE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BE00000" - -# 0x3BF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3BF00000" - -# 0x3C0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C000000" - -# 0x3C1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C100000" - -# 0x3C2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C200000" - -# 0x3C3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C300000" - -# 0x3C4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C400000" - -# 0x3C5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C500000" - -# 0x3C6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C600000" - -# 0x3C7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C700000" - -# 0x3C8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C800000" - -# 0x3C9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3C900000" - -# 0x3CA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CA00000" - -# 0x3CB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CB00000" - -# 0x3CC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CC00000" - -# 0x3CD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CD00000" - -# 0x3CE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CE00000" - -# 0x3CF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3CF00000" - -# 0x3D0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D000000" - -# 0x3D1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D100000" - -# 0x3D2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D200000" - -# 0x3D3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D300000" - -# 0x3D4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D400000" - -# 0x3D5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D500000" - -# 0x3D6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D600000" - -# 0x3D7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D700000" - -# 0x3D8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D800000" - -# 0x3D9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3D900000" - -# 0x3DA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DA00000" - -# 0x3DB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DB00000" - -# 0x3DC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DC00000" - -# 0x3DD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DD00000" - -# 0x3DE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DE00000" - -# 0x3DF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3DF00000" - -# 0x3E0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E000000" - -# 0x3E1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E100000" - -# 0x3E2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E200000" - -# 0x3E3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E300000" - -# 0x3E4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E400000" - -# 0x3E5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E500000" - -# 0x3E6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E600000" - -# 0x3E7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E700000" - -# 0x3E8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E800000" - -# 0x3E9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3E900000" - -# 0x3EA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EA00000" - -# 0x3EB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EB00000" - -# 0x3EC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EC00000" - -# 0x3ED: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3ED00000" - -# 0x3EE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EE00000" - -# 0x3EF: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3EF00000" - -# 0x3F0: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F000000" - -# 0x3F1: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F100000" - -# 0x3F2: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F200000" - -# 0x3F3: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F300000" - -# 0x3F4: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F400000" - -# 0x3F5: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F500000" - -# 0x3F6: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F600000" - -# 0x3F7: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F700000" - -# 0x3F8: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F800000" - -# 0x3F9: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3F900000" - -# 0x3FA: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FA00000" - -# 0x3FB: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FB00000" - -# 0x3FC: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FC00000" - -# 0x3FD: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FD00000" - -# 0x3FE: -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FE00000" - -# 0x3FF: JMP 0x3FF -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "3FF303FF" - -# Assembled from itest.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0048" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0161" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "026C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "036C" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "046F" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "0F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1A00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1B00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1C00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1D00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1E00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "1F00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "2100" -::chipscope::csejtag_tap shift_device_dr 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$CSE_ES 0 16 "C500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "C900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "CF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "D900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "DF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "E900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "ED00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "EF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F500" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F600" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F700" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F800" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "F900" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FA00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FB00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FC00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FD00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FE00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "FF00" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10000" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10100" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10200" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10300" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10400" -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 16 "10500" - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/make b/lib/CPUs/JCpu/asm/make deleted file mode 100644 index e7f598f..0000000 --- a/lib/CPUs/JCpu/asm/make +++ /dev/null @@ -1,50 +0,0 @@ -#!/bin/sh - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: rom-file generation for cpu_core -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -TARGET=$2 -DSTDIR=$1 - -JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools - -$JASM_HOME/jasm.rb $TARGET.jsm - -irom_tcl_snippet="$TARGET.irom.tcl.snip" -irom_vhdl_snippet="$TARGET.irom.vhdl.snip" -irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip" -xrom_tcl_snippet="$TARGET.xrom.tcl.snip" -xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip" -xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip" - -$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl -$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl - -$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl -$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl - -cat $irom_tcl_snippet > $TARGET.tcl.snip.snip -cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip -$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl - -rm -f *.snip diff --git a/lib/CPUs/JCpu/asm/mul8x8.jsm b/lib/CPUs/JCpu/asm/mul8x8.jsm deleted file mode 100644 index c9b6c3b..0000000 --- a/lib/CPUs/JCpu/asm/mul8x8.jsm +++ /dev/null @@ -1,29 +0,0 @@ -; ------------------------------------------------- -; Constants -; ------------------------------------------------- - -; Chip register -include "../../../jasm/cregs.inc.jsm" - -; ------------------------------------------------- -; Program -; ------------------------------------------------- - code - org 0x000 -reset: jmp init - -; ------------------------------------------------- -; Main -; ------------------------------------------------- -init: mov R0, 0x45 - mov R1, 0xF5 - - call mul8x8 -stop: jmp stop - - -; ------------------------------------------------- -include "../../../jasm/mul8x8.inc.jsm" - - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/asm/mul8x8.tcl b/lib/CPUs/JCpu/asm/mul8x8.tcl deleted file mode 100644 index 6bec87e..0000000 --- a/lib/CPUs/JCpu/asm/mul8x8.tcl +++ /dev/null @@ -1,154 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from mul8x8.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x001 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030001" - -# 0x001: MOV R00, 0x45 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00103450" - -# 0x002: MOV R01, 0xF5 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203F51" - -# 0x003: CALL 0x005 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0033B005" - -# 0x004: JMP 0x004 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00430004" - -# 0x005: PUSH R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0053C002" - -# 0x006: PUSH R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0063C003" - -# 0x007: PUSH R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0073C004" - -# 0x008: MOV R04, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00802014" - -# 0x009: MOV R01, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00903001" - -# 0x00A: MOV R02, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A03002" - -# 0x00B: MOV R03, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B03003" - -# 0x00C: CMP R04, 0x01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C0F014" - -# 0x00D: JEQ 0x015 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D39015" - -# 0x00E: SHR R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E1F004" - -# 0x00F: JNC 0x012 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F34012" - -# 0x010: ADD R02, R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01010002" - -# 0x011: ADDC R03, R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01112013" - -# 0x012: SHL R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0121E000" - -# 0x013: ROLC R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01322001" - -# 0x014: JMP 0x00C -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143000C" - -# 0x015: ADD R00, R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01510020" - -# 0x016: ADDC R01, R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01612031" - -# 0x017: POP R04 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0173D004" - -# 0x018: POP R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003" - -# 0x019: POP R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0193D002" - -# 0x01A: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A3E000" - -# Assembled from mul8x8.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/asm/reti_issue.jsm b/lib/CPUs/JCpu/asm/reti_issue.jsm deleted file mode 100644 index 78edc49..0000000 --- a/lib/CPUs/JCpu/asm/reti_issue.jsm +++ /dev/null @@ -1,50 +0,0 @@ -; ------------------------------------------------- -; Constants -; ------------------------------------------------- - -; Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; R/W - -; ------------------------------------------------- -; Program -; ------------------------------------------------- - code -reset: jmp init - - org 0x001 -; nop - reti - -; ------------------------------------------------- -; Main -; ------------------------------------------------- -init: mov R0, 0x05 - cout (cpu_int_ctrl), R0 - mov R0, 0x00 -loop: nop - inc R0 - nop - call subr - nop - push R3 - nop - push R2 - nop - push R1 - nop - push R0 - nop - pop R0 - nop - pop R1 - nop - pop R2 - nop - pop R3 - nop - jmp loop - -subr: ret diff --git a/lib/CPUs/JCpu/asm/reti_issue.tcl b/lib/CPUs/JCpu/asm/reti_issue.tcl deleted file mode 100644 index 5da9c56..0000000 --- a/lib/CPUs/JCpu/asm/reti_issue.tcl +++ /dev/null @@ -1,157 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE -# Assembled from reti_issue.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000010) into the Instruction Register of FPGA -# User 1 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C2"] - -# 0x000: JMP 0x002 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00030002" - -# 0x001: RETI -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0013F000" - -# 0x002: MOV R00, 0x05 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00203050" - -# 0x003: COUT (0x03), R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00326030" - -# 0x004: MOV R00, 0x00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00403000" - -# 0x005: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00500000" - -# 0x006: INC R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00611010" - -# 0x007: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00700000" - -# 0x008: CALL 0x01B -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0083B01B" - -# 0x009: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00900000" - -# 0x00A: PUSH R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00A3C003" - -# 0x00B: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00B00000" - -# 0x00C: PUSH R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00C3C002" - -# 0x00D: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00D00000" - -# 0x00E: PUSH R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00E3C001" - -# 0x00F: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "00F00000" - -# 0x010: PUSH R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0103C000" - -# 0x011: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01100000" - -# 0x012: POP R00 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0123D000" - -# 0x013: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01300000" - -# 0x014: POP R01 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0143D001" - -# 0x015: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01500000" - -# 0x016: POP R02 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0163D002" - -# 0x017: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01700000" - -# 0x018: POP R03 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "0183D003" - -# 0x019: NOP -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01900000" - -# 0x01A: JMP 0x005 -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01A30005" - -# 0x01B: RET -::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 32 "01B3E000" - -# Assembled from reti_issue.jsm -# --------------------------------------------------------------- -# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA -# User 2 -set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength "3C3"] - - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/doc/block_diagram.png b/lib/CPUs/JCpu/doc/block_diagram.png deleted file mode 100644 index 14bbb54..0000000 Binary files a/lib/CPUs/JCpu/doc/block_diagram.png and /dev/null differ diff --git a/lib/CPUs/JCpu/doc/memory_map.png b/lib/CPUs/JCpu/doc/memory_map.png deleted file mode 100644 index 30a22a0..0000000 Binary files a/lib/CPUs/JCpu/doc/memory_map.png and /dev/null differ diff --git a/lib/CPUs/JCpu/gpl-3.0.txt b/lib/CPUs/JCpu/gpl-3.0.txt deleted file mode 100644 index 94a9ed0..0000000 --- a/lib/CPUs/JCpu/gpl-3.0.txt +++ /dev/null @@ -1,674 +0,0 @@ - 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Limitation of Liability. - - IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING -WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS -THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY -GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE -USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF -DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD -PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), -EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF -SUCH DAMAGES. - - 17. Interpretation of Sections 15 and 16. - - If the disclaimer of warranty and limitation of liability provided -above cannot be given local legal effect according to their terms, -reviewing courts shall apply local law that most closely approximates -an absolute waiver of all civil liability in connection with the -Program, unless a warranty or assumption of liability accompanies a -copy of the Program in return for a fee. - - END OF TERMS AND CONDITIONS - - How to Apply These Terms to Your New Programs - - If you develop a new program, and you want it to be of the greatest -possible use to the public, the best way to achieve this is to make it -free software which everyone can redistribute and change under these terms. - - To do so, attach the following notices to the program. It is safest -to attach them to the start of each source file to most effectively -state the exclusion of warranty; and each file should have at least -the "copyright" line and a pointer to where the full notice is found. - - - Copyright (C) - - This program is free software: you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation, either version 3 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - -Also add information on how to contact you by electronic and paper mail. - - If the program does terminal interaction, make it output a short -notice like this when it starts in an interactive mode: - - Copyright (C) - This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. - This is free software, and you are welcome to redistribute it - under certain conditions; type `show c' for details. - -The hypothetical commands `show w' and `show c' should show the appropriate -parts of the General Public License. Of course, your program's commands -might be different; for a GUI interface, you would use an "about box". - - You should also get your employer (if you work as a programmer) or school, -if any, to sign a "copyright disclaimer" for the program, if necessary. -For more information on this, and how to apply and follow the GNU GPL, see -. - - The GNU General Public License does not permit incorporating your program -into proprietary programs. If your program is a subroutine library, you -may consider it more useful to permit linking proprietary applications with -the library. If this is what you want to do, use the GNU Lesser General -Public License instead of this License. But first, please read -. diff --git a/lib/CPUs/JCpu/sim/tb_cpu.fdo b/lib/CPUs/JCpu/sim/tb_cpu.fdo deleted file mode 100644 index 36b8dc0..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/test_irom.vhdl" -vcom -explicit -93 "../src/core/tb_cpu.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu.wdo} -view wave -view structure -view signals -run 50us diff --git a/lib/CPUs/JCpu/sim/tb_cpu.wdo b/lib/CPUs/JCpu/sim/tb_cpu.wdo deleted file mode 100644 index 2ef036e..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu.wdo +++ /dev/null @@ -1,107 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu/rst -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/ce -add wave -noupdate -format Logic /tb_cpu/uut/cpu_active -add wave -noupdate -format Logic /tb_cpu/int_in -add wave -noupdate -format Logic /tb_cpu/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr -add wave -noupdate -format Logic /tb_cpu/xmem_we -add wave -noupdate -format Logic /tb_cpu/xmem_re -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram -add wave -noupdate -format Logic /tb_cpu/uut/io_sel -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -divider CPU -add wave -noupdate -format Literal /tb_cpu/reg -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal /tb_cpu/uut/cpu_status -add wave -noupdate -format Literal /tb_cpu/uut/status_reg -add wave -noupdate -format Literal /tb_cpu/uut/ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result -add wave -noupdate -format Literal /tb_cpu/uut/alu_status -add wave -noupdate -format Logic /tb_cpu/uut/pc_inc -add wave -noupdate -format Logic /tb_cpu/uut/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/stk_we -add wave -noupdate -format Logic /tb_cpu/uut/cmem_we -add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase -add wave -noupdate -format Logic /tb_cpu/uut/was_pcld -add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc -add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load -add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/status_save -add wave -noupdate -format Logic /tb_cpu/uut/status_restore -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr -add wave -noupdate -divider Stack -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -divider Chipram -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -divider Sequencer -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem -add wave -noupdate -divider {Chip register} -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout -add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {136355 ps} 0} -configure wave -namecolwidth 166 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {93532 ps} {206468 ps} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo deleted file mode 100644 index dd965ec..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.fdo +++ /dev/null @@ -1,21 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/cpu_embedded.vhd" -vcom -explicit -93 "../src/tb_cpu_embedded.vhd" -vcom -explicit -93 "../src/test_irom.vhdl" -vsim -t 1ps -lib work tb_cpu_embedded -do {tb_cpu_embedded.wdo} -view wave -view structure -view signals -run 10us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo b/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo deleted file mode 100644 index caec2d7..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_embedded.wdo +++ /dev/null @@ -1,26 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu_embedded/rst -add wave -noupdate -format Logic /tb_cpu_embedded/clk -add wave -noupdate -format Logic /tb_cpu_embedded/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/sram -add wave -noupdate -format Logic /tb_cpu_embedded/int_in -add wave -noupdate -format Logic /tb_cpu_embedded/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/rom_data -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2168142 ps} 0} -configure wave -namecolwidth 143 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {10500 ns} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo deleted file mode 100644 index 77ca67d..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_itest.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/itest_irom.vhdl" -vcom -explicit -93 "../src/tb_cpu_itest.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu_itest.wdo} -view wave -view structure -view signals -run 400us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo b/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo deleted file mode 100644 index 747f9d3..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_itest.wdo +++ /dev/null @@ -1,123 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu/rst -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Logic /tb_cpu/ce -add wave -noupdate -format Logic /tb_cpu/int_in -add wave -noupdate -format Logic /tb_cpu/int_ack -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/xmem_addr -add wave -noupdate -format Logic /tb_cpu/xmem_we -add wave -noupdate -format Logic /tb_cpu/xmem_re -add wave -noupdate -format Logic /tb_cpu/xmem_wait -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/sram -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/reg -add wave -noupdate -format Logic /tb_cpu/uut/io_sel -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/mem_addr -add wave -noupdate -divider CPU -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal /tb_cpu/uut/cpu_status -add wave -noupdate -format Literal /tb_cpu/uut/status_reg -add wave -noupdate -format Literal /tb_cpu/uut/ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/pc_next -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/idata -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/int_pc_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/iphase -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/const_data -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_a_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_b_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/reg_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/alu_result -add wave -noupdate -format Literal /tb_cpu/uut/alu_status -add wave -noupdate -format Logic /tb_cpu/uut/pc_inc -add wave -noupdate -format Logic /tb_cpu/uut/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/cpu_active -add wave -noupdate -format Logic /tb_cpu/uut/stk_we -add wave -noupdate -format Logic /tb_cpu/uut/cmem_we -add wave -noupdate -format Literal /tb_cpu/uut/ctrl_iphase -add wave -noupdate -format Logic /tb_cpu/uut/was_pcld -add wave -noupdate -format Logic /tb_cpu/uut/was_pop2pc -add wave -noupdate -format Logic /tb_cpu/uut/int_pc_load -add wave -noupdate -format Logic /tb_cpu/uut/int_stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/status_save -add wave -noupdate -format Logic /tb_cpu/uut/status_restore -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/stk_ptr -add wave -noupdate -divider Stack -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -divider Chipram -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -divider Sequencer -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/inst_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/iphase_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/status_in -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/idout -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_dpath_ctrl/ddout -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/opcode -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu/uut/inst_reg_ab/mem -add wave -noupdate -divider {Chip register} -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/creg_dout -add wave -noupdate -format Literal /tb_cpu/uut/creg_ctrl_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/clk -add wave -noupdate -divider {Interrup Ctrl.} -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in -add wave -noupdate -format Literal -expand /tb_cpu/uut/inst_int_ctrl/ctrl_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_sampled -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {53866171 ps} 0} -configure wave -namecolwidth 166 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {420 us} diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo deleted file mode 100644 index f83b9b4..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/chipreg.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/irom_reti_issue.vhdl" -vcom -explicit -93 "../src/core/tb_cpu.vhd" -vsim -t 1ps -lib work tb_cpu -do {tb_cpu_reti_issue.wdo} -view wave -view structure -view signals -run 50us diff --git a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo b/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo deleted file mode 100644 index 1e67acb..0000000 --- a/lib/CPUs/JCpu/sim/tb_cpu_reti_issue.wdo +++ /dev/null @@ -1,82 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/ctrl_lines -add wave -noupdate -divider {Chip RAM} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clka -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/clkb -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/en_b -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_a -add wave -noupdate -format Logic /tb_cpu/uut/inst_chipram/we_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/addr_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/din_b -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_a -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_chipram/dout_b -add wave -noupdate -divider {Interrupt controller} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/clk -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/ctrl_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_in -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_reg -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_request_clr -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_exit -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/iphase_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_int_ctrl/pc_addr_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/int_ack -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_save_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stat_rest_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state -add wave -noupdate -format Literal /tb_cpu/uut/inst_int_ctrl/int_state_next -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/pc_load -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_pop_out -add wave -noupdate -format Logic /tb_cpu/uut/inst_int_ctrl/stk_push_out -add wave -noupdate -divider PC -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/inc -add wave -noupdate -format Logic /tb_cpu/uut/inst_pc/load -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_in -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_pc/pc_next -add wave -noupdate -divider {Stack controller} -add wave -noupdate -format Literal /tb_cpu/uut/iphase -add wave -noupdate -format Literal /tb_cpu/uut/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/rst -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/clk -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/push -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/pop -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr_out -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/dout -add wave -noupdate -format Logic /tb_cpu/uut/inst_stack_ctrl/mem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu/uut/inst_stack_ctrl/ptr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {8115990 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {8048536 ps} {8340629 ps} diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo b/lib/CPUs/JCpu/sim/tb_mul8x8.fdo deleted file mode 100644 index f727dff..0000000 --- a/lib/CPUs/JCpu/sim/tb_mul8x8.fdo +++ /dev/null @@ -1,21 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/cpu_pkg.vhd" -vcom -explicit -93 "../src/core/stack_ctrl.vhd" -vcom -explicit -93 "../src/core/reg_dual.vhd" -vcom -explicit -93 "../src/core/chipram.vhd" -vcom -explicit -93 "../src/core/pc.vhd" -vcom -explicit -93 "../src/core/dpath_ctrl.vhd" -vcom -explicit -93 "../src/core/int_ctrl.vhd" -vcom -explicit -93 "../src/core/alu.vhd" -vcom -explicit -93 "../src/core/cpu.vhd" -vcom -explicit -93 "../src/cpu_embedded.vhd" -vcom -explicit -93 "../src/tb_cpu_embedded.vhd" -vcom -explicit -93 "../src/mul8x8_irom.vhdl" -vsim -t 1ps -lib work tb_cpu_embedded -do {tb_mul8x8.wdo} -view wave -view structure -view signals -run 10us diff --git a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo b/lib/CPUs/JCpu/sim/tb_mul8x8.wdo deleted file mode 100644 index 355e0a4..0000000 --- a/lib/CPUs/JCpu/sim/tb_mul8x8.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/rst -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/clk -add wave -noupdate -format Logic /tb_cpu_embedded/uut/inst_cpu/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_din -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/instr_addr -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/cpu_status -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/status_reg -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_cpu_embedded/uut/inst_cpu/alu_result -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/alu_status -add wave -noupdate -format Literal /tb_cpu_embedded/uut/inst_cpu/inst_dpath_ctrl/dbg_iname -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_cpu_embedded/uut/inst_cpu/inst_reg_ab/mem -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {529679 ps} 0} -configure wave -namecolwidth 143 -configure wave -valuecolwidth 101 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {9002500 ps} {10052500 ps} diff --git a/lib/CPUs/JCpu/src/core/alu.vhd b/lib/CPUs/JCpu/src/core/alu.vhd deleted file mode 100644 index 19b3478..0000000 --- a/lib/CPUs/JCpu/src/core/alu.vhd +++ /dev/null @@ -1,236 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity alu is - Generic ( - data_width : integer := 8 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - op_en : in STD_LOGIC; - cy_in : in STD_LOGIC; - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - opsel : in alu_op_t; - res_out : out unsigned (data_width-1 downto 0); - stat_load : in STD_LOGIC; - stat_in : in alu_status_t; - stat_out : out alu_status_t - ); -end alu; - -architecture Behavioral of alu is - - signal sum_cy, sh_cy, sum_cy_in, sh_cy_in, left_shift, add_subn : STD_LOGIC; - signal result, sum_res, lf_res, sh_res, res_reg : unsigned (data_width-1 downto 0); - signal status, stat_reg : alu_status_t; - - -------------------------------------------------------------------------- - function test_zero(arg : unsigned) return STD_LOGIC is - variable result : STD_LOGIC; - begin - result := '0'; - for i in arg'range loop - result := result or To_X01(arg(i)); - end loop; - - return not result; - end test_zero; - --------------------------------------------------------------------------- -begin - --------------------------------------------------------------------------- -proc_logic_func: - process (op1_in, op2_in, opsel) - begin - - case opsel is - when op1_and_op2 => - lf_res <= op1_in and op2_in; - when op1_or_op2 => - lf_res <= op1_in or op2_in; - when op1_xor_op2 => - lf_res <= op1_in xor op2_in; - when others => - lf_res <= (others => '-'); - end case; - - end process; - --------------------------------------------------------------------------- -proc_shift_func: - process (op1_in, left_shift, sh_cy_in) - begin - if left_shift = '1' then - sh_res <= op1_in(op1_in'left-1 downto op1_in'right) & sh_cy_in; - sh_cy <= op1_in(op1_in'left); - else - sh_res <= sh_cy_in & op1_in(op1_in'left downto op1_in'right+1); - sh_cy <= op1_in(op1_in'right); - end if; - - end process; - --------------------------------------------------------------------------- -proc_alu_out: - process(opsel, op1_in, op2_in, res_reg, stat_reg, lf_res, sum_res, sh_res, sum_cy, sh_cy, cy_in) - - begin - - case opsel is - - when op1_add_op2 | op1_sub_op2 | op1_addc_op2 | op1_subc_op2 => - status.zero <= test_zero(res_reg); - status.carry <= sum_cy; - result <= sum_res; - when op1_and_op2 | op1_or_op2 | op1_xor_op2 => - status.zero <= test_zero(res_reg); - status.carry <= stat_reg.carry; - result <= lf_res; - when shl_op | shr_op | rol_op | ror_op | rolc_op | rorc_op => - status.zero <= test_zero(res_reg); - status.carry <= sh_cy; - result <= sh_res; - when swap_op => - result <= op1_in(op1_in'left-op1_in'length/2 downto op1_in'right) & op1_in(op1_in'left downto op1_in'right+op1_in'length/2); - status <= stat_reg; - when others => - result <= op2_in; - status.zero <= stat_reg.zero; - status.carry <= stat_reg.carry or cy_in; - end case; - - end process; - --------------------------------------------------------------------------- -proc_alu_in: - process(opsel, op1_in, stat_reg) - - begin - - add_subn <= '-'; - sum_cy_in <= '-'; - sh_cy_in <= '-'; - left_shift <= '-'; - - case opsel is - - when op1_add_op2 => - sum_cy_in <= '0'; - add_subn <= '1'; - - when op1_sub_op2 => - sum_cy_in <= '0'; - add_subn <= '0'; - - when op1_addc_op2 => - sum_cy_in <= stat_reg.carry; - add_subn <= '1'; - - when op1_subc_op2 => - sum_cy_in <= stat_reg.carry; - add_subn <= '0'; - - when shl_op => - sh_cy_in <= '0'; - left_shift <= '1'; - - when shr_op => - sh_cy_in <= '0'; - left_shift <= '0'; - - when rol_op => - sh_cy_in <= op1_in(op1_in'left); - left_shift <= '1'; - - when ror_op => - sh_cy_in <= op1_in(op1_in'right); - left_shift <= '0'; - - when rolc_op => - sh_cy_in <= stat_reg.carry; - left_shift <= '1'; - - when rorc_op => - sh_cy_in <= stat_reg.carry; - left_shift <= '0'; - - when others => null; - - end case; - - end process; - --------------------------------------------------------------------------- -proc_res_reg: - process(clk, rst, op_en, stat_load, res_reg, stat_reg) - begin - if rst = '1' then - res_reg <= (others => '0'); - stat_reg <= (others => '0'); - elsif rising_edge(clk) then - if op_en = '1' then - res_reg <= result; - stat_reg <= status; - elsif stat_load = '1' then - stat_reg <= stat_in; - end if; - end if; - res_out <= res_reg; - stat_out <= stat_reg; - - end process; - --------------------------------------------------------------------------- -alu_addsub: - process(op1_in, op2_in, sum_cy_in, add_subn) - variable sum : unsigned(data_width+1 downto 0); - variable op1, op2 : unsigned(data_width+1 downto 0); - begin - if add_subn = '1' then - op1 := '0' & op1_in & '1'; - op2 := '0' & op2_in & sum_cy_in; - sum := op1 + op2; - else - op1 := '0' & op1_in & not sum_cy_in; - op2 := '0' & op2_in & '1'; - sum := op1 - op2; - end if; - - -- Form sum + carry - sum_res <= sum(data_width downto 1); - sum_cy <= sum(sum'left); - - end process; - --------------------------------------------------------------------------- -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/chipram.vhd b/lib/CPUs/JCpu/src/core/chipram.vhd deleted file mode 100644 index a954a77..0000000 --- a/lib/CPUs/JCpu/src/core/chipram.vhd +++ /dev/null @@ -1,85 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-chip RAM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity chipram is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end chipram; - -architecture Behavioral of chipram is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - shared variable RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; - dout_a <= RAM(to_integer(addr_a)); - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/chipreg.vhd b/lib/CPUs/JCpu/src/core/chipreg.vhd deleted file mode 100644 index 483c627..0000000 --- a/lib/CPUs/JCpu/src/core/chipreg.vhd +++ /dev/null @@ -1,123 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-Chip registers --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity chipreg is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in dmem_addr_t; - din : in dmem_data_t; - dout : out dmem_data_t; - ctrl_in : in creg_ctrl_in_t; - ctrl_out : out creg_ctrl_out_t - ); -end chipreg; - -architecture Behavioral of chipreg is - - signal reg_page_sel : page_sel_t; - signal reg_int_ctrl : int_ctrl_in_t; - signal reg_stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - signal reg_cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - -begin - -proc_assign_ctrl_lines: - process (clk) - begin - if rising_edge(clk) then - ctrl_out.page_sel <= reg_page_sel; - ctrl_out.int_ctrl <= reg_int_ctrl; - ctrl_out.stk_high <= reg_stk_high; - ctrl_out.cmem_high <= reg_cmem_high; - end if; - end process; - -proc_reg_write: - process (rst, clk) - begin - if rst = '1' then - reg_stk_high <= (others => '0'); - reg_cmem_high <= (others => '0'); - reg_page_sel <= (others => '0'); - reg_int_ctrl.enable <= '0'; - reg_int_ctrl.polarity <= '1'; - reg_int_ctrl.edge_sens <= '1'; - elsif rising_edge(clk) then - reg_int_ctrl.request <= '0'; - if we = '1' then - case addr is - when X"01" => - reg_page_sel(page_sel_t'range) <= din(page_sel_t'range); - when X"03" => - reg_int_ctrl.enable <= din(0); - reg_int_ctrl.polarity <= din(1); - reg_int_ctrl.edge_sens <= din(2); - reg_int_ctrl.request <= din(7); - when X"04" => - reg_cmem_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - when X"05" => - reg_stk_high <= din(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - when others => null; - end case; - end if; - end if; - end process; - -proc_reg_read: - process (clk) - begin - if rising_edge(clk) then - case addr is - when X"00" => -- Revison - dout <= to_unsigned(REVISION, dmem_data_t'length); - when X"01" => -- Control 0 - dout <= (7 downto page_sel_t'length => '0') & reg_page_sel; - when X"02" => -- CPU status - dout <= "000000" & ctrl_in.alu.carry & ctrl_in.alu.zero; - when X"03" => -- Interrupt control - dout <= "00000" & reg_int_ctrl.edge_sens & reg_int_ctrl.polarity & reg_int_ctrl.enable; - when X"04" => -- Upper stack bits out - dout <= "0000" & reg_cmem_high; - when X"05" => -- Upper cmem bits out - dout <= "0000" & reg_stk_high; - when others => - if addr(0) = '0' then - dout <= X"DE"; - else - dout <= X"AD"; - end if; - end case; - - end if; - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/cpu.vhd b/lib/CPUs/JCpu/src/core/cpu.vhd deleted file mode 100644 index 1184806..0000000 --- a/lib/CPUs/JCpu/src/core/cpu.vhd +++ /dev/null @@ -1,566 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: JCPU top file --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity cpu is - Generic ( - use_instr_register : boolean := false; - use_ctrl_rom : boolean := true - - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out std_logic - ); -end cpu; - -architecture rtl of cpu is - - COMPONENT stack_ctrl - GENERIC ( - addr_width : integer - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - push : in STD_LOGIC; - pop : in STD_LOGIC; - din : in inst_addr_t; - dout : out inst_addr_t; - mem_we : out STD_LOGIC; - ptr_out : out unsigned (addr_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT pc - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - inc : in STD_LOGIC; - load : in STD_LOGIC; - pc_in : in inst_addr_t; - pc_out : out inst_addr_t; - pc_next : out inst_addr_t - ); - END COMPONENT; - - COMPONENT dpath_ctrl - GENERIC ( - use_rom : boolean - ); - Port ( - inst_in : in inst_t; - iphase_in : in iphase_t; - status_in : in cpu_status_t; - ctrl_out : out dpath_ctrl_out_t; - idout : out inst_addr_t; - ddout : out dmem_data_t - ); - END COMPONENT; - - COMPONENT int_ctrl - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ctrl_in : in int_ctrl_in_t; - int_in : in STD_LOGIC; - int_exit : in STD_LOGIC; - iphase_in : in iphase_t; - int_ack_out : out STD_LOGIC; - stat_save_out : out STD_LOGIC; - stat_rest_out : out STD_LOGIC; - pc_addr_out : out inst_addr_t; - pc_load_out : out STD_LOGIC; - stk_push_out : out STD_LOGIC; - stk_pop_out : out STD_LOGIC - ); - END COMPONENT; - - COMPONENT reg_dual - GENERIC ( - addr_width : integer; - data_width : integer - ); - Port ( - clk : in STD_LOGIC; - we_a : in STD_LOGIC; - ptr_a : in reg_ptr_t; - ptr_b : in reg_ptr_t; - din_a : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT chipram - GENERIC ( - addr_width : integer; - data_width : integer - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - COMPONENT chipreg - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in dmem_addr_t; - din : in dmem_data_t; - dout : out dmem_data_t; - ctrl_in : in creg_ctrl_in_t; - ctrl_out : out creg_ctrl_out_t - ); - END COMPONENT; - - COMPONENT alu - GENERIC ( - data_width : integer := 8 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - op_en : in STD_LOGIC; - cy_in : in STD_LOGIC; - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - opsel : in alu_op_t; - res_out : out unsigned (data_width-1 downto 0); - stat_load : in STD_LOGIC; - stat_in : in alu_status_t; - stat_out : out alu_status_t - ); - END COMPONENT; - - signal cpu_status, status_reg : cpu_status_t; -- := cpu_status_t(others => '0'); - signal ctrl : dpath_ctrl_out_t; - signal stk_out : inst_addr_t; - signal stk_in : inst_addr_t; - signal stk_reg : inst_addr_t; - signal pc_in, pc_out, pc_next, idata, int_pc_addr : inst_addr_t; - signal iphase : iphase_t; - signal const_data, reg_a_dout, reg_b_dout : dmem_data_t; - signal reg_din : dmem_data_t; - signal alu_op1, alu_op2, alu_result : dmem_data_t; - signal alu_status : alu_status_t; - signal pc_inc, pc_load, cpu_active, stk_we, cmem_we, creg_we : STD_LOGIC; - signal ctrl_inst : inst_t; - signal ctrl_iphase : iphase_t; - signal was_pcld, was_pop2pc, int_pc_load, int_stk_push, int_stk_pop, stk_push, stk_pop : STD_LOGIC; - signal status_save, status_restore : STD_LOGIC; - signal creg_dout : dmem_data_t; - signal cmem_din, cmem_dout : inst_addr_t; - signal stk_addr, cmem_addr : unsigned(CHIPRAM_SIZE_BITS-1 downto 0); - signal stk_ptr : unsigned(STACK_SIZE_BITS-1 downto 0); - signal creg_ctrl_out : creg_ctrl_out_t; - signal creg_ctrl_in : creg_ctrl_in_t; - signal irq_out : std_logic; - signal xio_sel, cio_sel : std_logic; - signal mem_data : dmem_data_t; - signal mem_addr : dmem_data_t; - -begin - io_sel <= xio_sel; - instr_addr <= pc_out; - pc_inc <= cpu_active and ctrl.lines.pc_inc; - stk_addr <= '0' & stk_ptr; - cpu_status.alu <= alu_status; - cpu_status.xmem_wait <= xmem_wait; - creg_ctrl_in.alu <= alu_status; - - xmem_dout <= mem_data; - xmem_addr <= mem_addr; - cmem_din <= creg_ctrl_out.cmem_high & mem_data; - cmem_addr <= '1' & creg_ctrl_out.page_sel & mem_addr(MIN(cmem_addr'length-creg_ctrl_out.page_sel'length-1, mem_addr'length)-1 downto 0); - --------------------------------------------------------------------- -mem_ctrl_lines: - process(ctrl.lines) - begin - xio_sel <= '0'; - xmem_re <= '0'; - xmem_we <= '0'; - cio_sel <= '0'; - cmem_we <= '0'; - creg_we <= '0'; - - case ctrl.lines.mem_access is - when xmem_access => - xmem_re <= ctrl.lines.mem_read; - xmem_we <= ctrl.lines.mem_write; - when xio_access => - xio_sel <= '1'; - xmem_re <= ctrl.lines.mem_read; - xmem_we <= ctrl.lines.mem_write; - when cmem_access => - cmem_we <= ctrl.lines.mem_write; - when cio_access => - cio_sel <= '1'; - creg_we <= ctrl.lines.mem_write; - when others => null; - end case; - end process; - -iphase_counter: - process(rst, clk, ce) - variable pos : integer; - begin - if rst = '1' then - iphase <= iphase_t'low; - cpu_active <= '0'; - elsif rising_edge(clk) then - cpu_active <= '0'; - if ce = '1' then - cpu_active <= '1'; - if iphase = iphase_t'high then - iphase <= iphase_t'low; - else - iphase <= iphase + 1; - end if; - end if; - end if; - end process; - -gen_instr_reg: -if use_instr_register = true generate - -instr_reg: - process (rst, clk, ce) - begin - if rst = '1' then - ctrl_inst <= (others => '0'); - ctrl_iphase <= 0; - elsif rising_edge(clk) and ce = '1' then - ctrl_inst <= instr_din; - ctrl_iphase <= iphase; - end if; - end process; - -end generate; - -gen_instr_direct: -if use_instr_register = false generate - - ctrl_inst <= instr_din; - ctrl_iphase <= iphase; - -end generate; - -status_register: - process(clk, status_save) - begin - if rising_edge(clk) and status_save = '1' then - status_reg.alu <= alu_status; - end if; - end process; - -pc_pushpop: - process(ctrl.lines, int_pc_load, int_stk_push, int_stk_pop, was_pop2pc) - begin - pc_load <= ctrl.lines.pc_load or int_pc_load; - stk_push <= (ctrl.lines.stk_pushd or ctrl.lines.stk_push) or (int_stk_push and not was_pop2pc); - stk_pop <= ctrl.lines.stk_popd or int_stk_pop or (ctrl.lines.stk_pop and not int_pc_load); - end process; - -lines_delay: - process(clk) - begin - if rising_edge(clk) then - was_pcld <= ctrl.lines.pc_load; - was_pop2pc <= ctrl.lines.stk_pop and ctrl.lines.pc_load; - end if; - end process; - -stk_mux: - process(ctrl.lines, was_pcld, int_stk_push, pc_next, idata, reg_a_dout, creg_ctrl_out) - begin - if was_pcld = '1' and int_stk_push = '1' then - stk_in <= idata; - elsif ctrl.lines.stk_pushd = '1' then - stk_in <= creg_ctrl_out.stk_high & reg_a_dout; - else - stk_in <= pc_next; - end if; - - end process; - -pc_mux: - process(ctrl.lines, int_pc_load, int_stk_pop, idata, int_pc_addr, stk_out) - begin - - pc_in <= stk_out; - if int_pc_load = '1' then - if int_stk_pop = '0' then - pc_in <= int_pc_addr; - end if; - elsif ctrl.lines.pc_load = '1' then - if ctrl.lines.stk_pop = '0' then - pc_in <= idata; - end if; - end if; - - end process; - -mem_data_mux: - process(ctrl.lines.ddata_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out) - begin - case ctrl.lines.ddata_src_sel is - when reg_a => - mem_data <= reg_a_dout; - when reg_b => - mem_data <= reg_b_dout; - when const => - mem_data <= const_data; - when others => - mem_data <= const_data; - end case; - - end process; - -mem_addr_mux: - process(ctrl.lines.daddr_src_sel, reg_a_dout, reg_b_dout, const_data, creg_ctrl_out.page_sel) - begin - case ctrl.lines.daddr_src_sel is - when reg_a => - mem_addr <= reg_a_dout; - when reg_b => - mem_addr <= reg_b_dout; - when const => - mem_addr <= const_data; - when others => - mem_addr <= const_data; - end case; - - end process; - -reg_in_mux: - process(ctrl.lines.reg_src_sel, cio_sel, xmem_din, alu_result, stk_out, cmem_dout, creg_dout) - variable data : dmem_data_t; - begin - case ctrl.lines.reg_src_sel is - when xmem_src => - data := xmem_din; - when cmem_src => - if cio_sel = '0' then - data := cmem_dout(dmem_data_t'range); - else - data := creg_dout(dmem_data_t'range); - end if; - when stk_src => - data := stk_out(dmem_data_t'range); - when others => - data := alu_result; - end case; - - reg_din <= data; - - end process; - -alu_op1_mux: - process(ctrl.lines.alu_op1_src_sel, reg_a_dout, reg_b_dout, const_data) - variable data : dmem_data_t; - begin - case ctrl.lines.alu_op1_src_sel is - when reg_a => - data := reg_a_dout; - when reg_b => - data := reg_b_dout; - when others => - data := const_data; - end case; - - alu_op1 <= data; - - end process; - -alu_op2_mux: - process(ctrl.lines.alu_op2_src_sel, reg_a_dout, reg_b_dout, const_data) - variable data : dmem_data_t; - begin - case ctrl.lines.alu_op2_src_sel is - when reg_a => - data := reg_a_dout; - when reg_b => - data := reg_b_dout; - when others => - data := const_data; - end case; - - alu_op2 <= data; - - end process; - --------------------------------------------------------------------- - inst_stack_ctrl: stack_ctrl - GENERIC MAP ( - addr_width => STACK_SIZE_BITS - ) - PORT MAP( - rst => rst, - clk => clk, - push => stk_push, - pop => stk_pop, - dout => stk_reg, - din => stk_in, - ptr_out => stk_ptr, - mem_we => stk_we - ); - - inst_pc: pc - PORT MAP( - rst => rst, - clk => clk, - inc => pc_inc, - load => pc_load, - pc_in => pc_in, - pc_out => pc_out, - pc_next => pc_next - ); - - inst_dpath_ctrl: dpath_ctrl - GENERIC MAP ( - use_rom => use_ctrl_rom - ) - PORT MAP( - inst_in => ctrl_inst, - iphase_in => ctrl_iphase, - status_in => cpu_status, - ctrl_out => ctrl, - ddout => const_data, - idout => idata - ); - - inst_int_ctrl: int_ctrl - PORT MAP( - rst => rst, - clk => clk, - ctrl_in => creg_ctrl_out.int_ctrl, - int_in => int_in, - int_ack_out => int_ack, - int_exit => ctrl.lines.int_exit, - iphase_in => ctrl_iphase, - stat_save_out => status_save, - stat_rest_out => status_restore, - pc_addr_out => int_pc_addr, - pc_load_out => int_pc_load, - stk_push_out => int_stk_push, - stk_pop_out => int_stk_pop - - ); - - inst_reg_ab: reg_dual - GENERIC MAP ( - addr_width => REG_SIZE_BITS, - data_width => DMEM_DATA_WIDTH - ) - PORT MAP( - clk => clk, - we_a => ctrl.lines.reg_we, - ptr_a => ctrl.reg_a_ptr, - ptr_b => ctrl.reg_b_ptr, - din_a => reg_din, - dout_a => reg_a_dout, - dout_b => reg_b_dout - ); - - inst_chipram: chipram - GENERIC MAP ( - addr_width => CHIPRAM_SIZE_BITS, - data_width => IMEM_ADDR_WIDTH - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => cpu_active, - en_b => cpu_active, - we_a => stk_we, - we_b => cmem_we, - addr_a => stk_addr, - addr_b => cmem_addr, - din_a => stk_reg, - din_b => cmem_din, - dout_a => stk_out, - dout_b => cmem_dout - ); - - inst_chipreg: chipreg - PORT MAP( - rst => rst, - clk => clk, - we => creg_we, - addr => mem_addr, - din => mem_data, - dout => creg_dout, - ctrl_in => creg_ctrl_in, - ctrl_out => creg_ctrl_out - ); - - inst_alu: alu - GENERIC MAP ( - data_width => DMEM_DATA_WIDTH - ) - PORT MAP( - rst => rst, - clk => clk, - op_en => ctrl.lines.alu_load, - cy_in => ctrl.lines.alu_cy_in, - op1_in => alu_op1, - op2_in => alu_op2, - opsel => ctrl.lines.alu_opsel, - res_out => alu_result, - stat_load => status_restore, - stat_in => status_reg.alu, - stat_out => alu_status - ); - -end rtl; diff --git a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd b/lib/CPUs/JCpu/src/core/cpu_pkg.vhd deleted file mode 100644 index 4c4d56c..0000000 --- a/lib/CPUs/JCpu/src/core/cpu_pkg.vhd +++ /dev/null @@ -1,904 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JCPU --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - - -package cpu_pkg is - - -- Revision of the CPU - constant REVISION : integer := 4; - - -- Chipram depth (valid values 9..floor(log2(BlockRamBytes))) - constant CHIPRAM_SIZE_BITS : integer := 10; - - -- Chipregister file depth - constant CHIPREG_SIZE_BITS : integer := 8; - - -- Number of registers (16 registers fixed) - constant REG_SIZE_BITS : integer := 4; - - -- Instruction memory - constant IMEM_ADDR_WIDTH : integer := 12; - - -- Data memory - constant DMEM_DATA_WIDTH : integer := 8; - constant DMEM_ADDR_WIDTH : integer := 8; - - -- Instruction format - constant INST_OPCODE_WIDTH : integer := 6; - constant IMEM_DATA_WIDTH : integer := INST_OPCODE_WIDTH + DMEM_DATA_WIDTH + REG_SIZE_BITS; - - -- Microcode ROM - constant MUCODE_ADDR_WIDTH : integer := 10; - - -- Stack depth (uses lower half of CHIPRAM) - constant STACK_SIZE_BITS : integer := CHIPRAM_SIZE_BITS-1; - - --Types - subtype iphase_t is integer range 0 to 1; - type mem_access_t is (cmem_access, xmem_access, cio_access, xio_access); - type reg_src_t is (alu_src, stk_src, cmem_src, xmem_src); - type alu_src_t is (reg_a, reg_b, const); - type ddata_src_t is (reg_a, reg_b, const); - type daddr_src_t is (reg_a, reg_b, const); - subtype instr_name_t is string(1 to 12); - type instr_name_array_t is array (0 to 63) of instr_name_t; - subtype opcode_t is unsigned (INST_OPCODE_WIDTH-1 downto 0); - subtype inst_data_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0); - subtype inst_addr_t is unsigned (IMEM_ADDR_WIDTH-1 downto 0); - subtype inst_t is unsigned (IMEM_DATA_WIDTH-1 downto 0); - subtype dmem_data_t is unsigned (DMEM_DATA_WIDTH-1 downto 0); - subtype dmem_addr_t is unsigned (DMEM_DATA_WIDTH-1 downto 0); - subtype reg_ptr_t is unsigned (3 downto 0); - type dmem_array_t is array (natural range <>) of dmem_data_t; - type instr_addr_array is array (integer range <>) of inst_addr_t; - subtype page_sel_t is unsigned (CHIPRAM_SIZE_BITS-DMEM_DATA_WIDTH-2 downto 0); - - type alu_op_t is - ( - pass_op2, - op1_add_op2, - op1_sub_op2, - op1_addc_op2, - op1_subc_op2, - op1_and_op2, - op1_or_op2, - op1_xor_op2, - swap_op, - shl_op, - shr_op, - rol_op, - ror_op, - rolc_op, - rorc_op - ); - - type alu_status_t is record - zero : STD_LOGIC; - carry : STD_LOGIC; - end record; - - type cpu_status_t is record - alu : alu_status_t; - xmem_wait : STD_LOGIC; - end record; - - type ctrl_lines_t is record - reg_we : STD_LOGIC; - reg_src_sel : reg_src_t; - alu_op1_src_sel : alu_src_t; - alu_op2_src_sel : alu_src_t; - alu_opsel : alu_op_t; - alu_load : STD_LOGIC; - alu_cy_in : STD_LOGIC; - ddata_src_sel : ddata_src_t; - daddr_src_sel : daddr_src_t; - pc_load : STD_LOGIC; - pc_inc : STD_LOGIC; - stk_push : STD_LOGIC; - stk_pop : STD_LOGIC; - stk_pushd : STD_LOGIC; - stk_popd : STD_LOGIC; - mem_access : mem_access_t; - mem_read : STD_LOGIC; - mem_write : STD_LOGIC; - int_exit : STD_LOGIC; - end record; - - type dpath_ctrl_out_t is record - lines : ctrl_lines_t; - reg_a_ptr : reg_ptr_t; - reg_b_ptr : reg_ptr_t; - end record; - - type int_ctrl_in_t is record - enable : std_logic; - polarity : std_logic; - edge_sens : std_logic; - request : std_logic; - end record; - - type creg_ctrl_out_t is record - page_sel : page_sel_t; - int_ctrl : int_ctrl_in_t; - stk_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - cmem_high : unsigned(IMEM_ADDR_WIDTH-DMEM_ADDR_WIDTH-1 downto 0); - end record; - - type creg_ctrl_in_t is record - alu : alu_status_t; - end record; - - - type murom_t is array (0 to integer(2**MUCODE_ADDR_WIDTH)-1) of ctrl_lines_t; - - constant instr_name_array : instr_name_array_t := - ( - "NOP ", -- 00 - "HALT ", -- 01 - "MOV|R|R ", -- 02 - "MOV|R|K ", -- 03 - "MOVX|R|Ri ", -- 04 - "MOVX|R|Ki ", -- 05 - "MOVX|Ri|R ", -- 06 - "MOVX|Ri|K ", -- 07 - "MOVX|Ki|R ", -- 08 - "MOVC|R|Ri ", -- 09 - "MOVC|R|Ki ", -- 0A - "MOVC|Ri|R ", -- 0B - "MOVC|Ri|K ", -- 0C - "MOVC|Ki|R ", -- 0D - "CMP|R|R ", -- 0E - "CMP|R|K ", -- 0F - "ADD|R|R ", -- 10 - "ADD|R|K ", -- 11 - "ADDC|R|R ", -- 12 - "ADDC|R|K ", -- 13 - "SUB|R|R ", -- 14 - "SUB|R|K ", -- 15 - "SUBC|R|R ", -- 16 - "SUBC|R|K ", -- 17 - "AND|R|R ", -- 18 - "AND|R|K ", -- 19 - "OR|R|R ", -- 1A - "OR|R|K ", -- 1B - "XOR|R|R ", -- 1C - "XOR|R|K ", -- 1D - "SHL|R ", -- 1E - "SHR|R ", -- 1F - "ROL|R ", -- 20 - "ROR|R ", -- 21 - "ROLC|R ", -- 22 - "RORC|R ", -- 23 - "XOUT|Ki|R ", -- 24 - "XOUT|Ri|K ", -- 25 - "COUT|Ki|R ", -- 26 - "COUT|Ri|K ", -- 27 - "XIN|R|Ki ", -- 28 - "CIN|R|Ki ", -- 29 - "SWAP|R ", -- 2A - "SETC ", -- 2B - "UNDEF ", -- 2C - "UNDEF ", -- 2D - "SUB|K|R ", -- 2E - "SUBC|K|R ", -- 2F - "JMP|K ", -- 30 - "JZ|K ", -- 31 - "JNZ|K ", -- 32 - "JC|K ", -- 33 - "JNC|K ", -- 34 - "JLT|K ", -- 35 - "JGT|K ", -- 36 - "JLE|K ", -- 37 - "JGE|K ", -- 38 - "JEQ|K ", -- 39 - "JNE|K ", -- 3A - "CALL|K ", -- 3B - "PUSH|R ", -- 3C - "POP|R ", -- 3D - "RET ", -- 3E - "RETI " -- 3F - ); - -- Functions - function Instr(opcode : opcode_t) return inst_t; - function Instr(opcode : opcode_t; data : inst_data_t) return inst_t; - function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t; - function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t; - function ctrl_lines_default return ctrl_lines_t; - function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t; - function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t; - function gen_murom return murom_t; - function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned; - function MIN (X, Y: INTEGER) return INTEGER; - function MAX (X, Y: INTEGER) return INTEGER; - -end cpu_pkg; - -package body cpu_pkg is - - function Instr(opcode : opcode_t) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - return inst; - - end Instr; - - function Instr(opcode : opcode_t; data : inst_data_t) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_addr_t'length) := data; - return inst; - - end Instr; - - function Instr(opcode : opcode_t; data : inst_data_t; reg : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(inst_t'length-opcode_t'length-1 downto inst_t'length-opcode_t'length-inst_data_t'length) := data; - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a, reg_b : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length)); - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function Instr(opcode : opcode_t; reg_a, reg_b, reg_c : integer) return inst_t is - variable inst : inst_t := (others => '0'); - begin - inst(inst_t'length-1 downto inst_t'length-opcode_t'length) := opcode; - inst(3*(reg_ptr_t'length)-1 downto 2*reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_c, reg_ptr_t'length)); - inst(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length) := reg_ptr_t(to_unsigned(reg_b, reg_ptr_t'length)); - inst(reg_ptr_t'length-1 downto 0) := reg_ptr_t(to_unsigned(reg_a, reg_ptr_t'length)); - - return inst; - - end Instr; - - function ctrl_lines_default return ctrl_lines_t is - variable result : ctrl_lines_t; - begin - result.pc_load := '0'; - result.pc_inc := '0'; - result.stk_push := '0'; - result.stk_pop := '0'; - result.stk_pushd := '0'; - result.stk_popd := '0'; - result.reg_we := '0'; - result.reg_src_sel := alu_src; - result.ddata_src_sel := reg_a; - result.daddr_src_sel := reg_b; - result.alu_opsel := pass_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.alu_load := '0'; - result.alu_cy_in := '0'; - result.mem_access := cmem_access; - result.mem_read := '0'; - result.mem_write := '0'; - result.int_exit := '0'; - return result; - - end ctrl_lines_default; - - function idecoder(opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is - variable instr_name : instr_name_t; - begin - instr_name := instr_name_array(to_integer(opcode)); - return idecoder(instr_name, iphase, status); - end idecoder; - - function idecoder(instr_name : instr_name_t; iphase : iphase_t; status : cpu_status_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable ze, cy, xmem_wait : STD_LOGIC; - - begin - ze := status.alu.zero; - cy := status.alu.carry; - xmem_wait := status.xmem_wait; - - result := ctrl_lines_default; - if iphase = 0 then - result.pc_inc := '1'; - end if; - - case instr_name is - - when "HALT " => - result.pc_inc := '0'; - when "SETC " => -- carry <= 1 - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - result.alu_cy_in := '1'; - when "MOV|R|R " => -- R(a) <= R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOV|R|K " => -- R(a) <= #kk - result.reg_src_sel := alu_src; - result.alu_opsel := pass_op2; - result.alu_op2_src_sel := const; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|Ri|R " => -- [R(b)] <= R(a) - result.mem_access := cmem_access; - result.daddr_src_sel := reg_b; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVC|Ri|K " => -- [R(a)] <= kk - result.mem_access := cmem_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "COUT|Ri|K " => -- [R(a)] <= kk - result.mem_access := cio_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVC|R|Ri " => -- R(a) <= [R(b)] - result.mem_access := cmem_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := reg_b; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|R|Ki " => -- R(a) <= [#addr] - result.mem_access := cmem_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := const; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "CIN|R|Ki " => -- R(a) <= [#addr] - result.mem_access := cio_access; - result.reg_src_sel := cmem_src; - result.daddr_src_sel := const; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "MOVC|Ki|R " => -- [#addr] <= R(a) - result.mem_access := cmem_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "COUT|Ki|R " => -- [#addr] <= R(a) - result.mem_access := cio_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - when "MOVX|Ri|R " => -- [R(b)] <= R(a) - result.mem_access := xmem_access; - result.daddr_src_sel := reg_b; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.mem_write := '1'; - result.pc_inc := '0'; - end if; - when "MOVX|Ri|K " => -- [R(a)] <= kk - result.mem_access := xmem_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.mem_write := '1'; - result.pc_inc := '0'; - end if; - when "XOUT|Ri|K " => -- [R(a)] <= kk - result.mem_access := xio_access; - result.daddr_src_sel := reg_a; - result.ddata_src_sel := const; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.pc_inc := '0'; - result.mem_write := '1'; - end if; - when "MOVX|R|Ri " => -- R(a) <= [R(b)] - result.mem_access := xmem_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := reg_b; - if iphase = 0 then - result.mem_read := '1'; - end if; - if xmem_wait = '0' then - if iphase = 1 then - result.reg_we := '1'; - end if; - else - result.pc_inc := '0'; - result.mem_read := '1'; - end if; - when "MOVX|R|Ki " => -- R(a) <= [#addr] - result.mem_access := xmem_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := const; - if iphase = 0 then - result.mem_read := '1'; - end if; - if xmem_wait = '0' then - if iphase = 1 then - result.reg_we := '1'; - end if; - else - result.pc_inc := '0'; - result.mem_read := '1'; - end if; - when "XIN|R|Ki " => -- R(a) <= [#addr] - result.mem_access := xio_access; - result.reg_src_sel := xmem_src; - result.daddr_src_sel := const; - if iphase = 0 then - result.mem_read := '1'; - end if; - if xmem_wait = '0' then - if iphase = 1 then - result.reg_we := '1'; - end if; - else - result.pc_inc := '0'; - result.mem_read := '1'; - end if; - when "MOVX|Ki|R " => -- [#addr] <= R(a) - result.mem_access := xmem_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.pc_inc := '0'; - result.mem_write := '1'; - end if; - when "XOUT|Ki|R " => -- [#addr] <= R(a) - result.mem_access := xio_access; - result.daddr_src_sel := const; - result.ddata_src_sel := reg_a; - if iphase = 0 then - result.mem_write := '1'; - end if; - if xmem_wait = '1' then - result.pc_inc := '0'; - result.mem_write := '1'; - end if; - when "ADD|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_add_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADD|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_add_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADDC|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_addc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ADDC|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_addc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUB|K|R " => -- R(a) <= k - R(a) - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := const; - result.alu_op2_src_sel := reg_a; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|R|R " => -- R(a) <= R(a) + R(b) - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|R|K " => -- R(a) <= R(a) + k - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SUBC|K|R " => -- R(a) <= K - R(a) - result.alu_opsel := op1_subc_op2; - result.alu_op1_src_sel := const; - result.alu_op2_src_sel := reg_a; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "AND|R|R " => -- R(a) <= R(a) and R(b) - result.alu_opsel := op1_and_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "AND|R|K " => -- R(a) <= R(a) and k - result.alu_opsel := op1_and_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "OR|R|R " => -- R(a) <= R(a) or R(b) - result.alu_opsel := op1_or_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "OR|R|K " => -- R(a) <= R(a) or R(b) - result.alu_opsel := op1_or_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "XOR|R|R " => -- R(a) <= R(a) xor R(b) - result.alu_opsel := op1_xor_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "XOR|R|K " => -- R(a) <= R(a) xor R(b) - result.alu_opsel := op1_xor_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.reg_src_sel := alu_src; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SWAP|R " => -- R(a) <= R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := swap_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SHL|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := shl_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "SHR|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := shr_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROL|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rol_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROR|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := ror_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "ROLC|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rolc_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "RORC|R " => -- R(a) <= R(a) xor R(b) - result.reg_src_sel := alu_src; - result.alu_opsel := rorc_op; - result.alu_op1_src_sel := reg_a; - result.alu_load := '1'; - if iphase = 1 then - result.reg_we := '1'; - end if; - when "CMP|R|R " => -- - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := reg_b; - result.alu_load := '1'; - when "CMP|R|K " => -- - result.alu_opsel := op1_sub_op2; - result.alu_op1_src_sel := reg_a; - result.alu_op2_src_sel := const; - result.alu_load := '1'; - when "JMP|K " => -- PC <= #addr - if iphase = 0 then - result.pc_load := '1'; - end if; - when "JZ|K " => -- PC <= #addr, zero - if iphase = 0 then - if ze = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNZ|K " => -- PC <= #addr, !zero - if iphase = 0 then - if ze = '0' then - result.pc_load := '1'; - end if; - end if; - when "JC|K " => -- PC <= #addr, carry - if iphase = 0 then - if cy = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNC|K " => -- PC <= #addr, !carry - if iphase = 0 then - if cy = '0' then - result.pc_load := '1'; - end if; - end if; - when "JLT|K " => -- PC <= #addr, !carry - if iphase = 0 then - if cy = '1' then - result.pc_load := '1'; - end if; - end if; - when "JGT|K " => -- - if iphase = 0 then - if (cy or ze) = '0' then - result.pc_load := '1'; - end if; - end if; - when "JLE|K " => -- - if iphase = 0 then - if (cy xor ze) = '1' then - result.pc_load := '1'; - end if; - end if; - when "JGE|K " => -- - if iphase = 0 then - if (not cy or ze) = '1' then - result.pc_load := '1'; - end if; - end if; - when "JEQ|K " => -- - if iphase = 0 then - if ze = '1' then - result.pc_load := '1'; - end if; - end if; - when "JNE|K " => -- - if iphase = 0 then - if ze = '0' then - result.pc_load := '1'; - end if; - end if; - when "PUSH|R " => -- push - if iphase = 0 then - result.stk_pushd := '1'; - end if; - when "POP|R " => -- pop - result.reg_src_sel := stk_src; - if iphase = 0 then - result.stk_popd := '1'; - elsif iphase = 1 then - result.reg_we := '1'; - end if; - when "CALL|K " => -- call - if iphase = 0 then - result.pc_load := '1'; - result.stk_push := '1'; - end if; - when "RET " => -- return - if iphase = 0 then - result.pc_load := '1'; - result.stk_pop := '1'; - end if; - when "RETI " => -- return - result.pc_inc := '0'; - result.int_exit := '1'; - - when others => null; -- nop - end case; - - return result; - - end idecoder; - - function gen_murom return murom_t is - variable result : murom_t; - variable opcode : opcode_t; - variable iphase : iphase_t; - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - variable status : cpu_status_t; - variable pos : integer := 0; - - begin - for i in 0 to 2**addr'length-1 loop - addr := to_unsigned(i, addr'length); - opcode := addr(opcode'length-1 downto 0); - pos := opcode'length; - iphase := 0; - if addr(pos) = '1' then - iphase := 1; - end if; - pos := pos + 1; - status.alu.zero := addr(pos); - pos := pos + 1; - status.alu.carry := addr(pos); - pos := pos + 1; - status.xmem_wait := addr(pos); - - result(i) := idecoder(opcode, iphase, status); - end loop; - - return result; - end gen_murom; - - function get_muromaddr (opcode : opcode_t; iphase : iphase_t; status : cpu_status_t) return unsigned is - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - begin - addr := status.xmem_wait & status.alu.carry & status.alu.zero & to_unsigned(iphase, 1) & opcode; - return addr; - - end get_muromaddr; - - ------------------------------------------------------------- - function MIN (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y < X then - res := Y; - end if; - - return res; - - end MIN; - - ------------------------------------------------------------- - function MAX (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y > X then - res := Y; - end if; - - return res; - - end MAX; - - -end cpu_pkg; - diff --git a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd b/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd deleted file mode 100644 index 1610d00..0000000 --- a/lib/CPUs/JCpu/src/core/dpath_ctrl.vhd +++ /dev/null @@ -1,87 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The datapath controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity dpath_ctrl is - Generic ( - use_rom : boolean := true - ); - Port ( - inst_in : in inst_t; - iphase_in : in iphase_t; - status_in : in cpu_status_t; - ctrl_out : out dpath_ctrl_out_t; - idout : out inst_addr_t; - ddout : out dmem_data_t - ); -end dpath_ctrl; - -architecture Behavioral of dpath_ctrl is - - signal opcode : opcode_t; - signal ctrl_lines : ctrl_lines_t; - signal dbg_iname : instr_name_t; - -begin - - idout <= inst_in(IMEM_ADDR_WIDTH-1 downto 0); - ddout <= inst_in(REG_SIZE_BITS+DMEM_DATA_WIDTH-1 downto REG_SIZE_BITS); - opcode <= inst_in(IMEM_DATA_WIDTH-1 downto IMEM_DATA_WIDTH-INST_OPCODE_WIDTH); - - ctrl_out.reg_a_ptr <= inst_in(reg_ptr_t'length-1 downto 0); - ctrl_out.reg_b_ptr <= inst_in(2*(reg_ptr_t'length)-1 downto reg_ptr_t'length); - ctrl_out.lines <= ctrl_lines; - - -- pragma translate_off - dbg_iname <= instr_name_array(to_integer(opcode)); - -- pragma translate_on - -gen_ctrl_rom: -if use_rom = true generate - - i_dec: - process(opcode, iphase_in, status_in) - constant rom_data : murom_t := gen_murom; - variable addr : unsigned(MUCODE_ADDR_WIDTH-1 downto 0); - begin - addr := get_muromaddr(opcode, iphase_in, status_in); - ctrl_lines <= rom_data(to_integer(addr)); - end process; -end generate; - -gen_ctrl: -if use_rom = false generate - i_dec: - process (opcode, iphase_in, status_in) - begin - ctrl_lines <= idecoder(opcode, iphase_in, status_in); - end process; -end generate; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/int_ctrl.vhd b/lib/CPUs/JCpu/src/core/int_ctrl.vhd deleted file mode 100644 index 2e54d67..0000000 --- a/lib/CPUs/JCpu/src/core/int_ctrl.vhd +++ /dev/null @@ -1,177 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Interrupt controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity int_ctrl is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ctrl_in : in int_ctrl_in_t; - int_in : in STD_LOGIC; - int_exit : in STD_LOGIC; - iphase_in : in iphase_t; - pc_addr_out : out inst_addr_t; - int_ack_out : out STD_LOGIC; - stat_save_out : out STD_LOGIC; - stat_rest_out : out STD_LOGIC; - pc_load_out : out STD_LOGIC; - stk_push_out : out STD_LOGIC; - stk_pop_out : out STD_LOGIC - ); -end int_ctrl; - -architecture Behavioral of int_ctrl is - - type int_state_t is (int_idle, int_inject, int_active, int_release); - type pin_state_t is (pin_s0, pin_s1, pin_s2); - - signal int_state, int_state_next : int_state_t; - signal pin_state, pin_state_next : pin_state_t; - signal pc_load, int_ack, stk_push, stk_pop : STD_LOGIC; - signal int_request : std_logic; - signal int_sampled : std_logic; - -begin - - int_ack_out <= int_ack; - pc_load_out <= pc_load; - stk_push_out <= stk_push; - stk_pop_out <= stk_pop; - ------------------------------------------------------------------------ -irg_ctrl_fsm: - process (int_state, iphase_in, int_request, int_exit) - begin - - pc_addr_out <= to_unsigned(1, inst_addr_t'length); - int_state_next <= int_state; - int_ack <= '0'; - pc_load <= '0'; - stk_push <= '0'; - stk_pop <= '0'; - - case int_state is - - when int_idle => - if int_request = '1' and iphase_in = 1 then - int_state_next <= int_inject; - end if; - when int_inject => - if iphase_in = 0 then - int_ack <= '1'; - pc_load <= '1'; - elsif iphase_in = 1 then - stk_push <= '1'; - int_state_next <= int_active; - end if; - when int_active => - if int_exit = '1' and iphase_in = 1 then - int_state_next <= int_release; - end if; - when int_release => - if iphase_in = 0 then - stk_pop <= '1'; - pc_load <= '1'; - elsif iphase_in = 1 then - int_state_next <= int_idle; - end if; - when others => - int_state_next <= int_idle; - end case; - - end process; - -irq_ctrl_states: - process (rst, clk, int_state_next) - begin - if rst = '1' then - int_state <= int_idle; - elsif rising_edge(clk) then - int_state <= int_state_next; - end if; - end process; - ------------------------------------------------------------------------ -pin_sample: - process (clk) - begin - if rising_edge(clk) then - int_sampled <= int_in xor (not ctrl_in.polarity); - end if; - end process; - ------------------------------------------------------------------------ -pin_fsm: - process (pin_state, int_sampled, int_ack, ctrl_in) - begin - int_request <= '0'; - pin_state_next <= pin_state; - case pin_state is - when pin_s0 => - if int_sampled = '1' or ctrl_in.request = '1' then - if ctrl_in.enable = '1' then - pin_state_next <= pin_s1; - end if; - end if; - when pin_s1 => - int_request <= '1'; - if int_ack = '1' then - pin_state_next <= pin_s2; - end if; - when pin_s2 => - if ctrl_in.edge_sens = '0' then - pin_state_next <= pin_s0; - elsif int_sampled = '0' then - pin_state_next <= pin_s0; - end if; - when others => - pin_state_next <= pin_s0; - end case; - end process; - -pin_states: - process (rst, clk, pin_state_next) - begin - if rst = '1' then - pin_state <= pin_s0; - elsif rising_edge(clk) then - pin_state <= pin_state_next; - end if; - end process; - ------------------------------------------------------------------------ -stat_save_restore: - process (clk, stk_push, stk_pop) - begin - if rising_edge(clk) then - stat_save_out <= stk_push; - stat_rest_out <= stk_pop; - end if; - end process; - -end Behavioral; diff --git a/lib/CPUs/JCpu/src/core/pc.vhd b/lib/CPUs/JCpu/src/core/pc.vhd deleted file mode 100644 index 6b1d575..0000000 --- a/lib/CPUs/JCpu/src/core/pc.vhd +++ /dev/null @@ -1,70 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Programm counter --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity pc is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - inc : in STD_LOGIC; - load : in STD_LOGIC; - pc_in : in inst_addr_t; - pc_out : out inst_addr_t; - pc_next : out inst_addr_t - ); -end pc; - -architecture Behavioral of pc is - -begin - -proc_pc: - process(rst, clk, inc, load, pc_in) - variable vpc, vpc_reg: inst_addr_t; - begin - if rst = '1' then - vpc_reg := (others => '0'); - elsif rising_edge(clk) then - if inc = '1' or load = '1' then - vpc_reg := vpc; - elsif inc = '0' then - pc_next <= vpc; - end if; - end if; - - if load = '1' then - vpc := pc_in; - else - vpc := vpc_reg + 1; - end if; - pc_out <= vpc_reg; - - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/reg_dual.vhd b/lib/CPUs/JCpu/src/core/reg_dual.vhd deleted file mode 100644 index 6b7e4d8..0000000 --- a/lib/CPUs/JCpu/src/core/reg_dual.vhd +++ /dev/null @@ -1,81 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: On-Chip work registers --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity reg_dual is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clk : in STD_LOGIC; - we_a : in STD_LOGIC; - ptr_a : in reg_ptr_t; - ptr_b : in reg_ptr_t; - din_a : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end reg_dual; - -architecture Behavioral of reg_dual is - - constant depth : integer := 2**addr_width; - type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal addr_a, addr_b : unsigned (addr_width-1 downto 0) := (others => '0'); - - signal mem : mem_t; -begin - - addr_a <= TO_01(ptr_a(addr_width-1 downto 0)); - addr_b <= TO_01(ptr_b(addr_width-1 downto 0)); - -reg_in_ab: - process(clk) - begin - if rising_edge(clk) then - if we_a = '1' then - mem(to_integer(addr_a)) <= din_a; - end if; - end if; - end process; - -reg_out_a: - process(mem, addr_a) - begin - dout_a <= TO_01(mem(to_integer(addr_a))); - end process; - -reg_out_b: - process(mem, addr_b) - begin - dout_b <= TO_01(mem(to_integer(addr_b))); - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd b/lib/CPUs/JCpu/src/core/stack_ctrl.vhd deleted file mode 100644 index 7eccae3..0000000 --- a/lib/CPUs/JCpu/src/core/stack_ctrl.vhd +++ /dev/null @@ -1,73 +0,0 @@ --------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity stack_ctrl is -Generic ( - addr_width : integer := 3 -); -Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - push : in STD_LOGIC; - pop : in STD_LOGIC; - ptr_out : out unsigned (addr_width-1 downto 0); - din : in inst_addr_t; - dout : out inst_addr_t; - mem_we : out STD_LOGIC - ); -end stack_ctrl; - -architecture Behavioral of stack_ctrl is - - signal ptr : unsigned (addr_width-1 downto 0); - -begin - - ptr_out <= ptr; - -stk_ptr: - process(rst, clk, ptr, push, pop) - begin - if rst = '1' then - ptr <= (others => '0'); - dout <= (others => '0'); - mem_we <= '0'; - elsif rising_edge(clk) then - mem_we <= push; - if push = '1' then - ptr <= ptr + 1; - dout <= din; - elsif pop = '1' then - ptr <= ptr - 1; - end if; - end if; - end process; - -end Behavioral; - diff --git a/lib/CPUs/JCpu/src/cpu_embedded.vhd b/lib/CPUs/JCpu/src/cpu_embedded.vhd deleted file mode 100644 index 1990170..0000000 --- a/lib/CPUs/JCpu/src/cpu_embedded.vhd +++ /dev/null @@ -1,109 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.cpu_pkg.all; - -entity cpu_embedded is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); -end cpu_embedded; - -architecture rtl of cpu_embedded is - - signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0); - signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0); - - COMPONENT cpu - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); - END COMPONENT; - - - COMPONENT irom - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - END COMPONENT; - -begin - -inst_cpu: cpu - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_wait => xmem_wait, - xmem_we => xmem_we, - xmem_re => xmem_re, - instr_din => irom_data, - instr_addr => irom_addr, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -inst_irom: irom - PORT MAP( - clk => clk, - ce => ce, - addr => irom_addr, - dout => irom_data - ); - -end rtl; diff --git a/lib/CPUs/JCpu/src/dctest_irom.vhdl b/lib/CPUs/JCpu/src/dctest_irom.vhdl deleted file mode 100644 index 7987a15..0000000 --- a/lib/CPUs/JCpu/src/dctest_irom.vhdl +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE dctest OF irom IS - - type imem_rom_t is array (0 to 17) of inst_t; - - -- Assembled from dctest.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"011", -- 0x001: JMP 0x011 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "110000" & X"010", -- 0x010: JMP 0x010 - "111111" & X"000" -- 0x011: RETI - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end dctest; - diff --git a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl deleted file mode 100644 index 223dd46..0000000 --- a/lib/CPUs/JCpu/src/dctest_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from dctest.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"011", -- 0x001: JMP 0x011 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - 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"000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000" - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/dctest_xrom.vhdl b/lib/CPUs/JCpu/src/dctest_xrom.vhdl deleted file mode 100644 index 24fe36c..0000000 --- a/lib/CPUs/JCpu/src/dctest_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE dctest OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from dctest.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"01", -- 0x04 - X"12", -- 0x05 - X"41", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"48", -- 0x17 - X"61", -- 0x18 - X"6C", -- 0x19 - X"6C", -- 0x1A - X"6F", -- 0x1B - X"0D", -- 0x1C - X"0A", -- 0x1D - X"00", -- 0x1E - X"4A", -- 0x1F - X"65", -- 0x20 - X"6E", -- 0x21 - X"73", -- 0x22 - X"00", -- 0x23 - X"57", -- 0x24 - X"65", -- 0x25 - X"6C", -- 0x26 - X"63", -- 0x27 - X"6F", -- 0x28 - X"6D", -- 0x29 - X"65", -- 0x2A - X"20", -- 0x2B - X"74", -- 0x2C - X"6F", -- 0x2D - X"20", -- 0x2E - X"4A", -- 0x2F - X"41", -- 0x30 - X"53", -- 0x31 - X"4D", -- 0x32 - X"20", -- 0x33 - X"43", -- 0x34 - X"50", -- 0x35 - X"55", -- 0x36 - X"00", -- 0x37 - X"52", -- 0x38 - X"65", -- 0x39 - X"61", -- 0x3A - X"64", -- 0x3B - X"79", -- 0x3C - X"00", -- 0x3D - X"54", -- 0x3E - X"65", -- 0x3F - X"73", -- 0x40 - X"74", -- 0x41 - X"69", -- 0x42 - X"6E", -- 0x43 - X"67", -- 0x44 - X"00", -- 0x45 - X"50", -- 0x46 - X"61", -- 0x47 - X"73", -- 0x48 - X"73", -- 0x49 - X"65", -- 0x4A - X"64", -- 0x4B - X"00", -- 0x4C - X"45", -- 0x4D - X"72", -- 0x4E - X"72", -- 0x4F - X"6F", -- 0x50 - X"72", -- 0x51 - X"00", -- 0x52 - X"0D", -- 0x53 - X"0A", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end dctest; - diff --git a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl deleted file mode 100644 index 802ba50..0000000 --- a/lib/CPUs/JCpu/src/dctest_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from dctest.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"01", -- 0x04 - X"12", -- 0x05 - X"41", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"48", -- 0x17 - X"61", -- 0x18 - X"6C", -- 0x19 - X"6C", -- 0x1A - X"6F", -- 0x1B - X"0D", -- 0x1C - X"0A", -- 0x1D - X"00", -- 0x1E - X"4A", -- 0x1F - X"65", -- 0x20 - X"6E", -- 0x21 - X"73", -- 0x22 - X"00", -- 0x23 - X"57", -- 0x24 - X"65", -- 0x25 - X"6C", -- 0x26 - X"63", -- 0x27 - X"6F", -- 0x28 - X"6D", -- 0x29 - X"65", -- 0x2A - X"20", -- 0x2B - X"74", -- 0x2C - X"6F", -- 0x2D - X"20", -- 0x2E - X"4A", -- 0x2F - X"41", -- 0x30 - X"53", -- 0x31 - X"4D", -- 0x32 - X"20", -- 0x33 - X"43", -- 0x34 - X"50", -- 0x35 - X"55", -- 0x36 - X"00", -- 0x37 - X"52", -- 0x38 - X"65", -- 0x39 - X"61", -- 0x3A - X"64", -- 0x3B - X"79", -- 0x3C - X"00", -- 0x3D - X"54", -- 0x3E - X"65", -- 0x3F - X"73", -- 0x40 - X"74", -- 0x41 - X"69", -- 0x42 - X"6E", -- 0x43 - X"67", -- 0x44 - X"00", -- 0x45 - X"50", -- 0x46 - X"61", -- 0x47 - X"73", -- 0x48 - X"73", -- 0x49 - X"65", -- 0x4A - X"64", -- 0x4B - X"00", -- 0x4C - X"45", -- 0x4D - X"72", -- 0x4E - X"72", -- 0x4F - X"6F", -- 0x50 - X"72", -- 0x51 - X"00", -- 0x52 - X"0D", -- 0x53 - X"0A", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/itest_irom.vhdl b/lib/CPUs/JCpu/src/itest_irom.vhdl deleted file mode 100644 index 94609a3..0000000 --- a/lib/CPUs/JCpu/src/itest_irom.vhdl +++ /dev/null @@ -1,1089 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.types_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Generic - ( - depth : integer := 4 - ); - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in addr_t; - dout : out word_t - ); -END irom; - -ARCHITECTURE itest OF irom IS - - type imem_rom_t is array (0 to depth-1) of word_t; - - -- Assembled from itest.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"288", -- 0x001: JMP 0x288 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "111011" & X"03B", -- 0x010: CALL 0x03B - "101001" & X"000", -- 0x011: CIN R00, (0x00) - "100100" & X"000", -- 0x012: XOUT (0x00), R00 - "111011" & X"04C", -- 0x013: CALL 0x04C - "000011" & X"010", -- 0x014: MOV R00, 0x01 - "100100" & X"010", -- 0x015: XOUT (0x01), R00 - "111011" & X"08D", -- 0x016: CALL 0x08D - "000011" & X"020", -- 0x017: MOV R00, 0x02 - "100100" & X"010", -- 0x018: XOUT (0x01), R00 - "111011" & X"0C9", -- 0x019: CALL 0x0C9 - "000011" & X"030", -- 0x01A: MOV R00, 0x03 - "100100" & X"010", -- 0x01B: XOUT (0x01), R00 - "111011" & X"0DB", -- 0x01C: CALL 0x0DB - "000011" & X"040", -- 0x01D: MOV R00, 0x04 - "100100" & X"010", -- 0x01E: XOUT (0x01), R00 - "111011" & X"0ED", -- 0x01F: CALL 0x0ED - "000011" & X"050", -- 0x020: MOV R00, 0x05 - "100100" & X"010", -- 0x021: XOUT (0x01), R00 - "111011" & X"0FF", -- 0x022: CALL 0x0FF - "000011" & X"060", -- 0x023: MOV R00, 0x06 - "100100" & X"010", -- 0x024: XOUT (0x01), R00 - "111011" & X"115", -- 0x025: CALL 0x115 - "000011" & X"070", -- 0x026: MOV R00, 0x07 - "100100" & X"010", -- 0x027: XOUT (0x01), R00 - "111011" & X"12B", -- 0x028: CALL 0x12B - "000011" & X"080", -- 0x029: MOV R00, 0x08 - "100100" & X"010", -- 0x02A: XOUT (0x01), R00 - "111011" & X"137", -- 0x02B: CALL 0x137 - "000011" & X"090", -- 0x02C: MOV R00, 0x09 - "100100" & X"010", -- 0x02D: XOUT (0x01), R00 - "111011" & X"15A", -- 0x02E: CALL 0x15A - "000011" & X"0A0", -- 0x02F: MOV R00, 0x0A - "100100" & X"010", -- 0x030: XOUT (0x01), R00 - "111011" & X"22A", -- 0x031: CALL 0x22A - "000011" & X"0B0", -- 0x032: MOV R00, 0x0B - "100100" & X"010", -- 0x033: XOUT (0x01), R00 - "111011" & X"24D", -- 0x034: CALL 0x24D - "000011" & X"0C0", -- 0x035: MOV R00, 0x0C - "100100" & X"010", -- 0x036: XOUT (0x01), R00 - "111011" & X"278", -- 0x037: CALL 0x278 - "000011" & X"FF0", -- 0x038: MOV R00, 0xFF - "100100" & X"010", -- 0x039: XOUT (0x01), R00 - "110000" & X"2FF", -- 0x03A: JMP 0x2FF - "000011" & X"000", -- 0x03B: MOV R00, 0x00 - "000011" & X"001", -- 0x03C: MOV R01, 0x00 - "000011" & X"002", -- 0x03D: MOV R02, 0x00 - "000011" & X"003", -- 0x03E: MOV R03, 0x00 - "000011" & X"004", -- 0x03F: MOV R04, 0x00 - "000011" & X"005", -- 0x040: MOV R05, 0x00 - "000011" & X"006", -- 0x041: MOV R06, 0x00 - "000011" & X"007", -- 0x042: MOV R07, 0x00 - "000011" & X"008", -- 0x043: MOV R08, 0x00 - "000011" & X"009", -- 0x044: MOV R09, 0x00 - "000011" & X"00A", -- 0x045: MOV R10, 0x00 - "000011" & X"00B", -- 0x046: MOV R11, 0x00 - "000011" & X"00C", -- 0x047: MOV R12, 0x00 - "000011" & X"00D", -- 0x048: MOV R13, 0x00 - "000011" & X"00E", -- 0x049: MOV R14, 0x00 - "000011" & X"00F", -- 0x04A: MOV R15, 0x00 - "111110" & X"000", -- 0x04B: RET - "000011" & X"100", -- 0x04C: MOV R00, 0x10 - "001111" & X"100", -- 0x04D: CMP R00, 0x10 - "111010" & X"3FF", -- 0x04E: JNE 0x3FF - "010001" & X"010", -- 0x04F: ADD R00, 0x01 - "000010" & X"001", -- 0x050: MOV R01, R00 - "001111" & X"111", -- 0x051: CMP R01, 0x11 - "111010" & X"3FF", -- 0x052: JNE 0x3FF - "010001" & X"011", -- 0x053: ADD R01, 0x01 - "000010" & X"012", -- 0x054: MOV R02, R01 - "001111" & X"122", -- 0x055: CMP R02, 0x12 - "111010" & X"3FF", -- 0x056: JNE 0x3FF - "010001" & X"012", -- 0x057: ADD R02, 0x01 - "000010" & X"023", -- 0x058: MOV R03, R02 - "001111" & X"133", -- 0x059: CMP R03, 0x13 - "111010" & X"3FF", -- 0x05A: JNE 0x3FF - "010001" & X"013", -- 0x05B: ADD R03, 0x01 - "000010" & X"034", -- 0x05C: MOV R04, R03 - "001111" & X"144", -- 0x05D: CMP R04, 0x14 - "111010" & X"3FF", -- 0x05E: JNE 0x3FF - "010001" & X"014", -- 0x05F: ADD R04, 0x01 - "000010" & X"045", -- 0x060: MOV R05, R04 - "001111" & X"155", -- 0x061: CMP R05, 0x15 - "111010" & X"3FF", -- 0x062: JNE 0x3FF - "010001" & X"015", -- 0x063: ADD R05, 0x01 - "000010" & X"056", -- 0x064: MOV R06, R05 - "001111" & X"166", -- 0x065: CMP R06, 0x16 - "111010" & X"3FF", -- 0x066: JNE 0x3FF - "010001" & X"016", -- 0x067: ADD R06, 0x01 - "000010" & X"067", -- 0x068: MOV R07, R06 - "001111" & X"177", -- 0x069: CMP R07, 0x17 - "111010" & X"3FF", -- 0x06A: JNE 0x3FF - "010001" & X"017", -- 0x06B: ADD R07, 0x01 - "000010" & X"078", -- 0x06C: MOV R08, R07 - "001111" & X"188", -- 0x06D: CMP R08, 0x18 - "111010" & X"3FF", -- 0x06E: JNE 0x3FF - "010001" & X"018", -- 0x06F: ADD R08, 0x01 - "000010" & X"089", -- 0x070: MOV R09, R08 - "001111" & X"199", -- 0x071: CMP R09, 0x19 - "111010" & X"3FF", -- 0x072: JNE 0x3FF - "010001" & X"019", -- 0x073: ADD R09, 0x01 - "000010" & X"09A", -- 0x074: MOV R10, R09 - "001111" & X"1AA", -- 0x075: CMP R10, 0x1A - "111010" & X"3FF", -- 0x076: JNE 0x3FF - "010001" & X"01A", -- 0x077: ADD R10, 0x01 - "000010" & X"0AB", -- 0x078: MOV R11, R10 - "001111" & X"1BB", -- 0x079: CMP R11, 0x1B - "111010" & X"3FF", -- 0x07A: JNE 0x3FF - "010001" & X"01B", -- 0x07B: ADD R11, 0x01 - "000010" & X"0BC", -- 0x07C: MOV R12, R11 - "001111" & X"1CC", -- 0x07D: CMP R12, 0x1C - "111010" & X"3FF", -- 0x07E: JNE 0x3FF - "010001" & X"01C", -- 0x07F: ADD R12, 0x01 - "000010" & X"0CD", -- 0x080: MOV R13, R12 - "001111" & X"1DD", -- 0x081: CMP R13, 0x1D - "111010" & X"3FF", -- 0x082: JNE 0x3FF - "010001" & X"01D", -- 0x083: ADD R13, 0x01 - "000010" & X"0DE", -- 0x084: MOV R14, R13 - "001111" & X"1EE", -- 0x085: CMP R14, 0x1E - "111010" & X"3FF", -- 0x086: JNE 0x3FF - "010001" & X"01E", -- 0x087: ADD R14, 0x01 - "000010" & X"0EF", -- 0x088: MOV R15, R14 - "001111" & X"1FF", -- 0x089: CMP R15, 0x1F - "111010" & X"3FF", -- 0x08A: JNE 0x3FF - "010001" & X"01F", -- 0x08B: ADD R15, 0x01 - "111110" & X"000", -- 0x08C: RET - "000011" & X"000", -- 0x08D: MOV R00, 0x00 - "001111" & X"000", -- 0x08E: TST R00 - "110010" & X"3FF", -- 0x08F: JNZ 0x3FF - "110011" & X"3FF", -- 0x090: JC 0x3FF - "001111" & X"000", -- 0x091: CMP R00, 0x00 - "111010" & X"3FF", -- 0x092: JNE 0x3FF - "110101" & X"3FF", -- 0x093: JLT 0x3FF - "110110" & X"3FF", -- 0x094: JGT 0x3FF - "110111" & X"097", -- 0x095: JLE 0x097 - "110000" & X"3FF", -- 0x096: JMP 0x3FF - "111001" & X"099", -- 0x097: JEQ 0x099 - "110000" & X"3FF", -- 0x098: JMP 0x3FF - "111000" & X"09B", -- 0x099: JGE 0x09B - "110000" & X"3FF", -- 0x09A: JMP 0x3FF - "001111" & X"550", -- 0x09B: CMP R00, 0x55 - "111001" & X"3FF", -- 0x09C: JEQ 0x3FF - "110101" & X"09F", -- 0x09D: JLT 0x09F - "110000" & X"3FF", -- 0x09E: JMP 0x3FF - "110111" & X"0A1", -- 0x09F: JLE 0x0A1 - "110000" & X"3FF", -- 0x0A0: JMP 0x3FF - "111000" & X"3FF", -- 0x0A1: JGE 0x3FF - "110110" & X"3FF", -- 0x0A2: JGT 0x3FF - "000011" & X"550", -- 0x0A3: MOV R00, 0x55 - "001111" & X"000", -- 0x0A4: TST R00 - "110001" & X"3FF", -- 0x0A5: JZ 0x3FF - "110011" & X"3FF", -- 0x0A6: JC 0x3FF - "001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA - "111001" & X"3FF", -- 0x0A8: JEQ 0x3FF - "111010" & X"0AB", -- 0x0A9: JNE 0x0AB - "110000" & X"3FF", -- 0x0AA: JMP 0x3FF - "110101" & X"0AD", -- 0x0AB: JLT 0x0AD - "110000" & X"3FF", -- 0x0AC: JMP 0x3FF - "110111" & X"0AF", -- 0x0AD: JLE 0x0AF - "110000" & X"3FF", -- 0x0AE: JMP 0x3FF - "110110" & X"3FF", -- 0x0AF: JGT 0x3FF - "001111" & X"550", -- 0x0B0: CMP R00, 0x55 - "111001" & X"0B3", -- 0x0B1: JEQ 0x0B3 - "110000" & X"3FF", -- 0x0B2: JMP 0x3FF - "111010" & X"3FF", -- 0x0B3: JNE 0x3FF - "110101" & X"3FF", -- 0x0B4: JLT 0x3FF - "110111" & X"0B7", -- 0x0B5: JLE 0x0B7 - "110000" & X"3FF", -- 0x0B6: JMP 0x3FF - "110110" & X"3FF", -- 0x0B7: JGT 0x3FF - "111000" & X"0BA", -- 0x0B8: JGE 0x0BA - "110000" & X"3FF", -- 0x0B9: JMP 0x3FF - "000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA - "001111" & X"000", -- 0x0BB: TST R00 - "110001" & X"3FF", -- 0x0BC: JZ 0x3FF - "110011" & X"3FF", -- 0x0BD: JC 0x3FF - "001111" & X"550", -- 0x0BE: CMP R00, 0x55 - "111001" & X"3FF", -- 0x0BF: JEQ 0x3FF - "111010" & X"0C2", -- 0x0C0: JNE 0x0C2 - "110000" & X"3FF", -- 0x0C1: JMP 0x3FF - "110110" & X"0C4", -- 0x0C2: JGT 0x0C4 - "110000" & X"3FF", -- 0x0C3: JMP 0x3FF - "111000" & X"0C6", -- 0x0C4: JGE 0x0C6 - "110000" & X"3FF", -- 0x0C5: JMP 0x3FF - "110101" & X"3FF", -- 0x0C6: JLT 0x3FF - "110111" & X"3FF", -- 0x0C7: JLE 0x3FF - "111110" & X"000", -- 0x0C8: RET - "000011" & X"000", -- 0x0C9: MOV R00, 0x00 - "000011" & X"001", -- 0x0CA: MOV R01, 0x00 - "000010" & X"002", -- 0x0CB: MOV R02, R00 - "000010" & X"013", -- 0x0CC: MOV R03, R01 - "010001" & X"010", -- 0x0CD: ADD R00, 0x01 - "010011" & X"001", -- 0x0CE: ADDC R01, 0x00 - "010001" & X"012", -- 0x0CF: ADD R02, 0x01 - "001111" & X"002", -- 0x0D0: CMP R02, 0x00 - "111010" & X"0D4", -- 0x0D1: JNE 0x0D4 - "010001" & X"013", -- 0x0D2: ADD R03, 0x01 - "001111" & X"023", -- 0x0D3: CMP R03, 0x02 - "111010" & X"0CD", -- 0x0D4: JNE 0x0CD - "001110" & X"020", -- 0x0D5: CMP R00, R02 - "111010" & X"3FF", -- 0x0D6: JNE 0x3FF - "001110" & X"031", -- 0x0D7: CMP R01, R03 - "111010" & X"3FF", -- 0x0D8: JNE 0x3FF - "000011" & X"000", -- 0x0D9: MOV R00, 0x00 - "111110" & X"000", -- 0x0DA: RET - "000011" & X"000", -- 0x0DB: MOV R00, 0x00 - "000011" & X"031", -- 0x0DC: MOV R01, 0x03 - "000010" & X"002", -- 0x0DD: MOV R02, R00 - "000010" & X"013", -- 0x0DE: MOV R03, R01 - "010101" & X"010", -- 0x0DF: SUB R00, 0x01 - "010111" & X"001", -- 0x0E0: SUBC R01, 0x00 - "010101" & X"012", -- 0x0E1: SUB R02, 0x01 - "001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF - "111010" & X"0E6", -- 0x0E3: JNE 0x0E6 - "010101" & X"013", -- 0x0E4: SUB R03, 0x01 - "001111" & X"003", -- 0x0E5: CMP R03, 0x00 - "111010" & X"0DF", -- 0x0E6: JNE 0x0DF - "001110" & X"020", -- 0x0E7: CMP R00, R02 - "111010" & X"3FF", -- 0x0E8: JNE 0x3FF - "001110" & X"031", -- 0x0E9: CMP R01, R03 - "111010" & X"3FF", -- 0x0EA: JNE 0x3FF - "000011" & X"000", -- 0x0EB: MOV R00, 0x00 - "111110" & X"000", -- 0x0EC: RET - "000011" & X"030", -- 0x0ED: MOV R00, 0x03 - "000011" & X"051", -- 0x0EE: MOV R01, 0x05 - "101110" & X"050", -- 0x0EF: SUB 0x05, R00 - "010101" & X"031", -- 0x0F0: SUB R01, 0x03 - "001110" & X"010", -- 0x0F1: CMP R00, R01 - "111010" & X"3FF", -- 0x0F2: JNE 0x3FF - "000011" & X"030", -- 0x0F3: MOV R00, 0x03 - "000011" & X"051", -- 0x0F4: MOV R01, 0x05 - "010100" & X"010", -- 0x0F5: SUB R00, R01 - "101111" & X"000", -- 0x0F6: SUBC 0x00, R00 - "001111" & X"010", -- 0x0F7: CMP R00, 0x01 - "111010" & X"3FF", -- 0x0F8: JNE 0x3FF - "010001" & X"000", -- 0x0F9: ADD R00, 0x00 - "010110" & X"001", -- 0x0FA: SUBC R01, R00 - "001111" & X"041", -- 0x0FB: CMP R01, 0x04 - "111010" & X"3FF", -- 0x0FC: JNE 0x3FF - "000011" & X"000", -- 0x0FD: MOV R00, 0x00 - "111110" & X"000", -- 0x0FE: RET - "000011" & X"010", -- 0x0FF: MOV R00, 0x01 - "001101" & X"5A0", -- 0x100: MOVC (0x5A), R00 - "010101" & X"010", -- 0x101: DEC R00 - "001101" & X"000", -- 0x102: MOVC (0x00), R00 - "001010" & X"5A1", -- 0x103: MOVC R01, (0x5A) - "001100" & X"A51", -- 0x104: MOVC (R01), 0xA5 - "001001" & X"010", -- 0x105: MOVC R00, (R01) - "001001" & X"011", -- 0x106: MOVC R01, (R01) - "010001" & X"5A1", -- 0x107: ADD R01, 0x5A - "001001" & X"010", -- 0x108: MOVC R00, (R01) - "001011" & X"000", -- 0x109: MOVC (R00), R00 - "001001" & X"002", -- 0x10A: MOVC R02, (R00) - "001110" & X"002", -- 0x10B: CMP R02, R00 - "111010" & X"3FF", -- 0x10C: JNE 0x3FF - "001011" & X"021", -- 0x10D: MOVC (R01), R02 - "001001" & X"022", -- 0x10E: MOVC R02, (R02) - "001110" & X"012", -- 0x10F: CMP R02, R01 - "111010" & X"3FF", -- 0x110: JNE 0x3FF - "010101" & X"011", -- 0x111: DEC R01 - "010001" & X"010", -- 0x112: INC R00 - "110010" & X"109", -- 0x113: JNZ 0x109 - "111110" & X"000", -- 0x114: RET - "000011" & X"010", -- 0x115: MOV R00, 0x01 - "001000" & X"600", -- 0x116: MOVX (0x60), R00 - "010101" & X"010", -- 0x117: DEC R00 - "001000" & X"060", -- 0x118: MOVX (0x06), R00 - "000101" & X"601", -- 0x119: MOVX R01, (0x60) - "000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5 - "000100" & X"010", -- 0x11B: MOVX R00, (R01) - "000100" & X"011", -- 0x11C: MOVX R01, (R01) - "010001" & X"5A1", -- 0x11D: ADD R01, 0x5A - "000100" & X"010", -- 0x11E: MOVX R00, (R01) - "000110" & X"000", -- 0x11F: MOVX (R00), R00 - "000100" & X"002", -- 0x120: MOVX R02, (R00) - "001110" & X"002", -- 0x121: CMP R02, R00 - "111010" & X"3FF", -- 0x122: JNE 0x3FF - "000110" & X"021", -- 0x123: MOVX (R01), R02 - "000100" & X"022", -- 0x124: MOVX R02, (R02) - "001110" & X"012", -- 0x125: CMP R02, R01 - "111010" & X"3FF", -- 0x126: JNE 0x3FF - "010101" & X"011", -- 0x127: DEC R01 - "010001" & X"010", -- 0x128: INC R00 - "110010" & X"11F", -- 0x129: JNZ 0x11F - "111110" & X"000", -- 0x12A: RET - "000011" & X"AA0", -- 0x12B: MOV R00, 0xAA - "000011" & X"001", -- 0x12C: MOV R01, 0x00 - "111100" & X"000", -- 0x12D: PUSH R00 - "010001" & X"010", -- 0x12E: INC R00 - "010101" & X"011", -- 0x12F: DEC R01 - "110010" & X"12D", -- 0x130: JNZ 0x12D - "111101" & X"000", -- 0x131: POP R00 - "010101" & X"011", -- 0x132: DEC R01 - "110010" & X"131", -- 0x133: JNZ 0x131 - "001111" & X"AA0", -- 0x134: CMP R00, 0xAA - "111010" & X"3FF", -- 0x135: JNE 0x3FF - "111110" & X"000", -- 0x136: RET - "000011" & X"550", -- 0x137: MOV R00, 0x55 - "111100" & X"000", -- 0x138: PUSH R00 - "000011" & X"000", -- 0x139: MOV R00, 0x00 - "000011" & X"FF1", -- 0x13A: MOV R01, 0xFF - "111011" & X"151", -- 0x13B: CALL 0x151 - "111101" & X"000", -- 0x13C: POP R00 - "001111" & X"550", -- 0x13D: CMP R00, 0x55 - "111010" & X"3FF", -- 0x13E: JNE 0x3FF - "000011" & X"010", -- 0x13F: MOV R00, 0x01 - "000011" & X"481", -- 0x140: MOV R01, 0x48 - "100110" & X"050", -- 0x141: COUT (0x05), R00 - "111100" & X"001", -- 0x142: PUSH R01 - "000011" & X"000", -- 0x143: MOV R00, 0x00 - "000011" & X"3B1", -- 0x144: MOV R01, 0x3B - "100110" & X"050", -- 0x145: COUT (0x05), R00 - "111100" & X"001", -- 0x146: PUSH R01 - "111110" & X"000", -- 0x147: RET - "000011" & X"010", -- 0x148: MOV R00, 0x01 - "000011" & X"501", -- 0x149: MOV R01, 0x50 - "100110" & X"050", -- 0x14A: COUT (0x05), R00 - "111100" & X"001", -- 0x14B: PUSH R01 - "000011" & X"000", -- 0x14C: MOV R00, 0x00 - "000011" & X"3B1", -- 0x14D: MOV R01, 0x3B - "100110" & X"050", -- 0x14E: COUT (0x05), R00 - "111100" & X"001", -- 0x14F: PUSH R01 - "111110" & X"000", -- 0x150: RET - "001110" & X"010", -- 0x151: CMP R00, R01 - "111001" & X"155", -- 0x152: JEQ 0x155 - "010001" & X"010", -- 0x153: INC R00 - "110000" & X"158", -- 0x154: JMP 0x158 - "010101" & X"010", -- 0x155: DEC R00 - "010101" & X"011", -- 0x156: DEC R01 - "111110" & X"000", -- 0x157: RET - "111011" & X"151", -- 0x158: CALL 0x151 - "110000" & X"155", -- 0x159: JMP 0x155 - "000011" & X"A50", -- 0x15A: MOV R00, 0xA5 - "000011" & X"5A1", -- 0x15B: MOV R01, 0x5A - "101010" & X"000", -- 0x15C: SWAP R00 - "001111" & X"5A0", -- 0x15D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x15E: JNE 0x3FF - "101010" & X"000", -- 0x15F: SWAP R00 - "001111" & X"A50", -- 0x160: CMP R00, 0xA5 - "111010" & X"3FF", -- 0x161: JNE 0x3FF - "000011" & X"D20", -- 0x162: MOV R00, 0xD2 - "101010" & X"000", -- 0x163: SWAP R00 - "001111" & X"2D0", -- 0x164: CMP R00, 0x2D - "111010" & X"3FF", -- 0x165: JNE 0x3FF - "101010" & X"001", -- 0x166: SWAP R01 - "001111" & X"2D0", -- 0x167: CMP R00, 0x2D - "111010" & X"3FF", -- 0x168: JNE 0x3FF - "001111" & X"A51", -- 0x169: CMP R01, 0xA5 - "111010" & X"3FF", -- 0x16A: JNE 0x3FF - "000011" & X"2D0", -- 0x16B: MOV R00, 0x2D - "011110" & X"000", -- 0x16C: SHL R00 - "001111" & X"5A0", -- 0x16D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x16E: JNE 0x3FF - "011110" & X"000", -- 0x16F: SHL R00 - "001111" & X"B40", -- 0x170: CMP R00, 0xB4 - "111010" & X"3FF", -- 0x171: JNE 0x3FF - "011110" & X"000", -- 0x172: SHL R00 - "001111" & X"680", -- 0x173: CMP R00, 0x68 - "111010" & X"3FF", -- 0x174: JNE 0x3FF - "011110" & X"000", -- 0x175: SHL R00 - "001111" & X"D00", -- 0x176: CMP R00, 0xD0 - "111010" & X"3FF", -- 0x177: JNE 0x3FF - "011110" & X"000", -- 0x178: SHL R00 - "001111" & X"A00", -- 0x179: CMP R00, 0xA0 - "111010" & X"3FF", -- 0x17A: JNE 0x3FF - "011110" & X"000", -- 0x17B: SHL R00 - "001111" & X"400", -- 0x17C: CMP R00, 0x40 - "111010" & X"3FF", -- 0x17D: JNE 0x3FF - "011110" & X"000", -- 0x17E: SHL R00 - "001111" & X"800", -- 0x17F: CMP R00, 0x80 - "111010" & X"3FF", -- 0x180: JNE 0x3FF - "011110" & X"000", -- 0x181: SHL R00 - "001111" & X"000", -- 0x182: CMP R00, 0x00 - "111010" & X"3FF", -- 0x183: JNE 0x3FF - "000011" & X"841", -- 0x184: MOV R01, 0x84 - "011111" & X"001", -- 0x185: SHR R01 - "001111" & X"421", -- 0x186: CMP R01, 0x42 - "111010" & X"3FF", -- 0x187: JNE 0x3FF - "011111" & X"001", -- 0x188: SHR R01 - "001111" & X"211", -- 0x189: CMP R01, 0x21 - "111010" & X"3FF", -- 0x18A: JNE 0x3FF - "011111" & X"001", -- 0x18B: SHR R01 - "001111" & X"101", -- 0x18C: CMP R01, 0x10 - "111010" & X"3FF", -- 0x18D: JNE 0x3FF - "011111" & X"001", -- 0x18E: SHR R01 - "001111" & X"081", -- 0x18F: CMP R01, 0x08 - "111010" & X"3FF", -- 0x190: JNE 0x3FF - "011111" & X"001", -- 0x191: SHR R01 - "001111" & X"041", -- 0x192: CMP R01, 0x04 - "111010" & X"3FF", -- 0x193: JNE 0x3FF - "011111" & X"001", -- 0x194: SHR R01 - "001111" & X"021", -- 0x195: CMP R01, 0x02 - "111010" & X"3FF", -- 0x196: JNE 0x3FF - "011111" & X"001", -- 0x197: SHR R01 - "001111" & X"011", -- 0x198: CMP R01, 0x01 - "111010" & X"3FF", -- 0x199: JNE 0x3FF - "011111" & X"001", -- 0x19A: SHR R01 - "001111" & X"001", -- 0x19B: CMP R01, 0x00 - "111010" & X"3FF", -- 0x19C: JNE 0x3FF - "000011" & X"C50", -- 0x19D: MOV R00, 0xC5 - "100000" & X"000", -- 0x19E: ROL R00 - "001111" & X"8B0", -- 0x19F: CMP R00, 0x8B - "111010" & X"3FF", -- 0x1A0: JNE 0x3FF - "100000" & X"000", -- 0x1A1: ROL R00 - "001111" & X"170", -- 0x1A2: CMP R00, 0x17 - "111010" & X"3FF", -- 0x1A3: JNE 0x3FF - "100000" & X"000", -- 0x1A4: ROL R00 - "001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E - "111010" & X"3FF", -- 0x1A6: JNE 0x3FF - "100000" & X"000", -- 0x1A7: ROL R00 - "001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C - "111010" & X"3FF", -- 0x1A9: JNE 0x3FF - "100000" & X"000", -- 0x1AA: ROL R00 - "001111" & X"B80", -- 0x1AB: CMP R00, 0xB8 - "111010" & X"3FF", -- 0x1AC: JNE 0x3FF - "100000" & X"000", -- 0x1AD: ROL R00 - "001111" & X"710", -- 0x1AE: CMP R00, 0x71 - "111010" & X"3FF", -- 0x1AF: JNE 0x3FF - "100000" & X"000", -- 0x1B0: ROL R00 - "001111" & X"E20", -- 0x1B1: CMP R00, 0xE2 - "111010" & X"3FF", -- 0x1B2: JNE 0x3FF - "100000" & X"000", -- 0x1B3: ROL R00 - "001111" & X"C50", -- 0x1B4: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1B5: JNE 0x3FF - "000011" & X"631", -- 0x1B6: MOV R01, 0x63 - "100001" & X"001", -- 0x1B7: ROR R01 - "001111" & X"B11", -- 0x1B8: CMP R01, 0xB1 - "111010" & X"3FF", -- 0x1B9: JNE 0x3FF - "100001" & X"001", -- 0x1BA: ROR R01 - "001111" & X"D81", -- 0x1BB: CMP R01, 0xD8 - "111010" & X"3FF", -- 0x1BC: JNE 0x3FF - "100001" & X"001", -- 0x1BD: ROR R01 - "001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C - "111010" & X"3FF", -- 0x1BF: JNE 0x3FF - "100001" & X"001", -- 0x1C0: ROR R01 - "001111" & X"361", -- 0x1C1: CMP R01, 0x36 - "111010" & X"3FF", -- 0x1C2: JNE 0x3FF - "100001" & X"001", -- 0x1C3: ROR R01 - "001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B - "111010" & X"3FF", -- 0x1C5: JNE 0x3FF - "100001" & X"001", -- 0x1C6: ROR R01 - "001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D - "111010" & X"3FF", -- 0x1C8: JNE 0x3FF - "100001" & X"001", -- 0x1C9: ROR R01 - "001111" & X"C61", -- 0x1CA: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x1CB: JNE 0x3FF - "100001" & X"001", -- 0x1CC: ROR R01 - "001111" & X"631", -- 0x1CD: CMP R01, 0x63 - "111010" & X"3FF", -- 0x1CE: JNE 0x3FF - "011100" & X"000", -- 0x1CF: XOR R00, R00 - "000011" & X"C50", -- 0x1D0: MOV R00, 0xC5 - "100010" & X"000", -- 0x1D1: ROLC R00 - "111100" & X"000", -- 0x1D2: PUSH R00 - "100010" & X"000", -- 0x1D3: ROLC R00 - "111100" & X"000", -- 0x1D4: PUSH R00 - "100010" & X"000", -- 0x1D5: ROLC R00 - "111100" & X"000", -- 0x1D6: PUSH R00 - "100010" & X"000", -- 0x1D7: ROLC R00 - "111100" & X"000", -- 0x1D8: PUSH R00 - "100010" & X"000", -- 0x1D9: ROLC R00 - "111100" & X"000", -- 0x1DA: PUSH R00 - "100010" & X"000", -- 0x1DB: ROLC R00 - "111100" & X"000", -- 0x1DC: PUSH R00 - "100010" & X"000", -- 0x1DD: ROLC R00 - "111100" & X"000", -- 0x1DE: PUSH R00 - "100010" & X"000", -- 0x1DF: ROLC R00 - "111100" & X"000", -- 0x1E0: PUSH R00 - "100010" & X"000", -- 0x1E1: ROLC R00 - "001111" & X"C50", -- 0x1E2: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1E3: JNE 0x3FF - "111101" & X"000", -- 0x1E4: POP R00 - "001111" & X"620", -- 0x1E5: CMP R00, 0x62 - "111010" & X"3FF", -- 0x1E6: JNE 0x3FF - "111101" & X"000", -- 0x1E7: POP R00 - "001111" & X"B10", -- 0x1E8: CMP R00, 0xB1 - "111010" & X"3FF", -- 0x1E9: JNE 0x3FF - "111101" & X"000", -- 0x1EA: POP R00 - "001111" & X"580", -- 0x1EB: CMP R00, 0x58 - "111010" & X"3FF", -- 0x1EC: JNE 0x3FF - "111101" & X"000", -- 0x1ED: POP R00 - "001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC - "111010" & X"3FF", -- 0x1EF: JNE 0x3FF - "111101" & X"000", -- 0x1F0: POP R00 - "001111" & X"560", -- 0x1F1: CMP R00, 0x56 - "111010" & X"3FF", -- 0x1F2: JNE 0x3FF - "111101" & X"000", -- 0x1F3: POP R00 - "001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B - "111010" & X"3FF", -- 0x1F5: JNE 0x3FF - "111101" & X"000", -- 0x1F6: POP R00 - "001111" & X"150", -- 0x1F7: CMP R00, 0x15 - "111010" & X"3FF", -- 0x1F8: JNE 0x3FF - "111101" & X"000", -- 0x1F9: POP R00 - "001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A - "111010" & X"3FF", -- 0x1FB: JNE 0x3FF - "011100" & X"011", -- 0x1FC: XOR R01, R01 - "000011" & X"631", -- 0x1FD: MOV R01, 0x63 - "100011" & X"001", -- 0x1FE: RORC R01 - "111100" & X"001", -- 0x1FF: PUSH R01 - "100011" & X"001", -- 0x200: RORC R01 - "111100" & X"001", -- 0x201: PUSH R01 - "100011" & X"001", -- 0x202: RORC R01 - "111100" & X"001", -- 0x203: PUSH R01 - "100011" & X"001", -- 0x204: RORC R01 - "111100" & X"001", -- 0x205: PUSH R01 - "100011" & X"001", -- 0x206: RORC R01 - "111100" & X"001", -- 0x207: PUSH R01 - "100011" & X"001", -- 0x208: RORC R01 - "111100" & X"001", -- 0x209: PUSH R01 - "100011" & X"001", -- 0x20A: RORC R01 - "111100" & X"001", -- 0x20B: PUSH R01 - "100011" & X"001", -- 0x20C: RORC R01 - "111100" & X"001", -- 0x20D: PUSH R01 - "100011" & X"001", -- 0x20E: RORC R01 - "001111" & X"631", -- 0x20F: CMP R01, 0x63 - "111010" & X"3FF", -- 0x210: JNE 0x3FF - "111101" & X"001", -- 0x211: POP R01 - "001111" & X"C61", -- 0x212: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x213: JNE 0x3FF - "111101" & X"001", -- 0x214: POP R01 - "001111" & X"8C1", -- 0x215: CMP R01, 0x8C - "111010" & X"3FF", -- 0x216: JNE 0x3FF - "111101" & X"001", -- 0x217: POP R01 - "001111" & X"191", -- 0x218: CMP R01, 0x19 - "111010" & X"3FF", -- 0x219: JNE 0x3FF - "111101" & X"001", -- 0x21A: POP R01 - "001111" & X"331", -- 0x21B: CMP R01, 0x33 - "111010" & X"3FF", -- 0x21C: JNE 0x3FF - "111101" & X"001", -- 0x21D: POP R01 - "001111" & X"661", -- 0x21E: CMP R01, 0x66 - "111010" & X"3FF", -- 0x21F: JNE 0x3FF - "111101" & X"001", -- 0x220: POP R01 - "001111" & X"CC1", -- 0x221: CMP R01, 0xCC - "111010" & X"3FF", -- 0x222: JNE 0x3FF - "111101" & X"001", -- 0x223: POP R01 - "001111" & X"981", -- 0x224: CMP R01, 0x98 - "111010" & X"3FF", -- 0x225: JNE 0x3FF - "111101" & X"001", -- 0x226: POP R01 - "001111" & X"311", -- 0x227: CMP R01, 0x31 - "111010" & X"3FF", -- 0x228: JNE 0x3FF - "111110" & X"000", -- 0x229: RET - "000011" & X"A50", -- 0x22A: MOV R00, 0xA5 - "101010" & X"000", -- 0x22B: SWAP R00 - "111100" & X"000", -- 0x22C: PUSH R00 - "011001" & X"0F0", -- 0x22D: AND R00, 0x0F - "001111" & X"0A0", -- 0x22E: CMP R00, 0x0A - "111010" & X"3FF", -- 0x22F: JNE 0x3FF - "111101" & X"000", -- 0x230: POP R00 - "111100" & X"000", -- 0x231: PUSH R00 - "011001" & X"0F0", -- 0x232: AND R00, 0x0F - "001111" & X"0A0", -- 0x233: CMP R00, 0x0A - "111101" & X"001", -- 0x234: POP R01 - "111010" & X"3FF", -- 0x235: JNE 0x3FF - "101010" & X"001", -- 0x236: SWAP R01 - "000011" & X"0F2", -- 0x237: MOV R02, 0x0F - "011000" & X"021", -- 0x238: AND R01, R02 - "001111" & X"051", -- 0x239: CMP R01, 0x05 - "111010" & X"3FF", -- 0x23A: JNE 0x3FF - "000011" & X"050", -- 0x23B: MOV R00, 0x05 - "000011" & X"A02", -- 0x23C: MOV R02, 0xA0 - "101010" & X"000", -- 0x23D: SWAP R00 - "011010" & X"002", -- 0x23E: OR R02, R00 - "001111" & X"F02", -- 0x23F: CMP R02, 0xF0 - "111010" & X"3FF", -- 0x240: JNE 0x3FF - "101010" & X"000", -- 0x241: SWAP R00 - "011011" & X"500", -- 0x242: OR R00, 0x50 - "001111" & X"550", -- 0x243: CMP R00, 0x55 - "111010" & X"3FF", -- 0x244: JNE 0x3FF - "000011" & X"011", -- 0x245: MOV R01, 0x01 - "000011" & X"010", -- 0x246: MOV R00, 0x01 - "011101" & X"010", -- 0x247: XOR R00, 0x01 - "110010" & X"3FF", -- 0x248: JNZ 0x3FF - "011100" & X"010", -- 0x249: XOR R00, R01 - "001111" & X"010", -- 0x24A: CMP R00, 0x01 - "111010" & X"3FF", -- 0x24B: JNE 0x3FF - "111110" & X"000", -- 0x24C: RET - "000011" & X"030", -- 0x24D: MOV R00, 0x03 - "100110" & X"030", -- 0x24E: COUT (0x03), R00 - "101000" & X"020", -- 0x24F: XIN R00, (0x02) - "011011" & X"010", -- 0x250: OR R00, 0x01 - "100100" & X"020", -- 0x251: XOUT (0x02), R00 - "000000" & X"000", -- 0x252: NOP - "000000" & X"000", -- 0x253: NOP - "000000" & X"000", -- 0x254: NOP - "000000" & X"000", -- 0x255: NOP - "000000" & X"000", -- 0x256: NOP - "000000" & X"000", -- 0x257: NOP - "101000" & X"020", -- 0x258: XIN R00, (0x02) - "011001" & X"FE0", -- 0x259: AND R00, 0xFE - "100100" & X"020", -- 0x25A: XOUT (0x02), R00 - "000000" & X"000", -- 0x25B: NOP - "000000" & X"000", -- 0x25C: NOP - "000000" & X"000", -- 0x25D: NOP - "000000" & X"000", -- 0x25E: NOP - "101001" & X"030", -- 0x25F: CIN R00, (0x03) - "011011" & X"800", -- 0x260: OR R00, 0x80 - "100110" & X"030", -- 0x261: COUT (0x03), R00 - "000000" & X"000", -- 0x262: NOP - "101001" & X"030", -- 0x263: CIN R00, (0x03) - "011011" & X"800", -- 0x264: OR R00, 0x80 - "100110" & X"030", -- 0x265: COUT (0x03), R00 - "000000" & X"000", -- 0x266: NOP - "101001" & X"030", -- 0x267: CIN R00, (0x03) - "011011" & X"800", -- 0x268: OR R00, 0x80 - "100110" & X"030", -- 0x269: COUT (0x03), R00 - "000000" & X"000", -- 0x26A: NOP - "101001" & X"030", -- 0x26B: CIN R00, (0x03) - "011011" & X"800", -- 0x26C: OR R00, 0x80 - "100110" & X"030", -- 0x26D: COUT (0x03), R00 - "000000" & X"000", -- 0x26E: NOP - "000000" & X"000", -- 0x26F: NOP - "000000" & X"000", -- 0x270: NOP - "000000" & X"000", -- 0x271: NOP - "000000" & X"000", -- 0x272: NOP - "000000" & X"000", -- 0x273: NOP - "000000" & X"000", -- 0x274: NOP - "000000" & X"000", -- 0x275: NOP - "000000" & X"000", -- 0x276: NOP - "111110" & X"000", -- 0x277: RET - "010101" & X"000", -- 0x278: SUB R00, 0x00 - "110011" & X"3FF", -- 0x279: JC 0x3FF - "101011" & X"000", -- 0x27A: SETC - "110100" & X"3FF", -- 0x27B: JNC 0x3FF - "000000" & X"000", -- 0x27C: NOP - "010101" & X"000", -- 0x27D: SUB R00, 0x00 - "110011" & X"3FF", -- 0x27E: JC 0x3FF - "000011" & X"000", -- 0x27F: MOV R00, 0x00 - "010101" & X"000", -- 0x280: CLRC - "110011" & X"3FF", -- 0x281: JC 0x3FF - "101011" & X"000", -- 0x282: SETC - "110100" & X"3FF", -- 0x283: JNC 0x3FF - "000000" & X"000", -- 0x284: NOP - "010101" & X"000", -- 0x285: CLRC - "110011" & X"3FF", -- 0x286: JC 0x3FF - "111110" & X"000", -- 0x287: RET - "010001" & X"01E", -- 0x288: INC R14 - "111111" & X"000", -- 0x289: RETI - "000000" & X"000", -- 0x28A: - "000000" & X"000", -- 0x28B: - "000000" & X"000", -- 0x28C: - "000000" & X"000", -- 0x28D: - "000000" & X"000", -- 0x28E: - "000000" & X"000", -- 0x28F: - "000000" & X"000", -- 0x290: - "000000" & X"000", -- 0x291: - "000000" & X"000", -- 0x292: - "000000" & X"000", -- 0x293: - "000000" & X"000", -- 0x294: - "000000" & X"000", -- 0x295: - "000000" & X"000", -- 0x296: - "000000" & X"000", -- 0x297: - "000000" & X"000", -- 0x298: - "000000" & X"000", -- 0x299: - "000000" & X"000", -- 0x29A: - "000000" & X"000", -- 0x29B: - "000000" & X"000", -- 0x29C: - "000000" & X"000", -- 0x29D: - "000000" & X"000", -- 0x29E: - "000000" & X"000", -- 0x29F: - "000000" & X"000", -- 0x2A0: - "000000" & X"000", -- 0x2A1: - "000000" & X"000", -- 0x2A2: - "000000" & X"000", -- 0x2A3: - "000000" & X"000", -- 0x2A4: - "000000" & X"000", -- 0x2A5: - "000000" & X"000", -- 0x2A6: - "000000" & X"000", -- 0x2A7: - "000000" & X"000", -- 0x2A8: - "000000" & X"000", -- 0x2A9: - "000000" & X"000", -- 0x2AA: - "000000" & X"000", -- 0x2AB: - "000000" & X"000", -- 0x2AC: - "000000" & X"000", -- 0x2AD: - "000000" & X"000", -- 0x2AE: - "000000" & X"000", -- 0x2AF: - "000000" & X"000", -- 0x2B0: - "000000" & X"000", -- 0x2B1: - "000000" & X"000", -- 0x2B2: - "000000" & X"000", -- 0x2B3: - "000000" & X"000", -- 0x2B4: - "000000" & X"000", -- 0x2B5: - "000000" & X"000", -- 0x2B6: - "000000" & X"000", -- 0x2B7: - "000000" & X"000", -- 0x2B8: - "000000" & X"000", -- 0x2B9: - "000000" & X"000", -- 0x2BA: - "000000" & X"000", -- 0x2BB: - "000000" & X"000", -- 0x2BC: - "000000" & X"000", -- 0x2BD: - "000000" & X"000", -- 0x2BE: - "000000" & X"000", -- 0x2BF: - "000000" & X"000", -- 0x2C0: - "000000" & X"000", -- 0x2C1: - "000000" & X"000", -- 0x2C2: - "000000" & X"000", -- 0x2C3: - "000000" & X"000", -- 0x2C4: - "000000" & X"000", -- 0x2C5: - "000000" & X"000", -- 0x2C6: - "000000" & X"000", -- 0x2C7: - "000000" & X"000", -- 0x2C8: - "000000" & X"000", -- 0x2C9: - "000000" & X"000", -- 0x2CA: - "000000" & X"000", -- 0x2CB: - "000000" & X"000", -- 0x2CC: - "000000" & X"000", -- 0x2CD: - "000000" & X"000", -- 0x2CE: - "000000" & X"000", -- 0x2CF: - "000000" & X"000", -- 0x2D0: - "000000" & X"000", -- 0x2D1: - "000000" & X"000", -- 0x2D2: - "000000" & X"000", -- 0x2D3: - "000000" & X"000", -- 0x2D4: - "000000" & X"000", -- 0x2D5: - "000000" & X"000", -- 0x2D6: - "000000" & X"000", -- 0x2D7: - "000000" & X"000", -- 0x2D8: - "000000" & X"000", -- 0x2D9: - "000000" & X"000", -- 0x2DA: - "000000" & X"000", -- 0x2DB: - "000000" & X"000", -- 0x2DC: - "000000" & X"000", -- 0x2DD: - "000000" & X"000", -- 0x2DE: - "000000" & X"000", -- 0x2DF: - "000000" & X"000", -- 0x2E0: - "000000" & X"000", -- 0x2E1: - "000000" & X"000", -- 0x2E2: - "000000" & X"000", -- 0x2E3: - "000000" & X"000", -- 0x2E4: - "000000" & X"000", -- 0x2E5: - "000000" & X"000", -- 0x2E6: - "000000" & X"000", -- 0x2E7: - "000000" & X"000", -- 0x2E8: - "000000" & X"000", -- 0x2E9: - "000000" & X"000", -- 0x2EA: - "000000" & X"000", -- 0x2EB: - "000000" & X"000", -- 0x2EC: - "000000" & X"000", -- 0x2ED: - "000000" & X"000", -- 0x2EE: - "000000" & X"000", -- 0x2EF: - "000000" & X"000", -- 0x2F0: - "000000" & X"000", -- 0x2F1: - "000000" & X"000", -- 0x2F2: - "000000" & X"000", -- 0x2F3: - "000000" & X"000", -- 0x2F4: - "000000" & X"000", -- 0x2F5: - "000000" & X"000", -- 0x2F6: - "000000" & X"000", -- 0x2F7: - "000000" & X"000", -- 0x2F8: - "000000" & X"000", -- 0x2F9: - "000000" & X"000", -- 0x2FA: - "000000" & X"000", -- 0x2FB: - "000000" & X"000", -- 0x2FC: - "000000" & X"000", -- 0x2FD: - "000000" & X"000", -- 0x2FE: - "110000" & X"2FF", -- 0x2FF: JMP 0x2FF - "000000" & X"000", -- 0x300: - "000000" & X"000", -- 0x301: - "000000" & X"000", -- 0x302: - "000000" & X"000", -- 0x303: - "000000" & X"000", -- 0x304: - "000000" & X"000", -- 0x305: - "000000" & X"000", -- 0x306: - "000000" & X"000", -- 0x307: - "000000" & X"000", -- 0x308: - "000000" & X"000", -- 0x309: - "000000" & X"000", -- 0x30A: - "000000" & X"000", -- 0x30B: - "000000" & X"000", -- 0x30C: - "000000" & X"000", -- 0x30D: - "000000" & X"000", -- 0x30E: - "000000" & X"000", -- 0x30F: - "000000" & X"000", -- 0x310: - "000000" & X"000", -- 0x311: - "000000" & X"000", -- 0x312: - "000000" & X"000", -- 0x313: - "000000" & X"000", -- 0x314: - "000000" & X"000", -- 0x315: - "000000" & X"000", -- 0x316: - "000000" & X"000", -- 0x317: - "000000" & X"000", -- 0x318: - "000000" & X"000", -- 0x319: - "000000" & X"000", -- 0x31A: - "000000" & X"000", -- 0x31B: - "000000" & X"000", -- 0x31C: - "000000" & X"000", -- 0x31D: - "000000" & X"000", -- 0x31E: - "000000" & X"000", -- 0x31F: - "000000" & X"000", -- 0x320: - "000000" & X"000", -- 0x321: - "000000" & X"000", -- 0x322: - "000000" & X"000", -- 0x323: - "000000" & X"000", -- 0x324: - "000000" & X"000", -- 0x325: - "000000" & X"000", -- 0x326: - "000000" & X"000", -- 0x327: - "000000" & X"000", -- 0x328: - "000000" & X"000", -- 0x329: - "000000" & X"000", -- 0x32A: - "000000" & X"000", -- 0x32B: - "000000" & X"000", -- 0x32C: - "000000" & X"000", -- 0x32D: - "000000" & X"000", -- 0x32E: - "000000" & X"000", -- 0x32F: - "000000" & X"000", -- 0x330: - "000000" & X"000", -- 0x331: - "000000" & X"000", -- 0x332: - "000000" & X"000", -- 0x333: - "000000" & X"000", -- 0x334: - "000000" & X"000", -- 0x335: - "000000" & X"000", -- 0x336: - "000000" & X"000", -- 0x337: - "000000" & X"000", -- 0x338: - "000000" & X"000", -- 0x339: - "000000" & X"000", -- 0x33A: - "000000" & X"000", -- 0x33B: - "000000" & X"000", -- 0x33C: - "000000" & X"000", -- 0x33D: - "000000" & X"000", -- 0x33E: - "000000" & X"000", -- 0x33F: - "000000" & X"000", -- 0x340: - "000000" & X"000", -- 0x341: - "000000" & X"000", -- 0x342: - "000000" & X"000", -- 0x343: - "000000" & X"000", -- 0x344: - "000000" & X"000", -- 0x345: - "000000" & X"000", -- 0x346: - "000000" & X"000", -- 0x347: - "000000" & X"000", -- 0x348: - "000000" & X"000", -- 0x349: - "000000" & X"000", -- 0x34A: - "000000" & X"000", -- 0x34B: - "000000" & X"000", -- 0x34C: - "000000" & X"000", -- 0x34D: - "000000" & X"000", -- 0x34E: - "000000" & X"000", -- 0x34F: - "000000" & X"000", -- 0x350: - "000000" & X"000", -- 0x351: - "000000" & X"000", -- 0x352: - "000000" & X"000", -- 0x353: - "000000" & X"000", -- 0x354: - "000000" & X"000", -- 0x355: - "000000" & X"000", -- 0x356: - "000000" & X"000", -- 0x357: - "000000" & X"000", -- 0x358: - "000000" & X"000", -- 0x359: - "000000" & X"000", -- 0x35A: - "000000" & X"000", -- 0x35B: - "000000" & X"000", -- 0x35C: - "000000" & X"000", -- 0x35D: - "000000" & X"000", -- 0x35E: - "000000" & X"000", -- 0x35F: - "000000" & X"000", -- 0x360: - "000000" & X"000", -- 0x361: - "000000" & X"000", -- 0x362: - "000000" & X"000", -- 0x363: - "000000" & X"000", -- 0x364: - "000000" & X"000", -- 0x365: - "000000" & X"000", -- 0x366: - "000000" & X"000", -- 0x367: - "000000" & X"000", -- 0x368: - "000000" & X"000", -- 0x369: - "000000" & X"000", -- 0x36A: - "000000" & X"000", -- 0x36B: - "000000" & X"000", -- 0x36C: - "000000" & X"000", -- 0x36D: - "000000" & X"000", -- 0x36E: - "000000" & X"000", -- 0x36F: - "000000" & X"000", -- 0x370: - "000000" & X"000", -- 0x371: - "000000" & X"000", -- 0x372: - "000000" & X"000", -- 0x373: - "000000" & X"000", -- 0x374: - "000000" & X"000", -- 0x375: - "000000" & X"000", -- 0x376: - "000000" & X"000", -- 0x377: - "000000" & X"000", -- 0x378: - "000000" & X"000", -- 0x379: - "000000" & X"000", -- 0x37A: - "000000" & X"000", -- 0x37B: - "000000" & X"000", -- 0x37C: - "000000" & X"000", -- 0x37D: - "000000" & X"000", -- 0x37E: - "000000" & X"000", -- 0x37F: - "000000" & X"000", -- 0x380: - "000000" & X"000", -- 0x381: - "000000" & X"000", -- 0x382: - "000000" & X"000", -- 0x383: - "000000" & X"000", -- 0x384: - "000000" & X"000", -- 0x385: - "000000" & X"000", -- 0x386: - "000000" & X"000", -- 0x387: - "000000" & X"000", -- 0x388: - "000000" & X"000", -- 0x389: - "000000" & X"000", -- 0x38A: - "000000" & X"000", -- 0x38B: - "000000" & X"000", -- 0x38C: - "000000" & X"000", -- 0x38D: - "000000" & X"000", -- 0x38E: - "000000" & X"000", -- 0x38F: - "000000" & X"000", -- 0x390: - "000000" & X"000", -- 0x391: - "000000" & X"000", -- 0x392: - "000000" & X"000", -- 0x393: - "000000" & X"000", -- 0x394: - "000000" & X"000", -- 0x395: - "000000" & X"000", -- 0x396: - "000000" & X"000", -- 0x397: - "000000" & X"000", -- 0x398: - "000000" & X"000", -- 0x399: - "000000" & X"000", -- 0x39A: - "000000" & X"000", -- 0x39B: - "000000" & X"000", -- 0x39C: - "000000" & X"000", -- 0x39D: - "000000" & X"000", -- 0x39E: - "000000" & X"000", -- 0x39F: - "000000" & X"000", -- 0x3A0: - "000000" & X"000", -- 0x3A1: - "000000" & X"000", -- 0x3A2: - "000000" & X"000", -- 0x3A3: - "000000" & X"000", -- 0x3A4: - "000000" & X"000", -- 0x3A5: - "000000" & X"000", -- 0x3A6: - "000000" & X"000", -- 0x3A7: - "000000" & X"000", -- 0x3A8: - "000000" & X"000", -- 0x3A9: - "000000" & X"000", -- 0x3AA: - "000000" & X"000", -- 0x3AB: - "000000" & X"000", -- 0x3AC: - "000000" & X"000", -- 0x3AD: - "000000" & X"000", -- 0x3AE: - "000000" & X"000", -- 0x3AF: - "000000" & X"000", -- 0x3B0: - "000000" & X"000", -- 0x3B1: - "000000" & X"000", -- 0x3B2: - "000000" & X"000", -- 0x3B3: - "000000" & X"000", -- 0x3B4: - "000000" & X"000", -- 0x3B5: - "000000" & X"000", -- 0x3B6: - "000000" & X"000", -- 0x3B7: - "000000" & X"000", -- 0x3B8: - "000000" & X"000", -- 0x3B9: - "000000" & X"000", -- 0x3BA: - "000000" & X"000", -- 0x3BB: - "000000" & X"000", -- 0x3BC: - "000000" & X"000", -- 0x3BD: - "000000" & X"000", -- 0x3BE: - "000000" & X"000", -- 0x3BF: - "000000" & X"000", -- 0x3C0: - "000000" & X"000", -- 0x3C1: - "000000" & X"000", -- 0x3C2: - "000000" & X"000", -- 0x3C3: - "000000" & X"000", -- 0x3C4: - "000000" & X"000", -- 0x3C5: - "000000" & X"000", -- 0x3C6: - "000000" & X"000", -- 0x3C7: - "000000" & X"000", -- 0x3C8: - "000000" & X"000", -- 0x3C9: - "000000" & X"000", -- 0x3CA: - "000000" & X"000", -- 0x3CB: - "000000" & X"000", -- 0x3CC: - "000000" & X"000", -- 0x3CD: - "000000" & X"000", -- 0x3CE: - "000000" & X"000", -- 0x3CF: - "000000" & X"000", -- 0x3D0: - "000000" & X"000", -- 0x3D1: - "000000" & X"000", -- 0x3D2: - "000000" & X"000", -- 0x3D3: - "000000" & X"000", -- 0x3D4: - "000000" & X"000", -- 0x3D5: - "000000" & X"000", -- 0x3D6: - "000000" & X"000", -- 0x3D7: - "000000" & X"000", -- 0x3D8: - "000000" & X"000", -- 0x3D9: - "000000" & X"000", -- 0x3DA: - "000000" & X"000", -- 0x3DB: - "000000" & X"000", -- 0x3DC: - "000000" & X"000", -- 0x3DD: - "000000" & X"000", -- 0x3DE: - "000000" & X"000", -- 0x3DF: - "000000" & X"000", -- 0x3E0: - "000000" & X"000", -- 0x3E1: - "000000" & X"000", -- 0x3E2: - "000000" & X"000", -- 0x3E3: - "000000" & X"000", -- 0x3E4: - "000000" & X"000", -- 0x3E5: - "000000" & X"000", -- 0x3E6: - "000000" & X"000", -- 0x3E7: - "000000" & X"000", -- 0x3E8: - "000000" & X"000", -- 0x3E9: - "000000" & X"000", -- 0x3EA: - "000000" & X"000", -- 0x3EB: - "000000" & X"000", -- 0x3EC: - "000000" & X"000", -- 0x3ED: - "000000" & X"000", -- 0x3EE: - "000000" & X"000", -- 0x3EF: - "000000" & X"000", -- 0x3F0: - "000000" & X"000", -- 0x3F1: - "000000" & X"000", -- 0x3F2: - "000000" & X"000", -- 0x3F3: - "000000" & X"000", -- 0x3F4: - "000000" & X"000", -- 0x3F5: - "000000" & X"000", -- 0x3F6: - "000000" & X"000", -- 0x3F7: - "000000" & X"000", -- 0x3F8: - "000000" & X"000", -- 0x3F9: - "000000" & X"000", -- 0x3FA: - "000000" & X"000", -- 0x3FB: - "000000" & X"000", -- 0x3FC: - "000000" & X"000", -- 0x3FD: - "000000" & X"000", -- 0x3FE: - "110000" & X"3FF" -- 0x3FF: JMP 0x3FF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end itest; - diff --git a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl b/lib/CPUs/JCpu/src/itest_irom_ld.vhdl deleted file mode 100644 index d4371a1..0000000 --- a/lib/CPUs/JCpu/src/itest_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from itest.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"010", -- 0x000: JMP 0x010 - "110000" & X"288", -- 0x001: JMP 0x288 - "000000" & X"000", -- 0x002: - "000000" & X"000", -- 0x003: - "000000" & X"000", -- 0x004: - "000000" & X"000", -- 0x005: - "000000" & X"000", -- 0x006: - "000000" & X"000", -- 0x007: - "000000" & X"000", -- 0x008: - "000000" & X"000", -- 0x009: - "000000" & X"000", -- 0x00A: - "000000" & X"000", -- 0x00B: - "000000" & X"000", -- 0x00C: - "000000" & X"000", -- 0x00D: - "000000" & X"000", -- 0x00E: - "000000" & X"000", -- 0x00F: - "111011" & X"03B", -- 0x010: CALL 0x03B - "101001" & X"000", -- 0x011: CIN R00, (0x00) - "100100" & X"000", -- 0x012: XOUT (0x00), R00 - "111011" & X"04C", -- 0x013: CALL 0x04C - "000011" & X"010", -- 0x014: MOV R00, 0x01 - "100100" & X"010", -- 0x015: XOUT (0x01), R00 - "111011" & X"08D", -- 0x016: CALL 0x08D - "000011" & X"020", -- 0x017: MOV R00, 0x02 - "100100" & X"010", -- 0x018: XOUT (0x01), R00 - "111011" & X"0C9", -- 0x019: CALL 0x0C9 - "000011" & X"030", -- 0x01A: MOV R00, 0x03 - "100100" & X"010", -- 0x01B: XOUT (0x01), R00 - "111011" & X"0DB", -- 0x01C: CALL 0x0DB - "000011" & X"040", -- 0x01D: MOV R00, 0x04 - "100100" & X"010", -- 0x01E: XOUT (0x01), R00 - "111011" & X"0ED", -- 0x01F: CALL 0x0ED - "000011" & X"050", -- 0x020: MOV R00, 0x05 - "100100" & X"010", -- 0x021: XOUT (0x01), R00 - "111011" & X"0FF", -- 0x022: CALL 0x0FF - "000011" & X"060", -- 0x023: MOV R00, 0x06 - "100100" & X"010", -- 0x024: XOUT (0x01), R00 - "111011" & X"115", -- 0x025: CALL 0x115 - "000011" & X"070", -- 0x026: MOV R00, 0x07 - "100100" & X"010", -- 0x027: XOUT (0x01), R00 - "111011" & X"12B", -- 0x028: CALL 0x12B - "000011" & X"080", -- 0x029: MOV R00, 0x08 - "100100" & X"010", -- 0x02A: XOUT (0x01), R00 - "111011" & X"137", -- 0x02B: CALL 0x137 - "000011" & X"090", -- 0x02C: MOV R00, 0x09 - "100100" & X"010", -- 0x02D: XOUT (0x01), R00 - "111011" & X"15A", -- 0x02E: CALL 0x15A - "000011" & X"0A0", -- 0x02F: MOV R00, 0x0A - "100100" & X"010", -- 0x030: XOUT (0x01), R00 - "111011" & X"22A", -- 0x031: CALL 0x22A - "000011" & X"0B0", -- 0x032: MOV R00, 0x0B - "100100" & X"010", -- 0x033: XOUT (0x01), R00 - "111011" & X"24D", -- 0x034: CALL 0x24D - "000011" & X"0C0", -- 0x035: MOV R00, 0x0C - "100100" & X"010", -- 0x036: XOUT (0x01), R00 - "111011" & X"278", -- 0x037: CALL 0x278 - "000011" & X"FF0", -- 0x038: MOV R00, 0xFF - "100100" & X"010", -- 0x039: XOUT (0x01), R00 - "110000" & X"2FF", -- 0x03A: JMP 0x2FF - "000011" & X"000", -- 0x03B: MOV R00, 0x00 - "000011" & X"001", -- 0x03C: MOV R01, 0x00 - "000011" & X"002", -- 0x03D: MOV R02, 0x00 - "000011" & X"003", -- 0x03E: MOV R03, 0x00 - "000011" & X"004", -- 0x03F: MOV R04, 0x00 - "000011" & X"005", -- 0x040: MOV R05, 0x00 - "000011" & X"006", -- 0x041: MOV R06, 0x00 - "000011" & X"007", -- 0x042: MOV R07, 0x00 - "000011" & X"008", -- 0x043: MOV R08, 0x00 - "000011" & X"009", -- 0x044: MOV R09, 0x00 - "000011" & X"00A", -- 0x045: MOV R10, 0x00 - "000011" & X"00B", -- 0x046: MOV R11, 0x00 - "000011" & X"00C", -- 0x047: MOV R12, 0x00 - "000011" & X"00D", -- 0x048: MOV R13, 0x00 - "000011" & X"00E", -- 0x049: MOV R14, 0x00 - "000011" & X"00F", -- 0x04A: MOV R15, 0x00 - "111110" & X"000", -- 0x04B: RET - "000011" & X"100", -- 0x04C: MOV R00, 0x10 - "001111" & X"100", -- 0x04D: CMP R00, 0x10 - "111010" & X"3FF", -- 0x04E: JNE 0x3FF - "010001" & X"010", -- 0x04F: ADD R00, 0x01 - "000010" & X"001", -- 0x050: MOV R01, R00 - "001111" & X"111", -- 0x051: CMP R01, 0x11 - "111010" & X"3FF", -- 0x052: JNE 0x3FF - "010001" & X"011", -- 0x053: ADD R01, 0x01 - "000010" & X"012", -- 0x054: MOV R02, R01 - "001111" & X"122", -- 0x055: CMP R02, 0x12 - "111010" & X"3FF", -- 0x056: JNE 0x3FF - "010001" & X"012", -- 0x057: ADD R02, 0x01 - "000010" & X"023", -- 0x058: MOV R03, R02 - "001111" & X"133", -- 0x059: CMP R03, 0x13 - "111010" & X"3FF", -- 0x05A: JNE 0x3FF - "010001" & X"013", -- 0x05B: ADD R03, 0x01 - "000010" & X"034", -- 0x05C: MOV R04, R03 - "001111" & X"144", -- 0x05D: CMP R04, 0x14 - "111010" & X"3FF", -- 0x05E: JNE 0x3FF - "010001" & X"014", -- 0x05F: ADD R04, 0x01 - "000010" & X"045", -- 0x060: MOV R05, R04 - "001111" & X"155", -- 0x061: CMP R05, 0x15 - "111010" & X"3FF", -- 0x062: JNE 0x3FF - "010001" & X"015", -- 0x063: ADD R05, 0x01 - "000010" & X"056", -- 0x064: MOV R06, R05 - "001111" & X"166", -- 0x065: CMP R06, 0x16 - "111010" & X"3FF", -- 0x066: JNE 0x3FF - "010001" & X"016", -- 0x067: ADD R06, 0x01 - "000010" & X"067", -- 0x068: MOV R07, R06 - "001111" & X"177", -- 0x069: CMP R07, 0x17 - "111010" & X"3FF", -- 0x06A: JNE 0x3FF - "010001" & X"017", -- 0x06B: ADD R07, 0x01 - "000010" & X"078", -- 0x06C: MOV R08, R07 - "001111" & X"188", -- 0x06D: CMP R08, 0x18 - "111010" & X"3FF", -- 0x06E: JNE 0x3FF - "010001" & X"018", -- 0x06F: ADD R08, 0x01 - "000010" & X"089", -- 0x070: MOV R09, R08 - "001111" & X"199", -- 0x071: CMP R09, 0x19 - "111010" & X"3FF", -- 0x072: JNE 0x3FF - "010001" & X"019", -- 0x073: ADD R09, 0x01 - "000010" & X"09A", -- 0x074: MOV R10, R09 - "001111" & X"1AA", -- 0x075: CMP R10, 0x1A - "111010" & X"3FF", -- 0x076: JNE 0x3FF - "010001" & X"01A", -- 0x077: ADD R10, 0x01 - "000010" & X"0AB", -- 0x078: MOV R11, R10 - "001111" & X"1BB", -- 0x079: CMP R11, 0x1B - "111010" & X"3FF", -- 0x07A: JNE 0x3FF - "010001" & X"01B", -- 0x07B: ADD R11, 0x01 - "000010" & X"0BC", -- 0x07C: MOV R12, R11 - "001111" & X"1CC", -- 0x07D: CMP R12, 0x1C - "111010" & X"3FF", -- 0x07E: JNE 0x3FF - "010001" & X"01C", -- 0x07F: ADD R12, 0x01 - "000010" & X"0CD", -- 0x080: MOV R13, R12 - "001111" & X"1DD", -- 0x081: CMP R13, 0x1D - "111010" & X"3FF", -- 0x082: JNE 0x3FF - "010001" & X"01D", -- 0x083: ADD R13, 0x01 - "000010" & X"0DE", -- 0x084: MOV R14, R13 - "001111" & X"1EE", -- 0x085: CMP R14, 0x1E - "111010" & X"3FF", -- 0x086: JNE 0x3FF - "010001" & X"01E", -- 0x087: ADD R14, 0x01 - "000010" & X"0EF", -- 0x088: MOV R15, R14 - "001111" & X"1FF", -- 0x089: CMP R15, 0x1F - "111010" & X"3FF", -- 0x08A: JNE 0x3FF - "010001" & X"01F", -- 0x08B: ADD R15, 0x01 - "111110" & X"000", -- 0x08C: RET - "000011" & X"000", -- 0x08D: MOV R00, 0x00 - "001111" & X"000", -- 0x08E: TST R00 - "110010" & X"3FF", -- 0x08F: JNZ 0x3FF - "110011" & X"3FF", -- 0x090: JC 0x3FF - "001111" & X"000", -- 0x091: CMP R00, 0x00 - "111010" & X"3FF", -- 0x092: JNE 0x3FF - "110101" & X"3FF", -- 0x093: JLT 0x3FF - "110110" & X"3FF", -- 0x094: JGT 0x3FF - "110111" & X"097", -- 0x095: JLE 0x097 - "110000" & X"3FF", -- 0x096: JMP 0x3FF - "111001" & X"099", -- 0x097: JEQ 0x099 - "110000" & X"3FF", -- 0x098: JMP 0x3FF - "111000" & X"09B", -- 0x099: JGE 0x09B - "110000" & X"3FF", -- 0x09A: JMP 0x3FF - "001111" & X"550", -- 0x09B: CMP R00, 0x55 - "111001" & X"3FF", -- 0x09C: JEQ 0x3FF - "110101" & X"09F", -- 0x09D: JLT 0x09F - "110000" & X"3FF", -- 0x09E: JMP 0x3FF - "110111" & X"0A1", -- 0x09F: JLE 0x0A1 - "110000" & X"3FF", -- 0x0A0: JMP 0x3FF - "111000" & X"3FF", -- 0x0A1: JGE 0x3FF - "110110" & X"3FF", -- 0x0A2: JGT 0x3FF - "000011" & X"550", -- 0x0A3: MOV R00, 0x55 - "001111" & X"000", -- 0x0A4: TST R00 - "110001" & X"3FF", -- 0x0A5: JZ 0x3FF - "110011" & X"3FF", -- 0x0A6: JC 0x3FF - "001111" & X"AA0", -- 0x0A7: CMP R00, 0xAA - "111001" & X"3FF", -- 0x0A8: JEQ 0x3FF - "111010" & X"0AB", -- 0x0A9: JNE 0x0AB - "110000" & X"3FF", -- 0x0AA: JMP 0x3FF - "110101" & X"0AD", -- 0x0AB: JLT 0x0AD - "110000" & X"3FF", -- 0x0AC: JMP 0x3FF - "110111" & X"0AF", -- 0x0AD: JLE 0x0AF - "110000" & X"3FF", -- 0x0AE: JMP 0x3FF - "110110" & X"3FF", -- 0x0AF: JGT 0x3FF - "001111" & X"550", -- 0x0B0: CMP R00, 0x55 - "111001" & X"0B3", -- 0x0B1: JEQ 0x0B3 - "110000" & X"3FF", -- 0x0B2: JMP 0x3FF - "111010" & X"3FF", -- 0x0B3: JNE 0x3FF - "110101" & X"3FF", -- 0x0B4: JLT 0x3FF - "110111" & X"0B7", -- 0x0B5: JLE 0x0B7 - "110000" & X"3FF", -- 0x0B6: JMP 0x3FF - "110110" & X"3FF", -- 0x0B7: JGT 0x3FF - "111000" & X"0BA", -- 0x0B8: JGE 0x0BA - "110000" & X"3FF", -- 0x0B9: JMP 0x3FF - "000011" & X"AA0", -- 0x0BA: MOV R00, 0xAA - "001111" & X"000", -- 0x0BB: TST R00 - "110001" & X"3FF", -- 0x0BC: JZ 0x3FF - "110011" & X"3FF", -- 0x0BD: JC 0x3FF - "001111" & X"550", -- 0x0BE: CMP R00, 0x55 - "111001" & X"3FF", -- 0x0BF: JEQ 0x3FF - "111010" & X"0C2", -- 0x0C0: JNE 0x0C2 - "110000" & X"3FF", -- 0x0C1: JMP 0x3FF - "110110" & X"0C4", -- 0x0C2: JGT 0x0C4 - "110000" & X"3FF", -- 0x0C3: JMP 0x3FF - "111000" & X"0C6", -- 0x0C4: JGE 0x0C6 - "110000" & X"3FF", -- 0x0C5: JMP 0x3FF - "110101" & X"3FF", -- 0x0C6: JLT 0x3FF - "110111" & X"3FF", -- 0x0C7: JLE 0x3FF - "111110" & X"000", -- 0x0C8: RET - "000011" & X"000", -- 0x0C9: MOV R00, 0x00 - "000011" & X"001", -- 0x0CA: MOV R01, 0x00 - "000010" & X"002", -- 0x0CB: MOV R02, R00 - "000010" & X"013", -- 0x0CC: MOV R03, R01 - "010001" & X"010", -- 0x0CD: ADD R00, 0x01 - "010011" & X"001", -- 0x0CE: ADDC R01, 0x00 - "010001" & X"012", -- 0x0CF: ADD R02, 0x01 - "001111" & X"002", -- 0x0D0: CMP R02, 0x00 - "111010" & X"0D4", -- 0x0D1: JNE 0x0D4 - "010001" & X"013", -- 0x0D2: ADD R03, 0x01 - "001111" & X"023", -- 0x0D3: CMP R03, 0x02 - "111010" & X"0CD", -- 0x0D4: JNE 0x0CD - "001110" & X"020", -- 0x0D5: CMP R00, R02 - "111010" & X"3FF", -- 0x0D6: JNE 0x3FF - "001110" & X"031", -- 0x0D7: CMP R01, R03 - "111010" & X"3FF", -- 0x0D8: JNE 0x3FF - "000011" & X"000", -- 0x0D9: MOV R00, 0x00 - "111110" & X"000", -- 0x0DA: RET - "000011" & X"000", -- 0x0DB: MOV R00, 0x00 - "000011" & X"031", -- 0x0DC: MOV R01, 0x03 - "000010" & X"002", -- 0x0DD: MOV R02, R00 - "000010" & X"013", -- 0x0DE: MOV R03, R01 - "010101" & X"010", -- 0x0DF: SUB R00, 0x01 - "010111" & X"001", -- 0x0E0: SUBC R01, 0x00 - "010101" & X"012", -- 0x0E1: SUB R02, 0x01 - "001111" & X"FF2", -- 0x0E2: CMP R02, 0xFF - "111010" & X"0E6", -- 0x0E3: JNE 0x0E6 - "010101" & X"013", -- 0x0E4: SUB R03, 0x01 - "001111" & X"003", -- 0x0E5: CMP R03, 0x00 - "111010" & X"0DF", -- 0x0E6: JNE 0x0DF - "001110" & X"020", -- 0x0E7: CMP R00, R02 - "111010" & X"3FF", -- 0x0E8: JNE 0x3FF - "001110" & X"031", -- 0x0E9: CMP R01, R03 - "111010" & X"3FF", -- 0x0EA: JNE 0x3FF - "000011" & X"000", -- 0x0EB: MOV R00, 0x00 - "111110" & X"000", -- 0x0EC: RET - "000011" & X"030", -- 0x0ED: MOV R00, 0x03 - "000011" & X"051", -- 0x0EE: MOV R01, 0x05 - "101110" & X"050", -- 0x0EF: SUB 0x05, R00 - "010101" & X"031", -- 0x0F0: SUB R01, 0x03 - "001110" & X"010", -- 0x0F1: CMP R00, R01 - "111010" & X"3FF", -- 0x0F2: JNE 0x3FF - "000011" & X"030", -- 0x0F3: MOV R00, 0x03 - "000011" & X"051", -- 0x0F4: MOV R01, 0x05 - "010100" & X"010", -- 0x0F5: SUB R00, R01 - "101111" & X"000", -- 0x0F6: SUBC 0x00, R00 - "001111" & X"010", -- 0x0F7: CMP R00, 0x01 - "111010" & X"3FF", -- 0x0F8: JNE 0x3FF - "010001" & X"000", -- 0x0F9: ADD R00, 0x00 - "010110" & X"001", -- 0x0FA: SUBC R01, R00 - "001111" & X"041", -- 0x0FB: CMP R01, 0x04 - "111010" & X"3FF", -- 0x0FC: JNE 0x3FF - "000011" & X"000", -- 0x0FD: MOV R00, 0x00 - "111110" & X"000", -- 0x0FE: RET - "000011" & X"010", -- 0x0FF: MOV R00, 0x01 - "001101" & X"5A0", -- 0x100: MOVC (0x5A), R00 - "010101" & X"010", -- 0x101: DEC R00 - "001101" & X"000", -- 0x102: MOVC (0x00), R00 - "001010" & X"5A1", -- 0x103: MOVC R01, (0x5A) - "001100" & X"A51", -- 0x104: MOVC (R01), 0xA5 - "001001" & X"010", -- 0x105: MOVC R00, (R01) - "001001" & X"011", -- 0x106: MOVC R01, (R01) - "010001" & X"5A1", -- 0x107: ADD R01, 0x5A - "001001" & X"010", -- 0x108: MOVC R00, (R01) - "001011" & X"000", -- 0x109: MOVC (R00), R00 - "001001" & X"002", -- 0x10A: MOVC R02, (R00) - "001110" & X"002", -- 0x10B: CMP R02, R00 - "111010" & X"3FF", -- 0x10C: JNE 0x3FF - "001011" & X"021", -- 0x10D: MOVC (R01), R02 - "001001" & X"022", -- 0x10E: MOVC R02, (R02) - "001110" & X"012", -- 0x10F: CMP R02, R01 - "111010" & X"3FF", -- 0x110: JNE 0x3FF - "010101" & X"011", -- 0x111: DEC R01 - "010001" & X"010", -- 0x112: INC R00 - "110010" & X"109", -- 0x113: JNZ 0x109 - "111110" & X"000", -- 0x114: RET - "000011" & X"010", -- 0x115: MOV R00, 0x01 - "001000" & X"600", -- 0x116: MOVX (0x60), R00 - "010101" & X"010", -- 0x117: DEC R00 - "001000" & X"060", -- 0x118: MOVX (0x06), R00 - "000101" & X"601", -- 0x119: MOVX R01, (0x60) - "000111" & X"A51", -- 0x11A: MOVX (R01), 0xA5 - "000100" & X"010", -- 0x11B: MOVX R00, (R01) - "000100" & X"011", -- 0x11C: MOVX R01, (R01) - "010001" & X"5A1", -- 0x11D: ADD R01, 0x5A - "000100" & X"010", -- 0x11E: MOVX R00, (R01) - "000110" & X"000", -- 0x11F: MOVX (R00), R00 - "000100" & X"002", -- 0x120: MOVX R02, (R00) - "001110" & X"002", -- 0x121: CMP R02, R00 - "111010" & X"3FF", -- 0x122: JNE 0x3FF - "000110" & X"021", -- 0x123: MOVX (R01), R02 - "000100" & X"022", -- 0x124: MOVX R02, (R02) - "001110" & X"012", -- 0x125: CMP R02, R01 - "111010" & X"3FF", -- 0x126: JNE 0x3FF - "010101" & X"011", -- 0x127: DEC R01 - "010001" & X"010", -- 0x128: INC R00 - "110010" & X"11F", -- 0x129: JNZ 0x11F - "111110" & X"000", -- 0x12A: RET - "000011" & X"AA0", -- 0x12B: MOV R00, 0xAA - "000011" & X"001", -- 0x12C: MOV R01, 0x00 - "111100" & X"000", -- 0x12D: PUSH R00 - "010001" & X"010", -- 0x12E: INC R00 - "010101" & X"011", -- 0x12F: DEC R01 - "110010" & X"12D", -- 0x130: JNZ 0x12D - "111101" & X"000", -- 0x131: POP R00 - "010101" & X"011", -- 0x132: DEC R01 - "110010" & X"131", -- 0x133: JNZ 0x131 - "001111" & X"AA0", -- 0x134: CMP R00, 0xAA - "111010" & X"3FF", -- 0x135: JNE 0x3FF - "111110" & X"000", -- 0x136: RET - "000011" & X"550", -- 0x137: MOV R00, 0x55 - "111100" & X"000", -- 0x138: PUSH R00 - "000011" & X"000", -- 0x139: MOV R00, 0x00 - "000011" & X"FF1", -- 0x13A: MOV R01, 0xFF - "111011" & X"151", -- 0x13B: CALL 0x151 - "111101" & X"000", -- 0x13C: POP R00 - "001111" & X"550", -- 0x13D: CMP R00, 0x55 - "111010" & X"3FF", -- 0x13E: JNE 0x3FF - "000011" & X"010", -- 0x13F: MOV R00, 0x01 - "000011" & X"481", -- 0x140: MOV R01, 0x48 - "100110" & X"050", -- 0x141: COUT (0x05), R00 - "111100" & X"001", -- 0x142: PUSH R01 - "000011" & X"000", -- 0x143: MOV R00, 0x00 - "000011" & X"3B1", -- 0x144: MOV R01, 0x3B - "100110" & X"050", -- 0x145: COUT (0x05), R00 - "111100" & X"001", -- 0x146: PUSH R01 - "111110" & X"000", -- 0x147: RET - "000011" & X"010", -- 0x148: MOV R00, 0x01 - "000011" & X"501", -- 0x149: MOV R01, 0x50 - "100110" & X"050", -- 0x14A: COUT (0x05), R00 - "111100" & X"001", -- 0x14B: PUSH R01 - "000011" & X"000", -- 0x14C: MOV R00, 0x00 - "000011" & X"3B1", -- 0x14D: MOV R01, 0x3B - "100110" & X"050", -- 0x14E: COUT (0x05), R00 - "111100" & X"001", -- 0x14F: PUSH R01 - "111110" & X"000", -- 0x150: RET - "001110" & X"010", -- 0x151: CMP R00, R01 - "111001" & X"155", -- 0x152: JEQ 0x155 - "010001" & X"010", -- 0x153: INC R00 - "110000" & X"158", -- 0x154: JMP 0x158 - "010101" & X"010", -- 0x155: DEC R00 - "010101" & X"011", -- 0x156: DEC R01 - "111110" & X"000", -- 0x157: RET - "111011" & X"151", -- 0x158: CALL 0x151 - "110000" & X"155", -- 0x159: JMP 0x155 - "000011" & X"A50", -- 0x15A: MOV R00, 0xA5 - "000011" & X"5A1", -- 0x15B: MOV R01, 0x5A - "101010" & X"000", -- 0x15C: SWAP R00 - "001111" & X"5A0", -- 0x15D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x15E: JNE 0x3FF - "101010" & X"000", -- 0x15F: SWAP R00 - "001111" & X"A50", -- 0x160: CMP R00, 0xA5 - "111010" & X"3FF", -- 0x161: JNE 0x3FF - "000011" & X"D20", -- 0x162: MOV R00, 0xD2 - "101010" & X"000", -- 0x163: SWAP R00 - "001111" & X"2D0", -- 0x164: CMP R00, 0x2D - "111010" & X"3FF", -- 0x165: JNE 0x3FF - "101010" & X"001", -- 0x166: SWAP R01 - "001111" & X"2D0", -- 0x167: CMP R00, 0x2D - "111010" & X"3FF", -- 0x168: JNE 0x3FF - "001111" & X"A51", -- 0x169: CMP R01, 0xA5 - "111010" & X"3FF", -- 0x16A: JNE 0x3FF - "000011" & X"2D0", -- 0x16B: MOV R00, 0x2D - "011110" & X"000", -- 0x16C: SHL R00 - "001111" & X"5A0", -- 0x16D: CMP R00, 0x5A - "111010" & X"3FF", -- 0x16E: JNE 0x3FF - "011110" & X"000", -- 0x16F: SHL R00 - "001111" & X"B40", -- 0x170: CMP R00, 0xB4 - "111010" & X"3FF", -- 0x171: JNE 0x3FF - "011110" & X"000", -- 0x172: SHL R00 - "001111" & X"680", -- 0x173: CMP R00, 0x68 - "111010" & X"3FF", -- 0x174: JNE 0x3FF - "011110" & X"000", -- 0x175: SHL R00 - "001111" & X"D00", -- 0x176: CMP R00, 0xD0 - "111010" & X"3FF", -- 0x177: JNE 0x3FF - "011110" & X"000", -- 0x178: SHL R00 - "001111" & X"A00", -- 0x179: CMP R00, 0xA0 - "111010" & X"3FF", -- 0x17A: JNE 0x3FF - "011110" & X"000", -- 0x17B: SHL R00 - "001111" & X"400", -- 0x17C: CMP R00, 0x40 - "111010" & X"3FF", -- 0x17D: JNE 0x3FF - "011110" & X"000", -- 0x17E: SHL R00 - "001111" & X"800", -- 0x17F: CMP R00, 0x80 - "111010" & X"3FF", -- 0x180: JNE 0x3FF - "011110" & X"000", -- 0x181: SHL R00 - "001111" & X"000", -- 0x182: CMP R00, 0x00 - "111010" & X"3FF", -- 0x183: JNE 0x3FF - "000011" & X"841", -- 0x184: MOV R01, 0x84 - "011111" & X"001", -- 0x185: SHR R01 - "001111" & X"421", -- 0x186: CMP R01, 0x42 - "111010" & X"3FF", -- 0x187: JNE 0x3FF - "011111" & X"001", -- 0x188: SHR R01 - "001111" & X"211", -- 0x189: CMP R01, 0x21 - "111010" & X"3FF", -- 0x18A: JNE 0x3FF - "011111" & X"001", -- 0x18B: SHR R01 - "001111" & X"101", -- 0x18C: CMP R01, 0x10 - "111010" & X"3FF", -- 0x18D: JNE 0x3FF - "011111" & X"001", -- 0x18E: SHR R01 - "001111" & X"081", -- 0x18F: CMP R01, 0x08 - "111010" & X"3FF", -- 0x190: JNE 0x3FF - "011111" & X"001", -- 0x191: SHR R01 - "001111" & X"041", -- 0x192: CMP R01, 0x04 - "111010" & X"3FF", -- 0x193: JNE 0x3FF - "011111" & X"001", -- 0x194: SHR R01 - "001111" & X"021", -- 0x195: CMP R01, 0x02 - "111010" & X"3FF", -- 0x196: JNE 0x3FF - "011111" & X"001", -- 0x197: SHR R01 - "001111" & X"011", -- 0x198: CMP R01, 0x01 - "111010" & X"3FF", -- 0x199: JNE 0x3FF - "011111" & X"001", -- 0x19A: SHR R01 - "001111" & X"001", -- 0x19B: CMP R01, 0x00 - "111010" & X"3FF", -- 0x19C: JNE 0x3FF - "000011" & X"C50", -- 0x19D: MOV R00, 0xC5 - "100000" & X"000", -- 0x19E: ROL R00 - "001111" & X"8B0", -- 0x19F: CMP R00, 0x8B - "111010" & X"3FF", -- 0x1A0: JNE 0x3FF - "100000" & X"000", -- 0x1A1: ROL R00 - "001111" & X"170", -- 0x1A2: CMP R00, 0x17 - "111010" & X"3FF", -- 0x1A3: JNE 0x3FF - "100000" & X"000", -- 0x1A4: ROL R00 - "001111" & X"2E0", -- 0x1A5: CMP R00, 0x2E - "111010" & X"3FF", -- 0x1A6: JNE 0x3FF - "100000" & X"000", -- 0x1A7: ROL R00 - "001111" & X"5C0", -- 0x1A8: CMP R00, 0x5C - "111010" & X"3FF", -- 0x1A9: JNE 0x3FF - "100000" & X"000", -- 0x1AA: ROL R00 - "001111" & X"B80", -- 0x1AB: CMP R00, 0xB8 - "111010" & X"3FF", -- 0x1AC: JNE 0x3FF - "100000" & X"000", -- 0x1AD: ROL R00 - "001111" & X"710", -- 0x1AE: CMP R00, 0x71 - "111010" & X"3FF", -- 0x1AF: JNE 0x3FF - "100000" & X"000", -- 0x1B0: ROL R00 - "001111" & X"E20", -- 0x1B1: CMP R00, 0xE2 - "111010" & X"3FF", -- 0x1B2: JNE 0x3FF - "100000" & X"000", -- 0x1B3: ROL R00 - "001111" & X"C50", -- 0x1B4: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1B5: JNE 0x3FF - "000011" & X"631", -- 0x1B6: MOV R01, 0x63 - "100001" & X"001", -- 0x1B7: ROR R01 - "001111" & X"B11", -- 0x1B8: CMP R01, 0xB1 - "111010" & X"3FF", -- 0x1B9: JNE 0x3FF - "100001" & X"001", -- 0x1BA: ROR R01 - "001111" & X"D81", -- 0x1BB: CMP R01, 0xD8 - "111010" & X"3FF", -- 0x1BC: JNE 0x3FF - "100001" & X"001", -- 0x1BD: ROR R01 - "001111" & X"6C1", -- 0x1BE: CMP R01, 0x6C - "111010" & X"3FF", -- 0x1BF: JNE 0x3FF - "100001" & X"001", -- 0x1C0: ROR R01 - "001111" & X"361", -- 0x1C1: CMP R01, 0x36 - "111010" & X"3FF", -- 0x1C2: JNE 0x3FF - "100001" & X"001", -- 0x1C3: ROR R01 - "001111" & X"1B1", -- 0x1C4: CMP R01, 0x1B - "111010" & X"3FF", -- 0x1C5: JNE 0x3FF - "100001" & X"001", -- 0x1C6: ROR R01 - "001111" & X"8D1", -- 0x1C7: CMP R01, 0x8D - "111010" & X"3FF", -- 0x1C8: JNE 0x3FF - "100001" & X"001", -- 0x1C9: ROR R01 - "001111" & X"C61", -- 0x1CA: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x1CB: JNE 0x3FF - "100001" & X"001", -- 0x1CC: ROR R01 - "001111" & X"631", -- 0x1CD: CMP R01, 0x63 - "111010" & X"3FF", -- 0x1CE: JNE 0x3FF - "011100" & X"000", -- 0x1CF: XOR R00, R00 - "000011" & X"C50", -- 0x1D0: MOV R00, 0xC5 - "100010" & X"000", -- 0x1D1: ROLC R00 - "111100" & X"000", -- 0x1D2: PUSH R00 - "100010" & X"000", -- 0x1D3: ROLC R00 - "111100" & X"000", -- 0x1D4: PUSH R00 - "100010" & X"000", -- 0x1D5: ROLC R00 - "111100" & X"000", -- 0x1D6: PUSH R00 - "100010" & X"000", -- 0x1D7: ROLC R00 - "111100" & X"000", -- 0x1D8: PUSH R00 - "100010" & X"000", -- 0x1D9: ROLC R00 - "111100" & X"000", -- 0x1DA: PUSH R00 - "100010" & X"000", -- 0x1DB: ROLC R00 - "111100" & X"000", -- 0x1DC: PUSH R00 - "100010" & X"000", -- 0x1DD: ROLC R00 - "111100" & X"000", -- 0x1DE: PUSH R00 - "100010" & X"000", -- 0x1DF: ROLC R00 - "111100" & X"000", -- 0x1E0: PUSH R00 - "100010" & X"000", -- 0x1E1: ROLC R00 - "001111" & X"C50", -- 0x1E2: CMP R00, 0xC5 - "111010" & X"3FF", -- 0x1E3: JNE 0x3FF - "111101" & X"000", -- 0x1E4: POP R00 - "001111" & X"620", -- 0x1E5: CMP R00, 0x62 - "111010" & X"3FF", -- 0x1E6: JNE 0x3FF - "111101" & X"000", -- 0x1E7: POP R00 - "001111" & X"B10", -- 0x1E8: CMP R00, 0xB1 - "111010" & X"3FF", -- 0x1E9: JNE 0x3FF - "111101" & X"000", -- 0x1EA: POP R00 - "001111" & X"580", -- 0x1EB: CMP R00, 0x58 - "111010" & X"3FF", -- 0x1EC: JNE 0x3FF - "111101" & X"000", -- 0x1ED: POP R00 - "001111" & X"AC0", -- 0x1EE: CMP R00, 0xAC - "111010" & X"3FF", -- 0x1EF: JNE 0x3FF - "111101" & X"000", -- 0x1F0: POP R00 - "001111" & X"560", -- 0x1F1: CMP R00, 0x56 - "111010" & X"3FF", -- 0x1F2: JNE 0x3FF - "111101" & X"000", -- 0x1F3: POP R00 - "001111" & X"2B0", -- 0x1F4: CMP R00, 0x2B - "111010" & X"3FF", -- 0x1F5: JNE 0x3FF - "111101" & X"000", -- 0x1F6: POP R00 - "001111" & X"150", -- 0x1F7: CMP R00, 0x15 - "111010" & X"3FF", -- 0x1F8: JNE 0x3FF - "111101" & X"000", -- 0x1F9: POP R00 - "001111" & X"8A0", -- 0x1FA: CMP R00, 0x8A - "111010" & X"3FF", -- 0x1FB: JNE 0x3FF - "011100" & X"011", -- 0x1FC: XOR R01, R01 - "000011" & X"631", -- 0x1FD: MOV R01, 0x63 - "100011" & X"001", -- 0x1FE: RORC R01 - "111100" & X"001", -- 0x1FF: PUSH R01 - "100011" & X"001", -- 0x200: RORC R01 - "111100" & X"001", -- 0x201: PUSH R01 - "100011" & X"001", -- 0x202: RORC R01 - "111100" & X"001", -- 0x203: PUSH R01 - "100011" & X"001", -- 0x204: RORC R01 - "111100" & X"001", -- 0x205: PUSH R01 - "100011" & X"001", -- 0x206: RORC R01 - "111100" & X"001", -- 0x207: PUSH R01 - "100011" & X"001", -- 0x208: RORC R01 - "111100" & X"001", -- 0x209: PUSH R01 - "100011" & X"001", -- 0x20A: RORC R01 - "111100" & X"001", -- 0x20B: PUSH R01 - "100011" & X"001", -- 0x20C: RORC R01 - "111100" & X"001", -- 0x20D: PUSH R01 - "100011" & X"001", -- 0x20E: RORC R01 - "001111" & X"631", -- 0x20F: CMP R01, 0x63 - "111010" & X"3FF", -- 0x210: JNE 0x3FF - "111101" & X"001", -- 0x211: POP R01 - "001111" & X"C61", -- 0x212: CMP R01, 0xC6 - "111010" & X"3FF", -- 0x213: JNE 0x3FF - "111101" & X"001", -- 0x214: POP R01 - "001111" & X"8C1", -- 0x215: CMP R01, 0x8C - "111010" & X"3FF", -- 0x216: JNE 0x3FF - "111101" & X"001", -- 0x217: POP R01 - "001111" & X"191", -- 0x218: CMP R01, 0x19 - "111010" & X"3FF", -- 0x219: JNE 0x3FF - "111101" & X"001", -- 0x21A: POP R01 - "001111" & X"331", -- 0x21B: CMP R01, 0x33 - "111010" & X"3FF", -- 0x21C: JNE 0x3FF - "111101" & X"001", -- 0x21D: POP R01 - "001111" & X"661", -- 0x21E: CMP R01, 0x66 - "111010" & X"3FF", -- 0x21F: JNE 0x3FF - "111101" & X"001", -- 0x220: POP R01 - "001111" & X"CC1", -- 0x221: CMP R01, 0xCC - "111010" & X"3FF", -- 0x222: JNE 0x3FF - "111101" & X"001", -- 0x223: POP R01 - "001111" & X"981", -- 0x224: CMP R01, 0x98 - "111010" & X"3FF", -- 0x225: JNE 0x3FF - "111101" & X"001", -- 0x226: POP R01 - "001111" & X"311", -- 0x227: CMP R01, 0x31 - "111010" & X"3FF", -- 0x228: JNE 0x3FF - "111110" & X"000", -- 0x229: RET - "000011" & X"A50", -- 0x22A: MOV R00, 0xA5 - "101010" & X"000", -- 0x22B: SWAP R00 - "111100" & X"000", -- 0x22C: PUSH R00 - "011001" & X"0F0", -- 0x22D: AND R00, 0x0F - "001111" & X"0A0", -- 0x22E: CMP R00, 0x0A - "111010" & X"3FF", -- 0x22F: JNE 0x3FF - "111101" & X"000", -- 0x230: POP R00 - "111100" & X"000", -- 0x231: PUSH R00 - "011001" & X"0F0", -- 0x232: AND R00, 0x0F - "001111" & X"0A0", -- 0x233: CMP R00, 0x0A - "111101" & X"001", -- 0x234: POP R01 - "111010" & X"3FF", -- 0x235: JNE 0x3FF - "101010" & X"001", -- 0x236: SWAP R01 - "000011" & X"0F2", -- 0x237: MOV R02, 0x0F - "011000" & X"021", -- 0x238: AND R01, R02 - "001111" & X"051", -- 0x239: CMP R01, 0x05 - "111010" & X"3FF", -- 0x23A: JNE 0x3FF - "000011" & X"050", -- 0x23B: MOV R00, 0x05 - "000011" & X"A02", -- 0x23C: MOV R02, 0xA0 - "101010" & X"000", -- 0x23D: SWAP R00 - "011010" & X"002", -- 0x23E: OR R02, R00 - "001111" & X"F02", -- 0x23F: CMP R02, 0xF0 - "111010" & X"3FF", -- 0x240: JNE 0x3FF - "101010" & X"000", -- 0x241: SWAP R00 - "011011" & X"500", -- 0x242: OR R00, 0x50 - "001111" & X"550", -- 0x243: CMP R00, 0x55 - "111010" & X"3FF", -- 0x244: JNE 0x3FF - "000011" & X"011", -- 0x245: MOV R01, 0x01 - "000011" & X"010", -- 0x246: MOV R00, 0x01 - "011101" & X"010", -- 0x247: XOR R00, 0x01 - "110010" & X"3FF", -- 0x248: JNZ 0x3FF - "011100" & X"010", -- 0x249: XOR R00, R01 - "001111" & X"010", -- 0x24A: CMP R00, 0x01 - "111010" & X"3FF", -- 0x24B: JNE 0x3FF - "111110" & X"000", -- 0x24C: RET - "000011" & X"030", -- 0x24D: MOV R00, 0x03 - "100110" & X"030", -- 0x24E: COUT (0x03), R00 - "101000" & X"020", -- 0x24F: XIN R00, (0x02) - "011011" & X"010", -- 0x250: OR R00, 0x01 - "100100" & X"020", -- 0x251: XOUT (0x02), R00 - "000000" & X"000", -- 0x252: NOP - "000000" & X"000", -- 0x253: NOP - "000000" & X"000", -- 0x254: NOP - "000000" & X"000", -- 0x255: NOP - "000000" & X"000", -- 0x256: NOP - "000000" & X"000", -- 0x257: NOP - "101000" & X"020", -- 0x258: XIN R00, (0x02) - "011001" & X"FE0", -- 0x259: AND R00, 0xFE - "100100" & X"020", -- 0x25A: XOUT (0x02), R00 - "000000" & X"000", -- 0x25B: NOP - "000000" & X"000", -- 0x25C: NOP - "000000" & X"000", -- 0x25D: NOP - "000000" & X"000", -- 0x25E: NOP - "101001" & X"030", -- 0x25F: CIN R00, (0x03) - "011011" & X"800", -- 0x260: OR R00, 0x80 - "100110" & X"030", -- 0x261: COUT (0x03), R00 - "000000" & X"000", -- 0x262: NOP - "101001" & X"030", -- 0x263: CIN R00, (0x03) - "011011" & X"800", -- 0x264: OR R00, 0x80 - "100110" & X"030", -- 0x265: COUT (0x03), R00 - "000000" & X"000", -- 0x266: NOP - "101001" & X"030", -- 0x267: CIN R00, (0x03) - "011011" & X"800", -- 0x268: OR R00, 0x80 - "100110" & X"030", -- 0x269: COUT (0x03), R00 - "000000" & X"000", -- 0x26A: NOP - "101001" & X"030", -- 0x26B: CIN R00, (0x03) - "011011" & X"800", -- 0x26C: OR R00, 0x80 - "100110" & X"030", -- 0x26D: COUT (0x03), R00 - "000000" & X"000", -- 0x26E: NOP - "000000" & X"000", -- 0x26F: NOP - "000000" & X"000", -- 0x270: NOP - "000000" & X"000", -- 0x271: NOP - "000000" & X"000", -- 0x272: NOP - "000000" & X"000", -- 0x273: NOP - "000000" & X"000", -- 0x274: NOP - "000000" & X"000", -- 0x275: NOP - "000000" & X"000", -- 0x276: NOP - "111110" & X"000", -- 0x277: RET - "010101" & X"000", -- 0x278: SUB R00, 0x00 - "110011" & X"3FF", -- 0x279: JC 0x3FF - "101011" & X"000", -- 0x27A: SETC - "110100" & X"3FF", -- 0x27B: JNC 0x3FF - "000000" & X"000", -- 0x27C: NOP - "010101" & X"000", -- 0x27D: SUB R00, 0x00 - "110011" & X"3FF", -- 0x27E: JC 0x3FF - "000011" & X"000", -- 0x27F: MOV R00, 0x00 - "010101" & X"000", -- 0x280: CLRC - "110011" & X"3FF", -- 0x281: JC 0x3FF - "101011" & X"000", -- 0x282: SETC - "110100" & X"3FF", -- 0x283: JNC 0x3FF - "000000" & X"000", -- 0x284: NOP - "010101" & X"000", -- 0x285: CLRC - "110011" & X"3FF", -- 0x286: JC 0x3FF - "111110" & X"000", -- 0x287: RET - "010001" & X"01E", -- 0x288: INC R14 - "111111" & X"000", -- 0x289: RETI - "000000" & X"000", -- 0x28A: - "000000" & X"000", -- 0x28B: - "000000" & X"000", -- 0x28C: - "000000" & X"000", -- 0x28D: - "000000" & X"000", -- 0x28E: - "000000" & X"000", -- 0x28F: - "000000" & X"000", -- 0x290: - "000000" & X"000", -- 0x291: - "000000" & X"000", -- 0x292: - "000000" & X"000", -- 0x293: - "000000" & X"000", -- 0x294: - "000000" & X"000", -- 0x295: - "000000" & X"000", -- 0x296: - "000000" & X"000", -- 0x297: - "000000" & X"000", -- 0x298: - "000000" & X"000", -- 0x299: - "000000" & X"000", -- 0x29A: - "000000" & X"000", -- 0x29B: - "000000" & X"000", -- 0x29C: - "000000" & X"000", -- 0x29D: - "000000" & X"000", -- 0x29E: - "000000" & X"000", -- 0x29F: - "000000" & X"000", -- 0x2A0: - "000000" & X"000", -- 0x2A1: - "000000" & X"000", -- 0x2A2: - "000000" & X"000", -- 0x2A3: - "000000" & X"000", -- 0x2A4: - "000000" & X"000", -- 0x2A5: - "000000" & X"000", -- 0x2A6: - "000000" & X"000", -- 0x2A7: - "000000" & X"000", -- 0x2A8: - "000000" & X"000", -- 0x2A9: - "000000" & X"000", -- 0x2AA: - "000000" & X"000", -- 0x2AB: - "000000" & X"000", -- 0x2AC: - "000000" & X"000", -- 0x2AD: - "000000" & X"000", -- 0x2AE: - "000000" & X"000", -- 0x2AF: - "000000" & X"000", -- 0x2B0: - "000000" & X"000", -- 0x2B1: - "000000" & X"000", -- 0x2B2: - "000000" & X"000", -- 0x2B3: - "000000" & X"000", -- 0x2B4: - "000000" & X"000", -- 0x2B5: - "000000" & X"000", -- 0x2B6: - "000000" & X"000", -- 0x2B7: - "000000" & X"000", -- 0x2B8: - "000000" & X"000", -- 0x2B9: - "000000" & X"000", -- 0x2BA: - "000000" & X"000", -- 0x2BB: - "000000" & X"000", -- 0x2BC: - "000000" & X"000", -- 0x2BD: - "000000" & X"000", -- 0x2BE: - "000000" & X"000", -- 0x2BF: - "000000" & X"000", -- 0x2C0: - "000000" & X"000", -- 0x2C1: - "000000" & X"000", -- 0x2C2: - "000000" & X"000", -- 0x2C3: - "000000" & X"000", -- 0x2C4: - "000000" & X"000", -- 0x2C5: - "000000" & X"000", -- 0x2C6: - "000000" & X"000", -- 0x2C7: - "000000" & X"000", -- 0x2C8: - "000000" & X"000", -- 0x2C9: - "000000" & X"000", -- 0x2CA: - "000000" & X"000", -- 0x2CB: - "000000" & X"000", -- 0x2CC: - "000000" & X"000", -- 0x2CD: - "000000" & X"000", -- 0x2CE: - "000000" & X"000", -- 0x2CF: - "000000" & X"000", -- 0x2D0: - "000000" & X"000", -- 0x2D1: - "000000" & X"000", -- 0x2D2: - "000000" & X"000", -- 0x2D3: - "000000" & X"000", -- 0x2D4: - "000000" & X"000", -- 0x2D5: - "000000" & X"000", -- 0x2D6: - "000000" & X"000", -- 0x2D7: - "000000" & X"000", -- 0x2D8: - "000000" & X"000", -- 0x2D9: - "000000" & X"000", -- 0x2DA: - "000000" & X"000", -- 0x2DB: - "000000" & X"000", -- 0x2DC: - "000000" & X"000", -- 0x2DD: - "000000" & X"000", -- 0x2DE: - "000000" & X"000", -- 0x2DF: - "000000" & X"000", -- 0x2E0: - "000000" & X"000", -- 0x2E1: - "000000" & X"000", -- 0x2E2: - "000000" & X"000", -- 0x2E3: - "000000" & X"000", -- 0x2E4: - "000000" & X"000", -- 0x2E5: - "000000" & X"000", -- 0x2E6: - "000000" & X"000", -- 0x2E7: - "000000" & X"000", -- 0x2E8: - "000000" & X"000", -- 0x2E9: - "000000" & X"000", -- 0x2EA: - "000000" & X"000", -- 0x2EB: - "000000" & X"000", -- 0x2EC: - "000000" & X"000", -- 0x2ED: - "000000" & X"000", -- 0x2EE: - "000000" & X"000", -- 0x2EF: - "000000" & X"000", -- 0x2F0: - "000000" & X"000", -- 0x2F1: - "000000" & X"000", -- 0x2F2: - "000000" & X"000", -- 0x2F3: - "000000" & X"000", -- 0x2F4: - "000000" & X"000", -- 0x2F5: - "000000" & X"000", -- 0x2F6: - "000000" & X"000", -- 0x2F7: - "000000" & X"000", -- 0x2F8: - "000000" & X"000", -- 0x2F9: - "000000" & X"000", -- 0x2FA: - "000000" & X"000", -- 0x2FB: - "000000" & X"000", -- 0x2FC: - "000000" & X"000", -- 0x2FD: - "000000" & X"000", -- 0x2FE: - "110000" & X"2FF", -- 0x2FF: JMP 0x2FF - "000000" & X"000", -- 0x300: - "000000" & X"000", -- 0x301: - "000000" & X"000", -- 0x302: - "000000" & X"000", -- 0x303: - "000000" & X"000", -- 0x304: - "000000" & X"000", -- 0x305: - "000000" & X"000", -- 0x306: - "000000" & X"000", -- 0x307: - "000000" & X"000", -- 0x308: - "000000" & X"000", -- 0x309: - "000000" & X"000", -- 0x30A: - "000000" & X"000", -- 0x30B: - "000000" & X"000", -- 0x30C: - "000000" & X"000", -- 0x30D: - "000000" & X"000", -- 0x30E: - "000000" & X"000", -- 0x30F: - "000000" & X"000", -- 0x310: - "000000" & X"000", -- 0x311: - "000000" & X"000", -- 0x312: - "000000" & X"000", -- 0x313: - "000000" & X"000", -- 0x314: - "000000" & X"000", -- 0x315: - "000000" & X"000", -- 0x316: - "000000" & X"000", -- 0x317: - "000000" & X"000", -- 0x318: - "000000" & X"000", -- 0x319: - "000000" & X"000", -- 0x31A: - "000000" & X"000", -- 0x31B: - "000000" & X"000", -- 0x31C: - "000000" & X"000", -- 0x31D: - "000000" & X"000", -- 0x31E: - "000000" & X"000", -- 0x31F: - "000000" & X"000", -- 0x320: - "000000" & X"000", -- 0x321: - "000000" & X"000", -- 0x322: - "000000" & X"000", -- 0x323: - "000000" & X"000", -- 0x324: - "000000" & X"000", -- 0x325: - "000000" & X"000", -- 0x326: - "000000" & X"000", -- 0x327: - "000000" & X"000", -- 0x328: - "000000" & X"000", -- 0x329: - "000000" & X"000", -- 0x32A: - "000000" & X"000", -- 0x32B: - "000000" & X"000", -- 0x32C: - "000000" & X"000", -- 0x32D: - "000000" & X"000", -- 0x32E: - "000000" & X"000", -- 0x32F: - "000000" & X"000", -- 0x330: - "000000" & X"000", -- 0x331: - "000000" & X"000", -- 0x332: - "000000" & X"000", -- 0x333: - "000000" & X"000", -- 0x334: - "000000" & X"000", -- 0x335: - "000000" & X"000", -- 0x336: - "000000" & X"000", -- 0x337: - "000000" & X"000", -- 0x338: - "000000" & X"000", -- 0x339: - "000000" & X"000", -- 0x33A: - "000000" & X"000", -- 0x33B: - "000000" & X"000", -- 0x33C: - "000000" & X"000", -- 0x33D: - "000000" & X"000", -- 0x33E: - "000000" & X"000", -- 0x33F: - "000000" & X"000", -- 0x340: - "000000" & X"000", -- 0x341: - "000000" & X"000", -- 0x342: - "000000" & X"000", -- 0x343: - "000000" & X"000", -- 0x344: - "000000" & X"000", -- 0x345: - "000000" & X"000", -- 0x346: - "000000" & X"000", -- 0x347: - "000000" & X"000", -- 0x348: - "000000" & X"000", -- 0x349: - "000000" & X"000", -- 0x34A: - "000000" & X"000", -- 0x34B: - "000000" & X"000", -- 0x34C: - "000000" & X"000", -- 0x34D: - "000000" & X"000", -- 0x34E: - "000000" & X"000", -- 0x34F: - "000000" & X"000", -- 0x350: - "000000" & X"000", -- 0x351: - "000000" & X"000", -- 0x352: - "000000" & X"000", -- 0x353: - "000000" & X"000", -- 0x354: - "000000" & X"000", -- 0x355: - "000000" & X"000", -- 0x356: - "000000" & X"000", -- 0x357: - "000000" & X"000", -- 0x358: - "000000" & X"000", -- 0x359: - "000000" & X"000", -- 0x35A: - "000000" & X"000", -- 0x35B: - "000000" & X"000", -- 0x35C: - "000000" & X"000", -- 0x35D: - "000000" & X"000", -- 0x35E: - "000000" & X"000", -- 0x35F: - "000000" & X"000", -- 0x360: - "000000" & X"000", -- 0x361: - "000000" & X"000", -- 0x362: - "000000" & X"000", -- 0x363: - "000000" & X"000", -- 0x364: - "000000" & X"000", -- 0x365: - "000000" & X"000", -- 0x366: - "000000" & X"000", -- 0x367: - "000000" & X"000", -- 0x368: - "000000" & X"000", -- 0x369: - "000000" & X"000", -- 0x36A: - "000000" & X"000", -- 0x36B: - "000000" & X"000", -- 0x36C: - "000000" & X"000", -- 0x36D: - "000000" & X"000", -- 0x36E: - "000000" & X"000", -- 0x36F: - "000000" & X"000", -- 0x370: - "000000" & X"000", -- 0x371: - "000000" & X"000", -- 0x372: - "000000" & X"000", -- 0x373: - "000000" & X"000", -- 0x374: - "000000" & X"000", -- 0x375: - "000000" & X"000", -- 0x376: - "000000" & X"000", -- 0x377: - "000000" & X"000", -- 0x378: - "000000" & X"000", -- 0x379: - "000000" & X"000", -- 0x37A: - "000000" & X"000", -- 0x37B: - "000000" & X"000", -- 0x37C: - "000000" & X"000", -- 0x37D: - "000000" & X"000", -- 0x37E: - "000000" & X"000", -- 0x37F: - "000000" & X"000", -- 0x380: - "000000" & X"000", -- 0x381: - "000000" & X"000", -- 0x382: - "000000" & X"000", -- 0x383: - "000000" & X"000", -- 0x384: - "000000" & X"000", -- 0x385: - "000000" & X"000", -- 0x386: - "000000" & X"000", -- 0x387: - "000000" & X"000", -- 0x388: - "000000" & X"000", -- 0x389: - "000000" & X"000", -- 0x38A: - "000000" & X"000", -- 0x38B: - "000000" & X"000", -- 0x38C: - "000000" & X"000", -- 0x38D: - "000000" & X"000", -- 0x38E: - "000000" & X"000", -- 0x38F: - "000000" & X"000", -- 0x390: - "000000" & X"000", -- 0x391: - "000000" & X"000", -- 0x392: - "000000" & X"000", -- 0x393: - "000000" & X"000", -- 0x394: - "000000" & X"000", -- 0x395: - "000000" & X"000", -- 0x396: - "000000" & X"000", -- 0x397: - "000000" & X"000", -- 0x398: - "000000" & X"000", -- 0x399: - "000000" & X"000", -- 0x39A: - "000000" & X"000", -- 0x39B: - "000000" & X"000", -- 0x39C: - "000000" & X"000", -- 0x39D: - "000000" & X"000", -- 0x39E: - "000000" & X"000", -- 0x39F: - "000000" & X"000", -- 0x3A0: - "000000" & X"000", -- 0x3A1: - "000000" & X"000", -- 0x3A2: - "000000" & X"000", -- 0x3A3: - "000000" & X"000", -- 0x3A4: - "000000" & X"000", -- 0x3A5: - "000000" & X"000", -- 0x3A6: - "000000" & X"000", -- 0x3A7: - "000000" & X"000", -- 0x3A8: - "000000" & X"000", -- 0x3A9: - "000000" & X"000", -- 0x3AA: - "000000" & X"000", -- 0x3AB: - "000000" & X"000", -- 0x3AC: - "000000" & X"000", -- 0x3AD: - "000000" & X"000", -- 0x3AE: - "000000" & X"000", -- 0x3AF: - "000000" & X"000", -- 0x3B0: - "000000" & X"000", -- 0x3B1: - "000000" & X"000", -- 0x3B2: - "000000" & X"000", -- 0x3B3: - "000000" & X"000", -- 0x3B4: - "000000" & X"000", -- 0x3B5: - "000000" & X"000", -- 0x3B6: - "000000" & X"000", -- 0x3B7: - "000000" & X"000", -- 0x3B8: - "000000" & X"000", -- 0x3B9: - "000000" & X"000", -- 0x3BA: - "000000" & X"000", -- 0x3BB: - "000000" & X"000", -- 0x3BC: - "000000" & X"000", -- 0x3BD: - "000000" & X"000", -- 0x3BE: - "000000" & X"000", -- 0x3BF: - "000000" & X"000", -- 0x3C0: - "000000" & X"000", -- 0x3C1: - "000000" & X"000", -- 0x3C2: - "000000" & X"000", -- 0x3C3: - "000000" & X"000", -- 0x3C4: - "000000" & X"000", -- 0x3C5: - "000000" & X"000", -- 0x3C6: - "000000" & X"000", -- 0x3C7: - "000000" & X"000", -- 0x3C8: - "000000" & X"000", -- 0x3C9: - "000000" & X"000", -- 0x3CA: - "000000" & X"000", -- 0x3CB: - "000000" & X"000", -- 0x3CC: - "000000" & X"000", -- 0x3CD: - "000000" & X"000", -- 0x3CE: - "000000" & X"000", -- 0x3CF: - "000000" & X"000", -- 0x3D0: - "000000" & X"000", -- 0x3D1: - "000000" & X"000", -- 0x3D2: - "000000" & X"000", -- 0x3D3: - "000000" & X"000", -- 0x3D4: - "000000" & X"000", -- 0x3D5: - "000000" & X"000", -- 0x3D6: - "000000" & X"000", -- 0x3D7: - "000000" & X"000", -- 0x3D8: - "000000" & X"000", -- 0x3D9: - "000000" & X"000", -- 0x3DA: - "000000" & X"000", -- 0x3DB: - "000000" & X"000", -- 0x3DC: - "000000" & X"000", -- 0x3DD: - "000000" & X"000", -- 0x3DE: - "000000" & X"000", -- 0x3DF: - "000000" & X"000", -- 0x3E0: - "000000" & X"000", -- 0x3E1: - "000000" & X"000", -- 0x3E2: - "000000" & X"000", -- 0x3E3: - "000000" & X"000", -- 0x3E4: - "000000" & X"000", -- 0x3E5: - "000000" & X"000", -- 0x3E6: - "000000" & X"000", -- 0x3E7: - "000000" & X"000", -- 0x3E8: - "000000" & X"000", -- 0x3E9: - "000000" & X"000", -- 0x3EA: - "000000" & X"000", -- 0x3EB: - "000000" & X"000", -- 0x3EC: - "000000" & X"000", -- 0x3ED: - "000000" & X"000", -- 0x3EE: - "000000" & X"000", -- 0x3EF: - "000000" & X"000", -- 0x3F0: - "000000" & X"000", -- 0x3F1: - "000000" & X"000", -- 0x3F2: - "000000" & X"000", -- 0x3F3: - "000000" & X"000", -- 0x3F4: - "000000" & X"000", -- 0x3F5: - "000000" & X"000", -- 0x3F6: - "000000" & X"000", -- 0x3F7: - "000000" & X"000", -- 0x3F8: - "000000" & X"000", -- 0x3F9: - "000000" & X"000", -- 0x3FA: - "000000" & X"000", -- 0x3FB: - "000000" & X"000", -- 0x3FC: - "000000" & X"000", -- 0x3FD: - "000000" & X"000", -- 0x3FE: - "110000" & X"3FF" -- 0x3FF: JMP 0x3FF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/itest_xrom.vhdl b/lib/CPUs/JCpu/src/itest_xrom.vhdl deleted file mode 100644 index 4206abc..0000000 --- a/lib/CPUs/JCpu/src/itest_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE itest OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from itest.jsm - constant xmem_rom : xmem_rom_t := - ( - X"48", -- 0x00 - X"61", -- 0x01 - X"6C", -- 0x02 - X"6C", -- 0x03 - X"6F", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end itest; - diff --git a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl b/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl deleted file mode 100644 index 60a84ac..0000000 --- a/lib/CPUs/JCpu/src/itest_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from itest.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"48", -- 0x00 - X"61", -- 0x01 - X"6C", -- 0x02 - X"6C", -- 0x03 - X"6F", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom.vhdl deleted file mode 100644 index 3b0de3b..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_irom.vhdl +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE mul8x8 OF irom IS - - type imem_rom_t is array (0 to 26) of inst_t; - - -- Assembled from mul8x8.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"001", -- 0x000: JMP 0x001 - "000011" & X"450", -- 0x001: MOV R00, 0x45 - "000011" & X"F51", -- 0x002: MOV R01, 0xF5 - "111011" & X"005", -- 0x003: CALL 0x005 - "110000" & X"004", -- 0x004: JMP 0x004 - "111100" & X"002", -- 0x005: PUSH R02 - "111100" & X"003", -- 0x006: PUSH R03 - "111100" & X"004", -- 0x007: PUSH R04 - "000010" & X"014", -- 0x008: MOV R04, R01 - "000011" & X"001", -- 0x009: MOV R01, 0x00 - "000011" & X"002", -- 0x00A: MOV R02, 0x00 - "000011" & X"003", -- 0x00B: MOV R03, 0x00 - "001111" & X"014", -- 0x00C: CMP R04, 0x01 - "111001" & X"015", -- 0x00D: JEQ 0x015 - "011111" & X"004", -- 0x00E: SHR R04 - "110100" & X"012", -- 0x00F: JNC 0x012 - "010000" & X"002", -- 0x010: ADD R02, R00 - "010010" & X"013", -- 0x011: ADDC R03, R01 - "011110" & X"000", -- 0x012: SHL R00 - "100010" & X"001", -- 0x013: ROLC R01 - "110000" & X"00C", -- 0x014: JMP 0x00C - "010000" & X"020", -- 0x015: ADD R00, R02 - "010010" & X"031", -- 0x016: ADDC R01, R03 - "111101" & X"004", -- 0x017: POP R04 - "111101" & X"003", -- 0x018: POP R03 - "111101" & X"002", -- 0x019: POP R02 - "111110" & X"000" -- 0x01A: RET - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end mul8x8; - diff --git a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl deleted file mode 100644 index 4303d08..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from mul8x8.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"001", -- 0x000: JMP 0x001 - "000011" & X"450", -- 0x001: MOV R00, 0x45 - "000011" & X"F51", -- 0x002: MOV R01, 0xF5 - "111011" & X"005", -- 0x003: CALL 0x005 - "110000" & X"004", -- 0x004: JMP 0x004 - "111100" & X"002", -- 0x005: PUSH R02 - "111100" & X"003", -- 0x006: PUSH R03 - "111100" & X"004", -- 0x007: PUSH R04 - "000010" & X"014", -- 0x008: MOV R04, R01 - "000011" & X"001", -- 0x009: MOV R01, 0x00 - "000011" & X"002", -- 0x00A: MOV R02, 0x00 - "000011" & X"003", -- 0x00B: MOV R03, 0x00 - "001111" & X"014", -- 0x00C: CMP R04, 0x01 - "111001" & X"015", -- 0x00D: JEQ 0x015 - "011111" & X"004", -- 0x00E: SHR R04 - "110100" & X"012", -- 0x00F: JNC 0x012 - "010000" & X"002", -- 0x010: ADD R02, R00 - "010010" & X"013", -- 0x011: ADDC R03, R01 - "011110" & X"000", -- 0x012: SHL R00 - "100010" & X"001", -- 0x013: ROLC R01 - "110000" & X"00C", -- 0x014: JMP 0x00C - "010000" & X"020", -- 0x015: ADD R00, R02 - "010010" & X"031", -- 0x016: ADDC R01, R03 - "111101" & X"004", -- 0x017: POP R04 - "111101" & X"003", -- 0x018: POP R03 - "111101" & X"002", -- 0x019: POP R02 - "111110" & X"000", -- 0x01A: RET - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - 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i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl deleted file mode 100644 index 508e8cf..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE mul8x8 OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from mul8x8.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end mul8x8; - diff --git a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl b/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl deleted file mode 100644 index a75d090..0000000 --- a/lib/CPUs/JCpu/src/mul8x8_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from mul8x8.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom.vhdl deleted file mode 100644 index 9355a7d..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_irom.vhdl +++ /dev/null @@ -1,89 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); -END irom; - -ARCHITECTURE reti_issue OF irom IS - - type imem_rom_t is array (0 to 27) of inst_t; - - -- Assembled from reti_issue.jsm - constant imem_rom : imem_rom_t := - ( - "110000" & X"002", -- 0x000: JMP 0x002 - "111111" & X"000", -- 0x001: RETI - "000011" & X"050", -- 0x002: MOV R00, 0x05 - "100110" & X"030", -- 0x003: COUT (0x03), R00 - "000011" & X"000", -- 0x004: MOV R00, 0x00 - "000000" & X"000", -- 0x005: NOP - "010001" & X"010", -- 0x006: INC R00 - "000000" & X"000", -- 0x007: NOP - "111011" & X"01B", -- 0x008: CALL 0x01B - "000000" & X"000", -- 0x009: NOP - "111100" & X"003", -- 0x00A: PUSH R03 - "000000" & X"000", -- 0x00B: NOP - "111100" & X"002", -- 0x00C: PUSH R02 - "000000" & X"000", -- 0x00D: NOP - "111100" & X"001", -- 0x00E: PUSH R01 - "000000" & X"000", -- 0x00F: NOP - "111100" & X"000", -- 0x010: PUSH R00 - "000000" & X"000", -- 0x011: NOP - "111101" & X"000", -- 0x012: POP R00 - "000000" & X"000", -- 0x013: NOP - "111101" & X"001", -- 0x014: POP R01 - "000000" & X"000", -- 0x015: NOP - "111101" & X"002", -- 0x016: POP R02 - "000000" & X"000", -- 0x017: NOP - "111101" & X"003", -- 0x018: POP R03 - "000000" & X"000", -- 0x019: NOP - "110000" & X"005", -- 0x01A: JMP 0x005 - "111110" & X"000" -- 0x01B: RET - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -end reti_issue; - diff --git a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl deleted file mode 100644 index d1b4bd1..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_irom_ld.vhdl +++ /dev/null @@ -1,1181 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from reti_issue.jsm - type imem_rom_t is array (0 to 1023) of inst_t; - signal imem_rom : imem_rom_t := - ( - "110000" & X"002", -- 0x000: JMP 0x002 - "111111" & X"000", -- 0x001: RETI - "000011" & X"050", -- 0x002: MOV R00, 0x05 - "100110" & X"030", -- 0x003: COUT (0x03), R00 - "000011" & X"000", -- 0x004: MOV R00, 0x00 - "000000" & X"000", -- 0x005: NOP - "010001" & X"010", -- 0x006: INC R00 - "000000" & X"000", -- 0x007: NOP - "111011" & X"01B", -- 0x008: CALL 0x01B - "000000" & X"000", -- 0x009: NOP - "111100" & X"003", -- 0x00A: PUSH R03 - "000000" & X"000", -- 0x00B: NOP - "111100" & X"002", -- 0x00C: PUSH R02 - "000000" & X"000", -- 0x00D: NOP - "111100" & X"001", -- 0x00E: PUSH R01 - "000000" & X"000", -- 0x00F: NOP - "111100" & X"000", -- 0x010: PUSH R00 - "000000" & X"000", -- 0x011: NOP - "111101" & X"000", -- 0x012: POP R00 - "000000" & X"000", -- 0x013: NOP - "111101" & X"001", -- 0x014: POP R01 - "000000" & X"000", -- 0x015: NOP - "111101" & X"002", -- 0x016: POP R02 - "000000" & X"000", -- 0x017: NOP - "111101" & X"003", -- 0x018: POP R03 - "000000" & X"000", -- 0x019: NOP - "110000" & X"005", -- 0x01A: JMP 0x005 - "111110" & X"000", -- 0x01B: RET - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - 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"000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000", - "000000" & X"000" - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl deleted file mode 100644 index a7a33f9..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_xrom.vhdl +++ /dev/null @@ -1,317 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); -END xrom; - -ARCHITECTURE reti_issue OF xrom IS - - type xmem_rom_t is array (0 to 255) of dmem_data_t; - - -- Assembled from reti_issue.jsm - constant xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - -begin - -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -end reti_issue; - diff --git a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl b/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl deleted file mode 100644 index 244c1b5..0000000 --- a/lib/CPUs/JCpu/src/reti_issue_xrom_ld.vhdl +++ /dev/null @@ -1,413 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - -- Assembled from reti_issue.jsm - type xmem_rom_t is array (0 to 255) of dmem_data_t; - signal xmem_rom : xmem_rom_t := - ( - X"00", -- 0x00 - X"00", -- 0x01 - X"00", -- 0x02 - X"00", -- 0x03 - X"00", -- 0x04 - X"00", -- 0x05 - X"00", -- 0x06 - X"00", -- 0x07 - X"00", -- 0x08 - X"00", -- 0x09 - X"00", -- 0x0A - X"00", -- 0x0B - X"00", -- 0x0C - X"00", -- 0x0D - X"00", -- 0x0E - X"00", -- 0x0F - X"00", -- 0x10 - X"00", -- 0x11 - X"00", -- 0x12 - X"00", -- 0x13 - X"00", -- 0x14 - X"00", -- 0x15 - X"00", -- 0x16 - X"00", -- 0x17 - X"00", -- 0x18 - X"00", -- 0x19 - X"00", -- 0x1A - X"00", -- 0x1B - X"00", -- 0x1C - X"00", -- 0x1D - X"00", -- 0x1E - X"00", -- 0x1F - X"00", -- 0x20 - X"00", -- 0x21 - X"00", -- 0x22 - X"00", -- 0x23 - X"00", -- 0x24 - X"00", -- 0x25 - X"00", -- 0x26 - X"00", -- 0x27 - X"00", -- 0x28 - X"00", -- 0x29 - X"00", -- 0x2A - X"00", -- 0x2B - X"00", -- 0x2C - X"00", -- 0x2D - X"00", -- 0x2E - X"00", -- 0x2F - X"00", -- 0x30 - X"00", -- 0x31 - X"00", -- 0x32 - X"00", -- 0x33 - X"00", -- 0x34 - X"00", -- 0x35 - X"00", -- 0x36 - X"00", -- 0x37 - X"00", -- 0x38 - X"00", -- 0x39 - X"00", -- 0x3A - X"00", -- 0x3B - X"00", -- 0x3C - X"00", -- 0x3D - X"00", -- 0x3E - X"00", -- 0x3F - X"00", -- 0x40 - X"00", -- 0x41 - X"00", -- 0x42 - X"00", -- 0x43 - X"00", -- 0x44 - X"00", -- 0x45 - X"00", -- 0x46 - X"00", -- 0x47 - X"00", -- 0x48 - X"00", -- 0x49 - X"00", -- 0x4A - X"00", -- 0x4B - X"00", -- 0x4C - X"00", -- 0x4D - X"00", -- 0x4E - X"00", -- 0x4F - X"00", -- 0x50 - X"00", -- 0x51 - X"00", -- 0x52 - X"00", -- 0x53 - X"00", -- 0x54 - X"00", -- 0x55 - X"00", -- 0x56 - X"00", -- 0x57 - X"00", -- 0x58 - X"00", -- 0x59 - X"00", -- 0x5A - X"00", -- 0x5B - X"00", -- 0x5C - X"00", -- 0x5D - X"00", -- 0x5E - X"00", -- 0x5F - X"00", -- 0x60 - X"00", -- 0x61 - X"00", -- 0x62 - X"00", -- 0x63 - X"00", -- 0x64 - X"00", -- 0x65 - X"00", -- 0x66 - X"00", -- 0x67 - X"00", -- 0x68 - X"00", -- 0x69 - X"00", -- 0x6A - X"00", -- 0x6B - X"00", -- 0x6C - X"00", -- 0x6D - X"00", -- 0x6E - X"00", -- 0x6F - X"00", -- 0x70 - X"00", -- 0x71 - X"00", -- 0x72 - X"00", -- 0x73 - X"00", -- 0x74 - X"00", -- 0x75 - X"00", -- 0x76 - X"00", -- 0x77 - X"00", -- 0x78 - X"00", -- 0x79 - X"00", -- 0x7A - X"00", -- 0x7B - X"00", -- 0x7C - X"00", -- 0x7D - X"00", -- 0x7E - X"00", -- 0x7F - X"00", -- 0x80 - X"00", -- 0x81 - X"00", -- 0x82 - X"00", -- 0x83 - X"00", -- 0x84 - X"00", -- 0x85 - X"00", -- 0x86 - X"00", -- 0x87 - X"00", -- 0x88 - X"00", -- 0x89 - X"00", -- 0x8A - X"00", -- 0x8B - X"00", -- 0x8C - X"00", -- 0x8D - X"00", -- 0x8E - X"00", -- 0x8F - X"00", -- 0x90 - X"00", -- 0x91 - X"00", -- 0x92 - X"00", -- 0x93 - X"00", -- 0x94 - X"00", -- 0x95 - X"00", -- 0x96 - X"00", -- 0x97 - X"00", -- 0x98 - X"00", -- 0x99 - X"00", -- 0x9A - X"00", -- 0x9B - X"00", -- 0x9C - X"00", -- 0x9D - X"00", -- 0x9E - X"00", -- 0x9F - X"00", -- 0xA0 - X"00", -- 0xA1 - X"00", -- 0xA2 - X"00", -- 0xA3 - X"00", -- 0xA4 - X"00", -- 0xA5 - X"00", -- 0xA6 - X"00", -- 0xA7 - X"00", -- 0xA8 - X"00", -- 0xA9 - X"00", -- 0xAA - X"00", -- 0xAB - X"00", -- 0xAC - X"00", -- 0xAD - X"00", -- 0xAE - X"00", -- 0xAF - X"00", -- 0xB0 - X"00", -- 0xB1 - X"00", -- 0xB2 - X"00", -- 0xB3 - X"00", -- 0xB4 - X"00", -- 0xB5 - X"00", -- 0xB6 - X"00", -- 0xB7 - X"00", -- 0xB8 - X"00", -- 0xB9 - X"00", -- 0xBA - X"00", -- 0xBB - X"00", -- 0xBC - X"00", -- 0xBD - X"00", -- 0xBE - X"00", -- 0xBF - X"00", -- 0xC0 - X"00", -- 0xC1 - X"00", -- 0xC2 - X"00", -- 0xC3 - X"00", -- 0xC4 - X"00", -- 0xC5 - X"00", -- 0xC6 - X"00", -- 0xC7 - X"00", -- 0xC8 - X"00", -- 0xC9 - X"00", -- 0xCA - X"00", -- 0xCB - X"00", -- 0xCC - X"00", -- 0xCD - X"00", -- 0xCE - X"00", -- 0xCF - X"00", -- 0xD0 - X"00", -- 0xD1 - X"00", -- 0xD2 - X"00", -- 0xD3 - X"00", -- 0xD4 - X"00", -- 0xD5 - X"00", -- 0xD6 - X"00", -- 0xD7 - X"00", -- 0xD8 - X"00", -- 0xD9 - X"00", -- 0xDA - X"00", -- 0xDB - X"00", -- 0xDC - X"00", -- 0xDD - X"00", -- 0xDE - X"00", -- 0xDF - X"00", -- 0xE0 - X"00", -- 0xE1 - X"00", -- 0xE2 - X"00", -- 0xE3 - X"00", -- 0xE4 - X"00", -- 0xE5 - X"00", -- 0xE6 - X"00", -- 0xE7 - X"00", -- 0xE8 - X"00", -- 0xE9 - X"00", -- 0xEA - X"00", -- 0xEB - X"00", -- 0xEC - X"00", -- 0xED - X"00", -- 0xEE - X"00", -- 0xEF - X"00", -- 0xF0 - X"00", -- 0xF1 - X"00", -- 0xF2 - X"00", -- 0xF3 - X"00", -- 0xF4 - X"00", -- 0xF5 - X"00", -- 0xF6 - X"00", -- 0xF7 - X"00", -- 0xF8 - X"00", -- 0xF9 - X"00", -- 0xFA - X"00", -- 0xFB - X"00", -- 0xFC - X"00", -- 0xFD - X"00", -- 0xFE - X"00" -- 0xFF - ); - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd b/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd deleted file mode 100644 index ede20d5..0000000 --- a/lib/CPUs/JCpu/src/tb_cpu_embedded.vhd +++ /dev/null @@ -1,129 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: testbench for embedded cpu with rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.cpu_pkg.all; - -ENTITY tb_cpu_embedded IS -END tb_cpu_embedded; - -ARCHITECTURE behavior OF tb_cpu_embedded IS - - COMPONENT cpu_embedded - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_ADDR_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - type sram_t is array (integer range <>) of dmem_data_t; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal int_in : std_logic := '0'; - signal int_ack : std_logic; - signal xmem_wait : std_logic := '0'; - signal xmem_din : dmem_data_t := (others => '-'); - signal xmem_dout : dmem_data_t; - signal xmem_addr : dmem_addr_t; - signal xmem_we : std_logic; - signal xmem_re : std_logic; - signal io_sel : std_logic; - signal sram : sram_t(0 to 2**dmem_addr_t'length-1); - - -BEGIN - -uut: cpu_embedded - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_wait => xmem_wait, - xmem_we => xmem_we, - xmem_re => xmem_re, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - rst <= '0'; - wait for 2*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - wait for 1000*CLK_PERIOD; - - assert false report "Test finished" severity error; - wait; - - end process; - -SRAM_RW: process(rst, clk, xmem_addr, xmem_dout, xmem_we) - begin - if (rst = '1') then - xmem_din <= X"00"; - elsif rising_edge(clk) then - if io_sel = '0' then - if xmem_we = '1' then - sram(to_integer(xmem_addr)) <= xmem_dout; - end if; - xmem_din <= to_01(sram(to_integer(xmem_addr))); - else - xmem_din <= X"FF"; - end if; - end if; - end process; - -END; diff --git a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd b/lib/CPUs/JCpu/src/tb_cpu_itest.vhd deleted file mode 100644 index 80d8c43..0000000 --- a/lib/CPUs/JCpu/src/tb_cpu_itest.vhd +++ /dev/null @@ -1,218 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Formal test of correct function of JCPU, --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.cpu_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_cpu IS -END tb_cpu; - -ARCHITECTURE behavior OF tb_cpu IS - - COMPONENT cpu - Generic ( - use_instr_register : boolean; - use_ctrl_rom : boolean - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - int_in : in STD_LOGIC; - int_ack : out STD_LOGIC; - xmem_wait : in STD_LOGIC; - xmem_we : out STD_LOGIC; - xmem_re : out STD_LOGIC; - instr_din : in unsigned (IMEM_DATA_WIDTH-1 downto 0); - instr_addr : out unsigned (IMEM_ADDR_WIDTH-1 downto 0); - xmem_din : in unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_dout : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - xmem_addr : out unsigned (DMEM_DATA_WIDTH-1 downto 0); - io_sel : out STD_LOGIC - - ); - END COMPONENT; - - COMPONENT irom - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - type prom_t is array (integer range <>) of inst_t; - type sram_t is array (integer range <>) of dmem_data_t; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal int_in : std_logic := '0'; - signal int_ack : std_logic; - signal xmem_wait : std_logic := '1'; - signal irom_data : unsigned (IMEM_DATA_WIDTH-1 downto 0) := (others => '-'); - signal irom_addr : unsigned (IMEM_ADDR_WIDTH-1 downto 0); - signal xmem_din : dmem_data_t := (others => '-'); - signal xmem_dout : dmem_data_t; - signal xmem_addr : unsigned (DMEM_DATA_WIDTH-1 downto 0); - signal xmem_we : std_logic; - signal xmem_re : std_logic; - signal io_sel : std_logic; - signal sram : sram_t(0 to 2**DMEM_DATA_WIDTH-1); - - type reg_t is record - revision : dmem_data_t; - testid : dmem_data_t; - interrupt : std_logic; - end record; - - signal reg : reg_t; - - -BEGIN - - int_in <= reg.interrupt; -uut: cpu - GENERIC MAP - ( - use_instr_register => false, - use_ctrl_rom => true - ) - PORT MAP( - rst => rst, - clk => clk, - ce => ce, - int_in => int_in, - int_ack => int_ack, - xmem_wait => xmem_wait, - xmem_we => xmem_we, - xmem_re => xmem_re, - instr_din => irom_data, - instr_addr => irom_addr, - xmem_din => xmem_din, - xmem_dout => xmem_dout, - xmem_addr => xmem_addr, - io_sel => io_sel - ); - -the_irom: irom - PORT MAP( - clk => clk, - ce => ce, - addr => irom_addr, - dout => irom_data - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -XWAIT_GEN:process(rst, clk) - variable cnt : unsigned(3 downto 0); - begin - if (rst = '1') then - cnt := (others => '1'); - elsif rising_edge(clk) then - if cnt /= "0000" then - cnt := cnt - 1; - else - cnt := (others => '1'); - xmem_wait <= not xmem_wait; - end if; - end if; - end process; - -STIMULUS: process - file RESULT: text open write_mode is "../tools/opc.list"; - variable L: line; - - begin - - for i in 0 to instr_name_array'length-1 loop - fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i)); - end loop; - - wait for 3*CLK_PERIOD; - rst <= '0'; - wait for 2*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - assert false report "Test finished" severity error; - wait; - - end process; - -SRAM_RW: process(rst, clk) - begin - if (rst = '1') then - reg.revision <= (others => '0'); - reg.testid <= (others => '0'); - reg.interrupt <= '0'; - elsif rising_edge(clk) then - if int_ack = '1' then --- reg.interrupt <= '0'; - end if; - if xmem_we = '1' then - if io_sel = '0' then - sram(to_integer(xmem_addr)) <= xmem_dout; - else - case xmem_addr is - when X"00" => - reg.revision <= xmem_dout; - when X"01" => - reg.testid <= xmem_dout; - when X"02" => - reg.interrupt <= xmem_dout(0); - when others => null; - end case; - end if; - else - if io_sel = '0' then - xmem_din <= to_01(sram(to_integer(xmem_addr))); - else - case xmem_addr is - when X"00" => - xmem_din <= reg.revision; - when X"01" => - xmem_din <= reg.testid; - when others => - xmem_din <= X"BC"; - end case; - end if; - end if; - end if; - end process; - -END; diff --git a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj b/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj deleted file mode 100644 index 18718bf..0000000 --- a/lib/CPUs/JCpu/syn/ise91/cpu_vhdl.prj +++ /dev/null @@ -1,10 +0,0 @@ -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu_pkg.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\stack_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\reg_dual.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\pc.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\int_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\dpath_ctrl.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipreg.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\chipram.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\alu.vhd" -vhdl work "W:\vhdl\lib\CPUs\JCpu\src\core\cpu.vhd" diff --git a/lib/CPUs/JCpu/tools/eval_scan.rb b/lib/CPUs/JCpu/tools/eval_scan.rb deleted file mode 100644 index 0c38397..0000000 --- a/lib/CPUs/JCpu/tools/eval_scan.rb +++ /dev/null @@ -1,42 +0,0 @@ -#!/usr/bin/env ruby - -str1 = %Q!lbl: dc "Hallo", ", ", 0, 1, " der","Jens"! - -i=0; - -def get_stri_lit (str) - res = [""]; - state = "out" - - j = 0; - k = 0; - for i in (0..str.length-1) - c = str[i]; - nstate = state - case state - when "out" - if c == "\""[0] - nstate = "in" - end - when "in" - if c == "\""[0] - nstate = "out" - if j > 0 - k = k + 1; - res[k] = "" - end - else - res[k] = res[k] + format("%c", c); - j = j + 1; - end - end - state = nstate - end; - return res -end - -get_stri_lit(str1).each do |word| - puts word -end - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/tools/insrom.rb b/lib/CPUs/JCpu/tools/insrom.rb deleted file mode 100644 index 6713f9f..0000000 --- a/lib/CPUs/JCpu/tools/insrom.rb +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: Insertion of code fragments into templates -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -rom_filename = arg[0].to_s -tpl_filename = arg[1].to_s - -subst_pattern = "JASM_ROM_INSERT_HERE" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -romfile = File.open(rom_filename, "r") -tplfile = File.open(tpl_filename, "r") -re = Regexp.new(subst_pattern) - -while (line = tplfile.gets) - puts line - line.scan(re).each do |word| - romfile.each do |raw_line| - puts raw_line - end - end -end diff --git a/lib/CPUs/JCpu/tools/irom.vhd.tpl b/lib/CPUs/JCpu/tools/irom.vhd.tpl deleted file mode 100644 index 5f11f86..0000000 --- a/lib/CPUs/JCpu/tools/irom.vhd.tpl +++ /dev/null @@ -1,32 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE - diff --git a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl deleted file mode 100644 index eaa41f3..0000000 --- a/lib/CPUs/JCpu/tools/irom_ld.vhd.tpl +++ /dev/null @@ -1,151 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : inst_addr_t; - signal jtag_ld_dout : inst_t; - signal jtag_ld_din : inst_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (31 downto 0); - constant id : unsigned (31 downto 0) := X"BABE" & X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-inst_addr_t'length+1); - jtag_ld_din <= user_regi(inst_t'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto inst_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/JCpu/tools/jasm.bak.rb b/lib/CPUs/JCpu/tools/jasm.bak.rb deleted file mode 100644 index 4c9feb0..0000000 --- a/lib/CPUs/JCpu/tools/jasm.bak.rb +++ /dev/null @@ -1,494 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: A small assembler for the JCPU - -# Copyright (C) 2007 J. Ahrensfeld - -# This library is free software; you can redistribute it and/or -# modify it under the terms of the GNU Lesser General Public -# License as published by the Free Software Foundation; either -# version 2.1 of the License, or (at your option) any later version. - -# This library is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# Lesser General Public License for more details. - -# You should have received a copy of the GNU Lesser General Public -# License along with this library; if not, write to the Free Software -# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - -# For questions and ideas, please contact the author at jens@jayfield.org - -# --------------------------------------------------------------------- - -arg = $* -MAX_SIZE_ROM = 1024 -PROJECT_NAME = arg.to_s.gsub(/\..*/, "") -ENTITY_NAME = "rom" -ENTITY_DATA_TYPE = "inst_t" -ENTITY_ADDR_TYPE = "inst_addr_t" -OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -filename = arg.to_s -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -# -------------------------------------------------------- -# Pass 1 -# -------------------------------------------------------- -lc = 0 # Line counter -pc = 0 # Program counter -chip_dc = [0,0,0,0] # chip data counter -xmem_dc = 0 # xmem data counter -curr_segment = "UNDEF"; -page = 0 - -label_list=[[],[]] -instr_list=[nil] -file = File.open(filename, "r") -file.each do |raw_line| - lc += 1 - - # Make all upper case - iline = "#{raw_line}".strip.upcase - - # Remove comments - iline = iline.gsub(/;.*/, "") - - # Split instruction at spaces - iline_member = iline.split(" ") - - if iline_member[0] == nil - next - end - - mc = 0; - label = nil - clean_line = nil - if (iline_member[0] =~ /\w+:/) - mc += 1 - label = iline_member[0].delete(":") - if label_list.rindex(label) != nil - STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label) - exit 1 - end - end - - case iline_member[mc] - when nil - value = format("0x%3.3X",pc) - when "EQU" - if 0 == (iline_member[mc+1] =~ /\d+/) - value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s)) - else - value = iline_member[mc+1] - end - when "ORG", "CODE" - pc = eval(iline_member[mc+1..iline_member.nitems].to_s) - value = format("0x%3.3X",pc) - when "CDATA", "CMEM" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: CDATA needs argument!", lc) - exit 1 - end - curr_segment = "CMEM"; - page = iline_member[mc+1].to_i(16) - when "XDATA", "XMEM" - curr_segment = "XMEM"; - when "DC" - len = 0; - iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte| - len += 1 - end - if curr_segment == "CMEM" - STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc) - exit 1 - else - value = format("0x%2.2X",xmem_dc) - puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment); - xmem_dc += len - end - when "DB" - len = iline_member[mc+1].to_i - if curr_segment == "CMEM" - value = format("0x%2.2X",chip_dc[page]) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page); - chip_dc[page] += len - else - value = format("0x%2.2X",xmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment); - xmem_dc += len - end - else - op_line = iline_member[mc+1..iline_member.nitems].to_s - value = format("0x%3.3X",pc) - opc = iline_member[mc] - if iline_member[mc+1] != nil - op1 = op_line.gsub(/,+.*$/, "") - end - if iline_member[mc+2] != nil - op2 = op_line.scan(/,.+$/).to_s.delete(", ") - end - if instr_list[pc] == nil - instr_list[pc] = [lc, pc, opc , op1 , op2] - pc += 1 - else - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc) - exit 1 - end - end; - - # Push labels - if label - label_list = label_list + [label, value] - end -end -file.close - -# -------------------------------------------------------- -def instr(opcode) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0) -end - -def tcl_bits(pc, opcode) - return format("%10.10B%6.6B%12.12B",pc, opcode ,0) -end - -def instr_k(opcode, k) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k) -end - -def tcl_bits_k(pc, opcode, k) - return format("%10.10B%6.6B%12.12B",pc, opcode ,k) -end - -def instr_r(opcode, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r) -end - -def tcl_bits_r(pc, opcode, r) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r) -end - -def instr_kr(opcode, k, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_kr(pc, opcode, k, r) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rk(opcode, r, k) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_rk(pc, opcode, r, k) - return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rr(opcode, ra, rb) - return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra) -end - -def tcl_bits_rr(pc, opcode, ra, rb) - return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra) -end - -# -------------------------------------------------------- -# Read mnemonic set -# -------------------------------------------------------- -filename = OPC_LIST_NAME -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -mnemo_list = [] -num_opcodes = 0 -file = File.open(filename, "r") -file.each do |raw_line| - mnemo_list[num_opcodes] = raw_line.split(" ")[1] - num_opcodes += 1 -end - -# -------------------------------------------------------- -# Pass 2 -# -------------------------------------------------------- -pc = 0 -opc_start = 2 -num_errors = 0 -vhdl_trans_list = [nil] -vhdl_comment_list = [nil] -vhdl_tcl_list = [nil] -instr_list.each do |instruct| - - # puts instruct - if instruct == nil - vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0) - vhdl_comment_list[pc] = format("0x%3.3X:", pc) - vhdl_tcl_list[pc] = tcl_bits(pc, 0) - pc += 1 - next - end - - # determine arglen of instruction - ilen = 0 - if instruct[opc_start+1] == nil - arglen = 0 - elsif instruct[opc_start+2] == nil - arglen = 1 - elsif instruct[opc_start+3] == nil - arglen = 2 - end - - # Symbol substitution - error = false - for i in (1..3) - subst_pos = opc_start+i - if instruct[subst_pos] == nil - next - end - expr_token = "" - expr_subst = nil - is_direct = true; - -# instruct[subst_pos] = instruct[subst_pos].delete(" ") - - # checks R0 .. R16, Mnemonics - instr_str = instruct[subst_pos] - if 0 == (instr_str =~ /\(.+\)/) - instr_str = instr_str.delete("()") - is_direct = false; - end - - expr_token = instr_str.split(/\+|\-|\*|\//)[0] - if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/)) - idx = label_list.rindex(expr_token) - if idx != nil - expr_subst = label_list[idx+1] - instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst) - else - STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token) - error = true - end - end - - if expr_subst != nil - if 0 == (expr_subst =~ /\d+/) - if is_direct == true - instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos])) - else - instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos])) - end - else - if 0 != (expr_subst =~ /R[0-9]+/) - STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst) - error = true - end - end - end - end - - # Parse operands - reg = [0,0] - kk = 0 - format = instruct[opc_start] - for i in (0..1) - if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+") - # Check indirect addressing - reg[i] = instruct[opc_start+i+1].delete("R()").to_i - format += "|R" - if reg[i] > 15 - STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i]) - error = true - end - else - if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+") - kk = instruct[opc_start+i+1].delete("()").to_i(16) - format += "|K" - end - end - if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)") - format += "i"; - end - end - - # Output instruction - opcode = mnemo_list.rindex(format).to_i - mnemo = instruct[2]; - - case format - when "NOP", "HALT", "RET", "RETI" - vhdl_trans_list[pc] = instr(opcode) - vhdl_tcl_list[pc] = tcl_bits(pc, opcode) - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - when "MOVC|R|Ri", "MOVX|R|Ri" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1]) - when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1]) - when "MOVC|Ri|R", "MOVX|Ri|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0]) - minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0]) - when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk) - when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R" - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1]) - when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K" - vhdl_trans_list[pc] = instr_k(opcode, kk) - vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk) - minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk) - when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R" - vhdl_trans_list[pc] = instr_r(opcode, reg[0]) - vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0]) - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - when "TST|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("CMP|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "INC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("ADD|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "DEC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - else - STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format) - error = true - end - - if error - num_errors += 1 - break - end - vhdl_comment_list[pc] = minstr_comment - - puts vhdl_trans_list[pc] + " -- " + minstr_comment - - pc += 1 -end - -# -------------------------------------------------------- -# Output ROM file -# -------------------------------------------------------- -if num_errors == 0 - - filename = format("rom_%s.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", ENTITY_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE) - file.puts format("\n") - file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("ROM file written to \"%s\"\n",filename) - file.close -end -if num_errors == 0 - - filename = format("preinit_%s.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - if pc < (MAX_SIZE_ROM-1) - file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n" - for i in (pc..(MAX_SIZE_ROM-2)) - file.puts "\t\t" + instr(0) + ",\n" - end; - file.puts "\t\t" + instr(0) + "\n" - else - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - end - file.puts format("\t);\n") - puts format("PREINIT file written to \"%s\"\n",filename) - file.close -end -if num_errors == 0 - filename = format("rom_%s.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - for i in (0..pc-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("\# %s", vhdl_comment_list[i]) - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2)); - end; - puts format("TCL snippet written to \"%s\"\n",filename) - file.close -end - -# -------------------------------------------------------- -# Output final statistics -# -------------------------------------------------------- -if num_errors == 0 - puts "Program uses #{pc} instruction addresses" - puts "No errors found" - exit 0 -else - puts "#{num_errors} errors found" - exit 1 -end diff --git a/lib/CPUs/JCpu/tools/jasm.rb b/lib/CPUs/JCpu/tools/jasm.rb deleted file mode 100644 index fdad0bb..0000000 --- a/lib/CPUs/JCpu/tools/jasm.rb +++ /dev/null @@ -1,814 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: A small assembler for the JCPU -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -FILE_SUFFIX = "jsm" -IROM_MAX_SIZE = 1024 -IROM_ENTITY_NAME = "irom" -IROM_DATA_TYPE = "inst_t" -IROM_ADDR_TYPE = "inst_addr_t" -XROM_MAX_SIZE = 256 -XROM_DATA_TYPE = "dmem_data_t" -XROM_ADDR_TYPE = "dmem_addr_t" -XROM_ENTITY_NAME = "xrom" -OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list" - -# -------------------------------------------------------- -class Parser - def curr_segment - @curr_segment - end - def curr_segment=(arg) - @curr_segment=arg - end - def add_label(labelname, addr) - @label_list = @label_list + [labelname, addr] - end - def getLabelIdByName(label) - return @label_list.rindex(label) - end - def getLabelNameById(id) - return @label_list[id] - end - def put_instr(name, lc, opc , op1 , op2) - if get_instr != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, @pc) - exit 1 - end - @instr_list[@pc] = [lc, @pc, opc , op1 , op2, name] - end - def get_instr - return @instr_list[@pc] - end - def put_xmem(value, lc) - if get_xmem != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, xmem_dc, curr_segment) - exit 1 - end - @xmem[xmem_dc] = value - @xmem_dc = xmem_dc + 1 - end - def get_xmem - return @xmem[xmem_dc] - end - def xmem - return @xmem - end - def put_cmem(value, lc) - if get_cmem(page) != nil - STDERR.puts format("Error in line %d: Overlapping sections at %3.3X (%s)", lc, cmem_dc, curr_segment) - exit 1 - end - @cmem[page][cmem_dc] = value - @cmem_dc[page] = cmem_dc + 1 - end - def get_cmem(pg) - return @cmem[pg][cmem_dc] - end - def cmem(page) - return @cmem[page] - end - def cmem_dc=(addr) - @cmem_dc[page] = addr - end - def cmem_dc - @cmem_dc[page] - end - def xmem_dc=(addr) - @xmem_dc = addr - end - def xmem_dc - @xmem_dc - end - def page=(page) - @page = page; - end - def page - @page; - end - def pc=(pc) - @pc = pc; - if (pc > @pc_max) - @pc_max = pc - end - end - def pc - @pc; - end - def pc_max - @pc_max; - end - def instr_list - @instr_list - end - def label_list - @label_list - end - - def initialize() - @pc_max = 0 - @pc = 0 # Program counter - @cmem_dc = [0,0,0,0] # chip data counter - @xmem_dc = 0 # xmem data counter - @curr_segment = "UNDEF"; - @page = 0 - @label_list=[[],[]] - @instr_list=[nil] - @cmem = [[],[]]; - @xmem = []; - end - def method_missing(name, *args) - puts "I don't know the method #{name}" - end -end - -# -------------------------------------------------------- -def parse(name, obj) - -lc = 0 # Line counter -file = File.open(name, "r") - -file.each do |raw_line| - lc += 1 - - # Make all upper case - iline = "#{raw_line}".strip - - # Remove comments - iline = iline.gsub(/;.*/, "") - - # Split instruction at spaces - iline_member = iline.split(" ") - - if iline_member[0] == nil - next - end - - mc = 0; - label = nil - clean_line = nil - if (iline_member[0] =~ /\w+:/) - mc += 1 - label = iline_member[0].delete(":") - if obj.getLabelIdByName(label) != nil - STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label) - exit 1 - end - end - - token = iline_member[mc] - if token - token = token.upcase - end - - case token - when nil - if obj.curr_segment == "CMEM" - curr_addr = format("0x%3.3X",obj.cmem_dc) - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%3.3X",obj.xmem_dc) - elsif obj.curr_segment == "CODE" - curr_addr = format("0x%3.3X",obj.pc) - else - STDERR.puts format("Error in line %d: Undefined segment", lc) - exit 1 - end - when "INCLUDE" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - inc_name = iline_member[mc+1].delete("\"") - puts format("Inserting \"%s\" into \"%s\" at line %d", inc_name, name, lc); - parse(inc_name, obj) - when "EQU" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - if 0 == (iline_member[mc+1] =~ /\d+/) - curr_addr = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s)) - else - curr_addr = iline_member[mc+1] - end - when "ORG" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - offset = eval(iline_member[mc+1..iline_member.nitems].to_s) - case obj.curr_segment - when "CODE" - obj.pc = offset - curr_addr = format("0x%3.3X",obj.pc) - when "CMEM" - obj.cmem_dc = offset - when "XMEM" - obj.xmem_dc = offset - - end - when "CODE" - curr_addr = format("0x%3.3X",obj.pc) - obj.curr_segment = "CODE"; - when "CDATA", "CMEM" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - obj.curr_segment = "CMEM"; - obj.page = iline_member[mc+1].to_i(16) - when "XDATA", "XMEM" - obj.curr_segment = "XMEM"; - when "DC" - len = 0; - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - if obj.curr_segment == "CMEM" - STDERR.puts format("Error in line %d: %s cannot be initialized!", lc, obj.curr_segment) - exit 1 - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%2.2X",obj.xmem_dc) - dc_old = obj.xmem_dc; - val_array = raw_line.split(/dc|DC|Dc|dC/)[1].delete("\t").gsub(/;.*/, "").split(",") - - # Parse string literals - val_array.each do |item| - if 0 == (item =~ /.*\".*\"/) - str = item.delete("\"") - puts item - for nn in (0..str.length-1) - if str[nn] > 31 - obj.put_xmem(str[nn], lc); - puts "S: " + str[nn].to_s - len += 1 - end - end; - else - argument = item - puts "B: " + argument - obj.put_xmem(eval(argument), lc); - len += 1 - end - end - puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, dc_old, obj.curr_segment); - else - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - when "DB" - if iline_member[mc+1] == nil - STDERR.puts format("Error in line %d: %s needs argument!", lc, token) - exit 1 - end - len = eval(iline_member[mc+1]).to_i - if obj.curr_segment == "CMEM" - curr_addr = format("0x%2.2X",obj.cmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, obj.cmem_dc, obj.curr_segment, obj.page); - for nn in (1..len) - obj.put_cmem(0, lc) - end - elsif obj.curr_segment == "XMEM" - curr_addr = format("0x%2.2X",obj.xmem_dc) - puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, obj.xmem_dc, obj.curr_segment); - for nn in (1..len) - obj.put_xmem(0, lc) - end - else - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - else - if obj.curr_segment != "CODE" - STDERR.puts format("Error in line %d: Invalid segment %s for \"%s\"", lc, obj.curr_segment, token) - exit 1 - end - - op_line = iline_member[mc+1..iline_member.nitems].to_s - curr_addr = format("0x%3.3X",obj.pc) - opc = token - if iline_member[mc+1] != nil - op1 = op_line.gsub(/,+.*$/, "") - end - if iline_member[mc+2] != nil - op2 = op_line.scan(/,.+$/).to_s.delete(", ") - end - obj.put_instr(name, lc, opc, op1, op2) - obj.pc = obj.pc + 1 - end; - - # Push labels - if label - obj.add_label(label, curr_addr) - end -end -file.close -return obj -end - -# -------------------------------------------------------- -# Instruction formatting -# -------------------------------------------------------- -def instr(opcode) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0) -end - -def tcl_bits(pc, opcode) - return format("%12.12B%8.8B%12.12B",pc, opcode ,0) -end - -def instr_k(opcode, k) - return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k) -end - -def tcl_bits_k(pc, opcode, k) - return format("%12.12B%8.8B%12.12B",pc, opcode ,k) -end - -def instr_r(opcode, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r) -end - -def tcl_bits_r(pc, opcode, r) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode ,0,r) -end - -def instr_kr(opcode, k, r) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_kr(pc, opcode, k, r) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rk(opcode, r, k) - return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r) -end - -def tcl_bits_rk(pc, opcode, r, k) - return format("%12.12B%8.8B%8.8B%4.4B",pc, opcode, k, r) -end - -def instr_rr(opcode, ra, rb) - return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra) -end - -def tcl_bits_rr(pc, opcode, ra, rb) - return format("%12.12B%8.8B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra) -end - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -filename = arg.to_s -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end -PROJECT_NAME = File.basename(filename, "." + FILE_SUFFIX) - -# -------------------------------------------------------- -# Pass 1 -# -------------------------------------------------------- -first_pass = Parser.new(); -parse(filename, first_pass) - -# -------------------------------------------------------- -# Read mnemonic set -# -------------------------------------------------------- -filename = OPC_LIST_NAME -if !File.exists?(filename) - STDERR.puts "#{filename} does not exist" - exit 1 -end - -mnemo_list = [] -num_opcodes = 0 -file = File.open(filename, "r") -file.each do |raw_line| - mnemo_list[num_opcodes] = raw_line.split(" ")[1] - num_opcodes += 1 -end - -# -------------------------------------------------------- -# Pass 2 -# -------------------------------------------------------- -pc = 0 -opc_start = 2 -num_errors = 0 -vhdl_trans_list = [nil] -vhdl_comment_list = [nil] -vhdl_tcl_list = [nil] - -# ToDo: Use class-methods -label_list = first_pass.label_list -instr_list = first_pass.instr_list - -instr_list.each do |instruct| - - # puts instruct - if instruct == nil - vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0) - vhdl_comment_list[pc] = format("0x%3.3X:", pc) - vhdl_tcl_list[pc] = tcl_bits(pc, 0) - pc += 1 - next - end - - # determine arglen of instruction - ilen = 0 - if instruct[opc_start+1] == nil - arglen = 0 - elsif instruct[opc_start+2] == nil - arglen = 1 - elsif instruct[opc_start+3] == nil - arglen = 2 - end - - # Symbol substitution - error = false - for i in (1..2) - subst_pos = opc_start+i - if instruct[subst_pos] == nil - next - end - expr_token = "" - expr_subst = nil - is_direct = true; - - # checks R0 .. R16, Mnemonics - instruct[subst_pos] = instruct[subst_pos].gsub(/'low/, "") - if (nil != (instruct[subst_pos] =~ /'high/)) - instruct[subst_pos]= format("%s/256", instruct[subst_pos].gsub(/'high/, "")) - end - instr_str = instruct[subst_pos] - if 0 == (instr_str =~ /\(.+\)/) - instr_str = instr_str.delete("()") - is_direct = false; - end - - expr_token = instr_str.split(/\+|\-|\*|\/|\||\&/)[0] - if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/)) - idx = label_list.rindex(expr_token) - if idx != nil - expr_subst = label_list[idx+1] - instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst) - else - STDERR.puts format("%s: Error in line %d: Symbol \"%s\" not found", instruct[5], instruct[0], expr_token) - error = true - end - end - - if expr_subst != nil - if 0 == (expr_subst =~ /\d+/) - if is_direct == true - instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos])) - else - instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos])) - end - else - if 0 != (expr_subst =~ /R[0-9]+/) - STDERR.puts format("%s: Error in line %d: Invalid expression \"%s\"", instruct[5], instruct[0], expr_subst) - error = true - end - end - end - end - - # Parse operands - reg = [0,0] - kk = 0 - format = instruct[opc_start] - for i in (0..1) - if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+") - # Check indirect addressing - reg[i] = instruct[opc_start+i+1].delete("R()").to_i - format += "|R" - if reg[i] > 15 - STDERR.puts format("%s: Error in line %d: Invalid register \"R%d\" specified", instruct[5], instruct[0], reg[i]) - error = true - end - else - if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+") - kk = eval(instruct[opc_start+i+1].delete("()")) - format += "|K" - end - end - if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)") - format += "i"; - end - end - - if error - num_errors += 1 - break - end - - # Output instruction - opcode = mnemo_list.rindex(format).to_i - mnemo = instruct[2]; - - case format - # Native instructions - when "NOP", "HALT", "RET", "RETI", "SETC" - vhdl_trans_list[pc] = instr(opcode) - vhdl_tcl_list[pc] = tcl_bits(pc, opcode) - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - when "MOVC|R|Ri", "MOVX|R|Ri" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1]) - when "MOV|R|R", "SUB|R|R", "SUBC|R|R", "ADD|R|R", "ADDC|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1]) - minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1]) - when "MOVC|Ri|R", "MOVX|Ri|R" - vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]); - vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0]) - minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0]) - when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K" - kk = kk % 256; - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk) - when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki" - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk) - when "MOV|R|K", "SUB|R|K", "SUBC|R|K", "ADD|R|K", "ADDC|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K" - kk = kk % 256; - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk) - when "SUB|K|R", "SUBC|K|R" - kk = kk % 256; - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s 0x%2.2d, R%2.2X", pc, mnemo, kk, reg[1]) - when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R" - vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]); - vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1]) - minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1]) - when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K" - vhdl_trans_list[pc] = instr_k(opcode, kk) - vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk) - minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk) - when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R", "SWAP|R" - vhdl_trans_list[pc] = instr_r(opcode, reg[0]) - vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0]) - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - # Synthetic instructions - when "CLRC" - kk = 0; - minstr_comment = format("0x%3.3X: %s", pc, mnemo) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "TST|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("CMP|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "NEG|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|K|R").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "NOT|R" - kk = 0 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("XOR|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "INC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("ADD|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - when "DEC|R" - kk = 1 - minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0]) - opcode = mnemo_list.rindex("SUB|R|K").to_i - vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk); - vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk) - else - STDERR.puts format("%s: Error in line %d: Not yet implemented %s", instruct[5], instruct[0], format) - error = true - end - - if error - num_errors += 1 - break - end - - vhdl_comment_list[pc] = minstr_comment - - puts vhdl_trans_list[pc] + " -- " + minstr_comment - - pc += 1 -end - -# -------------------------------------------------------- -# Output ROM file -# -------------------------------------------------------- -if num_errors == 0 - - # I-ROM VHDL-ROM - filename = format("%s.irom.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", IROM_ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", IROM_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", IROM_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", IROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, IROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", [IROM_MAX_SIZE, pc].min-1 , IROM_DATA_TYPE) - file.puts format("\n") - file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\tconstant imem_rom : imem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..[IROM_MAX_SIZE, pc].min-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= imem_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("I-ROM file written to \"%s\"\n",filename) - file.close - - # I-ROM VHDL-ROM (loadable) - filename = format("%s.irom_ld.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\ttype imem_rom_t is array (0 to %d) of %s;\n", IROM_MAX_SIZE-1, IROM_DATA_TYPE) - file.puts format("\tsignal imem_rom : imem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..pc-2) - file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n" - end; - if pc < (IROM_MAX_SIZE-1) - file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n" - for i in (pc..(IROM_MAX_SIZE-2)) - file.puts "\t\t" + instr(0) + ",\n" - end; - file.puts "\t\t" + instr(0) + "\n" - else - file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n" - end - file.puts format("\t);\n") - puts format("I-ROM (loadable) file written to \"%s\"\n",filename) - file.close - - # I-ROM TCL-Loader - filename = format("%s.irom.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("# ---------------------------------------------------------------"); - file.puts format("# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA"); - file.puts format("# User 1") - file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n") - for i in (0..pc-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("\# %s", vhdl_comment_list[i]) - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2)); - end; - puts format("I-ROM TCL-loader written to \"%s\"\n",filename) - file.close - - # X-ROM VHDL-ROM - filename = format("%s.xrom.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("ENTITY %s IS\n", XROM_ENTITY_NAME) - file.puts format("\tPort (\n") - file.puts format("\tclk\t\t\t: in STD_LOGIC;\n") - file.puts format("\tce\t\t\t: in STD_LOGIC;\n") - file.puts format("\taddr\t\t: in %s;\n", XROM_ADDR_TYPE) - file.puts format("\tdout\t\t: out %s\n", XROM_DATA_TYPE) - file.puts format("\t);\n") - file.puts format("END %s;\n", XROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, XROM_ENTITY_NAME) - file.puts format("\n") - file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE) - file.puts format("\n") - file.puts format("\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\tconstant xmem_rom : xmem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..XROM_MAX_SIZE-2) - file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i) - end; - i = XROM_MAX_SIZE-1 - file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i) - file.puts format("\t);\n") - file.puts format("\n") - file.puts format("begin") - file.puts format("\n") - file.puts format("PROM_READ:") - file.puts format("\tprocess(clk, ce)\n") - file.puts format("\tbegin\n") - file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n") - file.puts format("\t\t\tdout <= xmem_rom(to_integer(addr));\n") - file.puts format("\t\tend if;\n") - file.puts format("\tend process;\n") - file.puts format("\n") - file.puts format("end %s;\n", PROJECT_NAME) - puts format("X-ROM file written to \"%s\"\n",filename) - file.close - - # X-ROM VHDL-ROM (loadable) - filename = format("%s.xrom_ld.vhdl.snip", PROJECT_NAME) - file = File.open(filename, "w") - - file.puts format("\n\t-- Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("\ttype xmem_rom_t is array (0 to %d) of %s;\n", XROM_MAX_SIZE-1, XROM_DATA_TYPE) - file.puts format("\tsignal xmem_rom : xmem_rom_t :=\n") - file.puts format("\t(\n"); - for i in (0..XROM_MAX_SIZE-2) - file.puts format("\t\tX\"%2.2X\", -- 0x%2.2X\n", first_pass.xmem[i], i) - end; - i = XROM_MAX_SIZE-1 - file.puts format("\t\tX\"%2.2X\" -- 0x%2.2X\n", first_pass.xmem[i], i) - file.puts format("\t);\n") - puts format("X-ROM (loadable) file written to \"%s\"\n",filename) - file.close - - # X-ROM TCL-Loader - filename = format("%s.xrom.tcl.snip", PROJECT_NAME) - file = File.open(filename, "w") - file.puts format("# Assembled from %s.%s", PROJECT_NAME, FILE_SUFFIX) - file.puts format("# ---------------------------------------------------------------"); - file.puts format("# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA"); - file.puts format("# User 2") - file.puts format("set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n") - for i in (0..first_pass.xmem.length-1) - # Chipscope 8.1 -# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse); - - # Chipscope 9.1 - file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%2.2X%2.2X\"\n", 16, i, first_pass.xmem[i]); - end; - puts format("X-ROM TCL-loader written to \"%s\"\n",filename) - file.close - -end - -# -------------------------------------------------------- -# Output final statistics -# -------------------------------------------------------- -if num_errors == 0 - puts "Program uses #{first_pass.pc_max} instruction addresses" - puts "No errors found" - exit 0 -else - puts "#{num_errors} errors found" - exit 1 -end - diff --git a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm b/lib/CPUs/JCpu/tools/lib/cg.inc.jsm deleted file mode 100644 index 01c36c4..0000000 --- a/lib/CPUs/JCpu/tools/lib/cg.inc.jsm +++ /dev/null @@ -1,72 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xio-address equates for -; reg_cg_char_addr: equ 0xXX ; RW -; reg_cg_line_addr: equ 0xXX ; RW -; reg_cg_data: equ 0xXX ; RW -; reg_cg_ctrl: equ 0xXX ; WO - -; needs delay.inc.jsm - -; ------------------------------------------------- -cg_clr_line: push R0 - mov R0, 2 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -cg_clr_screen: push R0 - mov R0, 1 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -; R0 : char address -; R1 : line address -cg_set_addr: call cg_wait_rdy - xout (reg_cg_line_addr), R1 - xout (reg_cg_char_addr), R0 - ret - -; ------------------------------------------------- -; R0 : character -cg_putchar: call cg_wait_rdy - xout (reg_cg_data), R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts: push R0 -cg_p_lp: movx R0, (R1) - inc R1 - tst R0 - jz ex_cgp - call cg_putchar - jmp cg_p_lp -ex_cgp: pop R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_clr_puts: call cg_clr_line - call cg_puts - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts_clr: call cg_puts - call cg_clr_line - ret - -; ------------------------------------------------- -cg_wait_rdy: push R0 -cg_wr_lp: xin R0, (reg_hwstat) - and R0, 0x02 - jz cg_wr_lp - pop R0 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm b/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm deleted file mode 100644 index 06d39d9..0000000 --- a/lib/CPUs/JCpu/tools/lib/cregs.inc.jsm +++ /dev/null @@ -1,7 +0,0 @@ -; JCPU On-Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; RW -cpu_cmem_high: equ 0x04 ; RW -cpu_stack_high: equ 0x05 ; RW diff --git a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm b/lib/CPUs/JCpu/tools/lib/delays.inc.jsm deleted file mode 100644 index 6f002ee..0000000 --- a/lib/CPUs/JCpu/tools/lib/delays.inc.jsm +++ /dev/null @@ -1,64 +0,0 @@ -; ------------------------------------------------- -; Delays -; ------------------------------------------------- -delay1s: push R15 - mov R15, 10 -loop1s: call delay100ms - dec R15 - jnz loop1s - pop R15 - ret - -delay100ms: push R15 - mov R15, 10 -loop100ms: call delay10ms - dec R15 - jnz loop100ms - pop R15 - ret - -delay10ms: push R15 - mov R15, 10 -loop10ms: call delay1ms - dec R15 - jnz loop10ms - pop R15 - ret - -delay1ms: push R15 - mov R15, 10 -loop1ms: call delay100us - dec R15 - jnz loop1ms - pop R15 - ret - -delay100us: push R15 - mov R15, 10 -loop100us: call delay10us - dec R15 - jnz loop100us - pop R15 - ret - -delay10us: push R15 - mov R15, 99 -loop10us: nop - nop - nop - dec R15 - jnz loop10us - pop R15 - ret - -delay1us: push R15 - mov R15, 9 -loop1us: nop - nop - nop - dec R15 - jnz loop1us - pop R15 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm b/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm deleted file mode 100644 index d2883fa..0000000 --- a/lib/CPUs/JCpu/tools/lib/lcd.inc.jsm +++ /dev/null @@ -1,208 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - lcd_port (LCD-Base) - -; needs delay.inc.jsm - -; ------------------------------------------------- -lcd_cmd: equ 0x00 -lcd_rd: equ 0x20 -lcd_data: equ 0x40 -lcd_enable: equ 0x80 - -LCD_CMD_Z1: equ 0x80 -LCD_CMD_Z2: equ 0xC0 -LCD_CMD_CLEAR: equ 0x01 - -; ------------------------------------------------- -; Init LCD -; ------------------------------------------------- -LCD_init: mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - - mov R2, 0x00 - mov R0, 0x02 - call _write_lcd - call delay1ms - - ; 1. Function set: 4-Bit mode, two display lines - mov R0, 0x28 - call LCD_writecmd - - ; 2. Display on, no cursor - mov R0, 0x0C - call LCD_writecmd - - ; 3. Cursor shift during write - mov R0, 0x06 - call LCD_writecmd - - ; 4. Display clear - mov R0, 0x01 - call LCD_writecmd - - ret - -; ------------------------------------------------- -; LCD_waitbsy -; ------------------------------------------------- -LCD_waitbsy: push R0 -bsy_loop: call LCD_readstat - and R0, 0x80 - jz ex_bsy - call delay1us - jmp bsy_loop -ex_bsy: pop R0 - ret - -; ------------------------------------------------- -; LCD_writecmd -; ------------------------------------------------- -; R0 = cmd -LCD_writeaddr: -LCD_writecmd: push R2 - mov R2, lcd_cmd - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_putsx -; ------------------------------------------------- -; R1 = address of null-terminated string in XMEM -LCD_putsx: push R0 -putsx_loop: movx R0, (R1) - inc R1 - tst R0 - jz putsx_ex - call LCD_writechar - jmp putsx_loop -putsx_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_putsc -; ------------------------------------------------- -; R1 = address of null-terminated string in CMEM -LCD_putsc: push R0 -putsc_loop: movc R0, (R1) - inc R1 - tst R0 - jz putsc_ex - call LCD_writechar - jmp putsc_loop -putsc_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_writechar -; ------------------------------------------------- -; R0 = char -LCD_writedata: -LCD_writechar: push R2 - mov R2, lcd_data - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_write -; ------------------------------------------------- -; R0 = input -; R2 = register -LCD_write: call LCD_waitbsy - push R0 - swap R0 - call _write_lcd - pop R0 - call _write_lcd - ret - -; ------------------------------------------------- -; LCD_readstat -; ------------------------------------------------- -; R0 = status -LCD_readstat: push R2 - mov R2, lcd_cmd - call LCD_read - pop R2 - ret - -; ------------------------------------------------- -; LCD_read -; ------------------------------------------------- -; R0 = output -; R2 = register -LCD_read: call _read_lcd - swap R0 - push R0 - call _read_lcd - pop R2 - or R0, R2 - ret - -; ------------------------------------------------- -; _write -; ------------------------------------------------- -; R0 = input -_write_lcd: push R1 - - and R0, 0x0F - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - or R1, lcd_rd - xout (lcd_port), R1 - - pop R1 - ret - -; ------------------------------------------------- -; _read -; ------------------------------------------------- -; R0 = output -_read_lcd: push R1 - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, lcd_rd - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - xin R0, (lcd_port) - and R0, 0x0F - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - pop R1 - ret - - \ No newline at end of file diff --git a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm b/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm deleted file mode 100644 index 2f66e2a..0000000 --- a/lib/CPUs/JCpu/tools/lib/mul8x8.inc.jsm +++ /dev/null @@ -1,42 +0,0 @@ -; ------------------------------------------------- -; mul8x8.inc.jsm -; ------------------------------------------------- - -; ------------------------------------------------- -; Parameter: -; R0 : operand 1 -; R1 : operand 2 -; Return: -; R0 : product low -; R1 : product high -mul8x8: push R2 - push R3 - push R4 - - mov R4, R1 - mov R1, 0 - mov R2, 0 - mov R3, 0 - -loop1: cmp R4, 0x01 - jeq ende1 - - shr R4 - jnc next1 - - add R2, R0 - addc R3, R1 - -next1: shl R0 - rolc R1 - jmp loop1 - -ende1: add R0, R2 - addc R1, R3 - - pop R4 - pop R3 - pop R2 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm b/lib/CPUs/JCpu/tools/lib/uart.inc.jsm deleted file mode 100644 index 1733305..0000000 --- a/lib/CPUs/JCpu/tools/lib/uart.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; uart.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - uart_status (Status register) -; - uart_data (Data register) - -; ------------------------------------------------- -; sout -; ------------------------------------------------- -; R0 = input -sout: push R1 -sout1: xin R1, (uart_status) - and R1, 0x02 - jnz sout1 - xout (uart_data), R0 - pop R1 - ret - -; ------------------------------------------------- -; sin -; ------------------------------------------------- -; R0 = output -sin: push R1 -sin1: xin R1, (uart_status) - and R1, 0x10 - jnz sin1 - xin R0, (uart_data) - pop R1 - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm b/lib/CPUs/JCpu/tools/lib/utils.inc.jsm deleted file mode 100644 index f354d7c..0000000 --- a/lib/CPUs/JCpu/tools/lib/utils.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; utils.inc.jsm -; ------------------------------------------------- - - -; ------------------------------------------------- -; Parameter -; R0 : Bin value in lower nibble -; Return -; R0 : Hex character representing lower nibble -nibble2hex: and R0, 0x0F - cmp R0, 0x0A - jlt isNum1 - add R0, 0x07 -isNum1: add R0, 0x30 - ret - -; ------------------------------------------------- -; Parameter -; R0 : Bin value -; Return -; R0 : Hex character high -; R1 : Hex character low -bin2hex: push R0 - call nibble2hex - mov R1, R0 - pop R0 - swap R0 - call nibble2hex - ret - -; ------------------------------------------------- diff --git a/lib/CPUs/JCpu/tools/opc.list b/lib/CPUs/JCpu/tools/opc.list deleted file mode 100644 index 59b3cfa..0000000 --- a/lib/CPUs/JCpu/tools/opc.list +++ /dev/null @@ -1,64 +0,0 @@ -0 NOP -1 HALT -2 MOV|R|R -3 MOV|R|K -4 MOVX|R|Ri -5 MOVX|R|Ki -6 MOVX|Ri|R -7 MOVX|Ri|K -8 MOVX|Ki|R -9 MOVC|R|Ri -10 MOVC|R|Ki -11 MOVC|Ri|R -12 MOVC|Ri|K -13 MOVC|Ki|R -14 CMP|R|R -15 CMP|R|K -16 ADD|R|R -17 ADD|R|K -18 ADDC|R|R -19 ADDC|R|K -20 SUB|R|R -21 SUB|R|K -22 SUBC|R|R -23 SUBC|R|K -24 AND|R|R -25 AND|R|K -26 OR|R|R -27 OR|R|K -28 XOR|R|R -29 XOR|R|K -30 SHL|R -31 SHR|R -32 ROL|R -33 ROR|R -34 ROLC|R -35 RORC|R -36 XOUT|Ki|R -37 XOUT|Ri|K -38 COUT|Ki|R -39 COUT|Ri|K -40 XIN|R|Ki -41 CIN|R|Ki -42 SWAP|R -43 SETC -44 UNDEF -45 UNDEF -46 SUB|K|R -47 SUBC|K|R -48 JMP|K -49 JZ|K -50 JNZ|K -51 JC|K -52 JNC|K -53 JLT|K -54 JGT|K -55 JLE|K -56 JGE|K -57 JEQ|K -58 JNE|K -59 CALL|K -60 PUSH|R -61 POP|R -62 RET -63 RETI diff --git a/lib/CPUs/JCpu/tools/regx.rb b/lib/CPUs/JCpu/tools/regx.rb deleted file mode 100644 index 47775c9..0000000 --- a/lib/CPUs/JCpu/tools/regx.rb +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env ruby - -st = "\033[7m" -en = "\033[m" - - while TRUE - print "str> " - STDOUT.flush - str = gets - break if not str - str.chop! - print "pat> " - STDOUT.flush - re = gets - break if not re - re.chop! - str.gsub! re, "#{st}\\&#{en}" - print str, "\n" -end -print "\n" diff --git a/lib/CPUs/JCpu/tools/rom.tcl.tpl b/lib/CPUs/JCpu/tools/rom.tcl.tpl deleted file mode 100644 index 9f5c0dc..0000000 --- a/lib/CPUs/JCpu/tools/rom.tcl.tpl +++ /dev/null @@ -1,61 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/JCpu/tools/templates.rb b/lib/CPUs/JCpu/tools/templates.rb deleted file mode 100644 index 632f11c..0000000 --- a/lib/CPUs/JCpu/tools/templates.rb +++ /dev/null @@ -1,44 +0,0 @@ -#!/usr/bin/env ruby - - -template = <<'END' - -- (tv #1342) read output FIFO - ( - cycles => 1, - cm_i => bus_read_init(addr => ADDR_KS_OFIFO_DOUT), - sep => msg(""), - cm_o => bus_no_ack, - irq => (others => '0') - ), - - -- (tv #1343) wait while FIFO is read - ( - cycles => 2, - cm_i => bus_wait_ack, - sep => msg(""), - cm_o => bus_no_ack, - irq => (others => '0') - ), - - -- (tv #1343) wait for ack - ( - cycles => 1, - cm_i => bus_wait_ack, - sep => msg(""), - cm_o => bus_read_ack(dat => #{exp_data}), - irq => (others => '0') - ), - -END - -puts "KS-128 testvectors:\n" -puts "\n" * 3 - - -0.upto(10) { |sk_no| - 3.downto(0) { |sl_no| - exp_data = "slice_32(TC1_SUBKEYS(#{sk_no}), #{sl_no})" - t = template.gsub(/"/, '\\"') - puts eval("format(\"#{t}\")") - } -} diff --git a/lib/CPUs/JCpu/tools/xrom.vhd.tpl b/lib/CPUs/JCpu/tools/xrom.vhd.tpl deleted file mode 100644 index 5f11f86..0000000 --- a/lib/CPUs/JCpu/tools/xrom.vhd.tpl +++ /dev/null @@ -1,32 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.cpu_pkg.all; - --- JASM_ROM_INSERT_HERE - diff --git a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl b/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl deleted file mode 100644 index 696487f..0000000 --- a/lib/CPUs/JCpu/tools/xrom_ld.vhd.tpl +++ /dev/null @@ -1,151 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -library work; -use work.cpu_pkg.all; - -ENTITY xrom IS - Port ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in dmem_addr_t; - dout : out dmem_data_t - ); - -END xrom; - -ARCHITECTURE loadable OF xrom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : dmem_addr_t; - signal jtag_ld_dout : dmem_data_t; - signal jtag_ld_din : dmem_data_t; - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (15 downto 0); - constant id : unsigned (15 downto 0) := X"BEEF"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto user_regi'left-dmem_data_t'length+1); - jtag_ld_din <= user_regi(dmem_data_t'left downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto dmem_data_t'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk, ce) - begin - if rising_edge(clk) and ce = '1' then - dout <= xmem_rom(to_integer(addr)); - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - xmem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= xmem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/MIPS/sim/compile_simprim.do b/lib/CPUs/MIPS/sim/compile_simprim.do deleted file mode 100644 index 16b23bb..0000000 --- a/lib/CPUs/MIPS/sim/compile_simprim.do +++ /dev/null @@ -1,6 +0,0 @@ -vlib simprim - -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd diff --git a/lib/CPUs/MIPS/sim/compile_unisim.do b/lib/CPUs/MIPS/sim/compile_unisim.do deleted file mode 100644 index d35d8c9..0000000 --- a/lib/CPUs/MIPS/sim/compile_unisim.do +++ /dev/null @@ -1,6 +0,0 @@ -vlib unisim - -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd diff --git a/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo b/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo deleted file mode 100644 index 3b3c920..0000000 --- a/lib/CPUs/MIPS/sim/tb_eval_muldiv.fdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/tb_eval_muldiv.vhd" -vsim -t 1ps -lib work tb_eval_muldiv -do {tb_eval_muldiv.wdo} -view wave - -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo b/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo deleted file mode 100644 index e742ca4..0000000 --- a/lib/CPUs/MIPS/sim/tb_eval_muldiv.wdo +++ /dev/null @@ -1,27 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_eval_muldiv/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op1_in -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/op2_in -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp0 -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp1 -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp2 -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/pp3 -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result -add wave -noupdate -format Literal -radix hexadecimal /tb_eval_muldiv/result_reg -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {693234 ps} 0} {{Cursor 2} {290409 ps} 0} -configure wave -namecolwidth 149 -configure wave -valuecolwidth 171 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {2520 ns} diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo b/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo deleted file mode 100644 index 49ea3ab..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_idecode_rom.vhd" -vcom -explicit -93 "../src/core/mips_reg.vhd" -vcom -explicit -93 "../src/core/mips_shifter.vhd" -vcom -explicit -93 "../src/core/mips_alu.vhd" -vcom -explicit -93 "../src/core/mips_bcu.vhd" -vcom -explicit -93 "../src/core/mips_pipeline.vhd" -vcom -explicit -93 "../src/core/mips_top.vhd" -vcom -explicit -93 "../src/ram.vhd" -vcom -explicit -93 "../asm/fibonacci.vhd" -vcom -explicit -93 "../src/mips_embedded.vhd" -vcom -explicit -93 "../src/tb_mips_embedded.vhd" -vsim -t 1ps -lib work tb_mips_embedded -do {tb_mips_embedded.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo b/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo deleted file mode 100644 index 7115717..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded.wdo +++ /dev/null @@ -1,41 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_embedded/rst -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Logic /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/exception -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/pc -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_ram/sram -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/dmem_dout -add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_re -add wave -noupdate -format Logic -radix hexadecimal /tb_mips_embedded/uut/dmem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/imem_din -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/wb_stage -add wave -noupdate -format Logic /tb_mips_embedded/clk -add wave -noupdate -format Literal /tb_mips_embedded/uut/inst_mips_top/inst_pipeline/hdu -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {624000 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {2520 ns} diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo deleted file mode 100644 index 97872a0..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.fdo +++ /dev/null @@ -1,31 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_idecode_rom.vhd" -vcom -explicit -93 "../src/core/mips_reg.vhd" -vcom -explicit -93 "../src/core/mips_shifter.vhd" -vcom -explicit -93 "../src/core/mips_alu.vhd" -vcom -explicit -93 "../src/core/mips_bcu.vhd" -vcom -explicit -93 "../src/core/mips_pipeline.vhd" -vcom -explicit -93 "../src/core/mips_muldiv.vhd" -vcom -explicit -93 "../src/core/mips_cop.vhd" -vcom -explicit -93 "../src/core/mips_bui.vhd" -vcom -explicit -93 "../src/core/mips_top.vhd" -vcom -explicit -93 "../src/core/dcache.vhd" -vcom -explicit -93 "../asm/testbench.ROM.vhd" -vcom -explicit -93 "../src/mips_embedded.vhd" -vcom -explicit -93 "../src/mips_embedded_syn.vhd" -vcom -explicit -93 "../../../uart/bbfifo_16x8.vhd" -vcom -explicit -93 "../../../uart/kcuart_rx.vhd" -vcom -explicit -93 "../../../uart/kcuart_tx.vhd" -vcom -explicit -93 "../../../uart/uart_rx.vhd" -vcom -explicit -93 "../../../uart/uart_tx.vhd" -vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd" -vsim -t 1ps -lib work tb_mips_embedded_syn -do {tb_mips_embedded_syn.wdo} -view wave -view structure -view signals -run 100us diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo deleted file mode 100644 index f9e8902..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.tdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work - -vcom -explicit -93 "../syn/ise9/netgen/par/mips_embedded_syn_timesim.vhd" -vcom -explicit -93 "../src/tb_mips_embedded_syn.vhd" -vsim -t 1ps -sdfmax "/uut=../syn/ise9/netgen/par/mips_embedded_syn_timesim.sdf" -lib work tb_mips_embedded_syn -do {tb_mips_embedded_syn.wdo} -view wave -#add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo deleted file mode 100644 index 9b1276c..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_embedded_syn.wdo +++ /dev/null @@ -1,112 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_rx -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/sys_tx -add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_rst_n_in -add wave -noupdate -format Logic /tb_mips_embedded_syn/sys_clk_in -add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_led -add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_dip -add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_btn -add wave -noupdate -format Literal /tb_mips_embedded_syn/sys_error -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_rst -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/cpu_run -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_rx -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_tx -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/reg_uart_baud -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/uart_status_port -add wave -noupdate -format Literal -radix decimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_usec_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/cnt_sec -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_rdy -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_en -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_re -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/mem_dout -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_bui/s -add wave -noupdate -divider DMEM -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_dout -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_en -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/dmem_we -add wave -noupdate -divider IMEM -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/imem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_din -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/imem_en -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc_run -add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/pc -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/hdu -add wave -noupdate -divider Stages -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/halt -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_reg_dual_a/reg_mem -add wave -noupdate -divider Cop -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ir_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_id -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_pipe_ex -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cop_ex_en -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_in -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ctrl_out -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_entered -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/epc -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/cause -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/test_reg -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/stat_reg_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/events -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/eflags -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/badvaddr -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/rst -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exception -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_save -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/status_rest -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/exc_strobe -add wave -noupdate -format Literal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_cop/ip -add wave -noupdate -divider Stages -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/dmem_dout -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/wb_stage -add wave -noupdate -divider Muldiv -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/result -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/start -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/busy -add wave -noupdate -format Logic /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/hilo_sel -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_embedded_syn/uut/inst_mips_embedded/inst_mips_top/inst_pipeline/inst_muldiv/din_lo -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1121030000 ps} 0} {{Cursor 2} {1436367 ps} 0} {{Cursor 3} {1122030000 ps} 0} -configure wave -namecolwidth 179 -configure wave -valuecolwidth 89 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {1351336 ps} {1583596 ps} diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo deleted file mode 100644 index b272e38..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_muldiv.vhd" -vcom -explicit -93 "../src/tb_mips_muldiv.vhd" -vsim -t 1ps -lib work tb_mips_muldiv -do {tb_mips_muldiv.wdo} -view wave - -view structure -view signals -run 5000us diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo deleted file mode 100644 index 70cb8bb..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.ndo +++ /dev/null @@ -1,19 +0,0 @@ -## NOTE: Do not edit this file. -## Auto generated by Project Navigator for Post-Translate Simulation -## -vlib work -## Compile Post-Translate Model -vcom -explicit -93 "../syn/eval_muldiv/netgen/translate/muldiv_translate.vhd" -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/tb_mips_muldiv.vhd" - -vsim -t 1ps -lib work tb_mips_muldiv -#do {tb_mips_muldiv.udo} -view wave -add wave * -view structure -view signals -run 1000ns -## End diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo deleted file mode 100644 index 9546784..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.sdo +++ /dev/null @@ -1,19 +0,0 @@ -## NOTE: Do not edit this file. -## Auto generated by Project Navigator for Post-Translate Simulation -## -vlib work -## Compile Post-Translate Model -vcom -explicit -93 "../syn/eval_muldiv/netgen/synthesis/muldiv_synthesis.vhd" -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/tb_mips_muldiv.vhd" - -vsim -t 1ps -lib work tb_mips_muldiv -do {tb_mips_muldiv.wdo} -view wave -#add wave * -view structure -view signals -run 1000ns -## End diff --git a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo b/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo deleted file mode 100644 index 2fc4121..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_muldiv.wdo +++ /dev/null @@ -1,79 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_muldiv/rst -add wave -noupdate -format Logic /tb_mips_muldiv/clk -add wave -noupdate -format Logic /tb_mips_muldiv/mul_divn -add wave -noupdate -format Logic /tb_mips_muldiv/start -add wave -noupdate -format Logic /tb_mips_muldiv/busy -add wave -noupdate -format Logic /tb_mips_muldiv/s_un -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo -add wave -noupdate -format Logic /tb_mips_muldiv/hilo_sel -add wave -noupdate -format Logic /tb_mips_muldiv/hilo_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/result -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_result -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/ref_lo -add wave -noupdate -format Logic /tb_mips_muldiv/uut/pre_sum_vld -add wave -noupdate -format Logic /tb_mips_muldiv/uut/mul_en -add wave -noupdate -format Logic /tb_mips_muldiv/uut/sum_en -add wave -noupdate -divider FSM -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt -add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset -add wave -noupdate -format Literal /tb_mips_muldiv/uut/s -add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn -add wave -noupdate -divider {Multiplier internals} -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_muldiv/uut/pprod -add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyi -add wave -noupdate -format Literal /tb_mips_muldiv/uut/ppadd_cyo -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/ppadd_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_op2_r -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/add_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/pp_reg -add wave -noupdate -divider {Divider internals} -add wave -noupdate -format Logic /tb_mips_muldiv/busy -add wave -noupdate -format Logic /tb_mips_muldiv/s_un -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_start -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_hi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/din_lo -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/result -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_add_cyi -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op1 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_op2 -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_add_res -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_m_n -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_a -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_muldiv/uut/div_q -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_qbit -add wave -noupdate -format Logic /tb_mips_muldiv/uut/div_en -add wave -noupdate -divider FSM -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt -add wave -noupdate -format Logic /tb_mips_muldiv/uut/cycle_cnt_load -add wave -noupdate -format Literal /tb_mips_muldiv/uut/cycle_cnt_preset -add wave -noupdate -format Literal /tb_mips_muldiv/uut/s -add wave -noupdate -format Literal /tb_mips_muldiv/uut/sn -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {4999822285 ps} 0} {{Cursor 2} {1278050000 ps} 0} -configure wave -namecolwidth 149 -configure wave -valuecolwidth 171 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {5250 us} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.fdo b/lib/CPUs/MIPS/sim/tb_mips_top.fdo deleted file mode 100644 index 811b0b8..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.fdo +++ /dev/null @@ -1,22 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/core/mips_idecode_rom.vhd" -vcom -explicit -93 "../src/core/mips_reg.vhd" -vcom -explicit -93 "../src/core/mips_shifter.vhd" -vcom -explicit -93 "../src/core/mips_alu.vhd" -vcom -explicit -93 "../src/core/mips_bcu.vhd" -vcom -explicit -93 "../src/core/mips_pipeline.vhd" -vcom -explicit -93 "../src/core/mips_top.vhd" -vcom -explicit -93 "../asm/fibonacci.vhd" -vcom -explicit -93 "../src/ram.vhd" -vcom -explicit -93 "../src/tb_mips_top.vhd" -vsim -t 1ps -lib work tb_mips_top -do {tb_mips_top.wdo} -view wave -view structure -view signals -run 40000ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.mdo b/lib/CPUs/MIPS/sim/tb_mips_top.mdo deleted file mode 100644 index 1ba3832..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.mdo +++ /dev/null @@ -1,18 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -## Compile Post-Map Model -vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_map.vhd" -vsim -t 1ps -sdfmax "/mips_top=../syn/ise9/netgen/map/mips_top_map.sdf" -lib work mips_top -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/irom_hello.vhd" -vcom -explicit -93 "../src/tb_mips_top.vhd" -vsim -t 1ps -lib work tb_mips_top -do {tb_mips_top.mwdo} -view wave -#add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.mwdo b/lib/CPUs/MIPS/sim/tb_mips_top.mwdo deleted file mode 100644 index b24adae..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.mwdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr -add wave -noupdate -format Logic /tb_mips_top/dmem_we -add wave -noupdate -format Logic /tb_mips_top/dmem_re -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/sram -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_op2 -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline_ex_stage_alu_result -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {77481 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {729730 ps} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.sdo b/lib/CPUs/MIPS/sim/tb_mips_top.sdo deleted file mode 100644 index 25435ef..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.sdo +++ /dev/null @@ -1,16 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../syn/ise9/netgen/synthesis/mips_top_synthesis.vhd" -vcom -explicit -93 "../../../PCK_FIO-1.16/PCK_FIO.vhd" -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/irom_hello.vhd" -vcom -explicit -93 "../src/tb_mips_top.vhd" -vsim -t 1ps -lib work tb_mips_top -#do {tb_mips_top.wdo} -view wave -add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top.wdo b/lib/CPUs/MIPS/sim/tb_mips_top.wdo deleted file mode 100644 index 833e5af..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top.wdo +++ /dev/null @@ -1,51 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_top/rst -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/cpu_halt -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_dout -add wave -noupdate -format Logic /tb_mips_top/dmem_re -add wave -noupdate -format Logic /tb_mips_top/dmem_we -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/inst_ram/sram -add wave -noupdate -divider ALU -add wave -noupdate -format Literal /tb_mips_top/uut/inst_pipeline/hdu -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -divider PC -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/pc -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/exception -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Logic /tb_mips_top/uut/inst_pipeline/stall -add wave -noupdate -divider PC -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/uut/inst_pipeline/if_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/id_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/ex_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/mem_stage -add wave -noupdate -format Logic /tb_mips_top/clk -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top/dmem_din -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top/uut/inst_pipeline/wb_stage -add wave -noupdate -format Logic /tb_mips_top/clk -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {0 ps} 0} -configure wave -namecolwidth 188 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {42 us} diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo deleted file mode 100644 index 91b4dc0..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.mdo +++ /dev/null @@ -1,17 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -## Compile Post-Map Model -vcom -explicit -93 "../syn/ise9/netgen/map/mips_top_syn_map.vhd" -vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/map/mips_top_syn_map.sdf" -lib work mips_top_syn -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/irom_hello.vhd" -vcom -explicit -93 "../src/tb_mips_top_syn.vhd" -vsim -t 1ps -lib work tb_mips_top_syn -do {tb_mips_top_syn.wdo} -view wave -#add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo deleted file mode 100644 index cc7c65d..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.tdo +++ /dev/null @@ -1,17 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -## Compile Post-Map Model -vcom -explicit -93 "../syn/ise9/netgen/par/mips_top_syn_timesim.vhd" -vsim -t 1ps -sdfmax "/mips_top_syn=../syn/ise9/netgen/par/mips_top_syn_timesim.sdf" -lib work mips_top_syn -vcom -explicit -93 "../src/core/mips_types.vhd" -vcom -explicit -93 "../src/core/mips_instr.vhd" -vcom -explicit -93 "../src/irom_hello.vhd" -vcom -explicit -93 "../src/tb_mips_top_syn.vhd" -vsim -t 1ps -lib work tb_mips_top_syn -do {tb_mips_top_syn.wdo} -view wave -#add wave * -view structure -view signals -run 2400ns diff --git a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo b/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo deleted file mode 100644 index eafadd7..0000000 --- a/lib/CPUs/MIPS/sim/tb_mips_top_syn.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mips_top_syn/rst -add wave -noupdate -format Logic /tb_mips_top_syn/clk -add wave -noupdate -format Logic /tb_mips_top_syn/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_data -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/irom_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_din -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_dout -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/dmem_addr -add wave -noupdate -format Logic /tb_mips_top_syn/dmem_we -add wave -noupdate -format Logic /tb_mips_top_syn/dmem_re -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_id_stage_boff -add wave -noupdate -format Literal -radix hexadecimal /tb_mips_top_syn/uut/inst_mips_top_inst_pipeline_stage_ex_inst_alu_sum_res -add wave -noupdate -format Literal -radix hexadecimal -expand /tb_mips_top_syn/sram -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {118199 ps} 0} -configure wave -namecolwidth 188 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {2520 ns} diff --git a/lib/CPUs/MIPS/src/core/dcache.vhd b/lib/CPUs/MIPS/src/core/dcache.vhd deleted file mode 100644 index 367c9d5..0000000 --- a/lib/CPUs/MIPS/src/core/dcache.vhd +++ /dev/null @@ -1,430 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -library work; -use work.mips_types.all; - -ENTITY dcache IS - Generic - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - Port - ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_r_wn : in STD_LOGIC; - cpu_we : in unsigned(3 downto 0); - cpu_addr : in word_t; - cpu_din : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC - ); -END dcache; - -ARCHITECTURE behavior OF dcache IS - -COMPONENT dpram_1w1r - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - -COMPONENT dpram_2w2r is - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - - function lg2(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end lg2; - - function po2(x : natural) return natural is - begin - - return 2**lg2(x); - end po2; - - constant word_index_width : natural := lg2(line_size); - constant cache_index_width : natural := lg2(cache_size) - word_index_width; - constant tag_width : natural := 32 - word_index_width - cache_index_width - 2; - constant tag_parity_width : natural := 3; - constant tram_data_width : natural := 2 + tag_parity_width + tag_width; - constant tram_addr_width : natural := cache_index_width; - - subtype tram_data_t is unsigned (tram_data_width-1 downto 0); - - type dcache_entry_t is record - valid : std_logic; - dirty : std_logic; - tv_p : unsigned(tag_parity_width-1 downto 0); - tag : unsigned(tag_width-1 downto 0); - end record; - - alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); - alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - function to_dcache_entry(x : tram_data_t) return dcache_entry_t is - variable result : dcache_entry_t; - begin - result.valid := x(0); - result.dirty := x(1); - result.tv_p := x(4 downto 2); - result.tag := x(tag_width+4 downto 5); - - return result; - end to_dcache_entry; - - function to_tram_data(x : dcache_entry_t) return tram_data_t is - variable result : tram_data_t; - begin - result(0) := x.valid; - result(1) := x.dirty; - result(4 downto 2) := x.tv_p; - result(tag_width+4 downto 5) := x.tag; - - return result; - end to_tram_data; - - type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache, wr_cache); - signal s, sn : cache_state_t; - - signal cache_busy : std_logic; - signal cache_read_miss : std_logic; - signal cache_write_miss : std_logic; - signal tag_match : std_logic; - signal word_index_reg : unsigned(word_index_width-1 downto 0); - signal cache_index_reg : unsigned(cache_index_width-1 downto 0); - signal tag_index_reg : unsigned(tag_width-1 downto 0); - - signal cache_entry_in : dcache_entry_t; - signal cache_entry_out : dcache_entry_t; - signal cpu_dram_addr : unsigned(lg2(cache_size)-1 downto 0); - signal cpu_dram_dout : word_t; - signal cpu_dram_din : word_t; - signal cpu_data_reg : word_t; - signal cpu_we_reg : unsigned(3 downto 0); - signal ctrl_force_we : unsigned(3 downto 0); - signal cpu_was_write : std_logic; - signal ctrl_dram_addr : unsigned(lg2(cache_size)-1 downto 0); - signal ctrl_dram_din : word_t; - signal ctrl_dram_we : unsigned(3 downto 0); - signal cpu_dram_we : unsigned(3 downto 0); - signal dram_en : std_logic; - signal cpu_was_en : std_logic; - - signal tram_addr_rd : unsigned(cache_index_width-1 downto 0); - signal tram_dout : tram_data_t; - signal tram_addr_wr : unsigned(cache_index_width-1 downto 0); - signal tram_din : tram_data_t; - signal tram_re : std_logic; - signal tram_we : std_logic; - - signal ram_index_count : natural range 0 to 2**word_index_width-1; - signal ram_index_count_rst : std_logic; - signal cache_index_count : natural range 0 to 2**cache_index_width-1; - signal cache_index_count_en : std_logic; - signal mem_index_count : natural range 0 to 2**word_index_width-1; - signal mem_index_count_en : std_logic; - signal mem_index_count_rst : std_logic; - signal cpu_reg_en : std_logic; - signal was_miss : std_logic; - signal data_write : std_logic; - signal cpu_we2 : std_logic; - -begin - - -cpu_index_reg: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cache_index_reg <= (others => '0'); - tag_index_reg <= (others => '0'); - cpu_was_write <= '0'; - elsif cpu_reg_en = '1' and en = '1' then - word_index_reg <= cpu_word_index; - cache_index_reg <= cpu_cache_index; - tag_index_reg <= cpu_tag; - cpu_data_reg <= cpu_din; - cpu_we_reg <= cpu_we; - cpu_was_write <= not cpu_r_wn; - end if; - end if; - end process; - -cpu_was_wr_reg: - process(clk) - begin - if rising_edge(clk) then - cpu_was_en <= '0'; - cpu_we2 <= '0'; - if cpu_en = '1' and en = '1' then - cpu_we2 <= not cpu_r_wn; - cpu_was_en <= '1'; - cpu_dram_din <= cpu_din; - end if; - end if; - end process; - -inst_tag_ram : dpram_1w1r - GENERIC MAP ( - addr_width => tram_addr_width, - data_width => tram_data_width - ) - PORT MAP ( - clka => clk, - clkb => clk, - en_a => '1', - en_b => tram_re, - we_a => tram_we, - addr_a => tram_addr_wr, - addr_b => tram_addr_rd, - din_a => tram_din, - dout_b => tram_dout - ); - -gen_data_ram: - for i in 0 to 3 generate - begin - - inst_data_ram : dpram_2w2r - GENERIC MAP ( - addr_width => lg2(cache_size), - data_width => word_t'length/4 - ) - PORT MAP ( - clk_a => clk, - clk_b => clk, - en_a => '1', - en_b => dram_en, - we_a => ctrl_dram_we(i), - we_b => cpu_dram_we(i), - addr_a => ctrl_dram_addr, - addr_b => cpu_dram_addr, - din_a => ctrl_dram_din(8*(i+1)-1 downto 8*i), - din_b => cpu_dram_din(8*(i+1)-1 downto 8*i), - dout_a => open, - dout_b => cpu_dram_dout(8*(i+1)-1 downto 8*i) - ); - end generate; - -cache_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - cpu_busy <= cache_busy; - cpu_dout <= cpu_dram_dout; - - tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0'; - cache_read_miss <= not (tag_match and cache_entry_out.valid) and not cpu_was_write; - cache_write_miss <= not (tag_match and cache_entry_out.valid and cpu_was_write); - tram_din <= to_tram_data(cache_entry_in); - tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; - cache_entry_out <= to_dcache_entry(tram_dout); - cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_we2 = '0') else (cache_index_reg & word_index_reg); - mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; - ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); - ctrl_dram_din <= mem_din; - ctrl_dram_we <= (3 downto 0 => (data_write and mem_valid)) or ctrl_force_we; - cpu_dram_we <= cpu_we_reg when (cpu_we2 = '1' and cache_write_miss = '0') else (others => '0'); - -cache_state: - process(s, cache_read_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, cpu_r_wn, mem_gnt, mem_rdy, cpu_was_en, cpu_was_write, cpu_we_reg) - begin - cpu_reg_en <= '0'; - cache_busy <= '1'; - tram_we <= '0'; - cache_index_count_en <= '0'; - ram_index_count_rst <= '0'; - mem_index_count_en <= '0'; - mem_index_count_rst <= '0'; - mem_req <= '0'; - mem_en <= '0'; - dram_en <= '0'; - tram_re <= '0'; - was_miss <= '0'; - data_write <= '0'; - tram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); - cache_entry_in.tv_p <= (others => '0'); - cache_entry_in.tag <= tag_index_reg; - cache_entry_in.valid <= '0'; - cache_entry_in.dirty <= '0'; - ctrl_force_we <= (others => '0'); - sn <= s; - - case s is - when init => - sn <= flush; - when ready => - cache_busy <= '0'; - cpu_reg_en <= '1'; - dram_en <= cpu_en or cpu_was_en; - tram_re <= cpu_en; - if cpu_was_en = '1' then - if cache_read_miss = '1' then - sn <= mem_request; - cpu_reg_en <= '0'; - cache_busy <= '1'; - end if; - end if; - when flush => - cache_index_count_en <= '1'; - tram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); - tram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - if cache_index_count = 0 then - sn <= ready; - if cpu_en = '1' then - cpu_reg_en <= '1'; - dram_en <= '1'; - tram_re <= '1'; - end if; - end if; - when mem_request => - ram_index_count_rst <= '1'; - mem_index_count_rst <= '1'; - mem_req <= '1'; - if mem_gnt = '1' then - sn <= mem_access; - end if; - when mem_access => - data_write <= '1'; - mem_req <= '1'; - if mem_rdy = '1' then - mem_index_count_en <= '1'; - mem_en <= '1'; - if mem_index_count = 2**word_index_width-1 then - sn <= mem_data; - end if; - end if; - when mem_data => - mem_req <= '1'; - data_write <= '1'; - if ram_index_count = 2**word_index_width-1 then - if mem_valid = '1' then - sn <= upd_cache; - end if; - end if; - when upd_cache => - mem_req <= '1'; - tram_addr_wr <= cache_index_reg; - tram_we <= '1'; - cache_entry_in.valid <= '1'; - if cpu_was_write = '1' then - sn <= wr_cache; - else - sn <= rd_cache; - end if; - - when rd_cache => - tram_re <= '1'; - dram_en <= '1'; - was_miss <= '1'; - sn <= ready; - - when wr_cache => - tram_re <= '1'; - ctrl_force_we <= cpu_we_reg; - sn <= ready; - when others => - sn <= ready; - end case; - end process; - -cache_index_counter: - process(clk) - begin - if rising_edge(clk) then - if cache_index_count_en = '0' then - cache_index_count <= 2**cache_index_width-1; - elsif cache_index_count /= 0 then - cache_index_count <= cache_index_count - 1; - end if; - end if; - end process; - -ram_index_counter: - process(clk) - begin - if rising_edge(clk) then - if ram_index_count_rst = '1' then - ram_index_count <= 0; - elsif data_write = '1' and mem_valid = '1' then - if ram_index_count /= 2**word_index_width-1 then - ram_index_count <= ram_index_count + 1; - end if; - end if; - end if; - end process; - -mem_index_counter: - process(clk) - begin - if rising_edge(clk) then - if mem_index_count_rst = '1' then - mem_index_count <= 0; - elsif mem_index_count_en = '1' then - if mem_index_count /= 2**word_index_width-1 then - mem_index_count <= mem_index_count + 1; - end if; - end if; - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/icache.vhd b/lib/CPUs/MIPS/src/core/icache.vhd deleted file mode 100644 index d7e3026..0000000 --- a/lib/CPUs/MIPS/src/core/icache.vhd +++ /dev/null @@ -1,356 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -library work; -use work.mips_types.all; - -ENTITY icache IS - Generic - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - Port - ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_addr : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC - ); -END icache; - -ARCHITECTURE behavior OF icache IS - -COMPONENT dpram_1w1r - GENERIC - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - PORT ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -END COMPONENT; - - function lg2(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end lg2; - - function po2(x : natural) return natural is - begin - - return 2**lg2(x); - end po2; - - constant word_index_width : natural := lg2(line_size); - constant cache_index_width : natural := lg2(cache_size) - word_index_width; - constant tag_width : natural := 32 - word_index_width - cache_index_width - 2; - constant tag_parity_width : natural := 3; - constant tag_ram_data_width : natural := 1 + tag_parity_width + tag_width; - constant tag_ram_addr_width : natural := cache_index_width; - - subtype tag_ram_data_t is unsigned (tag_ram_data_width-1 downto 0); - - type icache_entry_t is record - valid : std_logic; - tv_p : unsigned(tag_parity_width-1 downto 0); - tag : unsigned(tag_width-1 downto 0); - end record; - - alias cpu_word_index is cpu_addr(word_index_width+1 downto 2); - alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2); - alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2); - - function to_icache_entry(x : tag_ram_data_t) return icache_entry_t is - variable result : icache_entry_t; - begin - result.valid := x(0); - result.tv_p := x(3 downto 1); - result.tag := x(tag_width+3 downto 4); - - return result; - end to_icache_entry; - - function to_tag_ram_data(x : icache_entry_t) return tag_ram_data_t is - variable result : tag_ram_data_t; - begin - result(0) := x.valid; - result(3 downto 1) := x.tv_p; - result(tag_width+3 downto 4) := x.tag; - - return result; - end to_tag_ram_data; - - type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache); - signal s, sn : cache_state_t; - - signal cache_busy : std_logic; - signal cache_miss : std_logic; - signal tag_match : std_logic; - signal word_index_reg : unsigned(word_index_width-1 downto 0); - signal cache_index_reg : unsigned(cache_index_width-1 downto 0); - signal tag_index_reg : unsigned(tag_width-1 downto 0); - - signal cache_entry_in : icache_entry_t; - signal cache_entry_out : icache_entry_t; - signal data_ram_addr_rd : unsigned(lg2(cache_size)-1 downto 0); - signal data_ram_data_rd : word_t; - signal data_ram_addr_wr : unsigned(lg2(cache_size)-1 downto 0); - signal data_ram_data_wr : word_t; - signal data_ram_we : std_logic; - signal data_ram_re : std_logic; - - signal tag_ram_addr_rd : unsigned(cache_index_width-1 downto 0); - signal tag_ram_data_rd : tag_ram_data_t; - signal tag_ram_addr_wr : unsigned(cache_index_width-1 downto 0); - signal tag_ram_data_wr : tag_ram_data_t; - signal tag_ram_re : std_logic; - signal tag_ram_we : std_logic; - - signal ram_index_count : natural range 0 to 2**word_index_width-1; - signal ram_index_count_rst : std_logic; - signal cache_index_count : natural range 0 to 2**cache_index_width-1; - signal cache_index_count_en : std_logic; - signal mem_index_count : natural range 0 to 2**word_index_width-1; - signal mem_index_count_en : std_logic; - signal mem_index_count_rst : std_logic; - signal cpu_reg_en : std_logic; - signal was_miss : std_logic; - signal data_write : std_logic; - -begin - - -cpu_index_reg: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cache_index_reg <= (others => '0'); - tag_index_reg <= (others => '0'); - elsif cpu_reg_en = '1' then - word_index_reg <= cpu_word_index; - cache_index_reg <= cpu_cache_index; - tag_index_reg <= cpu_tag; - end if; - end if; - end process; - -inst_tag_ram : dpram_1w1r - GENERIC MAP ( - addr_width => tag_ram_addr_width, - data_width => tag_ram_data_width - ) - PORT MAP ( - clka => clk, - clkb => clk, - en_a => '1', - en_b => tag_ram_re, - we_a => tag_ram_we, - addr_a => tag_ram_addr_wr, - addr_b => tag_ram_addr_rd, - din_a => tag_ram_data_wr, - dout_b => tag_ram_data_rd - ); - -inst_data_ram : dpram_1w1r - GENERIC MAP ( - addr_width => lg2(cache_size), - data_width => word_t'length - ) - PORT MAP ( - clka => clk, - clkb => clk, - en_a => '1', - en_b => data_ram_re, - we_a => data_ram_we, - addr_a => data_ram_addr_wr, - addr_b => data_ram_addr_rd, - din_a => data_ram_data_wr, - dout_b => data_ram_data_rd - ); - - -cache_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - cpu_busy <= cache_busy; - cpu_dout <= data_ram_data_rd; - - tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0'; - cache_miss <= not (tag_match and cache_entry_out.valid); - tag_ram_data_wr <= to_tag_ram_data(cache_entry_in); - tag_ram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg; - cache_entry_out <= to_icache_entry(tag_ram_data_rd); - data_ram_addr_rd <= (cpu_cache_index & cpu_word_index) when was_miss = '0' else (cache_index_reg & word_index_reg); - mem_addr <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00"; - data_ram_addr_wr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width); - data_ram_data_wr <= mem_din; - data_ram_we <= data_write and mem_valid; - -cache_state: - process(s, cache_miss, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, mem_valid, tag_index_reg, cpu_en, mem_gnt, mem_rdy, en) - begin - cpu_reg_en <= '0'; - cache_busy <= '1'; - tag_ram_we <= '0'; - cache_index_count_en <= '0'; - ram_index_count_rst <= '0'; - mem_index_count_en <= '0'; - mem_index_count_rst <= '0'; - mem_req <= '0'; - mem_en <= '0'; - data_ram_re <= '0'; - tag_ram_re <= '0'; - was_miss <= '0'; - data_write <= '0'; - tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); - cache_entry_in.tv_p <= (others => '0'); - cache_entry_in.tag <= tag_index_reg; - cache_entry_in.valid <= '0'; - sn <= s; - - case s is - when init => - sn <= flush; - when ready => - if en = '1' then - cache_busy <= '0'; - if cache_miss = '1' then - sn <= mem_request; - cpu_reg_en <= '0'; - cache_busy <= '1'; - elsif cpu_en = '1' then - cpu_reg_en <= '1'; - data_ram_re <= '1'; - tag_ram_re <= '1'; - end if; - end if; - when flush => - cache_index_count_en <= '1'; - tag_ram_addr_wr <= to_unsigned(cache_index_count, cache_index_width); - tag_ram_we <= '1'; - cache_entry_in.valid <= '0'; - cache_entry_in.tag <= (others => '0'); - if cache_index_count = 0 then - sn <= ready; - if cpu_en = '1' then - cpu_reg_en <= '1'; - data_ram_re <= '1'; - tag_ram_re <= '1'; - end if; - end if; - when mem_request => - ram_index_count_rst <= '1'; - mem_index_count_rst <= '1'; - mem_req <= '1'; - if mem_gnt = '1' then - sn <= mem_access; - end if; - when mem_access => - data_write <= '1'; - mem_req <= '1'; - if mem_rdy = '1' then - mem_index_count_en <= '1'; - mem_en <= '1'; - if mem_index_count = 2**word_index_width-1 then - sn <= mem_data; - end if; - end if; - when mem_data => - mem_req <= '1'; - data_write <= '1'; - if ram_index_count = 2**word_index_width-1 then - if mem_valid = '1' then - sn <= upd_cache; - end if; - end if; - when upd_cache => - mem_req <= '1'; - tag_ram_addr_wr <= cache_index_reg; - tag_ram_we <= '1'; - cache_entry_in.valid <= '1'; - sn <= rd_cache; - - when rd_cache => --- mem_req <= '1'; - tag_ram_re <= '1'; - data_ram_re <= '1'; - was_miss <= '1'; - sn <= ready; - when others => - sn <= ready; - end case; - end process; - -cache_index_counter: - process(clk) - begin - if rising_edge(clk) then - if cache_index_count_en = '0' then - cache_index_count <= 2**cache_index_width-1; - elsif cache_index_count /= 0 then - cache_index_count <= cache_index_count - 1; - end if; - end if; - end process; - -ram_index_counter: - process(clk) - begin - if rising_edge(clk) then - if ram_index_count_rst = '1' then - ram_index_count <= 0; - elsif data_write = '1' and mem_valid = '1' then - if ram_index_count /= 2**word_index_width-1 then - ram_index_count <= ram_index_count + 1; - end if; - end if; - end if; - end process; - -mem_index_counter: - process(clk) - begin - if rising_edge(clk) then - if mem_index_count_rst = '1' then - mem_index_count <= 0; - elsif mem_index_count_en = '1' then - if mem_index_count /= 2**word_index_width-1 then - mem_index_count <= mem_index_count + 1; - end if; - end if; - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_alu.vhd b/lib/CPUs/MIPS/src/core/mips_alu.vhd deleted file mode 100644 index a64b5a4..0000000 --- a/lib/CPUs/MIPS/src/core/mips_alu.vhd +++ /dev/null @@ -1,184 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity alu is - Generic - ( - data_width : integer := 8 - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); -end alu; - -architecture Behavioral of alu is - - signal sum_res : unsigned (data_width-1 downto 0); - signal and_res : unsigned (data_width-1 downto 0); - signal xor_res : unsigned (data_width-1 downto 0); - signal nor_res : unsigned (data_width-1 downto 0); - signal or_res : unsigned (data_width-1 downto 0); - signal eq, sa, sb, sr, c, z : STD_LOGIC; - signal lts, ltu : STD_LOGIC; - --------------------------------------------------------------------------- -begin - - eq <= '1' when op1_in = op2_in else '0' after 3 ns; - sa <= op1_in(op1_in'left); - sb <= op2_in(op2_in'left); - sr <= sum_res(sum_res'left); - z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns; - - flags.uvf <= (not ctrl.add) and ((sa and (not sb) and (not sr)) or ((not sa) and sb and sr)); - flags.ovf <= ctrl.add and ((sa and sb and (not sr)) or ((not sa) and (not sb) and sr)); --- lts <= (not eq) and (((not c) and sa and sb) or (((not sr) and sa) or (sa and (not sb)) or (sr and (not sb)))); - lts <= not eq and ((not c and sa) or (not sb and sa) or (not sb and sr)); - - ltu <= (not eq) and (not c); - flags.lts <= lts; - flags.ltu <= ltu; - flags.c <= c; - --------------------------------------------------------------------------- -proc_op_and: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - and_res <= (x1 and x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_xor: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - xor_res <= (x1 xor x2) after 2 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_nor: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - nor_res <= (x1 nor x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_proc_or: - process(op1_in, op2_in) - variable x1, x2 : unsigned (data_width-1 downto 0); - begin - x1 := op1_in; - x2 := op2_in; - - or_res <= (x1 or x2) after 1 ns; - - end process; - --------------------------------------------------------------------------- -proc_alu_out: - process(ctrl, sum_res, and_res, xor_res, nor_res, or_res, op2_shifted, lts, ltu) - begin - - result <= sum_res; - - case ctrl.outsel is - - when alu_adder => - result <= sum_res; - - when alu_and => - result <= and_res; - - when alu_xor => - result <= xor_res; - - when alu_nor => - result <= nor_res; - - when alu_or => - result <= or_res; - - when alu_shift2 => - result <= op2_shifted; - - when alu_ltu => - result <= (data_width-1 downto 1 => '0') & ltu; - - when alu_lts => - result <= (data_width-1 downto 1 => '0') & lts; - - when others => null; - - end case; - - end process; - --------------------------------------------------------------------------- -alu_addsub: - process(op1_in, op2_in, ctrl) - variable sum : unsigned(data_width+1 downto 0); - variable op1, op2 : unsigned(data_width+1 downto 0); - begin - - op1 := '0' & op1_in & not ctrl.add; - if (ctrl.add = '1') then - op2 := '0' & op2_in & '0'; - else - op2 := '0' & not op2_in & '1'; - end if; - sum := op1 + op2; - - -- Form sum + carry - sum_res <= unsigned(sum(data_width downto 1)) after 4 ns; - c <= sum(sum'left) after 4 ns; - - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_bcu.vhd b/lib/CPUs/MIPS/src/core/mips_bcu.vhd deleted file mode 100644 index 14e3f36..0000000 --- a/lib/CPUs/MIPS/src/core/mips_bcu.vhd +++ /dev/null @@ -1,53 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity bcu is - Generic - ( - data_width : integer := 8 - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); -end bcu; - -architecture Behavioral of bcu is - --------------------------------------------------------------------------- -begin - - flags.eq <= '1' when op1_in = op2_in else '0' after 3 ns; - flags.z <= '1' when op1_in = (data_width-1 downto 0 => '0') else '0' after 2 ns; - flags.ltz <= op1_in(op1_in'left) after 1 ns; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_bui.vhd b/lib/CPUs/MIPS/src/core/mips_bui.vhd deleted file mode 100644 index b1adabe..0000000 --- a/lib/CPUs/MIPS/src/core/mips_bui.vhd +++ /dev/null @@ -1,396 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity bui is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - cpu_wait : out STD_LOGIC; - cpu_imem_rdy : out STD_LOGIC; - cpu_imem_en : in STD_LOGIC; - cpu_imem_addr : in word_t; - cpu_imem_din : out word_t; - cpu_dmem_rdy : out STD_LOGIC; - cpu_dmem_en : in STD_LOGIC; - cpu_dmem_re : in STD_LOGIC; - cpu_dmem_we : in unsigned(3 downto 0); - cpu_dmem_dout : in word_t; - cpu_dmem_din : out word_t; - cpu_dmem_addr : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_dout : out word_t; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_ce : out STD_LOGIC - ); - -end bui; - -architecture behavior of bui is - -COMPONENT icache - GENERIC - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - PORT - ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_addr : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_en : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC - ); -END COMPONENT; - -COMPONENT dcache - GENERIC - ( - cache_size : natural := 2048; -- words - line_size : natural := 8 -- words - ); - PORT - ( - clk : in STD_LOGIC; - rst : in STD_LOGIC; - en : in STD_LOGIC; - cpu_en : in STD_LOGIC; - cpu_r_wn : in STD_LOGIC; - cpu_we : in unsigned(3 downto 0); - cpu_addr : in word_t; - cpu_din : in word_t; - cpu_dout : out word_t; - cpu_busy : out STD_LOGIC; - mem_req : out STD_LOGIC; - mem_gnt : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC - ); -END COMPONENT; - - type bus_state_t is (init, ready, i_cache_bus_access, d_cache_bus_access, d_bus_start, d_bus_access, d_bus_finish); - - signal s, sn : bus_state_t; - signal dmem_re : std_logic; - signal dmem_we : unsigned(3 downto 0); - signal dcache_dout : word_t; - signal dmem_dout : word_t; - signal dmem_din : word_t; - signal dmem_addr : word_t; - signal imem_addr : word_t; - signal imem_mem_out_en : std_logic; - signal dmem_mem_out_en : std_logic; - signal imem_valid : std_logic; - signal dmem_valid : std_logic; - signal dmem_ack : std_logic; - signal dcache_req : std_logic; - signal dcache_busy1 : std_logic; - signal dcache_busy2 : std_logic; - signal icache_busy : std_logic; - signal bus_req : std_logic; - signal bus_bsy : std_logic; - signal icache_mem_en : std_logic; - signal icache_mem_req : std_logic; - signal icache_mem_gnt : std_logic; - signal icache_mem_addr : word_t; - signal dcache_mem_en : std_logic; - signal dcache_mem_req : std_logic; - signal dcache_mem_gnt : std_logic; - signal dcache_mem_addr : word_t; - signal contention : std_logic; - signal dcached : std_logic; - signal duncached_access : std_logic; - -begin - - mem_ce <= mem_rdy and bus_req; - contention <= dcache_req and icache_mem_req; - - cpu_imem_rdy <= not icache_busy after 4.5 ns; --- cpu_imem_din <= imem_din; --- cpu_wait <= busy after 5.5 ns; - cpu_wait <= '0'; - cpu_dmem_rdy <= not (dcache_busy1 or dcache_busy2) after 4.5 ns; - -inst_icache : icache - GENERIC MAP - ( - cache_size => 2048, -- words - line_size => 8 - ) - PORT MAP - ( - clk => clk, - rst => rst, - en => '1', - cpu_en => cpu_imem_en, - cpu_addr => cpu_imem_addr, - cpu_dout => cpu_imem_din, - cpu_busy => icache_busy, - mem_en => icache_mem_en, - mem_req => icache_mem_req, - mem_gnt => icache_mem_gnt, - mem_addr => icache_mem_addr, - mem_din => mem_din, - mem_valid => imem_valid, - mem_rdy => mem_rdy - ); - -inst_dcache : dcache - GENERIC MAP - ( - cache_size => 2048, -- words - line_size => 8 - ) - PORT MAP - ( - clk => clk, - rst => rst, - en => dcached, - cpu_en => cpu_dmem_en, - cpu_r_wn => cpu_dmem_re, - cpu_we => cpu_dmem_we, - cpu_addr => cpu_dmem_addr, - cpu_din => cpu_dmem_dout, - cpu_dout => dcache_dout, - cpu_busy => dcache_busy2, - mem_req => dcache_mem_req, - mem_gnt => dcache_mem_gnt, - mem_en => dcache_mem_en, - mem_addr => dcache_mem_addr, - mem_din => mem_din, - mem_valid => dmem_valid, - mem_rdy => mem_rdy - ); - - dcached <= '1' when cpu_dmem_addr(31 downto 28) /= X"A" else '0'; - cpu_dmem_din <= dmem_din when duncached_access = '1' else dcache_dout; -- when dmem_valid = '1' else ram_dout after 0.5 ns; - -dcache_flags: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - dcache_busy1 <= '0'; - dcache_req <= '0'; - else - duncached_access <= '0'; - if dmem_ack = '1' then - duncached_access <= '1'; - dcache_req <= '0'; - if dmem_re = '1' then - if dmem_valid = '1' then - dcache_busy1 <= '0'; - end if; - else - dcache_busy1 <= '0'; - end if; - end if; - if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then - dcache_req <= '1'; - dcache_busy1 <= '1'; - if dcached = '1' and cpu_dmem_re = '1' then - dcache_req <= '0'; - dcache_busy1 <= '0'; - end if; - end if; - end if; - end if; - end process; - -dcache_regs: - process(clk) - begin - if rising_edge(clk) then - if cpu_dmem_en = '1' and dcache_busy1 = '0' and dcache_busy2 = '0' then - dmem_dout <= cpu_dmem_dout; - dmem_addr <= cpu_dmem_addr; - dmem_re <= cpu_dmem_re; - dmem_we <= cpu_dmem_we; - end if; - end if; - end process; - -dcache_data: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - dmem_din <= (others => '0'); - elsif dmem_valid = '1' then - dmem_din <= mem_din; - end if; - end if; - end process; - -bus_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= init; - elsif ce = '1' then - s <= sn; - end if; - end if; - end process; - -bus_state: - process(s, icache_mem_en, icache_mem_req, dcache_mem_req, dcache_mem_en, dcache_req, dmem_re, mem_rdy, mem_valid) - begin - - imem_mem_out_en <= '0'; - dmem_mem_out_en <= '0'; - icache_mem_gnt <= '0'; - dcache_mem_gnt <= '0'; - imem_valid <= '0'; - dmem_valid <= '0'; - dmem_ack <= '0'; - bus_bsy <= '1'; - - sn <= s; - case s is - when init => - if mem_rdy = '1' then - sn <= ready; - end if; - when ready => - bus_bsy <= not mem_rdy; - if dcache_req = '1' then - if dcache_busy1 = '1' then - if mem_rdy = '1' then - dmem_mem_out_en <= '1'; - if dmem_re = '0' then - dmem_ack <= '1'; - else - sn <= d_bus_access; - end if; - end if; - end if; - elsif icache_mem_req = '1' then - sn <= i_cache_bus_access; - elsif dcache_mem_req = '1' then - sn <= d_cache_bus_access; - end if; - when i_cache_bus_access => - icache_mem_gnt <= '1'; - if icache_mem_en = '1' then - imem_mem_out_en <= '1'; - elsif icache_mem_req = '0' then - sn <= ready; - end if; - imem_valid <= mem_valid; - when d_cache_bus_access => - dcache_mem_gnt <= '1'; - if dcache_mem_en = '1' then - dmem_mem_out_en <= '1'; - elsif dcache_mem_req = '0' then - sn <= ready; - end if; - dmem_valid <= mem_valid; - when d_bus_access => - if mem_valid = '1' then - dmem_ack <= '1'; - dmem_valid <= '1'; - sn <= ready; - end if; - when d_bus_finish => - if mem_rdy = '1' then - sn <= ready; - end if; - when others => - sn <= ready; - end case; - - end process; - -bus_request: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - bus_req <= '0'; - elsif dmem_mem_out_en = '1' or imem_mem_out_en = '1' then - bus_req <= '1'; - elsif mem_rdy = '1' then - bus_req <= '0'; - end if; - end if; - end process; - -bus_out: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - mem_dout <= (others => '0'); - mem_addr <= (others => '0'); - mem_re <= '0'; - mem_we <= (others => '0'); - elsif dmem_mem_out_en = '1' then - if dcache_mem_gnt = '1' then - mem_addr <= dcache_mem_addr; - mem_re <= '1'; - mem_we <= (others => '0'); - else - mem_dout <= dmem_dout; - mem_addr <= dmem_addr; - mem_re <= dmem_re; - mem_we <= dmem_we; - end if; - elsif imem_mem_out_en = '1' then - mem_addr <= icache_mem_addr; - mem_re <= '1'; - mem_we <= (others => '0'); - end if; - end if; - end process; - -------------------------------------------------------------------- - -end behavior; diff --git a/lib/CPUs/MIPS/src/core/mips_cop.vhd b/lib/CPUs/MIPS/src/core/mips_cop.vhd deleted file mode 100644 index d37de20..0000000 --- a/lib/CPUs/MIPS/src/core/mips_cop.vhd +++ /dev/null @@ -1,415 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; -use work.mips_instr.all; - -entity cop is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - sdu : in sdu_t; - IR_valid : in STD_LOGIC; - IR : in word_t; - events : in event_t; - ctrl_in : in cop_ctrl_in_t; - ctrl_out : out cop_ctrl_out_t; - din : in word_t; - dout : out word_t - ); -end cop; - -architecture Behavioral of cop is - - signal epc : word_t; - signal cause : word_t; - signal status : word_t; - signal BadVAddr : word_t; - signal exc_code : unsigned(4 downto 0); - signal test_reg : word_t; - signal test_reg_we : STD_LOGIC; - signal stat_reg_we : STD_LOGIC; - signal eflags_reg_we : STD_LOGIC; - signal epc_reg_we : STD_LOGIC; - signal code_reg_we : STD_LOGIC; - signal ip_reg_we : STD_LOGIC; - signal bd : STD_LOGIC; - signal ip : unsigned(7 downto 0); - signal im : unsigned(7 downto 0); - signal status_save : STD_LOGIC; - signal status_rest : STD_LOGIC; - signal exception : STD_LOGIC; - signal exception_end : STD_LOGIC; - signal eflags : exc_flags_t; - signal exc_enable : STD_LOGIC; - signal cop_EX_en : STD_LOGIC; - - type cop_pipe_t is record - din : word_t; - rs : reg_ptr_t; - rd : reg_ptr_t; - func : func_t; - we : std_logic; - re : std_logic; - cs : std_logic; - end record; - - signal cop_pipe_ID : cop_pipe_t; - signal cop_pipe_EX : cop_pipe_t; - - function eval_int(ip, im : unsigned) return STD_LOGIC is - variable result : STD_LOGIC; - begin - result := '0'; - for i in ip'range loop - result := result or (ip(i) and im(i)); - end loop; - - return result; - end eval_int; - - type exc_state_t is (exc_init, exc_idle, exc_commit_ID, exc_commit_EX, exc_commit_MEM); - signal exc_state, exc_staten : exc_state_t; - --------------------------------------------------------------------------- -begin - - cop_pipe_ID.din <= din; - cop_pipe_ID.cs <= IR_valid; - cop_pipe_ID.rs <= extract_rs(IR); - cop_pipe_ID.rd <= extract_rd(IR); - cop_pipe_ID.func <= extract_func(IR); - cop_pipe_ID.re <= cop_pipe_ID.cs when cop_pipe_ID.rs = "00000" else '0'; - cop_pipe_ID.we <= cop_pipe_ID.cs when cop_pipe_ID.rs = "00100" else '0'; - cop_EX_en <= exc_enable and not status_save; - - ctrl_out.ee <= exc_enable; - ctrl_out.ec <= status_save; - ctrl_out.RE <= status(25); - ctrl_out.user_mode <= status(1); - ctrl_out.int <= eflags.Int; - - ctrl_out.cop_read <= cop_pipe_EX.cs and cop_pipe_EX.re after 1 ns; - ctrl_out.reg_write <= cop_pipe_ID.re after 1 ns; - - im <= status(15 downto 8); - cause <= bd & (30 downto 16 => '0') & ip & '0' & exc_code & "00"; - - eflags.Ov <= events.alu_ovf or events.alu_uvf; - eflags.DAdEL <= events.data_load_err; - eflags.DAdES <= events.data_store_err; - eflags.IAdEL <= events.inst_load_err; - eflags.IAdEK <= events.inst_priv_addr and status(1); - eflags.Sys <= events.syscall; - eflags.Bp <= events.break; - eflags.RI <= events.illegal; - eflags.Int <= eval_int(ip, im) and status(0); - - exception <= eflags.Ov or eflags.Sys or eflags.Bp or eflags.RI or eflags.IAdEL or eflags.IAdEK or eflags.DAdEL or eflags.DAdES or eflags.Int after 1 ns; - -exception_state: - process(exc_state, ctrl_in, exception, sdu) - begin - - exc_enable <= '0'; - ctrl_out.exc_commit <= '0'; - ctrl_out.exc_pending <= '0'; - epc_reg_we <= '0'; - code_reg_we <= '0'; - status_save <= '0'; - eflags_reg_we <= '0'; - - exc_staten <= exc_state; - - case exc_state is - - when exc_init => - exc_staten <= exc_idle; - - when exc_idle => - exc_enable <= '1'; - if exception = '1' then - status_save <= '1'; - eflags_reg_we <= '1'; - code_reg_we <= '1'; - exc_staten <= exc_commit_ID; - end if; - - when exc_commit_ID => - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - if sdu.ID_stall = '0' then - exc_staten <= exc_commit_EX; - end if; - - when exc_commit_EX => - ctrl_out.exc_pending <= '1'; - ctrl_out.exc_commit <= '1'; - if sdu.EX_stall = '0' then - exc_staten <= exc_commit_MEM; - end if; - - when exc_commit_MEM => - ctrl_out.exc_pending <= '1'; - if sdu.MEM_stall = '0' then - epc_reg_we <= '1'; - exc_staten <= exc_idle; - end if; - - when others => - exc_staten <= exc_idle; - - end case; - end process; - -exception_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exc_state <= exc_init; - else - exc_state <= exc_staten; - end if; - end if; - end process; - -cop_exception_epc_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - bd <= '0'; - epc <= (others => '0'); - elsif epc_reg_we = '1' then - bd <= '0'; - epc <= ctrl_in.epc_mem; - if ctrl_in.bd_wb = '1' then - bd <= '1'; - epc <= ctrl_in.epc_wb; - end if; - end if; - end if; - end process; - -cop_exception_map: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exc_code <= (others => '0'); - BadVAddr <= (others => '0'); - elsif code_reg_we = '1' then - if eflags.Ov = '1' then - exc_code <= "01100"; - elsif eflags.Sys = '1' then - exc_code <= "01000"; - elsif eflags.Bp = '1' then - exc_code <= "01001"; - elsif eflags.RI = '1' then - exc_code <= "01010"; - elsif eflags.IAdEL = '1' then - exc_code <= "00100"; - BadVAddr <= ctrl_in.imem_addr; - elsif eflags.IAdEK = '1' then - exc_code <= "00100"; - BadVAddr <= ctrl_in.imem_addr; - elsif eflags.DAdEL = '1' then - exc_code <= "00100"; - BadVAddr <= ctrl_in.dmem_addr; - elsif eflags.DAdES = '1' then - exc_code <= "00101"; - BadVAddr <= ctrl_in.dmem_addr; - elsif eflags.Int = '1' then - exc_code <= "00000"; - end if; - end if; - end if; - end process; - - status_rest <= exception_end and ctrl_in.exc_left; - -cop_status_restore: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - exception_end <= '0'; - ctrl_out.exc_exit <= '0'; - else - if cop_pipe_ID.func = "10000" and exception_end = '0' then -- RFE - exception_end <= cop_pipe_ID.cs; - ctrl_out.exc_exit <= cop_pipe_ID.cs; - elsif exception_end = '1' and ctrl_in.exc_left = '1' then - exception_end <= '0'; - ctrl_out.exc_exit <= '0'; - end if; - end if; - end if; - end process; - -cop_ip_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - ip(1 downto 0) <= (others => '0'); - elsif ip_reg_we = '1' then - ip(1 downto 0) <= cop_pipe_EX.din(9 downto 8); - end if; - ip(7 downto 2) <= events.Int; - end if; - end process; - -cop_exc_vector: - process(clk) - begin - if rising_edge(clk) then - ctrl_out.exc_vec <= X"80000180"; - if status(22) = '1' then - ctrl_out.exc_vec <= X"BFC00180"; - end if; - end if; - end process; - -cop_pipe: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cop_pipe_EX.cs <= '0'; - cop_pipe_EX.we <= '0'; - cop_pipe_EX.re <= '0'; - else - if sdu.EX_stall = '0' then - cop_pipe_EX <= cop_pipe_ID; - end if; - end if; - end if; - end process; - -cop_register_read: - process(clk) - variable reg : word_t; - begin - if rising_edge(clk) and cop_pipe_ID.re = '1' and sdu.ID_stall = '0' then - case cop_pipe_ID.rd is - when "01000" => -- BadVAddr - reg := BadVAddr; - - when "01100" => -- Status - reg := status; - - when "01101" => -- Cause - reg := cause; - - when "01110" => -- EPC (Exception Program Counter) - reg := epc; - - when "01111" => -- PRId (Processor Revision Register) - reg := X"000002" & to_unsigned(REVISION ,8); - - when "11111" => -- test_reg - reg := test_reg; - - when others => - reg := X"DEADBEEF"; - - end case; - dout <= reg; - end if; - end process; - -cop_we_gen: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - test_reg_we <= '0'; - stat_reg_we <= '0'; - ip_reg_we <= '0'; - else - test_reg_we <= '0'; - stat_reg_we <= '0'; - ip_reg_we <= '0'; - if (cop_EX_en and cop_pipe_EX.we) = '1' then - - case cop_pipe_EX.rd is - - when "01100" => - stat_reg_we <= not status(1) or status(28); - when "01101" => - ip_reg_we <= not status(1) or status(28); - when "11111" => - test_reg_we <= not status(1) or status(28); - when others => null; - - end case; - - end if; - end if; - end if; - end process; - -cop_test_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - test_reg <= (others => '0'); - else --if ce = '1' then - if test_reg_we = '1' then - test_reg <= cop_pipe_EX.din; - end if; - end if; - end if; - end process; - -cop_status_reg_write: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - status <= X"00400000"; - else - if status_save = '1' then - status(5 downto 4) <= status(3 downto 2); - status(3 downto 2) <= status(1 downto 0); - status(1 downto 0) <= "00"; - elsif status_rest = '1' then - status(1 downto 0) <= status(3 downto 2); - status(3 downto 2) <= status(5 downto 4); - elsif stat_reg_we = '1' then - status <= cop_pipe_EX.din; - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd b/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd deleted file mode 100644 index 720e65c..0000000 --- a/lib/CPUs/MIPS/src/core/mips_idecode_rom.vhd +++ /dev/null @@ -1,101 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The datapath controller --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -entity idecode_rom is - Port - ( - nop : in std_logic; - inst_in : in word_t; - ctrl_out : out ctrl_lines_t - ); -end idecode_rom; - -architecture Behavioral of idecode_rom is - - signal ctrl_special : ctrl_lines_t; - signal ctrl_regimm : ctrl_lines_t; - signal ctrl_opcode : ctrl_lines_t; - - signal rom_special : rom_special_t := gen_rom_special; - signal rom_regimm : rom_regimm_t := gen_rom_regimm; - signal rom_opcode : rom_opcode_t := gen_rom_opcode; - - attribute rom_style : string; - - attribute rom_style of rom_special: signal is "distributed"; - attribute rom_style of rom_regimm: signal is "distributed"; - attribute rom_style of rom_opcode: signal is "distributed"; - -begin - -i_dec_special: - process(inst_in, rom_special) - variable func : func_t; - begin - func := extract_func(inst_in); - ctrl_special <= rom_special(to_integer(func)); - end process; - -i_dec_regimm: - process(inst_in, rom_regimm) - variable rt : reg_ptr_t; - begin - rt := extract_rt(inst_in); - ctrl_regimm <= rom_regimm(to_integer(rt)); - end process; - -i_dec_opcode: - process(inst_in, rom_opcode) - variable opc : opcode_t; - begin - opc := extract_opc(inst_in); - ctrl_opcode <= rom_opcode(to_integer(opc)); - end process; - -proc_decode: - process(inst_in, ctrl_special, ctrl_regimm, ctrl_opcode, nop) - variable opclass : opcode_t; - begin - opclass := extract_opc(inst_in); - ctrl_out <= ctrl_lines_default after 2 ns; - if nop = '0' then - case opclass is - when "000000" => - ctrl_out <= ctrl_special after 2 ns; - when "000001" => - ctrl_out <= ctrl_regimm after 2 ns; - when others => - ctrl_out <= ctrl_opcode after 2 ns; - end case; - end if; - end process; - -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_instr.vhd b/lib/CPUs/MIPS/src/core/mips_instr.vhd deleted file mode 100644 index 97a0c0b..0000000 --- a/lib/CPUs/MIPS/src/core/mips_instr.vhd +++ /dev/null @@ -1,997 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JCPU --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - --------------------------------------------------------------------------- -package mips_instr is - - function extract_opc(instr : word_t) return opcode_t; - function extract_rs(instr : word_t) return reg_ptr_t; - function extract_rt(instr : word_t) return reg_ptr_t; - function extract_rd(instr : word_t) return reg_ptr_t; - function extract_shamt(instr : word_t) return shamt_t; - function extract_func(instr : word_t) return func_t; - function extract_simm32(instr : word_t) return word_t; - function extract_uimm16(instr : word_t) return word_t; - function extract_jimm32(instr, pc : word_t) return word_t; - function extract_bimm18(instr, pc : word_t) return word_t; - function decode_op(instr : word_t) return op_t; - function ctrl_lines_default return ctrl_lines_t; - function special_ctrl_lines(func : func_t) return ctrl_lines_t; - function regimm_ctrl_lines(rt : reg_ptr_t) return ctrl_lines_t; - function opcode_ctrl_lines(opc : opcode_t) return ctrl_lines_t; - function gen_rom_opcode return rom_opcode_t; - function gen_rom_regimm return rom_regimm_t; - function gen_rom_special return rom_special_t; - -end mips_instr; - --------------------------------------------------------------------------- -library work; -use work.mips_types.all; - -package body mips_instr is - - function extract_opc(instr : word_t) return opcode_t is - variable result : opcode_t; - begin - result := instr(31 downto 26); - - return result; - - end extract_opc; - - function extract_rs(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(25 downto 21); - - return result; - - end extract_rs; - - function extract_rt(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(20 downto 16); - - return result; - - end extract_rt; - - function extract_rd(instr : word_t) return reg_ptr_t is - variable result : reg_ptr_t; - begin - result := instr(15 downto 11); - - return result; - - end extract_rd; - - function extract_shamt(instr : word_t) return shamt_t is - variable result : shamt_t; - begin - result := instr(10 downto 6); - - return result; - - end extract_shamt; - - function extract_func(instr : word_t) return func_t is - variable result : func_t; - begin - result := instr(5 downto 0); - - return result; - - end extract_func; - - function extract_simm32(instr : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 16 => instr(15)) & instr(15 downto 0); - - return result; - - end extract_simm32; - - function extract_uimm16(instr : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 16 => '0') & instr(15 downto 0); - - return result; - - end extract_uimm16; - - function extract_jimm32(instr, pc : word_t) return word_t is - variable result : word_t; - begin - result := pc(31 downto 28) & instr(25 downto 0) & "00"; - - return result; - - end extract_jimm32; - - function extract_bimm18(instr, pc : word_t) return word_t is - variable result : word_t; - begin - result := (31 downto 18 => instr(15)) & instr(15 downto 0) & "00"; - - return result; - - end extract_bimm18; - - function decode_op(instr : word_t) return op_t is - variable result : op_t; - variable opc : natural range 0 to 63; - variable func : natural range 0 to 63; - variable rt : natural range 0 to 31; - - begin - - opc := to_integer(extract_opc(instr)); - func := to_integer(extract_func(instr)); - rt := to_integer(extract_rt(instr)); - - result := op_sll; - - case opc is - - when 0 => - case func is - - when 0 => - result := op_sll; - - when 2 => - result := op_srl; - - when 3 => - result := op_sra; - - when 4 => - result := op_sllv; - - when 6 => - result := op_srlv; - - when 7 => - result := op_srav; - - when 8 => - result := op_jr; - - when 9 => - result := op_jalr; - - when 12 => - result := op_syscall; - - when 13 => - result := op_break; - - when 16 => - result := op_mfhi; - - when 17 => - result := op_mthi; - - when 18 => - result := op_mflo; - - when 19 => - result := op_mtlo; - - when 24 => - result := op_mult; - - when 25 => - result := op_multu; - - when 26 => - result := op_div; - - when 27 => - result := op_divu; - - when 32 => - result := op_add; - - when 33 => - result := op_addu; - - when 34 => - result := op_sub; - - when 35 => - result := op_subu; - - when 36 => - result := op_and; - - when 37 => - result := op_or; - - when 38 => - result := op_xor; - - when 39 => - result := op_nor; - - when 42 => - result := op_slt; - - when 43 => - result := op_sltu; - - when others => null; -- undef - - end case; - - when 1 => - case rt is - - when 0 => - result := op_bltz; - - when 1 => - result := op_bgez; - - when 16 => - result := op_bltzal; - - when 17 => - result := op_bgezal; - - when others => null; -- undef - - end case; - - when 2 => - result := op_j; - - when 3 => - result := op_jal; - - when 4 => - result := op_beq; - - when 5 => - result := op_bne; - - when 6 => - result := op_blez; - - when 7 => - result := op_bgtz; - - when 8 => - result := op_addi; - - when 9 => - result := op_addiu; - - when 10 => - result := op_slti; - - when 11 => - result := op_sltiu; - - when 12 => - result := op_andi; - - when 13 => - result := op_ori; - - when 14 => - result := op_xori; - - when 15 => - result := op_lui; - - when 16 => - result := op_cop0; - - when 17 => - result := op_cop1; - - when 18 => - result := op_cop2; - - when 19 => - result := op_cop3; - - when 32 => - result := op_lb; - - when 33 => - result := op_lh; - - when 34 => - result := op_lwl; - - when 35 => - result := op_lw; - - when 36 => - result := op_lbu; - - when 37 => - result := op_lhu; - - when 38 => - result := op_lwr; - - when 40 => - result := op_sb; - - when 41 => - result := op_sh; - - when 42 => - result := op_swl; - - when 43 => - result := op_sw; - - when 46 => - result := op_swr; - - when 49 => - result := op_lwc1; - - when 50 => - result := op_lwc2; - - when 51 => - result := op_lwc3; - - when 57 => - result := op_swc1; - - when 58 => - result := op_swc2; - - when 59 => - result := op_swc3; - - when others => null; -- undef - - end case; - - return result; - - end decode_op; - - function ctrl_lines_default return ctrl_lines_t is - variable result : ctrl_lines_t; - begin - result.cop_instr_en := '0'; - result.jump := '0'; - result.jump_long := '0'; - result.branch := '0'; - result.bc_src := bc_eq_ne; - result.bc_not := '0'; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.shift_right := '0'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_imm; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.imm_src := src_imm16; - result.reg_write := '0'; - result.dmem_we := '0'; - result.dmem_en := '0'; - result.wptr_srcsel := wptr_src_imm; - result.reg_link := '0'; - result.shift_offset := "00"; - result.shift_byp := '1'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '1'; - result.word4_en := '0'; - result.word2_en := '0'; - result.align_left := '0'; - result.load_signed := '0'; - result.mul_access := '0'; - result.mul_hilo_we := '0'; - result.mul_start := '0'; - result.mul_s_un := '0'; - result.mul_mul_divn := '0'; - result.mul_hilo_sel := '1'; - result.exc_break := '0'; - result.exc_syscall := '0'; - result.exc_illegal := '0'; - result.except_en := '0'; - result.alu_exc_en := '0'; - - return result; - - end ctrl_lines_default; - - - function special_ctrl_lines(func : func_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable op : integer range 0 to 2**func_t'length-1; - begin - - result := ctrl_lines_default; - - op := to_integer(func); - case op is - --- when op_add => - when 32 => - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - result.alu_exc_en := '1'; - --- when op_addu => - when 33 => - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_and => - when 36 => - result.alu.outsel := alu_and; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_break => - when 13 => - result.exc_break := '1'; - result.except_en := '1'; - --- when op_div => - when 26 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '1'; - result.mul_mul_divn := '0'; - --- when op_divu => - when 27 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '0'; - result.mul_mul_divn := '0'; - --- when op_jalr => - when 9 => - result.jump_long := '1'; - result.wptr_srcsel := wptr_src_imm; - result.reg_write := '1'; - result.reg_link := '1'; - --- when op_jr => - when 8 => - result.jump_long := '1'; - --- when op_mfhi => - when 16 => - result.reg_write := '1'; - result.mul_access := '1'; - result.mul_hilo_sel := '1'; - --- when op_mflo => - when 18 => - result.reg_write := '1'; - result.mul_access := '1'; - result.mul_hilo_sel := '0'; - --- when op_mthi => - when 17 => - result.mul_hilo_we := '1'; - result.mul_hilo_sel := '1'; - --- when op_mtlo => - when 19 => - result.mul_hilo_we := '1'; - result.mul_hilo_sel := '0'; - --- when op_mult => - when 24 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '1'; - result.mul_mul_divn := '1'; - --- when op_multu => - when 25 => - result.mul_access := '1'; - result.mul_start := '1'; - result.mul_s_un := '0'; - result.mul_mul_divn := '1'; - --- when op_or => - when 37 => - result.alu.outsel := alu_or; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_nor => - when 39 => - result.alu.outsel := alu_nor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_sll => - when 0 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '0'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - --- when op_sllv => - when 4 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '0'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - --- when op_slt => - when 42 => - result.alu.outsel := alu_lts; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_sltu => - when 43 => - result.alu.outsel := alu_ltu; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_sra => - when 3 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '1'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - --- when op_srav => - when 7 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '1'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - --- when op_srl => - when 2 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_imm; - result.reg_write := '1'; - --- when op_srlv => - when 6 => - result.alu.op2_src := alu_src_reg; - result.alu.outsel := alu_shift2; - result.alu.shift_right := '1'; - result.alu.shift_arith := '0'; - result.shamt2_srcsel := sa_src_reg; - result.reg_write := '1'; - --- when op_sub => - when 34 => - result.alu.outsel := alu_adder; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - result.alu_exc_en := '1'; - --- when op_subu => - when 35 => - result.alu.outsel := alu_adder; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - --- when op_syscall => - when 12 => - result.exc_syscall := '1'; - result.except_en := '1'; - --- when op_xor => - when 38 => - result.alu.outsel := alu_xor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_reg; - result.reg_write := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - - return result; - - end special_ctrl_lines; - - function gen_rom_special return rom_special_t is - variable result : rom_special_t; - variable func : func_t; - begin - - for i in 0 to 2**func_t'length-1 loop - func := to_unsigned(i, func_t'length); - result(i) := special_ctrl_lines(func); - end loop; - - return result; - end gen_rom_special; - - function regimm_ctrl_lines(rt : reg_ptr_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable op : integer range 0 to 2**reg_ptr_t'length-1; - begin - - result := ctrl_lines_default; - - op := to_integer(rt); - case op is - --- when op_bgez => - when 1 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '1'; - --- when op_bgezal => - when 17 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '1'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - --- when op_bltz => - when 0 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '0'; - --- when op_bltzal => - when 16 => - result.branch := '1'; - result.bc_src := bc_ltz_gez; - result.bc_not := '0'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - - return result; - - end regimm_ctrl_lines; - - function gen_rom_regimm return rom_regimm_t is - variable result : rom_regimm_t; - variable rt : reg_ptr_t; - begin - - for i in 0 to 2**reg_ptr_t'length-1 loop - rt := to_unsigned(i, reg_ptr_t'length); - result(i) := regimm_ctrl_lines(rt); - end loop; - - return result; - end gen_rom_regimm; - - function opcode_ctrl_lines(opc : opcode_t) return ctrl_lines_t is - variable result : ctrl_lines_t; - variable op : integer range 0 to 2**opcode_t'length-1; - begin - - result := ctrl_lines_default; - - op := to_integer(opc); - case op is - --- when op_addi => - when 8 => - result.imm_src := src_imm32; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - result.alu_exc_en := '1'; - --- when op_addiu => - when 9 => - result.imm_src := src_imm32; - result.alu.outsel := alu_adder; - result.alu.add := '1'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_andi => - when 12 => - result.imm_src := src_imm16; - result.alu.outsel := alu_and; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_beq => - when 4 => - result.branch := '1'; - result.bc_src := bc_eq_ne; - result.bc_not := '0'; - --- when op_bgtz => - when 7 => - result.branch := '1'; - result.bc_src := bc_lez_gtz; - result.bc_not := '1'; - --- when op_blez => - when 6 => - result.branch := '1'; - result.bc_src := bc_lez_gtz; - result.bc_not := '0'; - --- when op_bne => - when 5 => - result.branch := '1'; - result.bc_src := bc_eq_ne; - result.bc_not := '1'; - --- when op_cop => - when 16 | 17 | 18 | 19 => - result.cop_instr_en := '1'; - --- when op_j => - when 2 => - result.jump := '1'; - --- when op_jal => - when 3 => - result.jump := '1'; - result.wptr_srcsel := wptr_src_const; - result.reg_write := '1'; - result.reg_link := '1'; - --- when op_lb => - when 32 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '0'; - result.load_signed := '1'; - result.word4_en := '1'; - --- when op_lbu => - when 36 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '1'; - result.sign_ext_byp := '0'; - result.load_signed := '0'; - result.word4_en := '1'; - --- when op_lh => - when 33 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.sign_ext_byp := '0'; - result.byte_en_byp := '1'; - result.load_signed := '1'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_lhu => - when 37 => - result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.sign_ext_byp := '0'; - result.byte_en_byp := '1'; - result.load_signed := '0'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_lui => - when 15 => - result.imm_src := src_imm16_high; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.alu.outsel := alu_adder; - result.reg_write := '1'; - result.alu.add := '1'; - --- when op_lw => - when 35 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.except_en := '1'; - --- when op_lwl => - when 34 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "01"; - result.align_left := '1'; - --- when op_lwr => - when 38 => --- result.imm_src := src_imm32; - result.dmem_en := '1'; - result.reg_write := '1'; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "00"; - result.align_left := '0'; - --- when op_ori => - when 13 => - result.imm_src := src_imm16; - result.alu.outsel := alu_or; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - --- when op_sb => - when 40 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.word4_en := '1'; - --- when op_sh => - when 41 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.word2_en := '1'; - result.except_en := '1'; - --- when op_slti => - when 10 => - result.alu.outsel := alu_lts; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.imm_src := src_imm32; - result.reg_write := '1'; - --- when op_sltiu => - when 11 => - result.alu.outsel := alu_ltu; - result.alu.add := '0'; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.imm_src := src_imm32; - result.reg_write := '1'; - --- when op_sw => - when 43 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.except_en := '1'; - --- when op_swl => - when 42 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.shift_offset := "01"; - --- when op_swr => - when 46 => - result.dmem_en := '1'; - result.dmem_we := '1'; --- result.imm_src := src_imm32; - result.shift_byp := '0'; - result.byte_en_byp := '0'; - result.align_left := '1'; - --- when op_xori => - when 14 => - result.imm_src := src_imm16; - result.alu.outsel := alu_xor; - result.alu.op1_src := alu_src_reg; - result.alu.op2_src := alu_src_imm; - result.reg_write := '1'; - - when others => - result.exc_illegal := '1'; - - end case; - - return result; - - end opcode_ctrl_lines; - - function gen_rom_opcode return rom_opcode_t is - variable result : rom_opcode_t; - variable opc : opcode_t; - begin - - for i in 0 to 2**opcode_t'length-1 loop - opc := to_unsigned(i, opcode_t'length); - result(i) := opcode_ctrl_lines(opc); - end loop; - - return result; - end gen_rom_opcode; - -end mips_instr; - --------------------------------------------------------------------------- --------------------------------------------------------------------------- - diff --git a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd b/lib/CPUs/MIPS/src/core/mips_muldiv.vhd deleted file mode 100644 index efce36b..0000000 --- a/lib/CPUs/MIPS/src/core/mips_muldiv.vhd +++ /dev/null @@ -1,454 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); -end muldiv; - -architecture Behavioral of muldiv is - - subtype pprod_t is unsigned (39 downto 0); - subtype prod_t is unsigned (63 downto 0); - subtype byte_t is unsigned (7 downto 0); - - type pprod_array_t is array (natural range <>) of pprod_t; - type word_array_t is array (natural range <>) of word_t; - type byte_array_t is array (natural range <>) of byte_t; - - signal pprod : pprod_array_t(0 to 3); - signal sign1 : std_logic; - signal sign2 : std_logic; - signal s1_r : std_logic; - signal s2_r : std_logic; - signal sr_r : std_logic; - signal cy : unsigned (3 downto 0); - signal mul_start : std_logic; - signal mul_en : std_logic; - signal sum_en : std_logic; - signal pre_sum_vld : std_logic; - signal pp_reg : unsigned (63 downto 8); - signal pre_const : word_array_t(0 to 1); - signal result : prod_t; - signal add_op1 : unsigned (39 downto 0); - signal add_op2 : unsigned (39 downto 0); - signal add_res : unsigned (39 downto 0); - signal ppadd_op1 : word_array_t(0 to 3); - signal ppadd_op2 : word_array_t(0 to 3); - signal ppadd_res : word_array_t(0 to 3); - signal ppadd_cyi : unsigned (3 downto 0); - signal ppadd_cyo : unsigned (3 downto 0); - - signal pp_op1_r : word_t; - signal pp_op1 : word_t; - signal pp_op2 : word_t; - signal pp_op2_r : byte_array_t(0 to 3); - signal bsy : std_logic; - - signal div_add_res : unsigned (32 downto 0); - signal div_add_op1 : unsigned (32 downto 0); - signal div_add_op2 : unsigned (32 downto 0); - signal div_add_cyi : std_logic; - signal div_qbit : std_logic; - signal div_start : std_logic; - signal div_en : std_logic; - - signal div_A : unsigned (32 downto 0); - signal div_M : unsigned (32 downto 0); - signal div_M_n : unsigned (32 downto 0); - signal div_Q : word_t; - - type md_state_t is (md_rdy, mul_pre1, mul_pre2, mul_pp, mul_sum, div_process, div_post1, div_post2, div_post3); - signal s, sn : md_state_t; - signal cycle_cnt : natural range 0 to 31; - signal cycle_cnt_preset : natural range 0 to 31; - signal cycle_cnt_load : std_logic; - signal div_fin_en : unsigned (2 downto 0); - --------------------------------------------------------------------------- -begin --- 9A0CD0570B88D78 - - busy <= bsy; - - sign1 <= din_hi(din_hi'left) and s_un; - sign2 <= din_lo(din_lo'left) and s_un; - pp_op1 <= not din_hi when sign1 = '1' else din_hi; - pp_op2 <= not din_lo when sign2 = '1' else din_lo; - --------------------------------------------------------------------------- -md_state: - process(s, start, mul_divn, cycle_cnt) - begin - - bsy <= '1'; - cycle_cnt_load <= '0'; - cycle_cnt_preset <= 7; - - mul_en <= '0'; - div_en <= '0'; - sum_en <= '0'; - pre_sum_vld <= '0'; - mul_start <= '0'; - div_start <= '0'; - div_fin_en <= "000"; - sn <= s; - case s is - when md_rdy => - bsy <= '0'; - if start = '1' then - if mul_divn = '1' then - sn <= mul_pre1; - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 7; - mul_start <= '1'; - else - sn <= div_process; - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 31; - div_start <= '1'; - end if; - end if; - when mul_pre1 => - pre_sum_vld <= '1'; - mul_en <= '1'; - sn <= mul_pre2; - when mul_pre2 => - pre_sum_vld <= '1'; - mul_en <= '1'; - sn <= mul_pp; - when mul_pp => - mul_en <= '1'; - if cycle_cnt = 0 then - cycle_cnt_load <= '1'; - cycle_cnt_preset <= 3; - sn <= mul_sum; - end if; - when mul_sum => - sum_en <= '1'; - if cycle_cnt = 0 then - bsy <= '0'; - sn <= md_rdy; - end if; - when div_process => - div_en <= '1'; - if cycle_cnt = 0 then - sn <= div_post1; - end if; - when div_post1 => - div_fin_en <= "001"; - sn <= div_post2; - when div_post2 => - div_fin_en <= "010"; - sn <= div_post3; - when div_post3 => - div_fin_en <= "100"; - sn <= md_rdy; - bsy <= '0'; - when others => - sn <= md_rdy; - end case; - - end process; - -md_state_next: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - s <= md_rdy; - else - s <= sn; - end if; - end if; - end process; - -md_cycle_cnt: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - cycle_cnt <= 0; - elsif cycle_cnt_load = '1' then - cycle_cnt <= cycle_cnt_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - end if; - end if; - end process; - -proc_out_reg: - process(hilo_sel, result) - begin - if hilo_sel = '1' then - dout <= result(63 downto 32); - else - dout <= result(31 downto 0); - end if; - end process; - -proc_in_reg: - process(clk) - variable pre_cond : unsigned(1 downto 0); - begin - if rising_edge(clk) then - if mul_start = '1' or div_start = '1' then - pp_op1_r <= pp_op1; - pre_const(0) <= (others => '0'); - pre_const(1) <= (others => '0'); - pre_cond := (din_hi(din_hi'left) and s_un) & (din_lo(din_lo'left) and s_un); - s1_r <= pre_cond(1); - s2_r <= pre_cond(0); - sr_r <= pre_cond(0) xor pre_cond(1); - case pre_cond is - when "01" => - pre_const(0) <= din_hi; - pre_const(1) <= X"FFFF_FFFF"; - when "10" => - pre_const(0) <= X"0000_0000"; - pre_const(1) <= X"FFFF_FFFF"; - when "11" => - pre_const(0) <= not din_hi; - pre_const(1) <= X"0000_0001"; - when others => null; - end case; - elsif pre_sum_vld = '1' then - pre_const(0) <= pre_const(1); - end if; - end if; - end process; - -proc_mul_sr: - process(clk) - begin - if rising_edge(clk) then - if mul_start = '1' then - for i in 0 to 3 loop - cy(i) <= '0'; - pprod(i) <= ppadd_res(i) & X"00"; - end loop; - elsif mul_en = '1' then - for i in 0 to 3 loop - cy(i) <= ppadd_cyo(i); - pprod(i) <= ppadd_res(i) & pprod(i)(8 downto 1); - end loop; - elsif sum_en = '1' then - for i in 1 to 3 loop - pprod(i-1) <= pprod(i); - end loop; - end if; - end if; - end process; - -gen_mul32x8pp: - for i in 0 to 3 generate - begin - - pp_adder_mux: - process(mul_start, pp_op1, pp_op2, pp_op1_r, pp_op2_r(i), s1_r, sign1, pprod(i), cy(i)) - variable v2 : unsigned(7 downto 0); - begin - ppadd_cyi(i) <= '0'; - ppadd_op1(i) <= (others => '0'); - if mul_start = '1' then - ppadd_op2(i) <= (others => '0'); - v2 := pp_op2(8*(i+1)-1 downto 8*i); - if v2(0) = '1' then - ppadd_cyi(i) <= sign1; - ppadd_op1(i) <= pp_op1; - end if; - else - ppadd_op2(i) <= cy(i) & pprod(i)(39 downto 9); - v2 := pp_op2_r(i); - if v2(0) = '1' then - ppadd_cyi(i) <= s1_r; - ppadd_op1(i) <= pp_op1_r; - end if; - end if; - end process; - - pp_adder: - process(ppadd_op1(i), ppadd_op2(i), ppadd_cyi(i)) - variable sum_pp : unsigned(33 downto 0); - begin - sum_pp := ('0' & ppadd_op1(i) & ppadd_cyi(i)) + ('0' & ppadd_op2(i) & ppadd_cyi(i)); - ppadd_res(i) <= sum_pp(sum_pp'left-1 downto 1); - ppadd_cyo(i) <= sum_pp(sum_pp'left); - end process; - - proc_mul_ctrl: - process(clk) - begin - if rising_edge(clk) then - if mul_start = '1' then - pp_op2_r(i) <= '0' & pp_op2(8*(i+1)-1 downto 8*i+1); - elsif mul_en = '1' then - pp_op2_r(i) <= '0' & pp_op2_r(i)(7 downto 1); - end if; - end if; - end process; - - end generate; - -comb_mul_adder: - process(add_op1, add_op2) - variable sum_mul : unsigned(39 downto 0); - begin - sum_mul := (add_op1) + (add_op2); - add_res <= sum_mul(sum_mul'left downto 0); - end process; - -comb_mul_adder_mux: - process(pre_const, pre_sum_vld, pp_reg, pprod, sr_r) - variable s_ext : std_logic; - begin - if pre_sum_vld = '1' then - add_op1 <= pp_reg(63 downto 24); - add_op2 <= pre_const(0) & X"00"; - else - s_ext := pp_reg(63) and sr_r; - add_op1 <= (7 downto 0 => s_ext) & pp_reg(63 downto 32); - add_op2 <= pprod(0); - end if; - end process; - -comb_mul: - process(clk) - variable tmp : prod_t; - begin - if rising_edge(clk) then - if mul_start = '1' then - pp_reg <= (others => '0'); - elsif pre_sum_vld = '1' then - pp_reg <= add_res & X"0000"; - elsif sum_en = '1' then - tmp := add_res & pp_reg(31 downto 8); - pp_reg <= tmp(63 downto 8); - result <= tmp; - if sr_r = '1' then - result <= not tmp; - end if; - elsif div_fin_en(1) = '1' then - result(63 downto 32) <= div_A(31 downto 0); - if s1_r = '1' then - result(63 downto 32) <= div_add_res(31 downto 0); - end if; - elsif div_fin_en(2) = '1' then - result(31 downto 0) <= div_Q; - if sr_r = '1' then - result(31 downto 0) <= div_add_res(31 downto 0); - end if; - elsif hilo_we = '1' then - if hilo_sel = '1' then - result(63 downto 32) <= din_hi; - else - result(31 downto 0) <= din_hi; - end if; - end if; - end if; - end process; - -div_adder: - process(div_add_op1, div_add_op2, div_add_cyi) - variable sum_div : unsigned(33 downto 0); - begin - sum_div := (div_add_op1 & div_add_cyi) + (div_add_op2 & div_add_cyi); - div_add_res <= sum_div(sum_div'left downto 1); - end process; - -div_adder_mux: - process(div_start, div_en, div_fin_en, div_A, div_Q, pp_op1, sign1, s1_r, s2_r, sr_r, div_qbit, div_M, div_M_n) - begin - - div_add_cyi <= s2_r xor div_qbit; - div_add_op1 <= div_A(31 downto 0) & div_Q(31); - div_add_op2 <= (others => '0'); - if div_start = '1' then - div_add_op1 <= '0' & pp_op1; - div_add_cyi <= sign1; - elsif div_en = '1' then - div_add_op2 <= div_M; - if div_qbit = '1' then - div_add_op2 <= div_M_n; - end if; - elsif div_fin_en(0) = '1' then - div_add_op2 <= div_M; - div_add_cyi <= s2_r; - div_add_op1 <= '0' & div_A(31 downto 0); - elsif div_fin_en(1) = '1' then - div_add_cyi <= s1_r; - div_add_op1 <= '0' & not div_A(31 downto 0); - elsif div_fin_en(2) = '1' then - div_add_cyi <= sr_r; - div_add_op1 <= '0' & not div_Q; - end if; - end process; - -divide: - process(clk) - variable quo : std_logic; - begin - if rising_edge(clk) then - if div_start = '1' then - div_qbit <= '1'; - div_Q <= div_add_res(31 downto 0); - div_A <= (others => '0'); - if sign2 = '1' then - div_M_n <= '1' & din_lo; - div_M <= '0' & not din_lo; - else - div_M_n <= '1' & not din_lo; - div_M <= '0' & din_lo; - end if; - elsif div_en = '1' then - div_qbit <= not div_add_res(32); - div_A <= div_add_res(32 downto 0); - div_Q <= div_Q(30 downto 0) & not div_add_res(32); - elsif div_fin_en(0) = '1' then - if div_A(32) = '1' then - div_A <= '0' & div_add_res(31 downto 0); - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd b/lib/CPUs/MIPS/src/core/mips_pipeline.vhd deleted file mode 100644 index fbdc1e8..0000000 --- a/lib/CPUs/MIPS/src/core/mips_pipeline.vhd +++ /dev/null @@ -1,914 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The pipeline --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -entity pipeline is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned(5 downto 0); - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_we : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t - ); -end pipeline; - -architecture Behavioral of pipeline is - --------------------------------------------------------------------------- - COMPONENT reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_w : in STD_LOGIC; - en : in STD_LOGIC; - we : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT idecode_rom is - Port - ( - nop : in std_logic; - inst_in : in word_t; - ctrl_out : out ctrl_lines_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT shifter is - Generic - ( - data_width : integer - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT alu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - op2_shifted : in unsigned (data_width-1 downto 0); - ctrl : in alu_ctrl_t; - result : out unsigned (data_width-1 downto 0); - flags : out alu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT bcu is - Generic - ( - data_width : integer - ); - Port - ( - op1_in : in unsigned (data_width-1 downto 0); - op2_in : in unsigned (data_width-1 downto 0); - flags : out bcu_flags_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT cop is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - sdu : in sdu_t; - IR_valid : in STD_LOGIC; - IR : in word_t; - events : in event_t; - ctrl_in : in cop_ctrl_in_t; - ctrl_out : out cop_ctrl_out_t; - din : in word_t; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - start : in std_logic; - s_un : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - --------------------------------------------------------------------------- - constant RESET_VECTOR : word_t := X"BFC00000"; - - signal ID_stage : ID_t; - signal EX_stage : EX_t; - signal MEM_stage : MEM_t; - signal WB_stage : WB_t; - signal clk_2, clk_1 : STD_LOGIC; - signal hdu : hdu_t; - signal sdu : sdu_t; - signal cpu_rst : STD_LOGIC; - signal reg_a : word_t; - signal reg_b : word_t; - signal ctrl_lines : ctrl_lines_t; - signal cpu_run : STD_LOGIC; - signal branch_ce : STD_LOGIC; - signal run_en : STD_LOGIC; - signal mul_dep : STD_LOGIC; - signal imem_dep : STD_LOGIC; - signal dmem_dep : STD_LOGIC; - signal cop_ctrl : cop_ctrl_in_t; - signal cop_stat : cop_ctrl_out_t; - signal cop_din : word_t; - signal cop_dout : word_t; - signal alu_result : word_t; - signal mul_result : word_t; - signal mul_busy : STD_LOGIC; - signal EX_events_instr : event_t; - signal EX_events_alu : event_t; - signal EX_events_mem : event_t; - signal EX_events : event_t; - signal MEM_events : event_t; - signal bcu_op_a : word_t; - signal bcu_op_b : word_t; - signal bcu_flags : bcu_flags_t; - signal vaddr : word_t; - - attribute ram_style : string; - - attribute ram_style of reg_a: signal is "distributed"; - attribute ram_style of reg_b: signal is "distributed"; - - signal pc : pc_t; - --------------------------------------------------------------------------- -begin - - clk_1 <= clk; - clk_2 <= not clk; - cpu_run <= run_en; - - -- Stall Detection Unit --------------------------------------------------- - sdu.ID_nop <= imem_dep or cop_stat.exc_pending or EX_stage.exc or MEM_stage.exc; - sdu.EX_nop <= mul_dep or ID_stage.nop or ID_stage.exc; - sdu.MEM_nop <= EX_stage.nop or EX_stage.exc; - sdu.WB_nop <= dmem_dep or MEM_stage.nop; - - sdu.ID_stall <= dmem_dep or imem_dep or mul_dep or ID_stage.exc; - sdu.EX_stall <= dmem_dep; - sdu.MEM_stall <= dmem_dep; - sdu.WB_stall <= '0'; - - mul_dep <= ID_stage.ctrl.mul_access and (EX_stage.ctrl.mul_start or mul_busy); - imem_dep <= not imem_rdy; - dmem_dep <= not dmem_rdy and MEM_stage.ctrl.dmem_en; - --------------------------------------------------------------------------- - imem_en <= cpu_run and not (mul_dep or dmem_dep or cop_stat.exc_commit); - --------------------------------------------------------------------------- --- Muldiv --------------------------------------------------------------------------- -inst_muldiv: muldiv - PORT MAP - ( - rst => cpu_rst, - clk => clk, - hilo_we => EX_stage.ctrl.mul_hilo_we, - din_hi => EX_stage.reg_a, - din_lo => EX_stage.reg_b, - mul_divn => EX_stage.ctrl.mul_mul_divn, - start => EX_stage.ctrl.mul_start, - s_un => EX_stage.ctrl.mul_s_un, - hilo_sel => EX_stage.ctrl.mul_hilo_sel, - busy => mul_busy, - dout => mul_result - ); - --------------------------------------------------------------------------- --- Coprocessor --------------------------------------------------------------------------- -inst_cop: cop - PORT MAP - ( - rst => cpu_rst, - clk => clk, - sdu => sdu, - events => MEM_stage.events, - IR_valid => ID_stage.ctrl.cop_instr_en, - IR => ID_stage.IR, - ctrl_in => cop_ctrl, - ctrl_out => cop_stat, - dout => cop_dout, - din => cop_din - ); - - cop_ctrl.bd_wb <= WB_stage.bd; - cop_ctrl.epc_mem <= MEM_stage.pcn; - cop_ctrl.epc_wb <= MEM_stage.epc; - cop_ctrl.imem_addr <= pc.nxt; - cop_ctrl.dmem_addr <= MEM_stage.va; - --------------------------------------------------------------------------- --- IF stage --------------------------------------------------------------------------- - imem_addr <= pc.curr; - -proc_stage_pc: - process(pc, rst, cop_stat) - begin - if rst = '1' then - pc.curr <= RESET_VECTOR after 2 ns; - else - if pc.is_branch and cop_stat.exc_pending = '0' then - pc.curr <= pc.pc_branch after 2 ns; - else - pc.curr <= pc.nxt after 2 ns; - end if; - end if; - end process; - -proc_stage_pc_branch: - process(clk_1) - begin - if rising_edge(clk_1) then - if sdu.ID_stall = '0' then - pc.pc_branch <= pc.curr + ID_stage.bimm18; - end if; - end if; - end process; - -proc_stage_pc_next: - process(clk_1) - begin - if rising_edge(clk_1) then - branch_ce <= '0'; - cop_ctrl.exc_left <= '0'; - if rst = '1' then - pc.nxt <= RESET_VECTOR; - pc.last <= RESET_VECTOR; - elsif cop_stat.exc_commit = '1' then - pc.nxt <= cop_stat.exc_vec; - elsif sdu.ID_stall = '0' then - cop_ctrl.exc_left <= cop_stat.exc_exit; - branch_ce <= '1'; - pc.last <= pc.curr; - if ID_stage.ctrl.jump = '1' then - pc.nxt <= ID_stage.jimm32; - elsif ID_stage.ctrl.jump_long = '1' then - pc.nxt <= ID_stage.reg_a; - else - pc.nxt <= pc.curr + 4; - end if; - end if; - end if; - end process; - -proc_stage_branch: - process(clk_2) - begin - if rising_edge(clk_2) and branch_ce = '1' then - pc.is_branch <= false; - if EX_stage.ctrl.branch = '1' then - - case EX_stage.ctrl.bc_src is - - when bc_eq_ne => - if (EX_stage.ctrl.bc_not xor bcu_flags.eq) = '1' then - pc.is_branch <= true; - end if; - - when bc_lez_gtz => - if (EX_stage.ctrl.bc_not xor (bcu_flags.z or bcu_flags.ltz)) = '1' then - pc.is_branch <= true; - end if; - - when bc_ltz_gez => - if (EX_stage.ctrl.bc_not xor bcu_flags.ltz) = '1' then - pc.is_branch <= true; - end if; - - when others => null; - end case; - end if; - end if; - end process; - - process(rst, clk_1) - variable reset_delay : unsigned (5 downto 0); - begin - if rising_edge(clk_1) then - if rst = '1' then - reset_delay := (others => '1'); - cpu_rst <= '1'; - run_en <= '0'; - elsif reset_delay /= (5 downto 0 => '0') then - reset_delay := reset_delay - 1; - else - cpu_rst <= '0'; - end if; - if reset_delay(reset_delay'left-1) = '0' then - run_en <= '1'; - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ID stage --------------------------------------------------------------------------- - ID_stage.IR <= to_01(imem_data); - ID_stage.pcn <= pc.curr; - ID_stage.op <= decode_op(ID_stage.IR); - ID_stage.jimm32 <= extract_jimm32(ID_stage.IR, ID_stage.pcn); - ID_stage.bimm18 <= extract_bimm18(ID_stage.IR, ID_stage.pcn); - ID_stage.shamt <= extract_shamt(ID_stage.IR); - ID_stage.reg_a_rptr <= extract_rs(ID_stage.IR); - ID_stage.reg_b_rptr <= extract_rt(ID_stage.IR); - ID_stage.ctrl <= ctrl_lines; - ID_stage.reg_write <= ID_stage.ctrl.reg_write or cop_stat.reg_write; - ID_stage.epc <= pc.last; - ID_stage.exc <= event_is_active(ID_stage.events); -- Todo: works - ID_stage.nop <= sdu.ID_nop; - -proc_ID_except: - process(ID_stage, cop_stat, pc) - begin - ID_stage.events <= events_clr; - ID_stage.events.inst_load_err <= pc.nxt(1) or pc.nxt(0); - ID_stage.events.inst_priv_addr <= pc.nxt(word_t'left) and cop_stat.user_mode; - end process; - -proc_stage_hdu: - process(ID_stage, EX_stage, MEM_stage, WB_stage) - variable read_a, read_b : boolean; - variable raw_a_EX, raw_a_MEM, raw_a_WB : boolean; - variable raw_b_EX, raw_b_MEM, raw_b_WB : boolean; - variable reg_ptr_a : reg_ptr_t; - variable reg_ptr_b : reg_ptr_t; - begin - - reg_ptr_a := ID_stage.reg_a_rptr; - reg_ptr_b := ID_stage.reg_b_rptr; - raw_a_EX := reg_ptr_a = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_a_MEM := reg_ptr_a = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_a_WB := reg_ptr_a = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - raw_b_EX := reg_ptr_b = EX_stage.reg_wptr and EX_stage.wreg_we = '1'; - raw_b_MEM := reg_ptr_b = MEM_stage.reg_wptr and MEM_stage.wreg_we = '1'; - raw_b_WB := reg_ptr_b = WB_stage.reg_wptr and WB_stage.wreg_we = '1'; - - hdu.alu_fwd_a_ex <= raw_a_EX after 1 ns; - hdu.alu_fwd_a_mem <= raw_a_MEM after 1 ns; - hdu.alu_fwd_a_wb <= raw_a_WB after 1 ns; - hdu.alu_fwd_b_ex <= raw_b_EX after 1 ns; - hdu.alu_fwd_b_mem <= raw_b_MEM after 1 ns; - hdu.alu_fwd_b_wb <= raw_b_WB after 1 ns; - - end process; - -proc_stage_fwd_a: - process(reg_a, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_a; - if hdu.alu_fwd_a_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_a_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_a_wb then - data := WB_stage.data; - end if; - ID_stage.reg_a <= to_01(data) after 2 ns; - end process; - -proc_stage_fwd_b: - process(reg_b, hdu, EX_stage, MEM_stage, WB_stage) - variable data : word_t; - begin - data := reg_b; - if hdu.alu_fwd_b_ex then - data := EX_stage.result; - elsif hdu.alu_fwd_b_mem then - data := MEM_stage.data; - elsif hdu.alu_fwd_b_wb then - data := WB_stage.data; - end if; - ID_stage.reg_b <= to_01(data) after 2 ns; - end process; - -proc_imm_mux: - process(ID_stage) - variable data : word_t; - begin - data := extract_uimm16(ID_stage.IR); - - case ID_stage.ctrl.imm_src is - - when src_imm32 => - data := extract_simm32(ID_stage.IR); - - when src_imm16 => - data := extract_uimm16(ID_stage.IR); - - when src_imm16_high => - data := ID_stage.IR(word_t'length/2-1 downto 0) & (word_t'length/2-1 downto 0 => '0'); - - when others => null; - - end case; - - ID_stage.imm <= data after 2 ns; - - end process; - --------------------------------------------------------------------------- -inst_idecode_rom: idecode_rom - PORT MAP - ( - nop => sdu.ID_nop, - inst_in => ID_stage.IR, - ctrl_out => ctrl_lines - ); - -inst_reg_dual: reg_dual - GENERIC MAP - ( - addr_width => reg_ptr_t'length, - data_width => word_t'length - ) - PORT MAP - ( - clk_w => clk_1, - we => WB_stage.wreg_we, - en => '1', - wptr => WB_stage.reg_wptr, - din => WB_stage.data, - rptr_a => ID_stage.reg_a_rptr, - rptr_b => ID_stage.reg_b_rptr, - dout_a => reg_a, - dout_b => reg_b - ); - --------------------------------------------------------------------------- --- EX stage --------------------------------------------------------------------------- - EX_stage.reg_a_rptr <= extract_rs(EX_stage.IR); - EX_stage.reg_b_rptr <= extract_rt(EX_stage.IR); - EX_stage.result <= mul_result when EX_stage.ctrl.mul_access = '1' else alu_result; - -proc_stage_ID_EX_1: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - EX_stage.op <= NOP; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.reg_write <= '0'; - EX_stage.epc <= (others => '0'); - EX_stage.pcn <= (others => '0'); - EX_stage.events_in <= events_clr; - elsif sdu.EX_stall = '0' then - EX_stage.reg_a <= ID_stage.reg_a; - EX_stage.reg_b <= ID_stage.reg_b; - EX_stage.events_in <= ID_stage.events; - EX_stage.op <= ID_stage.op; - EX_stage.ctrl <= ID_stage.ctrl; - EX_stage.reg_write <= ID_stage.reg_write; - EX_stage.nop <= sdu.EX_nop; - EX_stage.IR <= ID_stage.IR; - EX_stage.pcn <= ID_stage.pcn; - if sdu.EX_nop = '1' then - EX_stage.op <= NOP; - EX_stage.IR <= (others => '0'); - EX_stage.ctrl <= ctrl_lines_default; - EX_stage.reg_write <= '0'; - else - EX_stage.epc <= ID_stage.epc; - end if; - end if; - end if; - end process; - -proc_stage_EX_instr_except: - process(EX_stage) - begin - EX_events_instr <= events_clr; - EX_events_instr.illegal <= EX_stage.ctrl.exc_illegal; - EX_events_instr.break <= EX_stage.ctrl.exc_break; - EX_events_instr.syscall <= EX_stage.ctrl.exc_syscall; - end process; - -proc_stage_EX_alu_except: - process(EX_stage) - begin - EX_events_alu <= events_clr; - if EX_stage.ctrl.alu_exc_en = '1' then - if EX_stage.alu_flags.ovf = '1' then - EX_events_alu.alu_ovf <= '1'; - end if; - if EX_stage.alu_flags.uvf = '1' then - EX_events_alu.alu_uvf <= '1'; - end if; - end if; - end process; - - vaddr <= ID_stage.reg_a + extract_simm32(ID_stage.IR); - -proc_stage_EX_mem_except: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - dmem_en <= '0'; - elsif sdu.EX_stall = '0' then - EX_events_mem <= events_clr; - dmem_en <= '0'; - if ID_stage.ctrl.dmem_en = '1' then - dmem_en <= '1'; - if ID_stage.ctrl.except_en = '1' then - if ID_stage.ctrl.word2_en = '1' then - if vaddr(0) = '1' then - EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we; - EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we; - dmem_en <= '0'; - end if; - elsif vaddr(1 downto 0) /= "00" then - EX_events_mem.data_load_err <= not ID_stage.ctrl.dmem_we; - EX_events_mem.data_store_err <= ID_stage.ctrl.dmem_we; - dmem_en <= '0'; - end if; - end if; - end if; - end if; - end if; - end process; - -proc_stage_DMEM_ADDR: - process(clk_1) - begin - if rising_edge(clk_1) then - if sdu.EX_stall = '0' then --and ID_stage.ctrl.dmem_en = '1' then - EX_stage.va <= vaddr; - if cop_stat.RE = '1' then - EX_stage.pa_off <= not vaddr(1 downto 0); - else - EX_stage.pa_off <= vaddr(1 downto 0); - end if; - end if; - end if; - end process; - dmem_we <= store_be(EX_stage.pa_off, EX_stage.ctrl.dmem_we, EX_stage.ctrl.word2_en, EX_stage.ctrl.word4_en, EX_stage.ctrl.align_left, EX_stage.ctrl.byte_en_byp) after 1 ns; - dmem_re <= not EX_stage.ctrl.dmem_we; - dmem_dout <= store_shift(EX_stage.reg_b, EX_stage.pa_off, EX_stage.ctrl.shift_offset, EX_stage.ctrl.shift_byp) after 1ns; - dmem_addr <= EX_stage.va; - cop_din <= EX_stage.reg_b; - EX_stage.events <= EX_events_instr or EX_events_mem or EX_events_alu or EX_stage.events_in; - EX_stage.exc <= event_is_active(EX_stage.events); - --------------------------------------------------------------------------- -proc_wptr_mux: - process(EX_stage) - variable opclass : opcode_t; - variable reg_wptr : reg_ptr_t; - begin - - opclass := extract_opc(EX_stage.IR); - case opclass is - when "000000" => - reg_wptr := extract_rd(EX_stage.IR); - when others => - reg_wptr := extract_rt(EX_stage.IR); - end case; - - EX_stage.wreg_we <= EX_stage.reg_write after 1 ns; - if reg_wptr = "00000" then - EX_stage.wreg_we <= '0' after 1 ns; - end if; - - EX_stage.reg_wptr <= reg_wptr after 1 ns; - case EX_stage.ctrl.wptr_srcsel is - when wptr_src_imm => - EX_stage.reg_wptr <= reg_wptr after 1 ns; - - when wptr_src_const => - EX_stage.reg_wptr <= to_unsigned(31, reg_ptr_t'length) after 1 ns; - EX_stage.wreg_we <= '1' after 1 ns; - - when others => null; - end case; - - end process; - --------------------------------------------------------------------------- -proc_stage_bcu_op: - process(clk_1) - begin - if rising_edge(clk_1) then - bcu_op_a <= ID_stage.reg_a; - bcu_op_b <= ID_stage.reg_b; - end if; - end process; - -alu_op1_mux: - process(EX_stage) - variable data : word_t; - begin - - data := EX_stage.reg_a; - --- case EX_stage.ctrl.alu.op1_src is --- --- when alu_src_reg => --- data := EX_stage.reg_a; --- --- when alu_src_muldiv => --- data := mul_result; --- --- when others => null; --- --- end case; - - EX_stage.alu_op1 <= data; - - end process; - -alu_op2_mux: - process(clk_1) - variable data : word_t; - begin - - if rising_edge(clk_1) and sdu.EX_stall = '0' then - data := ID_stage.reg_b; - - case ID_stage.ctrl.alu.op2_src is - - when alu_src_reg => - data := ID_stage.reg_b; - - when alu_src_imm => - data := ID_stage.imm; - - when others => null; - - end case; - - EX_stage.alu_op2 <= data; - end if; - - end process; - -shifter_sa_mux: - process(clk_1) - variable data : shamt_t; - variable data_inv : shamt_t; - - begin - if rising_edge(clk_1) and sdu.EX_stall = '0' then - data := ID_stage.reg_a(4 downto 0); - case ID_stage.ctrl.shamt2_srcsel is - - when sa_src_reg => - data := ID_stage.reg_a(4 downto 0); - - when sa_src_imm => - data := ID_stage.shamt; - - when others => null; - - end case; - data_inv := not data + 1; - if ID_stage.ctrl.alu.shift_right = '0' then - EX_stage.shift_ctrl.shamt_rnd <= data_inv after 2 ns; - else - EX_stage.shift_ctrl.shamt_rnd <= data after 2 ns; - end if; - EX_stage.shift_ctrl.shamt_nrm <= data after 1 ns; - EX_stage.shift_ctrl.shift_right <= ID_stage.ctrl.alu.shift_right; - EX_stage.shift_ctrl.shift_arith <= ID_stage.ctrl.alu.shift_arith; - end if; - - end process; - --------------------------------------------------------------------------- -inst_shifter: shifter - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - shift_ctrl => EX_stage.shift_ctrl, - din => EX_stage.reg_b, - dout => EX_stage.alu_op2_s - ); - -inst_alu: alu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => EX_stage.alu_op1, - op2_in => EX_stage.alu_op2, - op2_shifted => EX_stage.alu_op2_s, - ctrl => EX_stage.ctrl.alu, - result => alu_result, - flags => EX_stage.alu_flags - ); - -inst_bcu: bcu - GENERIC MAP - ( - data_width => word_t'length - ) - PORT MAP - ( - op1_in => bcu_op_a, - op2_in => bcu_op_b, - flags => bcu_flags - ); - --------------------------------------------------------------------------- --- MEM stage --------------------------------------------------------------------------- -proc_stage_MEM_n: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - MEM_stage.op <= NOP; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - MEM_stage.pa_off <= (others => '0'); - MEM_stage.events_in <= events_clr; --- MEM_stage.epc <= (others => '0'); --- MEM_stage.pcn <= (others => '0'); --- MEM_stage.va <= (others => '0'); --- MEM_stage.reg_wptr <= (others => '0'); --- MEM_stage.ex_result <= (others => '0'); - elsif sdu.MEM_stall = '0' then - MEM_stage.events_in <= EX_stage.events; - MEM_stage.op <= EX_stage.op; - MEM_stage.wreg_we <= EX_stage.wreg_we; - MEM_stage.ctrl <= EX_stage.ctrl; - MEM_stage.va <= EX_stage.va; - MEM_stage.pa_off <= EX_stage.pa_off; - MEM_stage.reg_wptr <= EX_stage.reg_wptr; - MEM_stage.nop <= sdu.MEM_nop; - if EX_stage.ctrl.dmem_en = '1' then - MEM_stage.ex_result <= EX_stage.reg_b; - else - MEM_stage.ex_result <= EX_stage.result; - if cop_stat.cop_read = '1' then - MEM_stage.ex_result <= cop_dout; - end if; - end if; - if sdu.MEM_nop = '1' then - MEM_stage.op <= NOP; - MEM_stage.wreg_we <= '0'; - MEM_stage.ctrl <= ctrl_lines_default; - else - MEM_stage.pcn <= EX_stage.pcn; - MEM_stage.epc <= EX_stage.epc; - end if; - end if; - end if; - end process; - -proc_stage_MEM_mux: - process(MEM_stage, dmem_din) - variable temp1 : word_t; - variable temp2 : word_t; - variable data : word_t; - variable be : unsigned(3 downto 0); - begin - data := MEM_stage.ex_result; - be := load_be(MEM_stage.pa_off, MEM_stage.ctrl.align_left, MEM_stage.ctrl.byte_en_byp); - if MEM_stage.ctrl.reg_link = '1' then - data := MEM_stage.pcn + 4; - elsif MEM_stage.ctrl.dmem_en = '1' then - temp1 := load_shift(dmem_din, MEM_stage.pa_off, MEM_stage.ctrl.shift_offset, MEM_stage.ctrl.shift_byp); - temp2 := load_sign_ext(temp1, MEM_stage.ctrl.sign_ext_byp, MEM_stage.ctrl.load_signed, MEM_stage.ctrl.word2_en, MEM_stage.ctrl.word4_en); - if be(0) = '1' then - data(7 downto 0) := temp2(7 downto 0); - end if; - if be(1) = '1' then - data(15 downto 8) := temp2(15 downto 8); - end if; - if be(2) = '1' then - data(23 downto 16) := temp2(23 downto 16); - end if; - if be(3) = '1' then - data(31 downto 24) := temp2(31 downto 24); - end if; - end if; - MEM_stage.data <= data after 1 ns; - - end process; - -proc_stage_MEM_except: - process(MEM_stage, int) - begin - MEM_stage.events <= MEM_stage.events_in; - MEM_stage.events.Int <= int; - end process; - - MEM_stage.exc <= cop_stat.int or event_is_active(MEM_stage.events_in); - --------------------------------------------------------------------------- --- WB stage --------------------------------------------------------------------------- -proc_stage_WB_p: - process(clk_1) - begin - if rising_edge(clk_1) then - if rst = '1' then - WB_stage.op <= NOP; - WB_stage.wreg_we <= '0'; --- WB_stage.epc <= (others => '0'); --- WB_stage.reg_wptr <= (others => '0'); --- WB_stage.data <= (others => '0'); - elsif sdu.WB_stall = '0' then - WB_stage.op <= MEM_stage.op; - WB_stage.wreg_we <= MEM_stage.wreg_we; - WB_stage.reg_wptr <= MEM_stage.reg_wptr; - WB_stage.data <= MEM_stage.data; - WB_stage.nop <= sdu.WB_nop; - if sdu.WB_nop = '1' then - WB_stage.op <= NOP; - WB_stage.wreg_we <= '0'; - else - WB_stage.epc <= MEM_stage.epc; - WB_stage.bd <= MEM_stage.ctrl.branch or MEM_stage.ctrl.jump or MEM_stage.ctrl.jump_long; -- Todo: works - end if; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/core/mips_reg.vhd b/lib/CPUs/MIPS/src/core/mips_reg.vhd deleted file mode 100644 index da76225..0000000 --- a/lib/CPUs/MIPS/src/core/mips_reg.vhd +++ /dev/null @@ -1,81 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: On-Chip work registers --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity reg_dual is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clk_w : in STD_LOGIC; - we : in STD_LOGIC; - en : in STD_LOGIC; - wptr : in unsigned (addr_width-1 downto 0); - din : in unsigned (data_width-1 downto 0); - rptr_a : in unsigned (addr_width-1 downto 0); - rptr_b : in unsigned (addr_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end reg_dual; - -architecture Behavioral of reg_dual is - - constant depth : integer := 2**addr_width; - type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0); - - function mem_clear(depth : natural) return mem_t is - variable result : mem_t; - begin - for i in 0 to depth-1 loop - result(i) := (others => '0'); - end loop; - return result; - end mem_clear; - - signal reg_mem : mem_t := mem_clear(depth); - -begin - -reg_in: - process(clk_w) - begin - if rising_edge(clk_w) then - if we = '1' and en = '1' then - reg_mem(to_integer(wptr)) <= din; - end if; - end if; - end process; - - dout_a <= reg_mem(to_integer(rptr_a)) after 2 ns; - dout_b <= reg_mem(to_integer(rptr_b)) after 2 ns; - -end Behavioral; - diff --git a/lib/CPUs/MIPS/src/core/mips_shifter.vhd b/lib/CPUs/MIPS/src/core/mips_shifter.vhd deleted file mode 100644 index cff2c7d..0000000 --- a/lib/CPUs/MIPS/src/core/mips_shifter.vhd +++ /dev/null @@ -1,114 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The shifter unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity shifter is - Generic - ( - data_width : integer := 8 - ); - Port - ( - shift_ctrl : in shift_ctrl_t; - din : in unsigned (data_width-1 downto 0); - dout : out unsigned (data_width-1 downto 0) - ); -end shifter; - -architecture Behavioral of shifter is - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 5) of word_t; - - signal rot_data : word_array_t; - signal sa_rnd : unsigned (4 downto 0); - signal fill : std_logic; - --------------------------------------------------------------------------- -function rot_stage(x : unsigned; en : std_logic; stage_num : natural) return unsigned is - variable result : unsigned(x'range); - constant sa : natural := 2**stage_num; - begin - if en = '1' then - result := x(sa-1 downto 0) & x(x'left downto sa); - else - result := x; - end if; - return result; - -end rot_stage; - -function rot_fill(x : unsigned; fill : std_logic; shift_right : std_logic; sa : natural) return unsigned is - variable result : unsigned(x'range) := (others => '0'); - variable j : integer; - begin - - if shift_right = '0' then - for i in 0 to x'left loop - if i >= sa then - result(i) := x(i); - else - result(i) := fill; - end if; - end loop; - else - j := x'left; - for i in 0 to x'left loop - if i < sa then - result(j) := fill; - else - result(j) := x(j); - end if; - j := j - 1; - end loop; - end if; - return result; - -end rot_fill; - --------------------------------------------------------------------------- -begin - - rot_data(0) <= din; - -gen_rotate_right: - for stage in 0 to 4 generate - begin - rot_data(stage+1) <= rot_stage(rot_data(stage), sa_rnd(stage), stage); - end generate; - - sa_rnd <= shift_ctrl.shamt_rnd; - fill <= shift_ctrl.shift_arith and din(data_width-1); - dout <= rot_fill(rot_data(5), fill, shift_ctrl.shift_right, to_integer(shift_ctrl.shamt_nrm)) after 5 ns; --- dout <= rot_data(5); - - - --------------------------------------------------------------------------- -end Behavioral; - diff --git a/lib/CPUs/MIPS/src/core/mips_top.vhd b/lib/CPUs/MIPS/src/core/mips_top.vhd deleted file mode 100644 index 3d25c3e..0000000 --- a/lib/CPUs/MIPS/src/core/mips_top.vhd +++ /dev/null @@ -1,164 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_top is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - int : in unsigned (5 downto 0); - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_en : out STD_LOGIC; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_din : in unsigned (WORD_WIDTH-1 downto 0); - mem_dout : out unsigned (WORD_WIDTH-1 downto 0); - mem_addr : out unsigned (WORD_WIDTH-1 downto 0) - ); - -end mips_top; - -architecture rtl of mips_top is - - COMPONENT pipeline is - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned (5 downto 0); - imem_rdy : in STD_LOGIC; - imem_en : out STD_LOGIC; - imem_addr : out word_t; - imem_data : in word_t; - dmem_rdy : in STD_LOGIC; - dmem_en : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_we : out unsigned(3 downto 0); - dmem_addr : out word_t; - dmem_din : in word_t; - dmem_dout : out word_t - ); - END COMPONENT; - signal halt : std_logic; - signal imem_rdy : std_logic; - signal imem_en : std_logic; - signal imem_addr : word_t; - signal imem_din : word_t; - signal dmem_rdy : std_logic; - signal dmem_en : std_logic; - signal dmem_re : std_logic; - signal dmem_addr : word_t; - signal dmem_dout : word_t; - signal dmem_din : word_t; - signal dmem_we : unsigned(3 downto 0); - - COMPONENT bui - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - cpu_wait : out STD_LOGIC; - cpu_imem_rdy : out STD_LOGIC; - cpu_imem_en : in STD_LOGIC; - cpu_imem_addr : in word_t; - cpu_imem_din : out word_t; - cpu_dmem_rdy : out STD_LOGIC; - cpu_dmem_en : in STD_LOGIC; - cpu_dmem_re : in STD_LOGIC; - cpu_dmem_we : in unsigned(3 downto 0); - cpu_dmem_addr : in word_t; - cpu_dmem_din : out word_t; - cpu_dmem_dout : in word_t; - mem_valid : in STD_LOGIC; - mem_rdy : in STD_LOGIC; - mem_addr : out word_t; - mem_din : in word_t; - mem_dout : out word_t; - mem_re : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_ce : out STD_LOGIC - ); - END COMPONENT; - -begin - -------------------------------------------------------------------- - -inst_pipeline: pipeline - PORT MAP - ( - rst => rst, - clk => clk, - halt => halt, - int => int, - imem_rdy => imem_rdy, - imem_en => imem_en, - imem_addr => imem_addr, - imem_data => imem_din, - dmem_rdy => dmem_rdy, - dmem_en => dmem_en, - dmem_re => dmem_re, - dmem_we => dmem_we, - dmem_addr => dmem_addr, - dmem_din => dmem_din, - dmem_dout => dmem_dout - ); - -inst_bui: bui - PORT MAP - ( - rst => rst, - clk => clk, - ce => '1', - cpu_wait => halt, - cpu_imem_rdy => imem_rdy, - cpu_imem_en => imem_en, - cpu_imem_addr => imem_addr, - cpu_imem_din => imem_din, - cpu_dmem_rdy => dmem_rdy, - cpu_dmem_en => dmem_en, - cpu_dmem_re => dmem_re, - cpu_dmem_we => dmem_we, - cpu_dmem_addr => dmem_addr, - cpu_dmem_din => dmem_din, - cpu_dmem_dout => dmem_dout, - mem_valid => mem_valid, - mem_rdy => mem_rdy, - mem_addr => mem_addr, - mem_din => mem_din, - mem_dout => mem_dout, - mem_re => mem_re, - mem_we => mem_we, - mem_ce => mem_en - ); - -end rtl; diff --git a/lib/CPUs/MIPS/src/core/mips_types.vhd b/lib/CPUs/MIPS/src/core/mips_types.vhd deleted file mode 100644 index 0dec8a1..0000000 --- a/lib/CPUs/MIPS/src/core/mips_types.vhd +++ /dev/null @@ -1,620 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Types, constants and functions for JIPS --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - - --------------------------------------------------------------------------- -package mips_types is - - -- Revision of the CPU - constant REVISION : integer := 1; - constant WORD_WIDTH : integer := 32; - - --Types - subtype instr_name_t is string(1 to 12); - type instr_name_array_t is array (0 to 63) of instr_name_t; - subtype opcode_t is unsigned (5 downto 0); - subtype word_t is unsigned (WORD_WIDTH-1 downto 0); - subtype reg_ptr_t is unsigned (4 downto 0); - subtype shamt_t is unsigned(4 downto 0); - subtype sa_t is natural range 0 to 63; - subtype func_t is unsigned(5 downto 0); - - type opclass_t is (special, regimm, opcode); - - type op_t is - ( - nop, - op_sll, - op_srl, - op_sra, - op_sllv, - op_srlv, - op_srav, - op_jr, - op_jalr, - op_syscall, - op_break, - op_mfhi, - op_mthi, - op_mflo, - op_mtlo, - op_mult, - op_multu, - op_div, - op_divu, - op_add, - op_addu, - op_sub, - op_subu, - op_and, - op_or, - op_xor, - op_nor, - op_slt, - op_sltu, - op_bltz, - op_bgez, - op_bltzal, - op_bgezal, - op_j, - op_jal, - op_beq, - op_bne, - op_blez, - op_bgtz, - op_addi, - op_addiu, - op_slti, - op_sltiu, - op_andi, - op_ori, - op_xori, - op_lui, - op_lb, - op_lh, - op_lwl, - op_lw, - op_lbu, - op_lhu, - op_lwr, - op_sb, - op_sh, - op_swl, - op_sw, - op_swr, - op_cop0, - op_cop1, - op_cop2, - op_cop3, - op_lwc1, - op_lwc2, - op_lwc3, - op_swc1, - op_swc2, - op_swc3 - ); - - attribute ENUM_ENCODING : string; - - type imm_src_t is (src_imm32, src_imm16, src_imm16_high); - type sa_src_t is (sa_src_reg, sa_src_imm); - type alu_src1_t is (alu_src_reg); - type alu_src2_t is (alu_src_reg, alu_src_imm); - type bc_src_t is (bc_eq_ne, bc_lez_gtz, bc_ltz_gez); - type shift_opsel_t is (shift_sll, shift_srl, shift_sra); - type wptr_src_t is (wptr_src_imm, wptr_src_const); - --- attribute ENUM_ENCODING of itype_t: type is "ONE-HOT"; - - type pc_t is record - curr : word_t; - last : word_t; - nxt : word_t; - pc_branch : word_t; - is_branch : boolean; - end record; - - type alu_outsel_t is - ( - alu_adder, - alu_shift2, - alu_and, - alu_or, - alu_xor, - alu_nor, - alu_ltu, - alu_lts - ); - - type alu_flags_t is record - c : STD_LOGIC; - uvf : STD_LOGIC; - ovf : STD_LOGIC; - ltu : STD_LOGIC; - lts : STD_LOGIC; - end record; - - type bcu_flags_t is record - z : STD_LOGIC; - eq : STD_LOGIC; - ltz : STD_LOGIC; - end record; - - type event_t is record - Int : unsigned(5 downto 0); - data_load_err : STD_LOGIC; - data_store_err : STD_LOGIC; - inst_load_err : STD_LOGIC; - inst_priv_addr : STD_LOGIC; - alu_ovf : STD_LOGIC; - alu_uvf : STD_LOGIC; - syscall : STD_LOGIC; - break : STD_LOGIC; - illegal : STD_LOGIC; - end record; - - type exc_flags_t is record - Int : STD_LOGIC; - DAdEL : STD_LOGIC; - DAdES : STD_LOGIC; - IAdEL : STD_LOGIC; - IAdEK : STD_LOGIC; - Ov : STD_LOGIC; - Sys : STD_LOGIC; - Bp : STD_LOGIC; - RI : STD_LOGIC; - IBE : STD_LOGIC; - DBE : STD_LOGIC; - end record; - - type except_t is record - act : STD_LOGIC; - epc : word_t; - cause : word_t; - end record; - - type cop_ctrl_in_t is record - bd_wb : STD_LOGIC; - epc_mem : word_t; - epc_wb : word_t; - imem_addr : word_t; - dmem_addr : word_t; - exc_left : STD_LOGIC; - end record; - - type cop_ctrl_out_t is record - RE : STD_LOGIC; - ee : STD_LOGIC; - ec : STD_LOGIC; - exc_commit : STD_LOGIC; - exc_pending : STD_LOGIC; - exc_exit : STD_LOGIC; - reg_write : STD_LOGIC; - cop_read : STD_LOGIC; - user_mode : STD_LOGIC; - int : STD_LOGIC; - exc_vec : word_t; - end record; - - type sdu_t is record - ID_nop : STD_LOGIC; - EX_nop : STD_LOGIC; - MEM_nop : STD_LOGIC; - WB_nop : STD_LOGIC; - ID_stall : STD_LOGIC; - EX_stall : STD_LOGIC; - MEM_stall : STD_LOGIC; - WB_stall : STD_LOGIC; - end record; - - type hdu_t is record - alu_fwd_a_ex : boolean; - alu_fwd_a_mem : boolean; - alu_fwd_a_wb : boolean; - alu_fwd_b_ex : boolean; - alu_fwd_b_mem : boolean; - alu_fwd_b_wb : boolean; - end record; - - type alu_ctrl_t is record - outsel : alu_outsel_t; - add : STD_LOGIC; - shift_right : STD_LOGIC; - shift_arith : STD_LOGIC; - op1_src : alu_src1_t; - op2_src : alu_src2_t; - end record; - - type shift_ctrl_t is record - shamt_nrm : shamt_t; - shamt_rnd : shamt_t; - shift_right : STD_LOGIC; - shift_arith : STD_LOGIC; - end record; - - type ctrl_lines_t is record - branch : STD_LOGIC; - jump_long : STD_LOGIC; - jump : STD_LOGIC; - bc_not : STD_LOGIC; - bc_src : bc_src_t; - imm_src : imm_src_t; - alu : alu_ctrl_t; - reg_write : STD_LOGIC; - reg_link : STD_LOGIC; - dmem_we : STD_LOGIC; - dmem_en : STD_LOGIC; - shamt2_srcsel : sa_src_t; - wptr_srcsel : wptr_src_t; - cop_instr_en : STD_LOGIC; - shift_offset : unsigned(1 downto 0); - shift_byp : STD_LOGIC; - byte_en_byp : STD_LOGIC; - sign_ext_byp : STD_LOGIC; - word4_en : STD_LOGIC; - word2_en : STD_LOGIC; - align_left : STD_LOGIC; - load_signed : STD_LOGIC; - mul_access : STD_LOGIC; - mul_hilo_we : STD_LOGIC; - mul_mul_divn : STD_LOGIC; - mul_start : STD_LOGIC; - mul_s_un : STD_LOGIC; - mul_hilo_sel : STD_LOGIC; - exc_break : STD_LOGIC; - exc_syscall : STD_LOGIC; - exc_illegal : STD_LOGIC; - except_en : STD_LOGIC; - alu_exc_en : STD_LOGIC; - end record; - - type ID_t is record - nop : STD_LOGIC; - exc : std_logic; - IR : word_t; - op : op_t; - pcn : word_t; - epc : word_t; - jimm32 : word_t; - bimm18 : word_t; - imm : word_t; - shamt : shamt_t; - ctrl : ctrl_lines_t; - reg_write : STD_LOGIC; - reg_a_rptr : reg_ptr_t; - reg_b_rptr : reg_ptr_t; - reg_a : word_t; - reg_b : word_t; - events : event_t; - end record; - - type EX_t is record - nop : STD_LOGIC; - exc : std_logic; - IR : word_t; - op : op_t; - pcn : word_t; - epc : word_t; - reg_a : word_t; - reg_b : word_t; - ctrl : ctrl_lines_t; - shift_ctrl : shift_ctrl_t; - alu_op1 : word_t; - alu_op2 : word_t; - alu_op2_s : word_t; - alu_flags : alu_flags_t; - result : word_t; - reg_write : STD_LOGIC; - wreg_we : STD_LOGIC; - reg_wptr : reg_ptr_t; - reg_a_rptr : reg_ptr_t; - reg_b_rptr : reg_ptr_t; - va : word_t; - pa_off : unsigned(1 downto 0); - events_in : event_t; - events : event_t; - end record; - - type MEM_t is record - nop : STD_LOGIC; - exc : std_logic; - op : op_t; - pcn : word_t; - epc : word_t; - ctrl : ctrl_lines_t; - ex_result : word_t; - reg_wptr : reg_ptr_t; - wreg_we : STD_LOGIC; - data : word_t; - va : word_t; - pa_off : unsigned(1 downto 0); - events_in : event_t; - events : event_t; - end record; - - type WB_t is record - nop : STD_LOGIC; - op : op_t; - epc : word_t; - reg_wptr : reg_ptr_t; - wreg_we : STD_LOGIC; - data : word_t; - bd : STD_LOGIC; - end record; - - - type rom_special_t is array (0 to 2**func_t'length-1) of ctrl_lines_t; - type rom_regimm_t is array (0 to 2**reg_ptr_t'length-1) of ctrl_lines_t; - type rom_opcode_t is array (0 to 2**opcode_t'length-1) of ctrl_lines_t; - - function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t; - function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned; - function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t; - function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned; - function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t; - function events_clr return event_t; - function event_is_active(e : event_t) return std_logic; - function "or" (a, b : event_t) return event_t; - -end mips_types; - --------------------------------------------------------------------------- -package body mips_types is - - function store_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is - variable stage1 : word_t; - variable result : word_t; - variable sa : unsigned(1 downto 0); - begin - - if bypass = '1' then - sa := "00"; - else - sa := va + shift_off; - end if; - - stage1 := x; - if sa(0) = '1' then - stage1 := x(23 downto 0) & x(31 downto 24); - end if; - result := stage1; - if sa(1) = '1' then - result := stage1(15 downto 0) & stage1(31 downto 16); - end if; - - return result; - end store_shift; - --------------------------------------------------------------------------- - function store_be(va : unsigned(1 downto 0); be_src, word2_en, word4_en, align_left, bypass : std_logic) return unsigned is - variable result : unsigned(3 downto 0); - begin - if bypass = '1' then - result := (3 downto 0 => be_src); - elsif word2_en = '1' then - case va is - when "00" | "01" => - result := "00" & be_src & be_src; - when "10" | "11" => - result := be_src & be_src & "00"; - when others => - result := "0000"; - end case; - elsif word4_en = '1' then - case va is - when "00" => - result := "000" & be_src; - when "01" => - result := "00" & be_src & '0'; - when "10" => - result := '0' & be_src & "00"; - when "11" => - result := be_src & "000"; - when others => - result := "0000"; - end case; - elsif align_left = '1' then - case va is - when "00" => - result := be_src & be_src & be_src & be_src; - when "01" => - result := be_src & be_src & be_src & '0'; - when "10" => - result := be_src & be_src & "00"; - when "11" => - result := be_src & "000"; - when others => - result := "0000"; - end case; - else - case va is - when "00" => - result := "000" & be_src; - when "01" => - result := "00" & be_src & be_src; - when "10" => - result := '0' & be_src & be_src & be_src; - when "11" => - result := be_src & be_src & be_src & be_src; - when others => - result := "0000"; - end case; - end if; - - return result; - - end store_be; - --------------------------------------------------------------------------- - function load_shift(x : word_t; va, shift_off : unsigned(1 downto 0); bypass : std_logic) return word_t is - variable stage1 : word_t; - variable result : word_t; - variable sa : unsigned(1 downto 0); - - begin - if bypass = '1' then - sa := "00"; - else - sa := va + shift_off; - end if; - - stage1 := x; - if sa(0) = '1' then - stage1 := x(7 downto 0) & x(31 downto 8); - end if; - result := stage1; - if sa(1) = '1' then - result := stage1(15 downto 0) & stage1(31 downto 16); - end if; - - return result; - end load_shift; - --------------------------------------------------------------------------- - function load_be(va : unsigned(1 downto 0); align_left, bypass : std_logic) return unsigned is - variable result : unsigned(3 downto 0); - begin - if bypass = '1' then - result := (3 downto 0 => '1'); - elsif align_left = '1' then - case va is - when "00" => - result := "1000"; - when "01" => - result := "1100"; - when "10" => - result := "1110"; - when "11" => - result := "1111"; - when others => - result := "0000"; - end case; - else - case va is - when "00" => - result := "1111"; - when "01" => - result := "0111"; - when "10" => - result := "0011"; - when "11" => - result := "0001"; - when others => - result := "0000"; - end case; - end if; - - return result; - - end load_be; - --------------------------------------------------------------------------- - function load_sign_ext(x : word_t; bypass, signed, word2_en, word4_en : std_logic) return word_t is - variable result : word_t; - variable sign : std_logic; - - begin - if bypass = '1' then - result := x; - elsif word2_en = '1' then - sign := signed and x(15); - result := (31 downto 16 => sign) & x(15 downto 0); - else - sign := signed and x(7); - result := (31 downto 8 => sign) & x(7 downto 0); - end if; - - return result; - end load_sign_ext; - --------------------------------------------------------------------------- - function events_clr return event_t is - variable result : event_t; - begin - result.Int := (others => '0'); - result.data_load_err := '0'; - result.data_store_err := '0'; - result.inst_load_err := '0'; - result.inst_priv_addr := '0'; - result.alu_ovf := '0'; - result.alu_uvf := '0'; - result.syscall := '0'; - result.break := '0'; - result.illegal := '0'; - - return result; - - end events_clr; - - function event_is_active(e : event_t) return std_logic is - variable result : std_logic; - begin - result := '0'; - - for i in e.Int'range loop - result := result or e.Int(i); - end loop; - - result := result or e.data_load_err; - result := result or e.data_store_err; - result := result or e.inst_load_err; - result := result or e.inst_priv_addr; - result := result or e.alu_ovf; - result := result or e.alu_uvf; - result := result or e.syscall; - result := result or e.break; - result := result or e.illegal; - - return result; - - end event_is_active; - - function "or" (a, b : event_t) return event_t is - variable result : event_t; - begin - for i in a.Int'range loop - result.Int(i) := a.Int(i) or b.Int(i); - end loop; - result.data_load_err := a.data_load_err or b.data_load_err; - result.data_store_err := a.data_store_err or b.data_store_err; - result.inst_load_err := a.inst_load_err or b.inst_load_err; - result.inst_priv_addr := a.inst_priv_addr or b.inst_priv_addr; - result.alu_ovf := a.alu_ovf or b.alu_ovf; - result.alu_uvf := a.alu_uvf or b.alu_uvf; - result.syscall := a.syscall or b.syscall; - result.break := a.break or b.break; - result.illegal := a.illegal or b.illegal; - - return result; - - end "or"; - --------------------------------------------------------------------------- -end mips_types; - --------------------------------------------------------------------------- --------------------------------------------------------------------------- diff --git a/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd b/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd deleted file mode 100644 index 759ad2a..0000000 --- a/lib/CPUs/MIPS/src/fibonacci.ROM_ld.vhd +++ /dev/null @@ -1,2174 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 2047) of word_t; - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - - signal word_array : word_array_t := - ( - - X"401A6000", -- 00000000 - X"3C1B0040", -- 00000004 - X"035BD024", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"401A7800", -- 00000014 - X"00000000", -- 00000018 - X"409AF800", -- 0000001C - X"3C1D7FFF", -- 00000020 - X"37BDEFFC", -- 00000024 - X"3C1A0040", -- 00000028 - X"275A02E4", -- 0000002C - X"0340F809", -- 00000030 - X"42000010", -- 00000034 - X"00000000", -- 00000038 - X"00000000", -- 0000003C - X"00000000", -- 00000040 - X"00000000", -- 00000044 - X"00000000", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"00000000", -- 00000054 - X"00000000", -- 00000058 - X"00000000", -- 0000005C - X"00000000", -- 00000060 - X"00000000", -- 00000064 - X"00000000", -- 00000068 - X"00000000", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"401A6800", -- 00000180 - X"3C1B8000", -- 00000184 - X"001AD082", -- 00000188 - X"335A000F", -- 0000018C - X"035BD025", -- 00000190 - X"AF7A0000", -- 00000194 - X"401A7000", -- 00000198 - X"00000000", -- 0000019C - X"03400008", -- 000001A0 - X"42000010", -- 000001A4 - X"24080002", -- 000001A8 - X"0107102A", -- 000001AC - X"ACC40000", -- 000001B0 - X"1040000B", -- 000001B4 - X"ACC50004", -- 000001B8 - X"24C60008", -- 000001BC - X"24E8FFFE", -- 000001C0 - X"8CC2FFF8", -- 000001C4 - X"8CC3FFFC", -- 000001C8 - X"2508FFFF", -- 000001CC - X"00431021", -- 000001D0 - X"ACC20000", -- 000001D4 - X"1500FFFA", -- 000001D8 - X"24C60004", -- 000001DC - X"00E04021", -- 000001E0 - X"03E00008", -- 000001E4 - X"01001021", -- 000001E8 - X"94820002", -- 000001EC - X"A0800000", -- 000001F0 - X"2442FFFF", -- 000001F4 - X"00021C00", -- 000001F8 - X"A4820002", -- 000001FC - X"00031C03", -- 00000200 - X"2402FFFF", -- 00000204 - X"8C850004", -- 00000208 - X"1062000F", -- 0000020C - X"00000000", -- 00000210 - X"2406FFFF", -- 00000214 - X"90A30000", -- 00000218 - X"90820000", -- 0000021C - X"00000000", -- 00000220 - X"00431021", -- 00000224 - X"A0820000", -- 00000228 - X"A0A20000", -- 0000022C - X"94830002", -- 00000230 - X"24A50001", -- 00000234 - X"2463FFFF", -- 00000238 - X"00031400", -- 0000023C - X"00021403", -- 00000240 - X"1446FFF4", -- 00000244 - X"A4830002", -- 00000248 - X"80820002", -- 0000024C - X"03E00008", -- 00000250 - X"00000000", -- 00000254 - X"3C028000", -- 00000258 - X"00042600", -- 0000025C - X"00042603", -- 00000260 - X"34450004", -- 00000264 - X"34430008", -- 00000268 - X"90620000", -- 0000026C - X"00000000", -- 00000270 - X"00021042", -- 00000274 - X"30420001", -- 00000278 - X"1440FFFB", -- 0000027C - X"00000000", -- 00000280 - X"03E00008", -- 00000284 - X"A0A40000", -- 00000288 - X"27BDFFE0", -- 0000028C - X"AFB10014", -- 00000290 - X"AFB00010", -- 00000294 - X"AFBF0018", -- 00000298 - X"80820000", -- 0000029C - X"00808821", -- 000002A0 - X"1040000A", -- 000002A4 - X"00008021", -- 000002A8 - X"00801821", -- 000002AC - X"80640000", -- 000002B0 - X"0C100096", -- 000002B4 - X"26100001", -- 000002B8 - X"02301821", -- 000002BC - X"80620000", -- 000002C0 - X"00000000", -- 000002C4 - X"1440FFF9", -- 000002C8 - X"00000000", -- 000002CC - X"8FBF0018", -- 000002D0 - X"8FB10014", -- 000002D4 - X"8FB00010", -- 000002D8 - X"03E00008", -- 000002DC - X"27BD0020", -- 000002E0 - X"27BDF020", -- 000002E4 - X"3C02AAAA", -- 000002E8 - X"24040041", -- 000002EC - X"AFBF0FDC", -- 000002F0 - X"AFBE0FD8", -- 000002F4 - X"AFB70FD4", -- 000002F8 - X"AFB60FD0", -- 000002FC - X"AFB50FCC", -- 00000300 - X"AFB40FC8", -- 00000304 - X"AFB30FC4", -- 00000308 - X"AFB00FB8", -- 0000030C - X"AFB20FC0", -- 00000310 - X"3450AAAA", -- 00000314 - X"0C100096", -- 00000318 - X"AFB10FBC", -- 0000031C - X"0C100096", -- 00000320 - X"24040020", -- 00000324 - X"0C100096", -- 00000328 - X"24040041", -- 0000032C - X"0C100096", -- 00000330 - X"24040020", -- 00000334 - X"0C100096", -- 00000338 - X"24040041", -- 0000033C - X"0C100096", -- 00000340 - X"24040020", -- 00000344 - X"0C100096", -- 00000348 - X"24040041", -- 0000034C - X"0C100096", -- 00000350 - X"24040020", -- 00000354 - X"0C100096", -- 00000358 - X"24040030", -- 0000035C - X"0C100096", -- 00000360 - X"24040031", -- 00000364 - X"0C100096", -- 00000368 - X"24040032", -- 0000036C - X"0C100096", -- 00000370 - X"24040033", -- 00000374 - X"0C100096", -- 00000378 - X"24040034", -- 0000037C - X"0C100096", -- 00000380 - X"24040035", -- 00000384 - X"0C100096", -- 00000388 - X"24040036", -- 0000038C - X"0C100096", -- 00000390 - X"24040037", -- 00000394 - X"0C100096", -- 00000398 - X"24040038", -- 0000039C - X"0C100096", -- 000003A0 - X"24040039", -- 000003A4 - X"0C100096", -- 000003A8 - X"24040041", -- 000003AC - X"0C100096", -- 000003B0 - X"24040042", -- 000003B4 - X"0C100096", -- 000003B8 - X"24040043", -- 000003BC - X"0C100096", -- 000003C0 - X"24040044", -- 000003C4 - X"0C100096", -- 000003C8 - X"24040045", -- 000003CC - X"0C100096", -- 000003D0 - X"24040046", -- 000003D4 - X"0C100096", -- 000003D8 - X"2404000D", -- 000003DC - X"0C100096", -- 000003E0 - X"2404000A", -- 000003E4 - X"3C148000", -- 000003E8 - X"00009821", -- 000003EC - X"27BE0010", -- 000003F0 - X"27B70FB0", -- 000003F4 - X"241503E8", -- 000003F8 - X"3C164000", -- 000003FC - X"00008821", -- 00000400 - X"00002021", -- 00000404 - X"03C01021", -- 00000408 - X"240603E7", -- 0000040C - X"24C6FFFF", -- 00000410 - X"AC500000", -- 00000414 - X"04C1FFFD", -- 00000418 - X"24420004", -- 0000041C - X"02041026", -- 00000420 - X"24920001", -- 00000424 - X"24420001", -- 00000428 - X"02402821", -- 0000042C - X"27A60010", -- 00000430 - X"240703E8", -- 00000434 - X"0C10006A", -- 00000438 - X"00028040", -- 0000043C - X"24070002", -- 00000440 - X"27C50008", -- 00000444 - X"08100116", -- 00000448 - X"240603E5", -- 0000044C - X"04C0000A", -- 00000450 - X"00000000", -- 00000454 - X"8CA20000", -- 00000458 - X"8CA3FFFC", -- 0000045C - X"8CA4FFF8", -- 00000460 - X"00431023", -- 00000464 - X"24C6FFFF", -- 00000468 - X"1482FFF8", -- 0000046C - X"24A50004", -- 00000470 - X"04C1FFF8", -- 00000474 - X"24E70001", -- 00000478 - X"10F50013", -- 0000047C - X"00000000", -- 00000480 - X"2A4203E8", -- 00000484 - X"1440FFDF", -- 00000488 - X"02402021", -- 0000048C - X"12350010", -- 00000490 - X"00000000", -- 00000494 - X"02761025", -- 00000498 - X"AE820000", -- 0000049C - X"02E02021", -- 000004A0 - X"24020FA0", -- 000004A4 - X"A7A20FB2", -- 000004A8 - X"A3A00FB0", -- 000004AC - X"0C10007B", -- 000004B0 - X"AFBE0FB4", -- 000004B4 - X"02028026", -- 000004B8 - X"26730001", -- 000004BC - X"00008821", -- 000004C0 - X"08100102", -- 000004C4 - X"00002021", -- 000004C8 - X"08100121", -- 000004CC - X"26310001", -- 000004D0 - X"08100128", -- 000004D4 - X"AE930000", -- 000004D8 - X"00000000", -- 000004DC - X"00000000", -- 000004E0 - X"00000000", -- 000004E4 - X"00000000", -- 000004E8 - X"00000000", -- 000004EC - X"00000000", -- 000004F0 - X"00000000", -- 000004F4 - X"00000000", -- 000004F8 - X"00000000", -- 000004FC - X"00000000", -- 00000500 - X"00000000", -- 00000504 - X"00000000", -- 00000508 - X"00000000", -- 0000050C - X"00000000", -- 00000510 - X"00000000", -- 00000514 - X"00000000", -- 00000518 - X"00000000", -- 0000051C - X"00000000", -- 00000520 - X"00000000", -- 00000524 - X"00000000", -- 00000528 - X"00000000", -- 0000052C - X"00000000", -- 00000530 - X"00000000", -- 00000534 - X"00000000", -- 00000538 - X"00000000", -- 0000053C - X"00000000", -- 00000540 - X"00000000", -- 00000544 - X"00000000", -- 00000548 - X"00000000", -- 0000054C - X"00000000", -- 00000550 - X"00000000", -- 00000554 - X"00000000", -- 00000558 - X"00000000", -- 0000055C - X"00000000", -- 00000560 - X"00000000", -- 00000564 - X"00000000", -- 00000568 - X"00000000", -- 0000056C - X"00000000", -- 00000570 - X"00000000", -- 00000574 - X"00000000", -- 00000578 - X"00000000", -- 0000057C - X"00000000", -- 00000580 - X"00000000", -- 00000584 - X"00000000", -- 00000588 - X"00000000", -- 0000058C - X"00000000", -- 00000590 - X"00000000", -- 00000594 - X"00000000", -- 00000598 - X"00000000", -- 0000059C - X"00000000", -- 000005A0 - X"00000000", -- 000005A4 - X"00000000", -- 000005A8 - X"00000000", -- 000005AC - X"00000000", -- 000005B0 - X"00000000", -- 000005B4 - X"00000000", -- 000005B8 - X"00000000", -- 000005BC - X"00000000", -- 000005C0 - X"00000000", -- 000005C4 - X"00000000", -- 000005C8 - X"00000000", -- 000005CC - X"00000000", -- 000005D0 - X"00000000", -- 000005D4 - X"00000000", -- 000005D8 - X"00000000", -- 000005DC - X"00000000", -- 000005E0 - X"00000000", -- 000005E4 - X"00000000", -- 000005E8 - X"00000000", -- 000005EC - X"00000000", -- 000005F0 - X"00000000", -- 000005F4 - X"00000000", -- 000005F8 - X"00000000", -- 000005FC - X"00000000", -- 00000600 - X"00000000", -- 00000604 - X"00000000", -- 00000608 - X"00000000", -- 0000060C - X"00000000", -- 00000610 - X"00000000", -- 00000614 - X"00000000", -- 00000618 - X"00000000", -- 0000061C - X"00000000", -- 00000620 - X"00000000", -- 00000624 - X"00000000", -- 00000628 - X"00000000", -- 0000062C - X"00000000", -- 00000630 - X"00000000", -- 00000634 - X"00000000", -- 00000638 - X"00000000", -- 0000063C - X"00000000", -- 00000640 - X"00000000", -- 00000644 - X"00000000", -- 00000648 - X"00000000", -- 0000064C - X"00000000", -- 00000650 - X"00000000", -- 00000654 - X"00000000", -- 00000658 - X"00000000", -- 0000065C - X"00000000", -- 00000660 - X"00000000", -- 00000664 - X"00000000", -- 00000668 - X"00000000", -- 0000066C - X"00000000", -- 00000670 - X"00000000", -- 00000674 - X"00000000", -- 00000678 - X"00000000", -- 0000067C - X"00000000", -- 00000680 - X"00000000", -- 00000684 - X"00000000", -- 00000688 - X"00000000", -- 0000068C - X"00000000", -- 00000690 - X"00000000", -- 00000694 - X"00000000", -- 00000698 - X"00000000", -- 0000069C - X"00000000", -- 000006A0 - X"00000000", -- 000006A4 - X"00000000", -- 000006A8 - X"00000000", -- 000006AC - X"00000000", -- 000006B0 - X"00000000", -- 000006B4 - X"00000000", -- 000006B8 - X"00000000", -- 000006BC - X"00000000", -- 000006C0 - X"00000000", -- 000006C4 - X"00000000", -- 000006C8 - X"00000000", -- 000006CC - X"00000000", -- 000006D0 - X"00000000", -- 000006D4 - X"00000000", -- 000006D8 - X"00000000", -- 000006DC - X"00000000", -- 000006E0 - X"00000000", -- 000006E4 - X"00000000", -- 000006E8 - X"00000000", -- 000006EC - X"00000000", -- 000006F0 - X"00000000", -- 000006F4 - X"00000000", -- 000006F8 - X"00000000", -- 000006FC - X"00000000", -- 00000700 - X"00000000", -- 00000704 - X"00000000", -- 00000708 - X"00000000", -- 0000070C - X"00000000", -- 00000710 - X"00000000", -- 00000714 - X"00000000", -- 00000718 - X"00000000", -- 0000071C - X"00000000", -- 00000720 - X"00000000", -- 00000724 - X"00000000", -- 00000728 - X"00000000", -- 0000072C - X"00000000", -- 00000730 - X"00000000", -- 00000734 - X"00000000", -- 00000738 - X"00000000", -- 0000073C - X"00000000", -- 00000740 - X"00000000", -- 00000744 - X"00000000", -- 00000748 - X"00000000", -- 0000074C - X"00000000", -- 00000750 - X"00000000", -- 00000754 - X"00000000", -- 00000758 - X"00000000", -- 0000075C - X"00000000", -- 00000760 - X"00000000", -- 00000764 - X"00000000", -- 00000768 - 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X"00000000", -- 00001514 - X"00000000", -- 00001518 - X"00000000", -- 0000151C - X"00000000", -- 00001520 - X"00000000", -- 00001524 - X"00000000", -- 00001528 - X"00000000", -- 0000152C - X"00000000", -- 00001530 - X"00000000", -- 00001534 - X"00000000", -- 00001538 - X"00000000", -- 0000153C - X"00000000", -- 00001540 - X"00000000", -- 00001544 - X"00000000", -- 00001548 - X"00000000", -- 0000154C - X"00000000", -- 00001550 - X"00000000", -- 00001554 - X"00000000", -- 00001558 - X"00000000", -- 0000155C - X"00000000", -- 00001560 - X"00000000", -- 00001564 - X"00000000", -- 00001568 - X"00000000", -- 0000156C - X"00000000", -- 00001570 - X"00000000", -- 00001574 - X"00000000", -- 00001578 - X"00000000", -- 0000157C - X"00000000", -- 00001580 - X"00000000", -- 00001584 - X"00000000", -- 00001588 - X"00000000", -- 0000158C - X"00000000", -- 00001590 - X"00000000", -- 00001594 - X"00000000", -- 00001598 - X"00000000", -- 0000159C - X"00000000", -- 000015A0 - X"00000000", -- 000015A4 - X"00000000", -- 000015A8 - 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X"00000000", -- 000016DC - X"00000000", -- 000016E0 - X"00000000", -- 000016E4 - X"00000000", -- 000016E8 - X"00000000", -- 000016EC - X"00000000", -- 000016F0 - X"00000000", -- 000016F4 - X"00000000", -- 000016F8 - X"00000000", -- 000016FC - X"00000000", -- 00001700 - X"00000000", -- 00001704 - X"00000000", -- 00001708 - X"00000000", -- 0000170C - X"00000000", -- 00001710 - X"00000000", -- 00001714 - X"00000000", -- 00001718 - X"00000000", -- 0000171C - X"00000000", -- 00001720 - X"00000000", -- 00001724 - X"00000000", -- 00001728 - X"00000000", -- 0000172C - X"00000000", -- 00001730 - X"00000000", -- 00001734 - X"00000000", -- 00001738 - X"00000000", -- 0000173C - X"00000000", -- 00001740 - X"00000000", -- 00001744 - X"00000000", -- 00001748 - X"00000000", -- 0000174C - X"00000000", -- 00001750 - X"00000000", -- 00001754 - X"00000000", -- 00001758 - X"00000000", -- 0000175C - X"00000000", -- 00001760 - X"00000000", -- 00001764 - X"00000000", -- 00001768 - X"00000000", -- 0000176C - X"00000000", -- 00001770 - X"00000000", -- 00001774 - X"00000000", -- 00001778 - X"00000000", -- 0000177C - X"00000000", -- 00001780 - X"00000000", -- 00001784 - X"00000000", -- 00001788 - X"00000000", -- 0000178C - X"00000000", -- 00001790 - X"00000000", -- 00001794 - X"00000000", -- 00001798 - X"00000000", -- 0000179C - X"00000000", -- 000017A0 - X"00000000", -- 000017A4 - X"00000000", -- 000017A8 - X"00000000", -- 000017AC - X"00000000", -- 000017B0 - X"00000000", -- 000017B4 - X"00000000", -- 000017B8 - X"00000000", -- 000017BC - X"00000000", -- 000017C0 - X"00000000", -- 000017C4 - X"00000000", -- 000017C8 - X"00000000", -- 000017CC - X"00000000", -- 000017D0 - X"00000000", -- 000017D4 - X"00000000", -- 000017D8 - X"00000000", -- 000017DC - X"00000000", -- 000017E0 - X"00000000", -- 000017E4 - X"00000000", -- 000017E8 - X"00000000", -- 000017EC - X"00000000", -- 000017F0 - X"00000000", -- 000017F4 - X"00000000", -- 000017F8 - X"00000000", -- 000017FC - X"00000000", -- 00001800 - X"00000000", -- 00001804 - X"00000000", -- 00001808 - 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X"00000000", -- 000019D4 - X"00000000", -- 000019D8 - X"00000000", -- 000019DC - X"00000000", -- 000019E0 - X"00000000", -- 000019E4 - X"00000000", -- 000019E8 - X"00000000", -- 000019EC - X"00000000", -- 000019F0 - X"00000000", -- 000019F4 - X"00000000", -- 000019F8 - X"00000000", -- 000019FC - X"00000000", -- 00001A00 - X"00000000", -- 00001A04 - X"00000000", -- 00001A08 - X"00000000", -- 00001A0C - X"00000000", -- 00001A10 - X"00000000", -- 00001A14 - X"00000000", -- 00001A18 - X"00000000", -- 00001A1C - X"00000000", -- 00001A20 - X"00000000", -- 00001A24 - X"00000000", -- 00001A28 - X"00000000", -- 00001A2C - X"00000000", -- 00001A30 - X"00000000", -- 00001A34 - X"00000000", -- 00001A38 - X"00000000", -- 00001A3C - X"00000000", -- 00001A40 - X"00000000", -- 00001A44 - X"00000000", -- 00001A48 - X"00000000", -- 00001A4C - X"00000000", -- 00001A50 - X"00000000", -- 00001A54 - X"00000000", -- 00001A58 - X"00000000", -- 00001A5C - X"00000000", -- 00001A60 - X"00000000", -- 00001A64 - X"00000000", -- 00001A68 - X"00000000", -- 00001A6C - X"00000000", -- 00001A70 - X"00000000", -- 00001A74 - X"00000000", -- 00001A78 - X"00000000", -- 00001A7C - X"00000000", -- 00001A80 - X"00000000", -- 00001A84 - X"00000000", -- 00001A88 - X"00000000", -- 00001A8C - X"00000000", -- 00001A90 - X"00000000", -- 00001A94 - X"00000000", -- 00001A98 - X"00000000", -- 00001A9C - X"00000000", -- 00001AA0 - X"00000000", -- 00001AA4 - X"00000000", -- 00001AA8 - X"00000000", -- 00001AAC - X"00000000", -- 00001AB0 - X"00000000", -- 00001AB4 - X"00000000", -- 00001AB8 - X"00000000", -- 00001ABC - X"00000000", -- 00001AC0 - X"00000000", -- 00001AC4 - X"00000000", -- 00001AC8 - X"00000000", -- 00001ACC - X"00000000", -- 00001AD0 - X"00000000", -- 00001AD4 - X"00000000", -- 00001AD8 - X"00000000", -- 00001ADC - X"00000000", -- 00001AE0 - X"00000000", -- 00001AE4 - X"00000000", -- 00001AE8 - X"00000000", -- 00001AEC - X"00000000", -- 00001AF0 - X"00000000", -- 00001AF4 - X"00000000", -- 00001AF8 - X"00000000", -- 00001AFC - X"00000000", -- 00001B00 - X"00000000", -- 00001B04 - X"00000000", -- 00001B08 - X"00000000", -- 00001B0C - X"00000000", -- 00001B10 - X"00000000", -- 00001B14 - X"00000000", -- 00001B18 - X"00000000", -- 00001B1C - X"00000000", -- 00001B20 - X"00000000", -- 00001B24 - X"00000000", -- 00001B28 - X"00000000", -- 00001B2C - X"00000000", -- 00001B30 - X"00000000", -- 00001B34 - X"00000000", -- 00001B38 - X"00000000", -- 00001B3C - X"00000000", -- 00001B40 - X"00000000", -- 00001B44 - X"00000000", -- 00001B48 - X"00000000", -- 00001B4C - X"00000000", -- 00001B50 - X"00000000", -- 00001B54 - X"00000000", -- 00001B58 - X"00000000", -- 00001B5C - X"00000000", -- 00001B60 - X"00000000", -- 00001B64 - X"00000000", -- 00001B68 - X"00000000", -- 00001B6C - X"00000000", -- 00001B70 - X"00000000", -- 00001B74 - X"00000000", -- 00001B78 - X"00000000", -- 00001B7C - X"00000000", -- 00001B80 - X"00000000", -- 00001B84 - X"00000000", -- 00001B88 - X"00000000", -- 00001B8C - X"00000000", -- 00001B90 - X"00000000", -- 00001B94 - X"00000000", -- 00001B98 - X"00000000", -- 00001B9C - X"00000000", -- 00001BA0 - X"00000000", -- 00001BA4 - X"00000000", -- 00001BA8 - X"00000000", -- 00001BAC - X"00000000", -- 00001BB0 - X"00000000", -- 00001BB4 - X"00000000", -- 00001BB8 - X"00000000", -- 00001BBC - X"00000000", -- 00001BC0 - X"00000000", -- 00001BC4 - X"00000000", -- 00001BC8 - X"00000000", -- 00001BCC - X"00000000", -- 00001BD0 - X"00000000", -- 00001BD4 - X"00000000", -- 00001BD8 - X"00000000", -- 00001BDC - X"00000000", -- 00001BE0 - X"00000000", -- 00001BE4 - X"00000000", -- 00001BE8 - X"00000000", -- 00001BEC - X"00000000", -- 00001BF0 - X"00000000", -- 00001BF4 - X"00000000", -- 00001BF8 - X"00000000", -- 00001BFC - X"00000000", -- 00001C00 - X"00000000", -- 00001C04 - X"00000000", -- 00001C08 - X"00000000", -- 00001C0C - X"00000000", -- 00001C10 - X"00000000", -- 00001C14 - X"00000000", -- 00001C18 - X"00000000", -- 00001C1C - X"00000000", -- 00001C20 - X"00000000", -- 00001C24 - X"00000000", -- 00001C28 - X"00000000", -- 00001C2C - X"00000000", -- 00001C30 - X"00000000", -- 00001C34 - X"00000000", -- 00001C38 - X"00000000", -- 00001C3C - X"00000000", -- 00001C40 - X"00000000", -- 00001C44 - X"00000000", -- 00001C48 - X"00000000", -- 00001C4C - X"00000000", -- 00001C50 - X"00000000", -- 00001C54 - X"00000000", -- 00001C58 - X"00000000", -- 00001C5C - X"00000000", -- 00001C60 - X"00000000", -- 00001C64 - X"00000000", -- 00001C68 - X"00000000", -- 00001C6C - X"00000000", -- 00001C70 - X"00000000", -- 00001C74 - X"00000000", -- 00001C78 - X"00000000", -- 00001C7C - X"00000000", -- 00001C80 - X"00000000", -- 00001C84 - X"00000000", -- 00001C88 - X"00000000", -- 00001C8C - X"00000000", -- 00001C90 - X"00000000", -- 00001C94 - X"00000000", -- 00001C98 - X"00000000", -- 00001C9C - X"00000000", -- 00001CA0 - X"00000000", -- 00001CA4 - X"00000000", -- 00001CA8 - X"00000000", -- 00001CAC - X"00000000", -- 00001CB0 - X"00000000", -- 00001CB4 - X"00000000", -- 00001CB8 - X"00000000", -- 00001CBC - X"00000000", -- 00001CC0 - X"00000000", -- 00001CC4 - X"00000000", -- 00001CC8 - X"00000000", -- 00001CCC - X"00000000", -- 00001CD0 - X"00000000", -- 00001CD4 - X"00000000", -- 00001CD8 - X"00000000", -- 00001CDC - X"00000000", -- 00001CE0 - X"00000000", -- 00001CE4 - X"00000000", -- 00001CE8 - X"00000000", -- 00001CEC - X"00000000", -- 00001CF0 - X"00000000", -- 00001CF4 - X"00000000", -- 00001CF8 - X"00000000", -- 00001CFC - X"00000000", -- 00001D00 - X"00000000", -- 00001D04 - X"00000000", -- 00001D08 - X"00000000", -- 00001D0C - X"00000000", -- 00001D10 - X"00000000", -- 00001D14 - X"00000000", -- 00001D18 - X"00000000", -- 00001D1C - X"00000000", -- 00001D20 - X"00000000", -- 00001D24 - X"00000000", -- 00001D28 - X"00000000", -- 00001D2C - X"00000000", -- 00001D30 - X"00000000", -- 00001D34 - X"00000000", -- 00001D38 - X"00000000", -- 00001D3C - X"00000000", -- 00001D40 - X"00000000", -- 00001D44 - X"00000000", -- 00001D48 - X"00000000", -- 00001D4C - X"00000000", -- 00001D50 - X"00000000", -- 00001D54 - X"00000000", -- 00001D58 - X"00000000", -- 00001D5C - X"00000000", -- 00001D60 - X"00000000", -- 00001D64 - X"00000000", -- 00001D68 - X"00000000", -- 00001D6C - X"00000000", -- 00001D70 - X"00000000", -- 00001D74 - X"00000000", -- 00001D78 - X"00000000", -- 00001D7C - X"00000000", -- 00001D80 - X"00000000", -- 00001D84 - X"00000000", -- 00001D88 - X"00000000", -- 00001D8C - X"00000000", -- 00001D90 - X"00000000", -- 00001D94 - X"00000000", -- 00001D98 - X"00000000", -- 00001D9C - X"00000000", -- 00001DA0 - X"00000000", -- 00001DA4 - X"00000000", -- 00001DA8 - X"00000000", -- 00001DAC - X"00000000", -- 00001DB0 - X"00000000", -- 00001DB4 - X"00000000", -- 00001DB8 - X"00000000", -- 00001DBC - X"00000000", -- 00001DC0 - X"00000000", -- 00001DC4 - X"00000000", -- 00001DC8 - X"00000000", -- 00001DCC - X"00000000", -- 00001DD0 - X"00000000", -- 00001DD4 - X"00000000", -- 00001DD8 - X"00000000", -- 00001DDC - X"00000000", -- 00001DE0 - X"00000000", -- 00001DE4 - X"00000000", -- 00001DE8 - X"00000000", -- 00001DEC - X"00000000", -- 00001DF0 - X"00000000", -- 00001DF4 - X"00000000", -- 00001DF8 - X"00000000", -- 00001DFC - X"00000000", -- 00001E00 - X"00000000", -- 00001E04 - X"00000000", -- 00001E08 - X"00000000", -- 00001E0C - X"00000000", -- 00001E10 - X"00000000", -- 00001E14 - X"00000000", -- 00001E18 - X"00000000", -- 00001E1C - X"00000000", -- 00001E20 - X"00000000", -- 00001E24 - X"00000000", -- 00001E28 - X"00000000", -- 00001E2C - X"00000000", -- 00001E30 - X"00000000", -- 00001E34 - X"00000000", -- 00001E38 - X"00000000", -- 00001E3C - X"00000000", -- 00001E40 - X"00000000", -- 00001E44 - X"00000000", -- 00001E48 - X"00000000", -- 00001E4C - X"00000000", -- 00001E50 - X"00000000", -- 00001E54 - X"00000000", -- 00001E58 - X"00000000", -- 00001E5C - X"00000000", -- 00001E60 - X"00000000", -- 00001E64 - X"00000000", -- 00001E68 - X"00000000", -- 00001E6C - X"00000000", -- 00001E70 - X"00000000", -- 00001E74 - X"00000000", -- 00001E78 - X"00000000", -- 00001E7C - X"00000000", -- 00001E80 - X"00000000", -- 00001E84 - X"00000000", -- 00001E88 - X"00000000", -- 00001E8C - X"00000000", -- 00001E90 - X"00000000", -- 00001E94 - X"00000000", -- 00001E98 - X"00000000", -- 00001E9C - X"00000000", -- 00001EA0 - X"00000000", -- 00001EA4 - X"00000000", -- 00001EA8 - X"00000000", -- 00001EAC - X"00000000", -- 00001EB0 - X"00000000", -- 00001EB4 - X"00000000", -- 00001EB8 - X"00000000", -- 00001EBC - X"00000000", -- 00001EC0 - X"00000000", -- 00001EC4 - X"00000000", -- 00001EC8 - X"00000000", -- 00001ECC - X"00000000", -- 00001ED0 - X"00000000", -- 00001ED4 - X"00000000", -- 00001ED8 - X"00000000", -- 00001EDC - X"00000000", -- 00001EE0 - X"00000000", -- 00001EE4 - X"00000000", -- 00001EE8 - X"00000000", -- 00001EEC - X"00000000", -- 00001EF0 - X"00000000", -- 00001EF4 - X"00000000", -- 00001EF8 - X"00000000", -- 00001EFC - X"00000000", -- 00001F00 - X"00000000", -- 00001F04 - X"00000000", -- 00001F08 - X"00000000", -- 00001F0C - X"00000000", -- 00001F10 - X"00000000", -- 00001F14 - X"00000000", -- 00001F18 - X"00000000", -- 00001F1C - X"00000000", -- 00001F20 - X"00000000", -- 00001F24 - X"00000000", -- 00001F28 - X"00000000", -- 00001F2C - X"00000000", -- 00001F30 - X"00000000", -- 00001F34 - X"00000000", -- 00001F38 - X"00000000", -- 00001F3C - X"00000000", -- 00001F40 - X"00000000", -- 00001F44 - X"00000000", -- 00001F48 - X"00000000", -- 00001F4C - X"00000000", -- 00001F50 - X"00000000", -- 00001F54 - X"00000000", -- 00001F58 - X"00000000", -- 00001F5C - X"00000000", -- 00001F60 - X"00000000", -- 00001F64 - X"00000000", -- 00001F68 - X"00000000", -- 00001F6C - X"00000000", -- 00001F70 - X"00000000", -- 00001F74 - X"00000000", -- 00001F78 - X"00000000", -- 00001F7C - X"00000000", -- 00001F80 - X"00000000", -- 00001F84 - X"00000000", -- 00001F88 - X"00000000", -- 00001F8C - X"00000000", -- 00001F90 - X"00000000", -- 00001F94 - X"00000000", -- 00001F98 - X"00000000", -- 00001F9C - X"00000000", -- 00001FA0 - X"00000000", -- 00001FA4 - X"00000000", -- 00001FA8 - X"00000000", -- 00001FAC - X"00000000", -- 00001FB0 - X"00000000", -- 00001FB4 - X"00000000", -- 00001FB8 - X"00000000", -- 00001FBC - X"00000000", -- 00001FC0 - X"00000000", -- 00001FC4 - X"00000000", -- 00001FC8 - X"00000000", -- 00001FCC - X"00000000", -- 00001FD0 - X"00000000", -- 00001FD4 - X"00000000", -- 00001FD8 - X"00000000", -- 00001FDC - X"00000000", -- 00001FE0 - X"00000000", -- 00001FE4 - X"00000000", -- 00001FE8 - X"00000000", -- 00001FEC - X"00000000", -- 00001FF0 - X"00000000", -- 00001FF4 - X"00000000", -- 00001FF8 - X"00000000" -- 00001FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(12 downto 2))); - end if; - end process; - - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; - - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - word_array(to_integer(jtag_ld_addr(10 downto 0))) <= jtag_ld_din; - else - jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(10 downto 0))); - end if; - end if; - end process; - -end data; diff --git a/lib/CPUs/MIPS/src/irom_hello.vhd b/lib/CPUs/MIPS/src/irom_hello.vhd deleted file mode 100644 index 21ee2eb..0000000 --- a/lib/CPUs/MIPS/src/irom_hello.vhd +++ /dev/null @@ -1,320 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - clk : in STD_LOGIC; - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3C1D7FFF", -- 00000000 - X"0C100014", -- 00000004 - X"37BDEFFC", -- 00000008 - X"24080002", -- 0000000C - X"0107102A", -- 00000010 - X"ACC40000", -- 00000014 - X"1040000B", -- 00000018 - X"ACC50004", -- 0000001C - X"24C60008", -- 00000020 - X"24E8FFFE", -- 00000024 - X"8CC2FFF8", -- 00000028 - X"8CC3FFFC", -- 0000002C - X"2508FFFF", -- 00000030 - X"00431021", -- 00000034 - X"ACC20000", -- 00000038 - X"1500FFFA", -- 0000003C - X"24C60004", -- 00000040 - X"00E04021", -- 00000044 - X"03E00008", -- 00000048 - X"01001021", -- 0000004C - X"27BDFF78", -- 00000050 - X"3C021003", -- 00000054 - X"3C030001", -- 00000058 - X"AFB60078", -- 0000005C - X"3456FFFC", -- 00000060 - X"3C02AAAA", -- 00000064 - X"AFB7007C", -- 00000068 - X"AFB50074", -- 0000006C - X"AFB40070", -- 00000070 - X"AFB20068", -- 00000074 - X"AFB00060", -- 00000078 - X"AFBF0080", -- 0000007C - X"AFB3006C", -- 00000080 - X"AFB10064", -- 00000084 - X"AEC00000", -- 00000088 - X"3450AAAA", -- 0000008C - X"347786A0", -- 00000090 - X"27B20010", -- 00000094 - X"24150014", -- 00000098 - X"3474869F", -- 0000009C - X"00009821", -- 000000A0 - X"00002021", -- 000000A4 - X"02401021", -- 000000A8 - X"24060013", -- 000000AC - X"24C6FFFF", -- 000000B0 - X"AC500000", -- 000000B4 - X"04C1FFFD", -- 000000B8 - X"24420004", -- 000000BC - X"02041026", -- 000000C0 - X"24910001", -- 000000C4 - X"24420001", -- 000000C8 - X"02202821", -- 000000CC - X"27A60010", -- 000000D0 - X"24070014", -- 000000D4 - X"0C100003", -- 000000D8 - X"00028040", -- 000000DC - X"24070002", -- 000000E0 - X"26450008", -- 000000E4 - X"0810003E", -- 000000E8 - X"24060011", -- 000000EC - X"04C0000A", -- 000000F0 - X"00000000", -- 000000F4 - X"8CA20000", -- 000000F8 - X"8CA3FFFC", -- 000000FC - X"8CA4FFF8", -- 00000100 - X"00431023", -- 00000104 - X"24C6FFFF", -- 00000108 - X"1482FFF8", -- 0000010C - X"24A50004", -- 00000110 - X"04C1FFF8", -- 00000114 - X"24E70001", -- 00000118 - X"10F5000C", -- 0000011C - X"00000000", -- 00000120 - X"0291102A", -- 00000124 - X"1040FFDF", -- 00000128 - X"02202021", -- 0000012C - X"1677FFDB", -- 00000130 - X"00009821", -- 00000134 - X"8EC20000", -- 00000138 - X"00000000", -- 0000013C - X"24420001", -- 00000140 - X"AEC20000", -- 00000144 - X"0810002A", -- 00000148 - X"00002021", -- 0000014C - X"08100049", -- 00000150 - X"26730001", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"00000000", -- 00000180 - X"00000000", -- 00000184 - X"00000000", -- 00000188 - X"00000000", -- 0000018C - X"00000000", -- 00000190 - X"00000000", -- 00000194 - X"00000000", -- 00000198 - X"00000000", -- 0000019C - X"00000000", -- 000001A0 - X"00000000", -- 000001A4 - X"00000000", -- 000001A8 - X"00000000", -- 000001AC - X"00000000", -- 000001B0 - X"00000000", -- 000001B4 - X"00000000", -- 000001B8 - X"00000000", -- 000001BC - X"00000000", -- 000001C0 - X"00000000", -- 000001C4 - X"00000000", -- 000001C8 - X"00000000", -- 000001CC - X"00000000", -- 000001D0 - X"00000000", -- 000001D4 - X"00000000", -- 000001D8 - X"00000000", -- 000001DC - X"00000000", -- 000001E0 - X"00000000", -- 000001E4 - X"00000000", -- 000001E8 - X"00000000", -- 000001EC - X"00000000", -- 000001F0 - X"00000000", -- 000001F4 - X"00000000", -- 000001F8 - X"00000000", -- 000001FC - X"00000000", -- 00000200 - X"00000000", -- 00000204 - X"00000000", -- 00000208 - X"00000000", -- 0000020C - X"00000000", -- 00000210 - X"00000000", -- 00000214 - X"00000000", -- 00000218 - X"00000000", -- 0000021C - X"00000000", -- 00000220 - X"00000000", -- 00000224 - X"00000000", -- 00000228 - X"00000000", -- 0000022C - X"00000000", -- 00000230 - X"00000000", -- 00000234 - X"00000000", -- 00000238 - X"00000000", -- 0000023C - X"00000000", -- 00000240 - X"00000000", -- 00000244 - X"00000000", -- 00000248 - X"00000000", -- 0000024C - X"00000000", -- 00000250 - X"00000000", -- 00000254 - X"00000000", -- 00000258 - X"00000000", -- 0000025C - X"00000000", -- 00000260 - X"00000000", -- 00000264 - X"00000000", -- 00000268 - X"00000000", -- 0000026C - X"00000000", -- 00000270 - X"00000000", -- 00000274 - X"00000000", -- 00000278 - X"00000000", -- 0000027C - X"00000000", -- 00000280 - X"00000000", -- 00000284 - X"00000000", -- 00000288 - X"00000000", -- 0000028C - X"00000000", -- 00000290 - X"00000000", -- 00000294 - X"00000000", -- 00000298 - X"00000000", -- 0000029C - X"00000000", -- 000002A0 - X"00000000", -- 000002A4 - X"00000000", -- 000002A8 - X"00000000", -- 000002AC - X"00000000", -- 000002B0 - X"00000000", -- 000002B4 - X"00000000", -- 000002B8 - X"00000000", -- 000002BC - X"00000000", -- 000002C0 - X"00000000", -- 000002C4 - X"00000000", -- 000002C8 - X"00000000", -- 000002CC - X"00000000", -- 000002D0 - X"00000000", -- 000002D4 - X"00000000", -- 000002D8 - X"00000000", -- 000002DC - X"00000000", -- 000002E0 - X"00000000", -- 000002E4 - X"00000000", -- 000002E8 - X"00000000", -- 000002EC - X"00000000", -- 000002F0 - X"00000000", -- 000002F4 - X"00000000", -- 000002F8 - X"00000000", -- 000002FC - X"00000000", -- 00000300 - X"00000000", -- 00000304 - X"00000000", -- 00000308 - X"00000000", -- 0000030C - X"00000000", -- 00000310 - X"00000000", -- 00000314 - X"00000000", -- 00000318 - X"00000000", -- 0000031C - X"00000000", -- 00000320 - X"00000000", -- 00000324 - X"00000000", -- 00000328 - X"00000000", -- 0000032C - X"00000000", -- 00000330 - X"00000000", -- 00000334 - X"00000000", -- 00000338 - X"00000000", -- 0000033C - X"00000000", -- 00000340 - X"00000000", -- 00000344 - X"00000000", -- 00000348 - X"00000000", -- 0000034C - X"00000000", -- 00000350 - X"00000000", -- 00000354 - X"00000000", -- 00000358 - X"00000000", -- 0000035C - X"00000000", -- 00000360 - X"00000000", -- 00000364 - X"00000000", -- 00000368 - X"00000000", -- 0000036C - X"00000000", -- 00000370 - X"00000000", -- 00000374 - X"00000000", -- 00000378 - X"00000000", -- 0000037C - X"00000000", -- 00000380 - X"00000000", -- 00000384 - X"00000000", -- 00000388 - X"00000000", -- 0000038C - X"00000000", -- 00000390 - X"00000000", -- 00000394 - X"00000000", -- 00000398 - X"00000000", -- 0000039C - X"00000000", -- 000003A0 - X"00000000", -- 000003A4 - X"00000000", -- 000003A8 - X"00000000", -- 000003AC - X"00000000", -- 000003B0 - X"00000000", -- 000003B4 - X"00000000", -- 000003B8 - X"00000000", -- 000003BC - X"00000000", -- 000003C0 - X"00000000", -- 000003C4 - X"00000000", -- 000003C8 - X"00000000", -- 000003CC - X"00000000", -- 000003D0 - X"00000000", -- 000003D4 - X"00000000", -- 000003D8 - X"00000000", -- 000003DC - X"00000000", -- 000003E0 - X"00000000", -- 000003E4 - X"00000000", -- 000003E8 - X"00000000", -- 000003EC - X"00000000", -- 000003F0 - X"00000000", -- 000003F4 - X"00000000", -- 000003F8 - X"00000000" -- 000003FC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) then - dout <= word_array(to_integer(addr)); - end if; - end process; - - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test1.vhd b/lib/CPUs/MIPS/src/irom_test1.vhd deleted file mode 100644 index 24007c4..0000000 --- a/lib/CPUs/MIPS/src/irom_test1.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"08100001", -- [0x00400000] j 0x00400004 [main] - X"3c011234", -- [0x00400004] lui $1, 4660 - X"34215678", -- [0x00400008] ori $1, $1, 22136 - X"3021f00f", -- [0x0040000c] andi $1, $1, -4081 - X"2021affc", -- [0x00400010] addi $1, $1, -20484 - X"2021ffff", -- [0x00400014] addi $1, $1, -1 - X"1c20fffe", -- [0x00400018] bgtz $1 -8 [loop-0x00400018] - X"3c020000", -- [0x0040001c] lui $2, 0 - X"34420001", -- [0x00400020] ori $2, $2, 1 - X"3c010000", -- [0x00400024] lui $1, 0 - X"34210004", -- [0x00400028] ori $1, $1, 4 - X"00220822", -- [0x0040002c] sub $1, $1, $2 - X"1c20fffe", -- [0x00400030] bgtz $1 -8 [loop2-0x00400030] - X"3c1f0040", -- [0x00400034] lui $31, 64 - X"03e00008", -- [0x00400038] jr $31 - X"00000000", -- [0x0040003c] nop - X"00000000", -- [0x00400040] nop - X"00000000", -- [0x00400044] nop - X"00000000", -- [0x00400048] nop - X"00000000", -- [0x0040004c] nop - X"00000000", -- [0x00400050] nop - X"00000000", -- [0x00400054] nop - X"00000000", -- [0x00400058] nop - X"00000000", -- [0x0040005c] nop - X"00000000", -- [0x00400060] nop - X"00000000", -- [0x00400064] nop - X"00000000", -- [0x00400068] nop - X"00000000", -- [0x0040006c] nop - X"00000000", -- [0x00400070] nop - X"00000000", -- [0x00400074] nop - X"00000000", -- [0x00400078] nop - X"00000000", -- [0x0040007c] nop - X"00000000", -- [0x00400080] nop - X"00000000", -- [0x00400084] nop - X"00000000", -- [0x00400088] nop - X"00000000", -- [0x0040008c] nop - X"00000000", -- [0x00400090] nop - X"00000000", -- [0x00400094] nop - X"00000000", -- [0x00400098] nop - X"00000000", -- [0x0040009c] nop - X"00000000", -- [0x004000a0] nop - X"00000000", -- [0x004000a4] nop - X"00000000", -- [0x004000a8] nop - X"00000000", -- [0x004000ac] nop - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] nop - X"00000000", -- [0x004000bc] nop - X"00000000", -- [0x004000c0] nop - X"00000000", -- [0x004000c4] nop - X"00000000", -- [0x004000c8] nop - X"00000000", -- [0x004000cc] nop - X"00000000", -- [0x004000d0] nop - X"00000000", -- [0x004000d4] nop - X"00000000", -- [0x004000d8] nop - X"00000000", -- [0x004000dc] nop - X"00000000", -- [0x004000e0] nop - X"00000000", -- [0x004000e4] nop - X"00000000", -- [0x004000e8] nop - X"00000000", -- [0x004000ec] nop - X"00000000", -- [0x004000f0] nop - X"00000000", -- [0x004000f4] nop - X"00000000", -- [0x004000f8] nop - X"00000000" -- [0x004000fc] nop - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test2.vhd b/lib/CPUs/MIPS/src/irom_test2.vhd deleted file mode 100644 index 289c9f9..0000000 --- a/lib/CPUs/MIPS/src/irom_test2.vhd +++ /dev/null @@ -1,73 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"08100001", -- j 0x00400004 [main] ; 5: j main - X"3c011234", -- lui $1, 4660 ; 7: lui $1, 0x1234 - X"34215678", -- ori $1, $1, 22136 ; 8: ori $1, $1, 0x5678 - X"3c035555", -- lui $3, 21845 ; 9: lui $3, 0x5555 - X"3463aaaa", -- ori $3, $3, -21846 ; 10: ori $3, $3, 0xAAAA - X"3c021000", -- lui $2, 4096 ; 11: lui $2, 0x1000 - X"ac410000", -- sw $1, 0($2) ; 12: sw $1, 0($2) - X"ac430004", -- sw $3, 4($2) ; 13: sw $3, 4($2) - X"00000000", -- nop ; 14: sll $0, $0, 0 - X"ac400000", -- sw $0, 0($2) ; 15: sw $0, 0($2) - X"ac400004", -- sw $0, 4($2) ; 16: sw $0, 4($2) - X"8c410000", -- lw $1, 0($2) ; 17: lw $1, 0($2) - X"8c430004", -- lw $3, 4($2) ; 18: lw $3, 4($2) - X"00000000", -- nop ; 19: sll $0, $0, 0 - X"00000000", -- nop ; 20: sll $0, $0, 0 - X"08100001" -- j 0x00400004 [main] ; 21: j main - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test3.vhd b/lib/CPUs/MIPS/src/irom_test3.vhd deleted file mode 100644 index 7d53d2a..0000000 --- a/lib/CPUs/MIPS/src/irom_test3.vhd +++ /dev/null @@ -1,122 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - - X"08100001", -- [0x00400000] j 0x00400004 [main] - X"3c011234", -- [0x00400004] lui $1, 4660 - X"34215a5a", -- [0x00400008] ori $1, $1, 23130 - X"00010840", -- [0x0040000c] sll $1, $1, 1 - X"00010900", -- [0x00400010] sll $1, $1, 4 - X"00010880", -- [0x00400014] sll $1, $1, 2 - X"00010840", -- [0x00400018] sll $1, $1, 1 - X"00010a00", -- [0x0040001c] sll $1, $1, 8 - X"00010882", -- [0x00400020] srl $1, $1, 2 - X"00010942", -- [0x00400024] srl $1, $1, 5 - X"00010842", -- [0x00400028] srl $1, $1, 1 - X"00010a02", -- [0x0040002c] srl $1, $1, 8 - X"3821ffff", -- [0x00400030] xori $1, $1, -1 - X"3c1f0040", -- [0x00400034] lui $31, 64 - X"03e00008", -- [0x00400038] jr $31 - X"003f0826", -- [0x0040003c] xor $1, $1, $31 - X"00000000", -- [0x00400040] nop - X"00000000", -- [0x00400044] nop - X"00000000", -- [0x00400048] nop - X"00000000", -- [0x0040004c] nop - X"00000000", -- [0x00400050] nop - X"00000000", -- [0x00400054] nop - X"00000000", -- [0x00400058] nop - X"00000000", -- [0x0040005c] nop - X"00000000", -- [0x00400060] nop - X"00000000", -- [0x00400064] nop - X"00000000", -- [0x00400068] nop - X"00000000", -- [0x0040006c] nop - X"00000000", -- [0x00400070] nop - X"00000000", -- [0x00400074] nop - X"00000000", -- [0x00400078] nop - X"00000000", -- [0x0040007c] nop - X"00000000", -- [0x00400080] nop - X"00000000", -- [0x00400084] nop - X"00000000", -- [0x00400088] nop - X"00000000", -- [0x0040008c] nop - X"00000000", -- [0x00400090] nop - X"00000000", -- [0x00400094] nop - X"00000000", -- [0x00400098] nop - X"00000000", -- [0x0040009c] nop - X"00000000", -- [0x004000a0] nop - X"00000000", -- [0x004000a4] nop - X"00000000", -- [0x004000a8] nop - X"00000000", -- [0x004000ac] nop - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test4.vhd b/lib/CPUs/MIPS/src/irom_test4.vhd deleted file mode 100644 index bbce904..0000000 --- a/lib/CPUs/MIPS/src/irom_test4.vhd +++ /dev/null @@ -1,122 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - - X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main - X"00000000", -- [0x00400004] nop ; 7: sll $0, $0, 0 - X"3c011000", -- [0x00400008] lui $1, 4096 ; 8: lui $1, 0x1000 - X"20220000", -- [0x0040000c] addi $2, $1, 0 ; 9: addi $2, $1, 0 - X"3c071234", -- [0x00400010] lui $7, 4660 ; 10: lui $7, 0x1234 - X"3c050001", -- [0x00400014] lui $5, 1 ; 11: lui $5, 0x0001 - X"ac270000", -- [0x00400018] sw $7, 0($1) ; 12: sw $7, 0($1) - X"8c430000", -- [0x0040001c] lw $3, 0($2) ; 13: lw $3, 0($2) - X"00654020", -- [0x00400020] add $8, $3, $5 ; 14: add $8, $3, $5 - X"00654820", -- [0x00400024] add $9, $3, $5 ; 15: add $9, $3, $5 - X"00655020", -- [0x00400028] add $10, $3, $5 ; 16: add $10, $3, $5 - X"00655820", -- [0x0040002c] add $11, $3, $5 ; 17: add $11, $3, $5 - X"00000000", -- [0x00400030] nop ; 18: sll $0, $0, 0 - X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0 - X"08100001", -- [0x00400038] j 0x00400004 [main] ; 20: j main - X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0 - X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0 - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test5.vhd b/lib/CPUs/MIPS/src/irom_test5.vhd deleted file mode 100644 index 490bdd9..0000000 --- a/lib/CPUs/MIPS/src/irom_test5.vhd +++ /dev/null @@ -1,122 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - - X"08100001", -- [0x00400000] j 0x00400004 [main] - X"3c018000", -- [0x00400004] lui $1, -32768 - X"3c020000", -- [0x00400008] lui $2, 0 - X"3c030000", -- [0x0040000c] lui $3, 0 - X"34420001", -- [0x00400010] ori $2, $2, 1 - X"34630003", -- [0x00400014] ori $3, $3, 3 - X"00010842", -- [0x00400018] srl $1, $1, 1 - X"00010840", -- [0x0040001c] sll $1, $1, 1 - X"00010843", -- [0x00400020] sra $1, $1, 1 - X"000108c3", -- [0x00400024] sra $1, $1, 3 - X"00612004", -- [0x00400028] sllv $4, $1, $3 - X"00412807", -- [0x0040002c] srav $5, $1, $2 - X"00613007", -- [0x00400030] srav $6, $1, $3 - X"3c1f0040", -- [0x00400034] lui $31, 64 - X"03e00008", -- [0x00400038] jr $31 - X"00000000", -- [0x0040003c] nop - X"00000000", -- [0x00400040] nop - X"00000000", -- [0x00400044] nop - X"00000000", -- [0x00400048] nop - X"00000000", -- [0x0040004c] nop - X"00000000", -- [0x00400050] nop - X"00000000", -- [0x00400054] nop - X"00000000", -- [0x00400058] nop - X"00000000", -- [0x0040005c] nop - X"00000000", -- [0x00400060] nop - X"00000000", -- [0x00400064] nop - X"00000000", -- [0x00400068] nop - X"00000000", -- [0x0040006c] nop - X"00000000", -- [0x00400070] nop - X"00000000", -- [0x00400074] nop - X"00000000", -- [0x00400078] nop - X"00000000", -- [0x0040007c] nop - X"00000000", -- [0x00400080] nop - X"00000000", -- [0x00400084] nop - X"00000000", -- [0x00400088] nop - X"00000000", -- [0x0040008c] nop - X"00000000", -- [0x00400090] nop - X"00000000", -- [0x00400094] nop - X"00000000", -- [0x00400098] nop - X"00000000", -- [0x0040009c] nop - X"00000000", -- [0x004000a0] nop - X"00000000", -- [0x004000a4] nop - X"00000000", -- [0x004000a8] nop - X"00000000", -- [0x004000ac] nop - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] nop - X"00000000", -- [0x004000bc] nop - X"00000000", -- [0x004000c0] nop - X"00000000", -- [0x004000c4] nop - X"00000000", -- [0x004000c8] nop - X"00000000", -- [0x004000cc] nop - X"00000000", -- [0x004000d0] nop - X"00000000", -- [0x004000d4] nop - X"00000000", -- [0x004000d8] nop - X"00000000", -- [0x004000dc] nop - X"00000000", -- [0x004000e0] nop - X"00000000", -- [0x004000e4] nop - X"00000000", -- [0x004000e8] nop - X"00000000", -- [0x004000ec] nop - X"00000000", -- [0x004000f0] nop - X"00000000", -- [0x004000f4] nop - X"00000000", -- [0x004000f8] nop - X"00000000" -- [0x004000fc] nop - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test6.vhd b/lib/CPUs/MIPS/src/irom_test6.vhd deleted file mode 100644 index 5231af8..0000000 --- a/lib/CPUs/MIPS/src/irom_test6.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"08100001", -- [0x00400000] j 0x00400004 [main] ; 5: j main - X"3c080000", -- [0x00400004] lui $8, 0 ; 7: lui $8, 0 - X"00000000", -- [0x00400008] nop ; 8: sll $0, $0, 0 - X"0c100009", -- [0x0040000c] jal 0x00400024 [subr1] ; 9: jal subr1 - X"3c010040", -- [0x00400010] lui $1, 64 [subr2] ; 10: la $2, subr2 - X"34220030", -- [0x00400014] ori $2, $1, 48 [subr2] - X"00407809", -- [0x00400018] jalr $15, $2 ; 11: jalr $15, $2 - X"00000000", -- [0x0040001c] nop ; 12: sll $0, $0, 0 - X"08100002", -- [0x00400020] j 0x00400008 [loop] ; 13: j loop - X"21080001", -- [0x00400024] addi $8, $8, 1 ; 15: addi $8, 1 - X"00000000", -- [0x00400028] nop ; 16: sll $0, $0, 0 - X"03e00008", -- [0x0040002c] jr $31 ; 17: jr $31 - X"21080010", -- [0x00400030] addi $8, $8, 16 ; 18: addi $8, 16 - X"00000000", -- [0x00400034] nop ; 19: sll $0, $0, 0 - X"01e00008", -- [0x00400038] jr $15 ; 20: jr $15 - X"00000000", -- [0x0040003c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400040] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400044] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400048] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040004c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400050] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400054] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400058] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040005c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400060] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400064] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400068] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040006c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400070] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400074] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400078] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040007c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400080] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400084] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400088] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040008c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400090] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400094] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x00400098] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x0040009c] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000a8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000ac] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000b8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000bc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000c8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000cc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000d8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000dc] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000e8] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000ec] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f0] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f4] nop ; 21: sll $0, $0, 0 - X"00000000", -- [0x004000f8] nop ; 21: sll $0, $0, 0 - X"00000000" -- [0x004000fc] nop ; 21: sll $0, $0, 0 - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test_addsub.vhd b/lib/CPUs/MIPS/src/irom_test_addsub.vhd deleted file mode 100644 index bbe764f..0000000 --- a/lib/CPUs/MIPS/src/irom_test_addsub.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3c011234", -- [0x00400000] lui $1, 4660 - X"34225678", -- [0x00400004] ori $2, $1, 22136 - X"3c012345", -- [0x00400008] lui $1, 9029 - X"34236789", -- [0x0040000c] ori $3, $1, 26505 - X"3c018765", -- [0x00400010] lui $1, -30875 - X"34244321", -- [0x00400014] ori $4, $1, 17185 - X"3c019876", -- [0x00400018] lui $1, -26506 - X"34255432", -- [0x0040001c] ori $5, $1, 21554 - X"00000000", -- [0x00400020] nop - X"00427823", -- [0x00400024] subu $15, $2, $2 - X"00437823", -- [0x00400028] subu $15, $2, $3 - X"00447823", -- [0x0040002c] subu $15, $2, $4 - X"00457823", -- [0x00400030] subu $15, $2, $5 - X"00627823", -- [0x00400034] subu $15, $3, $2 - X"00637823", -- [0x00400038] subu $15, $3, $3 - X"00647823", -- [0x0040003c] subu $15, $3, $4 - X"00657823", -- [0x00400040] subu $15, $3, $5 - X"00827823", -- [0x00400044] subu $15, $4, $2 - X"00837823", -- [0x00400048] subu $15, $4, $3 - X"00847823", -- [0x0040004c] subu $15, $4, $4 - X"00857823", -- [0x00400050] subu $15, $4, $5 - X"00a27823", -- [0x00400054] subu $15, $5, $2 - X"00a37823", -- [0x00400058] subu $15, $5, $3 - X"00a47823", -- [0x0040005c] subu $15, $5, $4 - X"00a57823", -- [0x00400060] subu $15, $5, $5 - X"00000000", -- [0x00400064] nop - X"00427822", -- [0x00400068] sub $15, $2, $2 - X"00437822", -- [0x0040006c] sub $15, $2, $3 - X"00447822", -- [0x00400070] sub $15, $2, $4 - X"00457822", -- [0x00400074] sub $15, $2, $5 - X"00627822", -- [0x00400078] sub $15, $3, $2 - X"00637822", -- [0x0040007c] sub $15, $3, $3 - X"00647822", -- [0x00400080] sub $15, $3, $4 - X"00657822", -- [0x00400084] sub $15, $3, $5 - X"00827822", -- [0x00400088] sub $15, $4, $2 - X"00837822", -- [0x0040008c] sub $15, $4, $3 - X"00847822", -- [0x00400090] sub $15, $4, $4 - X"00857822", -- [0x00400094] sub $15, $4, $5 - X"00a27822", -- [0x00400098] sub $15, $5, $2 - X"00a37822", -- [0x0040009c] sub $15, $5, $3 - X"00a47822", -- [0x004000a0] sub $15, $5, $4 - X"00a57822", -- [0x004000a4] sub $15, $5, $5 - X"00000000", -- [0x004000a8] nop - X"08104000", -- [0x004000ac] j 0x00410000 [main] - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test_slt.vhd b/lib/CPUs/MIPS/src/irom_test_slt.vhd deleted file mode 100644 index 5fcf2fe..0000000 --- a/lib/CPUs/MIPS/src/irom_test_slt.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3c011234", -- [0x00400000] lui $1, 4660 - X"34225678", -- [0x00400004] ori $2, $1, 22136 - X"3c012345", -- [0x00400008] lui $1, 9029 - X"34236789", -- [0x0040000c] ori $3, $1, 26505 - X"3c018765", -- [0x00400010] lui $1, -30875 - X"34244321", -- [0x00400014] ori $4, $1, 17185 - X"3c019876", -- [0x00400018] lui $1, -26506 - X"34255432", -- [0x0040001c] ori $5, $1, 21554 - X"3c081000", -- [0x00400020] lui $8, 4096 - X"00000000", -- [0x00400024] nop - X"0042782b", -- [0x00400028] sltu $15, $2, $2 - X"0043782b", -- [0x0040002c] sltu $15, $2, $3 - X"0044782b", -- [0x00400030] sltu $15, $2, $4 - X"0045782b", -- [0x00400034] sltu $15, $2, $5 - X"0062782b", -- [0x00400038] sltu $15, $3, $2 - X"0063782b", -- [0x0040003c] sltu $15, $3, $3 - X"0064782b", -- [0x00400040] sltu $15, $3, $4 - X"0065782b", -- [0x00400044] sltu $15, $3, $5 - X"0082782b", -- [0x00400048] sltu $15, $4, $2 - X"0083782b", -- [0x0040004c] sltu $15, $4, $3 - X"0084782b", -- [0x00400050] sltu $15, $4, $4 - X"0085782b", -- [0x00400054] sltu $15, $4, $5 - X"00a2782b", -- [0x00400058] sltu $15, $5, $2 - X"00a3782b", -- [0x0040005c] sltu $15, $5, $3 - X"00a4782b", -- [0x00400060] sltu $15, $5, $4 - X"00a5782b", -- [0x00400064] sltu $15, $5, $5 - X"00000000", -- [0x00400068] nop - X"0042782a", -- [0x0040006c] slt $15, $2, $2 - X"0043782a", -- [0x00400070] slt $15, $2, $3 - X"0044782a", -- [0x00400074] slt $15, $2, $4 - X"0045782a", -- [0x00400078] slt $15, $2, $5 - X"0062782a", -- [0x0040007c] slt $15, $3, $2 - X"0063782a", -- [0x00400080] slt $15, $3, $3 - X"0064782a", -- [0x00400084] slt $15, $3, $4 - X"0065782a", -- [0x00400088] slt $15, $3, $5 - X"0082782a", -- [0x0040008c] slt $15, $4, $2 - X"0083782a", -- [0x00400090] slt $15, $4, $3 - X"0084782a", -- [0x00400094] slt $15, $4, $4 - X"0085782a", -- [0x00400098] slt $15, $4, $5 - X"00a2782a", -- [0x0040009c] slt $15, $5, $2 - X"00a3782a", -- [0x004000a0] slt $15, $5, $3 - X"00a4782a", -- [0x004000a4] slt $15, $5, $4 - X"00a5782a", -- [0x004000a8] slt $15, $5, $5 - X"00000000", -- [0x004000ac] nop - X"08104000", -- [0x004000b0] j 0x00410000 [main] - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test_slti.vhd b/lib/CPUs/MIPS/src/irom_test_slti.vhd deleted file mode 100644 index b87fd8a..0000000 --- a/lib/CPUs/MIPS/src/irom_test_slti.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3c011234", -- [0x00400000] lui $1, 4660 - X"34225678", -- [0x00400004] ori $2, $1, 22136 - X"3c012345", -- [0x00400008] lui $1, 9029 - X"34236789", -- [0x0040000c] ori $3, $1, 26505 - X"3c018765", -- [0x00400010] lui $1, -30875 - X"34244321", -- [0x00400014] ori $4, $1, 17185 - X"3c019876", -- [0x00400018] lui $1, -26506 - X"34255432", -- [0x0040001c] ori $5, $1, 21554 - X"3c081000", -- [0x00400020] lui $8, 4096 - X"00000000", -- [0x00400024] nop - X"2c4f1234", -- [0x00400028] sltiu $15, $2, 4660 - X"2c4f2345", -- [0x0040002c] sltiu $15, $2, 9029 - X"2c4fedcc", -- [0x00400030] sltiu $15, $2, -4660 - X"2c4fdcbb", -- [0x00400034] sltiu $15, $2, -9029 - X"2c6f1234", -- [0x00400038] sltiu $15, $3, 4660 - X"2c6f2345", -- [0x0040003c] sltiu $15, $3, 9029 - X"2c6fedcc", -- [0x00400040] sltiu $15, $3, -4660 - X"2c6fdcbb", -- [0x00400044] sltiu $15, $3, -9029 - X"2c8f1234", -- [0x00400048] sltiu $15, $4, 4660 - X"2c8f2345", -- [0x0040004c] sltiu $15, $4, 9029 - X"2c8fedcc", -- [0x00400050] sltiu $15, $4, -4660 - X"2c8fdcbb", -- [0x00400054] sltiu $15, $4, -9029 - X"2caf1234", -- [0x00400058] sltiu $15, $5, 4660 - X"2caf2345", -- [0x0040005c] sltiu $15, $5, 9029 - X"2cafedcc", -- [0x00400060] sltiu $15, $5, -4660 - X"2cafdcbb", -- [0x00400064] sltiu $15, $5, -9029 - X"00000000", -- [0x00400068] nop - X"284f1234", -- [0x0040006c] slti $15, $2, 4660 - X"284f2345", -- [0x00400070] slti $15, $2, 9029 - X"284fedcc", -- [0x00400074] slti $15, $2, -4660 - X"284fdcbb", -- [0x00400078] slti $15, $2, -9029 - X"286f1234", -- [0x0040007c] slti $15, $3, 4660 - X"286f2345", -- [0x00400080] slti $15, $3, 9029 - X"286fedcc", -- [0x00400084] slti $15, $3, -4660 - X"286fdcbb", -- [0x00400088] slti $15, $3, -9029 - X"288f1234", -- [0x0040008c] slti $15, $4, 4660 - X"288f2345", -- [0x00400090] slti $15, $4, 9029 - X"288fedcc", -- [0x00400094] slti $15, $4, -4660 - X"288fdcbb", -- [0x00400098] slti $15, $4, -9029 - X"28af1234", -- [0x0040009c] slti $15, $5, 4660 - X"28af2345", -- [0x004000a0] slti $15, $5, 9029 - X"28afedcc", -- [0x004000a4] slti $15, $5, -4660 - X"28afdcbb", -- [0x004000a8] slti $15, $5, -9029 - X"00000000", -- [0x004000ac] nop - X"08104000", -- [0x004000b0] j 0x00410000 [main] - X"00000000", -- [0x004000b4] nop - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/irom_test_sub.vhd b/lib/CPUs/MIPS/src/irom_test_sub.vhd deleted file mode 100644 index bbe764f..0000000 --- a/lib/CPUs/MIPS/src/irom_test_sub.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY rom IS - Generic - ( - addr_width : integer := 2; - data_width : integer := 32 - ); - Port - ( - addr : in unsigned(addr_width-1 downto 0); - dout : out unsigned(data_width-1 downto 0) - ); -END rom; - -ARCHITECTURE itest OF rom IS - - subtype word_t is unsigned(data_width-1 downto 0); - type word_array_t is array (0 to 2**addr_width-1) of word_t; - - -- Assembled from itest.jsm - constant word_array : word_array_t := - ( - X"3c011234", -- [0x00400000] lui $1, 4660 - X"34225678", -- [0x00400004] ori $2, $1, 22136 - X"3c012345", -- [0x00400008] lui $1, 9029 - X"34236789", -- [0x0040000c] ori $3, $1, 26505 - X"3c018765", -- [0x00400010] lui $1, -30875 - X"34244321", -- [0x00400014] ori $4, $1, 17185 - X"3c019876", -- [0x00400018] lui $1, -26506 - X"34255432", -- [0x0040001c] ori $5, $1, 21554 - X"00000000", -- [0x00400020] nop - X"00427823", -- [0x00400024] subu $15, $2, $2 - X"00437823", -- [0x00400028] subu $15, $2, $3 - X"00447823", -- [0x0040002c] subu $15, $2, $4 - X"00457823", -- [0x00400030] subu $15, $2, $5 - X"00627823", -- [0x00400034] subu $15, $3, $2 - X"00637823", -- [0x00400038] subu $15, $3, $3 - X"00647823", -- [0x0040003c] subu $15, $3, $4 - X"00657823", -- [0x00400040] subu $15, $3, $5 - X"00827823", -- [0x00400044] subu $15, $4, $2 - X"00837823", -- [0x00400048] subu $15, $4, $3 - X"00847823", -- [0x0040004c] subu $15, $4, $4 - X"00857823", -- [0x00400050] subu $15, $4, $5 - X"00a27823", -- [0x00400054] subu $15, $5, $2 - X"00a37823", -- [0x00400058] subu $15, $5, $3 - X"00a47823", -- [0x0040005c] subu $15, $5, $4 - X"00a57823", -- [0x00400060] subu $15, $5, $5 - X"00000000", -- [0x00400064] nop - X"00427822", -- [0x00400068] sub $15, $2, $2 - X"00437822", -- [0x0040006c] sub $15, $2, $3 - X"00447822", -- [0x00400070] sub $15, $2, $4 - X"00457822", -- [0x00400074] sub $15, $2, $5 - X"00627822", -- [0x00400078] sub $15, $3, $2 - X"00637822", -- [0x0040007c] sub $15, $3, $3 - X"00647822", -- [0x00400080] sub $15, $3, $4 - X"00657822", -- [0x00400084] sub $15, $3, $5 - X"00827822", -- [0x00400088] sub $15, $4, $2 - X"00837822", -- [0x0040008c] sub $15, $4, $3 - X"00847822", -- [0x00400090] sub $15, $4, $4 - X"00857822", -- [0x00400094] sub $15, $4, $5 - X"00a27822", -- [0x00400098] sub $15, $5, $2 - X"00a37822", -- [0x0040009c] sub $15, $5, $3 - X"00a47822", -- [0x004000a0] sub $15, $5, $4 - X"00a57822", -- [0x004000a4] sub $15, $5, $5 - X"00000000", -- [0x004000a8] nop - X"08104000", -- [0x004000ac] j 0x00410000 [main] - X"00000000", -- [0x004000b0] nop - X"00000000", -- [0x004000b4] - X"00000000", -- [0x004000b8] - X"00000000", -- [0x004000bc] - X"00000000", -- [0x004000c0] - X"00000000", -- [0x004000c4] - X"00000000", -- [0x004000c8] - X"00000000", -- [0x004000cc] - X"00000000", -- [0x004000d0] - X"00000000", -- [0x004000d4] - X"00000000", -- [0x004000d8] - X"00000000", -- [0x004000dc] - X"00000000", -- [0x004000e0] - X"00000000", -- [0x004000e4] - X"00000000", -- [0x004000e8] - X"00000000", -- [0x004000ec] - X"00000000", -- [0x004000f0] - X"00000000", -- [0x004000f4] - X"00000000", -- [0x004000f8] - X"00000000" -- [0x004000fc] - ); - -begin - -PROM_READ: - dout <= word_array(to_integer(addr)); - -end itest; diff --git a/lib/CPUs/MIPS/src/mips_embedded.vhd b/lib/CPUs/MIPS/src/mips_embedded.vhd deleted file mode 100644 index 47d7bd7..0000000 --- a/lib/CPUs/MIPS/src/mips_embedded.vhd +++ /dev/null @@ -1,332 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_embedded is - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned(5 downto 0); - rxd : in STD_LOGIC; - txd : out STD_LOGIC; - dout : out word_t - ); -end mips_embedded; - -architecture rtl of mips_embedded is - - COMPONENT mips_top - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - int : in unsigned(5 downto 0); - mem_rdy : in STD_LOGIC; - mem_re : out STD_LOGIC; - mem_en : out STD_LOGIC; - mem_we : out unsigned(3 downto 0); - mem_din : in word_t; - mem_dout : out word_t; - mem_addr : out word_t - - ); - END COMPONENT; - - signal mem_din : word_t; - signal mem_dout : word_t; - signal mem_addr : word_t; - signal mem_re : std_logic; - signal mem_en : std_logic; - signal mem_we : unsigned(3 downto 0); - signal mem_rdy : std_logic; - - subtype tick_usec_t is natural range 0 to 99; - signal tick_usec : tick_usec_t; - signal cnt_usec : word_t; - signal cnt_sec : word_t; - signal cnt_usec_preset : word_t; - signal cnt_sec_preset : word_t; - signal cnt_usec_en : std_logic; - signal cnt_usec_we : std_logic; - signal cnt_sec_en : std_logic; - signal cnt_sec_we : std_logic; - - COMPONENT uart_tx - Port - ( - data_in : in std_logic_vector(7 downto 0); - write_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic - ); - END COMPONENT; - - COMPONENT uart_rx - Port - ( - serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - read_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - buffer_data_present : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic - ); - END COMPONENT; - - signal baud_count : unsigned(7 downto 0); - signal en_16_x_baud : std_logic; - signal reg_we_uart_tx : std_logic; - signal tx_full : std_logic; - signal tx_half_full : std_logic; - signal reg_uart_tx : unsigned(7 downto 0); - signal reg_re_uart_rx : std_logic; - signal reg_uart_rx : std_logic_vector(7 downto 0); - signal rx_data_present : std_logic; - signal rx_full : std_logic; - signal rx_half_full : std_logic; - signal uart_status_port : unsigned(7 downto 0); - signal reg_uart_ctrl : unsigned(7 downto 0); - signal reg_uart_baud : unsigned(7 downto 0); - -begin - -registers_write: - process(clk) - begin - if rising_edge(clk) then - reg_we_uart_tx <= '0'; - cnt_usec_we <= '0'; - cnt_sec_we <= '0'; - if rst = '1' then - dout <= (others => '0'); - reg_uart_baud <= to_unsigned(53, 8); - reg_uart_ctrl <= to_unsigned(0, 8); - elsif mem_en = '1' then - case mem_addr(5 downto 2) is - - when "0000" => - if mem_we(0) = '1' then - dout(7 downto 0) <= mem_dout(7 downto 0); - end if; - if mem_we(1) = '1' then - dout(15 downto 8) <= mem_dout(15 downto 8); - end if; - if mem_we(2) = '1' then - dout(23 downto 16) <= mem_dout(23 downto 16); - end if; - if mem_we(3) = '1' then - dout(31 downto 24) <= mem_dout(31 downto 24); - end if; - - when "0001" => - if mem_we(0) = '1' then - reg_we_uart_tx <= '1'; - reg_uart_tx <= mem_dout(7 downto 0); - end if; - - when "0010" => - if mem_we(0) = '1' then - reg_uart_ctrl <= mem_dout(7 downto 0); - end if; - if mem_we(1) = '1' then - reg_uart_baud <= mem_dout(15 downto 8); - end if; - - when "0100" => - if mem_we(3) = '1' then - cnt_usec_we <= '1'; - cnt_usec_preset <= mem_dout; - end if; - - when "0101" => - if mem_we(3) = '1' then - cnt_sec_we <= '1'; - cnt_sec_preset <= mem_dout; - end if; - - when others => null; - end case; - end if; - end if; - end process; - -registers_read: - process(clk) - begin - if rising_edge(clk) then - reg_re_uart_rx <= '0'; - if mem_en = '1' then - mem_din <= (others => '0'); - case mem_addr(5 downto 2) is - - when "0000" => null; - - when "0001" => - reg_re_uart_rx <= '1'; - mem_din(7 downto 0) <= unsigned(reg_uart_rx); - - when "0010" => - mem_din(7 downto 0) <= uart_status_port; - mem_din(15 downto 8) <= reg_uart_baud; - - when "0100" => - mem_din <= cnt_usec; - - when "0101" => - mem_din <= cnt_sec; - - when others => null; - end case; - end if; - end if; - end process; - - mem_rdy <= not halt; - -inst_mips_top: mips_top - PORT MAP - ( - rst => rst, - clk => clk, - int => int, - mem_rdy => mem_rdy, - mem_en => mem_en, - mem_we => mem_we, - mem_din => mem_din, - mem_dout => mem_dout, - mem_addr => mem_addr - ); - -inst_uart_tx: uart_tx - port map - ( - data_in => std_logic_vector(reg_uart_tx), - write_buffer => reg_we_uart_tx, - reset_buffer => rst, - en_16_x_baud => en_16_x_baud, - serial_out => txd, - buffer_full => tx_full, - buffer_half_full => tx_half_full, - clk => clk - ); - -inst_uart_rx: uart_rx - port map - ( - serial_in => rxd, - data_out => reg_uart_rx, - read_buffer => reg_re_uart_rx, - reset_buffer => rst, - en_16_x_baud => en_16_x_baud, - buffer_data_present => rx_data_present, - buffer_full => rx_full, - buffer_half_full => rx_half_full, - clk => clk - ); - - uart_status_port <= (7 downto 5 => '0') & rx_data_present & rx_full & rx_half_full & tx_full & tx_half_full; - -tick_usec_timer: - process(clk) - begin - if clk'event and clk='1' then - cnt_usec_en <= '0'; - if rst = '1' then - tick_usec <= 0; - cnt_usec_en <= '0'; - elsif tick_usec = tick_usec_t'high then - tick_usec <= 0; - cnt_usec_en <= '1'; - else - tick_usec <= tick_usec + 1; - end if; - end if; - end process; - -cnt_usec_timer: - process(clk) - begin - if clk'event and clk='1' then - cnt_sec_en <= '0'; - if rst = '1' then - cnt_usec <= (others => '0'); - cnt_sec_en <= '0'; - elsif cnt_usec_we = '1' then - cnt_usec <= cnt_usec_preset; - elsif cnt_usec_en = '1' then - if cnt_usec = to_unsigned(1E6 - 1, word_t'length) then - cnt_usec <= (others => '0'); - cnt_sec_en <= '1'; - else - cnt_usec <= cnt_usec + 1; - end if; - end if; - end if; - end process; - -cnt_sec_timer: - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - cnt_sec <= (others => '0'); - elsif cnt_sec_we = '1' then - cnt_sec <= cnt_sec_preset; - elsif cnt_sec_en = '1' then - cnt_sec <= cnt_sec + 1; - end if; - end if; - end process; - -baud_timer: - process(clk) - begin - if clk'event and clk='1' then - if rst = '1' then - baud_count <= (others => '0'); - elsif baud_count = reg_uart_baud then - baud_count <= (others => '0'); - en_16_x_baud <= '1'; - else - baud_count <= baud_count + 1; - en_16_x_baud <= '0'; - end if; - end if; - end process; - -end rtl; diff --git a/lib/CPUs/MIPS/src/mips_embedded_syn.vhd b/lib/CPUs/MIPS/src/mips_embedded_syn.vhd deleted file mode 100644 index 9de77e7..0000000 --- a/lib/CPUs/MIPS/src/mips_embedded_syn.vhd +++ /dev/null @@ -1,137 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: JIPS top file --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library work; -use work.mips_types.all; - -entity mips_embedded_syn is - Port - ( - sys_rst_n_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_dip : in STD_LOGIC_VECTOR (7 downto 0); - sys_btn : in STD_LOGIC_VECTOR (8 downto 0); - sys_led : out STD_LOGIC_VECTOR (7 downto 0); - sys_rx : in STD_LOGIC; - sys_tx : out STD_LOGIC; - sys_error : out STD_LOGIC_VECTOR (1 downto 0) - ); - -end mips_embedded_syn; - -architecture struct of mips_embedded_syn is - - COMPONENT mips_embedded - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - int : in unsigned(5 downto 0); - rxd : in STD_LOGIC; - txd : out STD_LOGIC; - dout : out word_t - ); - END COMPONENT; - - signal dout : word_t; - signal rst : STD_LOGIC; - signal clk : STD_LOGIC; - signal halt : STD_LOGIC; - signal int : unsigned(5 downto 0); - signal btn_r : unsigned (8 downto 0); - signal dip_r : unsigned (7 downto 0); - -begin - -------------------------------------------------------------------- -inst_mips_embedded: mips_embedded - PORT MAP - ( - rst => rst, - clk => clk, - halt => halt, - int => int, - rxd => sys_rx, - txd => sys_tx, - dout => dout - ); - - clk <= sys_clk_in; - rst <= not sys_rst_n_in; - -ERR_LED_reg: - process(rst, clk) - begin - if rst = '1' then - sys_error <= (others => '1'); - elsif rising_edge(clk) then - sys_error <= STD_LOGIC_VECTOR(dout(31 downto 30)); - end if; - end process; - -LED_reg: - process(rst, clk) - begin - if rst = '1' then - sys_led <= (others => '0'); - elsif rising_edge(clk) then - sys_led <= STD_LOGIC_VECTOR(dout(7 downto 0)); - end if; - end process; - -DIP_reg: - process(rst, clk) - begin - if rst = '1' then - dip_r <= (others => '0'); - elsif rising_edge(clk) then - dip_r <= unsigned(sys_dip); - end if; - end process; - -BTN_reg: - process(rst, clk) - begin - if rst = '1' then - btn_r <= (others => '0'); - elsif rising_edge(clk) then - btn_r <= unsigned(sys_btn); - end if; - end process; - - halt <= btn_r(4) after 6.5 ns; - int(0) <= dip_r(0) and btn_r(3) after 1 ns; - int(1) <= dip_r(1) and btn_r(3) after 1 ns; - int(2) <= dip_r(2) and btn_r(3) after 1 ns; - int(3) <= dip_r(3) and btn_r(3) after 1 ns; - int(4) <= dip_r(4) and btn_r(3) after 1 ns; - int(5) <= dip_r(5) and btn_r(3) after 1 ns; - -------------------------------------------------------------------- - -end struct; diff --git a/lib/CPUs/MIPS/src/mips_muldiv.vhd b/lib/CPUs/MIPS/src/mips_muldiv.vhd deleted file mode 100644 index 34016d9..0000000 --- a/lib/CPUs/MIPS/src/mips_muldiv.vhd +++ /dev/null @@ -1,83 +0,0 @@ --------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The arithmetic logic unit --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.mips_types.all; - -entity muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - din_vld_hi : in std_logic; - din_vld_lo : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - hilo_sel : in std_logic; - dout : out word_t - ); -end muldiv; - -architecture Behavioral of muldiv is - - signal reg_hi, reg_lo : word_t; - --------------------------------------------------------------------------- -begin - --------------------------------------------------------------------------- -proc_reg_out: - process(hilo_sel, reg_hi, reg_lo) - begin - if hilo_sel = '1' then - dout <= reg_hi; - else - dout <= reg_lo; - end if; - end process; - -proc_reg_in: - process(clk) - begin - if rising_edge(clk) then - if rst = '1' then - reg_hi <= (others => '0'); - reg_lo <= (others => '0'); - elsif din_vld_hi = '1' then - if hilo_sel = '1' then - reg_hi <= din_hi; - else - reg_lo <= din_hi; - end if; - end if; - if din_vld_lo = '1' then - reg_lo <= din_lo; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/CPUs/MIPS/src/ram.vhd b/lib/CPUs/MIPS/src/ram.vhd deleted file mode 100644 index d054c72..0000000 --- a/lib/CPUs/MIPS/src/ram.vhd +++ /dev/null @@ -1,115 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - we : in unsigned(3 downto 0); - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - constant depth : natural := 2**word_addr_width; - - type sram_t is array (0 to depth-1) of unsigned(7 downto 0); - - function sram_clear return sram_t is - - variable result : sram_t; - begin - for i in 0 to sram_t'length-1 loop - result(i) := (others => '0'); - end loop; - return result; - end sram_clear; - - signal sram0, sram1, sram2, sram3 : sram_t := sram_clear; - -BEGIN - - -SRAM_RW: - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(0) = '1' then - sram0(index)<= din(7 downto 0); - end if; - dout(7 downto 0) <= sram0(index); - end if; - end process; - - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(1) = '1' then - sram1(index)<= din(15 downto 8); - end if; - dout(15 downto 8) <= sram1(index); - end if; - end process; - - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(2) = '1' then - sram2(index)<= din(23 downto 16); - end if; - dout(23 downto 16) <= sram2(index); - end if; - end process; - - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(3) = '1' then - sram3(index)<= din(31 downto 24); - end if; - dout(31 downto 24) <= sram3(index); - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/ram_ld.vhd b/lib/CPUs/MIPS/src/ram_ld.vhd deleted file mode 100644 index 7a36b13..0000000 --- a/lib/CPUs/MIPS/src/ram_ld.vhd +++ /dev/null @@ -1,177 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - COMPONENT dpram_2w2r - Generic - ( - addr_width : integer; - data_width : integer - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); - END COMPONENT; - - signal jtag_clk : STD_LOGIC; - signal jtag_we : unsigned(3 downto 0); - signal jtag_addr : unsigned (15 downto 0); - signal jtag_dout : unsigned (31 downto 0); - signal jtag_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - -BEGIN - -gen_sram: - for i in 0 to 3 generate - begin - inst_dpram_2w2r : dpram_2w2r - GENERIC MAP - ( - addr_width => word_addr_width, - data_width => 8 - ) - PORT MAP - ( - clk_a => clk, - en_a => ce, - we_a => we(i), - addr_a => addr(word_addr_width+1 downto 2), - din_a => din((i+1)*8-1 downto i*8), - dout_a => dout((i+1)*8-1 downto i*8), - - clk_b => jtag_clk, - en_b => jtag_we(i), - we_b => jtag_we(i), - addr_b => jtag_addr(word_addr_width-1 downto 0), - din_b => jtag_din((i+1)*8-1 downto i*8), - dout_b => jtag_dout((i+1)*8-1 downto i*8) - ); - end generate; - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst2 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 2 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_addr <= user_regi(user_regi'left downto jtag_dout'length); - jtag_din <= user_regi(jtag_dout'length-1 downto 0); - jtag_clk <= bs_update1; - jtag_we <= (3 downto 0 => bs_sel); - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_dout'length => '0') & jtag_dout; - end if; - end if; - end process; - --------------------------------------------------------------------------- -end behavior; diff --git a/lib/CPUs/MIPS/src/ram_sim.vhd b/lib/CPUs/MIPS/src/ram_sim.vhd deleted file mode 100644 index 6d26672..0000000 --- a/lib/CPUs/MIPS/src/ram_sim.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - - -ENTITY ram IS - Generic - ( - word_addr_width : integer := 6 - ); - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - we : in unsigned(3 downto 0); - addr : in unsigned(31 downto 0); - din : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END ram; - -ARCHITECTURE behavior OF ram IS - - constant depth : natural := 2**word_addr_width; - - type sram_t is array (0 to depth-1) of unsigned(31 downto 0); - - function sram_clear return sram_t is - - variable result : sram_t; - begin - for i in 0 to sram_t'length-1 loop - result(i) := (others => '0'); - end loop; - return result; - end sram_clear; - - signal sram : sram_t := sram_clear; - -BEGIN - - -SRAM_RW: - process(clk) - variable index : natural range 0 to depth-1; - begin - if rising_edge(clk) and ce = '1' then - index := to_integer(addr(word_addr_width+1 downto 2)); - if we(0) = '1' then - sram(index)(7 downto 0) <= din(7 downto 0); - end if; - if we(1) = '1' then - sram(index)(15 downto 8) <= din(15 downto 8); - end if; - if we(2) = '1' then - sram(index)(23 downto 16) <= din(23 downto 16); - end if; - if we(3) = '1' then - sram(index)(31 downto 24) <= din(31 downto 24); - end if; - dout <= sram(index); - end if; - end process; - -end behavior; diff --git a/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd b/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd deleted file mode 100644 index b0c6fe3..0000000 --- a/lib/CPUs/MIPS/src/rmd160_test.ROM_ld.vhd +++ /dev/null @@ -1,4222 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY rom IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END rom; - -ARCHITECTURE data OF rom IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 4095) of word_t; - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - - signal word_array : word_array_t := - ( - - X"401A6000", -- 00000000 - X"3C1B0040", -- 00000004 - X"035BD024", -- 00000008 - X"375A000C", -- 0000000C - X"409A6000", -- 00000010 - X"401A7800", -- 00000014 - X"00000000", -- 00000018 - X"409AF800", -- 0000001C - X"3C1D7FFF", -- 00000020 - X"37BDEFFC", -- 00000024 - X"3C1A0040", -- 00000028 - X"275A05B4", -- 0000002C - X"0340F809", -- 00000030 - X"42000010", -- 00000034 - X"00000000", -- 00000038 - X"00000000", -- 0000003C - X"00000000", -- 00000040 - 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X"00561026", -- 000016D4 - X"00C73021", -- 000016D8 - X"00D53021", -- 000016DC - X"00481021", -- 000016E0 - X"00C9A821", -- 000016E4 - X"00521021", -- 000016E8 - X"004A9021", -- 000016EC - X"00151E42", -- 000016F0 - X"001511C0", -- 000016F4 - X"00431025", -- 000016F8 - X"00123682", -- 000016FC - X"00121980", -- 00001700 - X"0059A821", -- 00001704 - X"00661825", -- 00001708 - X"00143D82", -- 0000170C - X"00141280", -- 00001710 - X"00779021", -- 00001714 - X"0047A025", -- 00001718 - X"00183027", -- 0000171C - X"00113D82", -- 00001720 - X"00111A80", -- 00001724 - X"00678825", -- 00001728 - X"00D53025", -- 0000172C - X"8CA30024", -- 00001730 - X"001E1027", -- 00001734 - X"00D43026", -- 00001738 - X"00521025", -- 0000173C - X"00511026", -- 00001740 - X"00C33021", -- 00001744 - X"00D93021", -- 00001748 - X"004C1021", -- 0000174C - X"00C9C821", -- 00001750 - X"00571021", -- 00001754 - X"004AB821", -- 00001758 - X"00191C82", -- 0000175C - X"00191380", -- 00001760 - X"00431025", -- 00001764 - X"00173682", -- 00001768 - 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X"00171027", -- 00001804 - X"00121A80", -- 00001808 - X"00679025", -- 0000180C - X"00D53026", -- 00001810 - X"8FA7002C", -- 00001814 - X"00561025", -- 00001818 - X"00521026", -- 0000181C - X"00CD3021", -- 00001820 - X"00D43021", -- 00001824 - X"00471021", -- 00001828 - X"00C9A021", -- 0000182C - X"00511021", -- 00001830 - X"004A8821", -- 00001834 - X"00141CC2", -- 00001838 - X"00141340", -- 0000183C - X"00431025", -- 00001840 - X"00113502", -- 00001844 - X"00111B00", -- 00001848 - X"0058A021", -- 0000184C - X"00661825", -- 00001850 - X"00193D82", -- 00001854 - X"00133027", -- 00001858 - X"00191280", -- 0000185C - X"007E8821", -- 00001860 - X"0047C825", -- 00001864 - X"8CA80004", -- 00001868 - X"00D43025", -- 0000186C - X"00173D82", -- 00001870 - X"00161027", -- 00001874 - X"00171A80", -- 00001878 - X"0067B825", -- 0000187C - X"00D93026", -- 00001880 - X"00511025", -- 00001884 - X"00571026", -- 00001888 - X"00C83021", -- 0000188C - X"00D83021", -- 00001890 - X"004D1021", -- 00001894 - X"00C9C021", -- 00001898 - X"005E1021", -- 0000189C - X"004AF021", -- 000018A0 - X"00181C42", -- 000018A4 - X"001813C0", -- 000018A8 - X"00431025", -- 000018AC - X"001E34C2", -- 000018B0 - X"001E1B40", -- 000018B4 - X"0055C021", -- 000018B8 - X"00661825", -- 000018BC - X"00133D82", -- 000018C0 - X"00131280", -- 000018C4 - X"0072F021", -- 000018C8 - X"00479825", -- 000018CC - X"00143027", -- 000018D0 - X"00163D82", -- 000018D4 - X"00161A80", -- 000018D8 - X"0067B025", -- 000018DC - X"00D83025", -- 000018E0 - X"8FA30000", -- 000018E4 - X"00111027", -- 000018E8 - X"8FA70018", -- 000018EC - X"00D33026", -- 000018F0 - X"005E1025", -- 000018F4 - X"00561026", -- 000018F8 - X"00C33021", -- 000018FC - X"00D53021", -- 00001900 - X"00471021", -- 00001904 - X"00C9A821", -- 00001908 - X"00521021", -- 0000190C - X"004A9021", -- 00001910 - X"00151C82", -- 00001914 - X"00151380", -- 00001918 - X"00431025", -- 0000191C - X"001236C2", -- 00001920 - X"00121940", -- 00001924 - X"0059A821", -- 00001928 - X"00661825", -- 0000192C - X"00143D82", -- 00001930 - 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X"00141180", -- 00001A64 - X"00431025", -- 00001A68 - X"001134C2", -- 00001A6C - X"00111B40", -- 00001A70 - X"0058A021", -- 00001A74 - X"8CA80010", -- 00001A78 - X"00661825", -- 00001A7C - X"00193D82", -- 00001A80 - X"00191280", -- 00001A84 - X"007E8821", -- 00001A88 - X"0047C825", -- 00001A8C - X"00133027", -- 00001A90 - X"00173D82", -- 00001A94 - X"00171A80", -- 00001A98 - X"AFA80038", -- 00001A9C - X"0067B825", -- 00001AA0 - X"00D43025", -- 00001AA4 - X"8CA30034", -- 00001AA8 - X"00161027", -- 00001AAC - X"00D93026", -- 00001AB0 - X"00511025", -- 00001AB4 - X"00571026", -- 00001AB8 - X"00C33021", -- 00001ABC - X"00D83021", -- 00001AC0 - X"00481021", -- 00001AC4 - X"00C9C021", -- 00001AC8 - X"005E1021", -- 00001ACC - X"004AF021", -- 00001AD0 - X"00181EC2", -- 00001AD4 - X"00181140", -- 00001AD8 - X"00431025", -- 00001ADC - X"001E3642", -- 00001AE0 - X"001E19C0", -- 00001AE4 - X"0055C021", -- 00001AE8 - X"00661825", -- 00001AEC - X"00133D82", -- 00001AF0 - X"00131280", -- 00001AF4 - X"0072F021", -- 00001AF8 - X"00479825", -- 00001AFC - X"00143027", -- 00001B00 - X"00163D82", -- 00001B04 - X"00111027", -- 00001B08 - X"00161A80", -- 00001B0C - X"0067B025", -- 00001B10 - X"8FA80034", -- 00001B14 - X"8CA7002C", -- 00001B18 - X"00D83025", -- 00001B1C - X"005E1025", -- 00001B20 - X"00D33026", -- 00001B24 - X"00561026", -- 00001B28 - X"00C73021", -- 00001B2C - X"00481021", -- 00001B30 - X"00D53021", -- 00001B34 - X"00521021", -- 00001B38 - X"00C9A821", -- 00001B3C - X"004A9021", -- 00001B40 - X"00151D02", -- 00001B44 - X"00123EC2", -- 00001B48 - X"00151300", -- 00001B4C - X"00123140", -- 00001B50 - X"00431025", -- 00001B54 - X"00C73025", -- 00001B58 - X"00141A80", -- 00001B5C - X"00143D82", -- 00001B60 - X"00D79021", -- 00001B64 - X"0059A821", -- 00001B68 - X"0067A025", -- 00001B6C - X"00181027", -- 00001B70 - X"00113582", -- 00001B74 - X"00111A80", -- 00001B78 - X"00668825", -- 00001B7C - X"00551025", -- 00001B80 - X"8CA30014", -- 00001B84 - X"00541026", -- 00001B88 - X"00123027", -- 00001B8C - X"00D13024", -- 00001B90 - X"00431021", -- 00001B94 - X"025E1824", -- 00001B98 - X"00661825", -- 00001B9C - X"00591021", -- 00001BA0 - X"006D1821", -- 00001BA4 - X"3C0B7A6D", -- 00001BA8 - X"356B76E9", -- 00001BAC - X"0049C821", -- 00001BB0 - X"00771821", -- 00001BB4 - X"006BB821", -- 00001BB8 - X"00193642", -- 00001BBC - X"001911C0", -- 00001BC0 - X"00461025", -- 00001BC4 - X"00174442", -- 00001BC8 - X"001733C0", -- 00001BCC - X"0053C821", -- 00001BD0 - X"00C83025", -- 00001BD4 - X"00183D82", -- 00001BD8 - X"00181280", -- 00001BDC - X"00D6B821", -- 00001BE0 - X"0047C025", -- 00001BE4 - X"00151827", -- 00001BE8 - X"001E3582", -- 00001BEC - X"001E1280", -- 00001BF0 - X"0046F025", -- 00001BF4 - X"00791825", -- 00001BF8 - X"8CA60030", -- 00001BFC - X"00781826", -- 00001C00 - X"00661821", -- 00001C04 - X"00173027", -- 00001C08 - X"00DE3024", -- 00001C0C - X"02F21024", -- 00001C10 - X"00731821", -- 00001C14 - X"00461025", -- 00001C18 - X"00699821", -- 00001C1C - X"004C1021", -- 00001C20 - X"001346C2", -- 00001C24 - X"00153D82", -- 00001C28 - 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X"00143D82", -- 00001FBC - X"00153200", -- 00001FC0 - X"00141280", -- 00001FC4 - X"0047A025", -- 00001FC8 - X"00C83025", -- 00001FCC - X"006BF021", -- 00001FD0 - X"00D9A821", -- 00001FD4 - X"001E1E82", -- 00001FD8 - X"00141027", -- 00001FDC - X"001E3180", -- 00001FE0 - X"00C33025", -- 00001FE4 - X"00581024", -- 00001FE8 - X"02B41824", -- 00001FEC - X"00621825", -- 00001FF0 - X"00163D82", -- 00001FF4 - X"00161280", -- 00001FF8 - X"00D2F021", -- 00001FFC - X"0047B025", -- 00002000 - X"8CA60034", -- 00002004 - X"8CA70030", -- 00002008 - X"001E1027", -- 0000200C - X"AFA70044", -- 00002010 - X"00561024", -- 00002014 - X"00661821", -- 00002018 - X"03D13024", -- 0000201C - X"00791821", -- 00002020 - X"00C23025", -- 00002024 - X"8FA20044", -- 00002028 - X"006AC821", -- 0000202C - X"001945C2", -- 00002030 - X"00183D82", -- 00002034 - X"00C23021", -- 00002038 - X"00191A40", -- 0000203C - X"00181280", -- 00002040 - X"0047C025", -- 00002044 - X"00681825", -- 00002048 - X"00D23021", -- 0000204C - X"0073C821", -- 00002050 - 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X"00000000", -- 00003B0C - X"00000000", -- 00003B10 - X"00000000", -- 00003B14 - X"00000000", -- 00003B18 - X"00000000", -- 00003B1C - X"00000000", -- 00003B20 - X"00000000", -- 00003B24 - X"00000000", -- 00003B28 - X"00000000", -- 00003B2C - X"00000000", -- 00003B30 - X"00000000", -- 00003B34 - X"00000000", -- 00003B38 - X"00000000", -- 00003B3C - X"00000000", -- 00003B40 - X"00000000", -- 00003B44 - X"00000000", -- 00003B48 - X"00000000", -- 00003B4C - X"00000000", -- 00003B50 - X"00000000", -- 00003B54 - X"00000000", -- 00003B58 - X"00000000", -- 00003B5C - X"00000000", -- 00003B60 - X"00000000", -- 00003B64 - X"00000000", -- 00003B68 - X"00000000", -- 00003B6C - X"00000000", -- 00003B70 - X"00000000", -- 00003B74 - X"00000000", -- 00003B78 - X"00000000", -- 00003B7C - X"00000000", -- 00003B80 - X"00000000", -- 00003B84 - X"00000000", -- 00003B88 - X"00000000", -- 00003B8C - X"00000000", -- 00003B90 - X"00000000", -- 00003B94 - X"00000000", -- 00003B98 - X"00000000", -- 00003B9C - X"00000000", -- 00003BA0 - X"00000000", -- 00003BA4 - X"00000000", -- 00003BA8 - X"00000000", -- 00003BAC - X"00000000", -- 00003BB0 - X"00000000", -- 00003BB4 - X"00000000", -- 00003BB8 - X"00000000", -- 00003BBC - X"00000000", -- 00003BC0 - X"00000000", -- 00003BC4 - X"00000000", -- 00003BC8 - X"00000000", -- 00003BCC - X"00000000", -- 00003BD0 - X"00000000", -- 00003BD4 - X"00000000", -- 00003BD8 - X"00000000", -- 00003BDC - X"00000000", -- 00003BE0 - X"00000000", -- 00003BE4 - X"00000000", -- 00003BE8 - X"00000000", -- 00003BEC - X"00000000", -- 00003BF0 - X"00000000", -- 00003BF4 - X"00000000", -- 00003BF8 - X"00000000", -- 00003BFC - X"00000000", -- 00003C00 - X"00000000", -- 00003C04 - X"00000000", -- 00003C08 - X"00000000", -- 00003C0C - X"00000000", -- 00003C10 - X"00000000", -- 00003C14 - X"00000000", -- 00003C18 - X"00000000", -- 00003C1C - X"00000000", -- 00003C20 - X"00000000", -- 00003C24 - X"00000000", -- 00003C28 - X"00000000", -- 00003C2C - X"00000000", -- 00003C30 - X"00000000", -- 00003C34 - X"00000000", -- 00003C38 - X"00000000", -- 00003C3C - X"00000000", -- 00003C40 - X"00000000", -- 00003C44 - X"00000000", -- 00003C48 - X"00000000", -- 00003C4C - X"00000000", -- 00003C50 - X"00000000", -- 00003C54 - X"00000000", -- 00003C58 - X"00000000", -- 00003C5C - X"00000000", -- 00003C60 - X"00000000", -- 00003C64 - X"00000000", -- 00003C68 - X"00000000", -- 00003C6C - X"00000000", -- 00003C70 - X"00000000", -- 00003C74 - X"00000000", -- 00003C78 - X"00000000", -- 00003C7C - X"00000000", -- 00003C80 - X"00000000", -- 00003C84 - X"00000000", -- 00003C88 - X"00000000", -- 00003C8C - X"00000000", -- 00003C90 - X"00000000", -- 00003C94 - X"00000000", -- 00003C98 - X"00000000", -- 00003C9C - X"00000000", -- 00003CA0 - X"00000000", -- 00003CA4 - X"00000000", -- 00003CA8 - X"00000000", -- 00003CAC - X"00000000", -- 00003CB0 - X"00000000", -- 00003CB4 - X"00000000", -- 00003CB8 - X"00000000", -- 00003CBC - X"00000000", -- 00003CC0 - X"00000000", -- 00003CC4 - X"00000000", -- 00003CC8 - X"00000000", -- 00003CCC - X"00000000", -- 00003CD0 - X"00000000", -- 00003CD4 - X"00000000", -- 00003CD8 - X"00000000", -- 00003CDC - X"00000000", -- 00003CE0 - X"00000000", -- 00003CE4 - X"00000000", -- 00003CE8 - X"00000000", -- 00003CEC - X"00000000", -- 00003CF0 - X"00000000", -- 00003CF4 - X"00000000", -- 00003CF8 - X"00000000", -- 00003CFC - X"00000000", -- 00003D00 - X"00000000", -- 00003D04 - X"00000000", -- 00003D08 - X"00000000", -- 00003D0C - X"00000000", -- 00003D10 - X"00000000", -- 00003D14 - X"00000000", -- 00003D18 - X"00000000", -- 00003D1C - X"00000000", -- 00003D20 - X"00000000", -- 00003D24 - X"00000000", -- 00003D28 - X"00000000", -- 00003D2C - X"00000000", -- 00003D30 - X"00000000", -- 00003D34 - X"00000000", -- 00003D38 - X"00000000", -- 00003D3C - X"00000000", -- 00003D40 - X"00000000", -- 00003D44 - X"00000000", -- 00003D48 - X"00000000", -- 00003D4C - X"00000000", -- 00003D50 - X"00000000", -- 00003D54 - X"00000000", -- 00003D58 - X"00000000", -- 00003D5C - X"00000000", -- 00003D60 - X"00000000", -- 00003D64 - X"00000000", -- 00003D68 - X"00000000", -- 00003D6C - X"00000000", -- 00003D70 - X"00000000", -- 00003D74 - X"00000000", -- 00003D78 - X"00000000", -- 00003D7C - X"00000000", -- 00003D80 - X"00000000", -- 00003D84 - X"00000000", -- 00003D88 - X"00000000", -- 00003D8C - X"00000000", -- 00003D90 - X"00000000", -- 00003D94 - X"00000000", -- 00003D98 - X"00000000", -- 00003D9C - X"00000000", -- 00003DA0 - X"00000000", -- 00003DA4 - X"00000000", -- 00003DA8 - X"00000000", -- 00003DAC - X"00000000", -- 00003DB0 - X"00000000", -- 00003DB4 - X"00000000", -- 00003DB8 - X"00000000", -- 00003DBC - X"00000000", -- 00003DC0 - X"00000000", -- 00003DC4 - X"00000000", -- 00003DC8 - X"00000000", -- 00003DCC - X"00000000", -- 00003DD0 - X"00000000", -- 00003DD4 - X"00000000", -- 00003DD8 - X"00000000", -- 00003DDC - X"00000000", -- 00003DE0 - X"00000000", -- 00003DE4 - X"00000000", -- 00003DE8 - X"00000000", -- 00003DEC - X"00000000", -- 00003DF0 - X"00000000", -- 00003DF4 - X"00000000", -- 00003DF8 - X"00000000", -- 00003DFC - X"00000000", -- 00003E00 - X"00000000", -- 00003E04 - X"00000000", -- 00003E08 - X"00000000", -- 00003E0C - X"00000000", -- 00003E10 - X"00000000", -- 00003E14 - X"00000000", -- 00003E18 - X"00000000", -- 00003E1C - X"00000000", -- 00003E20 - X"00000000", -- 00003E24 - X"00000000", -- 00003E28 - X"00000000", -- 00003E2C - X"00000000", -- 00003E30 - X"00000000", -- 00003E34 - X"00000000", -- 00003E38 - X"00000000", -- 00003E3C - X"00000000", -- 00003E40 - X"00000000", -- 00003E44 - X"00000000", -- 00003E48 - X"00000000", -- 00003E4C - X"00000000", -- 00003E50 - X"00000000", -- 00003E54 - X"00000000", -- 00003E58 - X"00000000", -- 00003E5C - X"00000000", -- 00003E60 - X"00000000", -- 00003E64 - X"00000000", -- 00003E68 - X"00000000", -- 00003E6C - X"00000000", -- 00003E70 - X"00000000", -- 00003E74 - X"00000000", -- 00003E78 - X"00000000", -- 00003E7C - X"00000000", -- 00003E80 - X"00000000", -- 00003E84 - X"00000000", -- 00003E88 - X"00000000", -- 00003E8C - X"00000000", -- 00003E90 - X"00000000", -- 00003E94 - X"00000000", -- 00003E98 - X"00000000", -- 00003E9C - X"00000000", -- 00003EA0 - X"00000000", -- 00003EA4 - X"00000000", -- 00003EA8 - X"00000000", -- 00003EAC - X"00000000", -- 00003EB0 - X"00000000", -- 00003EB4 - X"00000000", -- 00003EB8 - X"00000000", -- 00003EBC - X"00000000", -- 00003EC0 - X"00000000", -- 00003EC4 - X"00000000", -- 00003EC8 - X"00000000", -- 00003ECC - X"00000000", -- 00003ED0 - X"00000000", -- 00003ED4 - X"00000000", -- 00003ED8 - X"00000000", -- 00003EDC - X"00000000", -- 00003EE0 - X"00000000", -- 00003EE4 - X"00000000", -- 00003EE8 - X"00000000", -- 00003EEC - X"00000000", -- 00003EF0 - X"00000000", -- 00003EF4 - X"00000000", -- 00003EF8 - X"00000000", -- 00003EFC - X"00000000", -- 00003F00 - X"00000000", -- 00003F04 - X"00000000", -- 00003F08 - X"00000000", -- 00003F0C - X"00000000", -- 00003F10 - X"00000000", -- 00003F14 - X"00000000", -- 00003F18 - X"00000000", -- 00003F1C - X"00000000", -- 00003F20 - X"00000000", -- 00003F24 - X"00000000", -- 00003F28 - X"00000000", -- 00003F2C - X"00000000", -- 00003F30 - X"00000000", -- 00003F34 - X"00000000", -- 00003F38 - X"00000000", -- 00003F3C - X"00000000", -- 00003F40 - X"00000000", -- 00003F44 - X"00000000", -- 00003F48 - X"00000000", -- 00003F4C - X"00000000", -- 00003F50 - X"00000000", -- 00003F54 - X"00000000", -- 00003F58 - X"00000000", -- 00003F5C - X"00000000", -- 00003F60 - X"00000000", -- 00003F64 - X"00000000", -- 00003F68 - X"00000000", -- 00003F6C - X"00000000", -- 00003F70 - X"00000000", -- 00003F74 - X"00000000", -- 00003F78 - X"00000000", -- 00003F7C - X"00000000", -- 00003F80 - X"00000000", -- 00003F84 - X"00000000", -- 00003F88 - X"00000000", -- 00003F8C - X"00000000", -- 00003F90 - X"00000000", -- 00003F94 - X"00000000", -- 00003F98 - X"00000000", -- 00003F9C - X"00000000", -- 00003FA0 - X"00000000", -- 00003FA4 - X"00000000", -- 00003FA8 - X"00000000", -- 00003FAC - X"00000000", -- 00003FB0 - X"00000000", -- 00003FB4 - X"00000000", -- 00003FB8 - X"00000000", -- 00003FBC - X"00000000", -- 00003FC0 - X"00000000", -- 00003FC4 - X"00000000", -- 00003FC8 - X"00000000", -- 00003FCC - X"00000000", -- 00003FD0 - X"00000000", -- 00003FD4 - X"00000000", -- 00003FD8 - X"00000000", -- 00003FDC - X"00000000", -- 00003FE0 - X"00000000", -- 00003FE4 - X"00000000", -- 00003FE8 - X"00000000", -- 00003FEC - X"00000000", -- 00003FF0 - X"00000000", -- 00003FF4 - X"00000000", -- 00003FF8 - X"00000000" -- 00003FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(13 downto 2))); - end if; - end process; - - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; - - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - word_array(to_integer(jtag_ld_addr(11 downto 0))) <= jtag_ld_din; - else - jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(11 downto 0))); - end if; - end if; - end process; - -end data; diff --git a/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd b/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd deleted file mode 100644 index e4bbef2..0000000 --- a/lib/CPUs/MIPS/src/tb_eval_muldiv.vhd +++ /dev/null @@ -1,156 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -ENTITY tb_eval_muldiv IS -END tb_eval_muldiv; - -ARCHITECTURE behavior OF tb_eval_muldiv IS - - constant CLK_PERIOD : time := 10 ns; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal ce : std_logic := '0'; - signal mul_divn : std_logic := '1'; - signal op_valid : std_logic := '0'; - signal op1_in : word_t := (others => '-'); - signal op2_in : word_t := (others => '-'); - signal result : unsigned (2*word_t'length-1 downto 0); - signal res_valid : std_logic; - signal busy : std_logic; - signal result_reg : unsigned (2*word_t'length-1 downto 0); - subtype pp_t is unsigned (39 downto 0); - - signal pp0, pp1, pp2, pp3 : pp_t; - - signal signed_mul : std_logic := '1'; - signal sign1 : std_logic; - signal sign2 : std_logic; - signal cy : std_logic; - -BEGIN - - sign1 <= signed_mul and op1_in(op1_in'left); - sign2 <= signed_mul and op2_in(op1_in'left); - cy <= sign1; - - pp0 <= op1_in * op2_in(7 downto 0); - pp1 <= op1_in * op2_in(15 downto 8); - pp2 <= op1_in * op2_in(23 downto 16); - pp3 <= op1_in * op2_in(31 downto 24); - - result <= ((63 downto 40 => '0') & pp0) - + ((63 downto 48 => '0') & pp1 & (7 downto 0 => '0')) - + ((63 downto 56 => '0') & pp2 & (15 downto 0 => '0')) - + (pp3 & (23 downto 0 => '0')); - - result_reg <= (63 downto 0 => sign1) xor (result + ((63 downto 0 => sign1) and X"0000_0000_0000_0000")); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 10*CLK_PERIOD; - - wait until rising_edge(clk); - ce <= '1'; - - wait for 10*CLK_PERIOD; - op1_in <= X"FFFF_FFFA"; -- (-6) - op2_in <= X"0000_0005"; -- (+5) - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"0000_0006"; -- (+6) - op2_in <= X"FFFF_FFFB"; -- (-5) - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"1234_5678"; - op2_in <= X"8765_4321"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"8765_4321"; - op2_in <= X"1234_5678"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"1234_5678"; - op2_in <= X"1234_5678"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"8765_4321"; - op2_in <= X"8765_4321"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"789A_BCDE"; - op2_in <= X"8765_4321"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait for 10*CLK_PERIOD; - op1_in <= X"8765_4321"; - op2_in <= X"789A_BCDE"; - op_valid <= '1'; - wait until rising_edge(clk); - op_valid <= '0'; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_embedded.vhd b/lib/CPUs/MIPS/src/tb_mips_embedded.vhd deleted file mode 100644 index cbae0b7..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_embedded.vhd +++ /dev/null @@ -1,82 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.mips_types.all; - -ENTITY tb_mips_embedded IS -END tb_mips_embedded; - -ARCHITECTURE behavior OF tb_mips_embedded IS - - COMPONENT mips_embedded - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - dout : out word_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal halt : std_logic := '0'; - signal dout : word_t; - -BEGIN - -uut: mips_embedded - PORT MAP( - rst => rst, - clk => clk, - halt => halt, - dout => dout - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -STIMULUS: process - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd b/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd deleted file mode 100644 index ac471b4..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_embedded_syn.vhd +++ /dev/null @@ -1,123 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -ENTITY tb_mips_embedded_syn IS -END tb_mips_embedded_syn; - -ARCHITECTURE behavior OF tb_mips_embedded_syn IS - - COMPONENT mips_embedded_syn - Port - ( - sys_rst_n_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_dip : in STD_LOGIC_VECTOR (7 downto 0); - sys_btn : in STD_LOGIC_VECTOR (8 downto 0); - sys_led : out STD_LOGIC_VECTOR (7 downto 0); - sys_rx : in STD_LOGIC; - sys_tx : out STD_LOGIC; - sys_error : out STD_LOGIC_VECTOR (1 downto 0) - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10.0 ns; - - signal sys_rst_n_in : std_logic := '0'; - signal sys_clk_in : std_logic := '1'; - signal sys_led : STD_LOGIC_VECTOR (7 downto 0); - signal sys_btn : STD_LOGIC_VECTOR (8 downto 0) := "000000000"; - signal sys_dip : STD_LOGIC_VECTOR (7 downto 0) := "10001001"; - signal sys_error : STD_LOGIC_VECTOR (1 downto 0); - signal sys_rx : std_logic := '1'; - signal sys_tx : std_logic; - -BEGIN - -uut: mips_embedded_syn - PORT MAP - ( - sys_rst_n_in => sys_rst_n_in, - sys_clk_in => sys_clk_in, - sys_btn => sys_btn, - sys_dip => sys_dip, - sys_led => sys_led, - sys_rx => sys_rx, - sys_tx => sys_tx, - sys_error => sys_error - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - sys_clk_in <= not sys_clk_in; - end process; - -STIMULUS1: process - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(sys_clk_in); - sys_rst_n_in <= '1'; - - - --- wait for 9994999*CLK_PERIOD; --- for i in 1 to 10000 loop --- wait for 100*CLK_PERIOD; --- sys_btn(3) <= '1'; --- wait for 10*CLK_PERIOD; --- sys_btn(3) <= '0'; --- end loop; - - wait until rising_edge(sys_clk_in) and now = 38980 ns; - sys_btn <= "000001000"; - wait until rising_edge(sys_clk_in); - sys_btn <= "000000000"; - - wait; - - end process; - -STIMULUS2: process - begin - - - wait for 9999999*CLK_PERIOD; - for i in 1 to 10000 loop - wait for 137*CLK_PERIOD; - sys_btn(4) <= '1'; - wait for 21*CLK_PERIOD; - sys_btn(4) <= '0'; - end loop; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd b/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd deleted file mode 100644 index 8235438..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_muldiv.vhd +++ /dev/null @@ -1,308 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -ENTITY tb_mips_muldiv IS -END tb_mips_muldiv; - -ARCHITECTURE behavior OF tb_mips_muldiv IS - - COMPONENT muldiv is - Port - ( - rst : in std_logic; - clk : in std_logic; - hilo_we : in std_logic; - din_hi : in word_t; - din_lo : in word_t; - mul_divn : in std_logic; - s_un : in std_logic; - start : in std_logic; - hilo_sel : in std_logic; - busy : out std_logic; - dout : out word_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - signal ENABLE_FAIL_REPORT : boolean := true; - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal busy : std_logic; - signal mul_divn : std_logic := '0'; - signal s_un : std_logic := '1'; - signal hilo_we : std_logic := '0'; - signal start : std_logic := '0'; - signal din_hi : word_t := (others => '-'); - signal din_lo : word_t := (others => '-'); - signal ref_hi : word_t := (others => '-'); - signal ref_lo : word_t := (others => '-'); - signal dout : word_t; - signal hilo_sel : std_logic := '0'; - signal result : unsigned (2*word_t'length-1 downto 0); - signal ref_result : unsigned (2*word_t'length-1 downto 0); - - type word_array_t is array (natural range <>) of word_t; - - constant operands : word_array_t(0 to 63) := - ( - X"00000000", - X"00000001", - X"00000010", - X"00000100", - X"00001000", - X"00010000", - X"00100000", - X"01000000", - X"10000000", - X"0000000F", - X"000000FF", - X"00000FFF", - X"0000FFFF", - X"000FFFFF", - X"00FFFFFF", - X"0FFFFFFF", - X"12345678", - X"23456789", - X"7FFFFFFF", - X"80000000", - X"A541B3B9", - X"80000001", - X"80000010", - X"80000100", - X"80001000", - X"80010000", - X"80100000", - X"81000000", - X"87654321", - X"98765432", - X"FFFFFFFF", - X"FFFFFFFE", - X"FFFFFFFD", - X"FFFFFFFB", - X"FFFFFFF7", - X"FFFFFFEF", - X"FFFFFFDF", - X"FFFFFFBF", - X"FFFFFF7F", - X"FFFFFEFF", - X"FFFFFDFF", - X"FFFFFBFF", - X"FFFFF7FF", - X"FFFFEFFF", - X"FFFFDFFF", - X"FFFFBFFF", - X"FFFF7FFF", - X"FFFEFFFF", - X"FFFDFFFF", - X"FFFBFFFF", - X"FFF7FFFF", - X"FFEFFFFF", - X"FFDFFFFF", - X"FFBFFFFF", - X"FF7FFFFF", - X"FEFFFFFF", - X"FDFFFFFF", - X"FBFFFFFF", - X"F7FFFFFF", - X"EFFFFFFF", - X"DFFFFFFF", - X"BFFFFFFF", - X"CFFFFFFF", - X"7FFFFFFF" - ); - -BEGIN - -uut: muldiv - PORT MAP( - rst => rst, - clk => clk, - hilo_we => hilo_we, - din_hi => din_hi, - din_lo => din_lo, - mul_divn => mul_divn, - s_un => s_un, - start => start, - hilo_sel => hilo_sel, - busy => busy, - dout => dout - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -REF_GEN: process - variable tmp : unsigned (2*word_t'length-1 downto 0); - variable tmp2 : unsigned (word_t'length-1 downto 0); - begin - if mul_divn = '0' then - wait until rising_edge(clk) and start = '1'; - ref_lo <= din_lo; - ref_hi <= din_hi; - wait until rising_edge(clk) and busy = '0'; - wait until rising_edge(clk); - wait until rising_edge(clk); - if s_un = '1' then - tmp := unsigned(signed(result(31 downto 0)) * signed(ref_lo)); - tmp2 := unsigned(signed(tmp(31 downto 0)) + signed(result(63 downto 32))); - ref_result <= X"00000000" & tmp2(31 downto 0); - else - tmp := result(31 downto 0) * ref_lo; - tmp2 := tmp(31 downto 0) + result(63 downto 32); - ref_result <= X"00000000" & tmp2(31 downto 0); - end if; - wait until rising_edge(clk); - - if ref_lo /= X"00000000" then - if ENABLE_FAIL_REPORT then - assert ref_hi = ref_result(31 downto 0) report "Error on divison" severity failure; - end if; - end if; - else - wait until rising_edge(clk) and start = '1'; - wait until rising_edge(clk) and busy = '0'; - if s_un = '1' then - ref_result <= unsigned(signed(din_hi) * signed(din_lo)); - else - ref_result <= unsigned(din_hi) * unsigned(din_lo); - end if; - wait until rising_edge(clk); - wait until rising_edge(clk); - wait until rising_edge(clk); - if ENABLE_FAIL_REPORT then - assert ref_result = result report "Error on multiplication" severity failure; - end if; - end if; - - end process; - -STIMULUS: process - - begin - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 2*CLK_PERIOD; - - mul_divn <= '0'; - s_un <= '0'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - result(31 downto 0) <= dout; - hilo_sel <= '1'; - wait until rising_edge(clk); - result(63 downto 32) <= dout; - wait for 2*CLK_PERIOD; - end loop; - end loop; - - s_un <= '1'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - result(31 downto 0) <= dout; - hilo_sel <= '1'; - wait until rising_edge(clk); - result(63 downto 32) <= dout; - wait for 2*CLK_PERIOD; - end loop; - end loop; - - mul_divn <= '1'; - s_un <= '0'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - result(31 downto 0) <= dout; - hilo_sel <= '1'; - wait until rising_edge(clk); - result(63 downto 32) <= dout; - end loop; - end loop; - - s_un <= '1'; - for i in 0 to operands'length-1 loop - for j in 0 to operands'length-1 loop - wait until rising_edge(clk) and busy = '0'; - din_hi <= operands(i); - din_lo <= operands(j); - start <= '1'; - wait until rising_edge(clk); - start <= '0'; - hilo_sel <= '0'; - - -- Read result - wait until rising_edge(clk) and busy = '0'; - result(31 downto 0) <= dout; - hilo_sel <= '1'; - wait until rising_edge(clk); - result(63 downto 32) <= dout; - end loop; - end loop; - - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/tb_mips_top.vhd b/lib/CPUs/MIPS/src/tb_mips_top.vhd deleted file mode 100644 index 0bf5fed..0000000 --- a/lib/CPUs/MIPS/src/tb_mips_top.vhd +++ /dev/null @@ -1,174 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: Testbench for JCPU --- also writes 'opc.lst' for JASM-assembler --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.mips_types.all; -use work.mips_instr.all; - -ENTITY tb_mips_top IS -END tb_mips_top; - -ARCHITECTURE behavior OF tb_mips_top IS - - COMPONENT mips_top - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - halt : in STD_LOGIC; - imem_din : in unsigned (WORD_WIDTH-1 downto 0); - imem_addr : out unsigned (WORD_WIDTH-1 downto 0); - dmem_we : out STD_LOGIC; - dmem_re : out STD_LOGIC; - dmem_din : in unsigned (WORD_WIDTH-1 downto 0); - dmem_dout : out unsigned (WORD_WIDTH-1 downto 0); - dmem_addr : out unsigned (WORD_WIDTH-1 downto 0) - - ); - END COMPONENT; - - COMPONENT rom - Port - ( - clk : in STD_LOGIC; - addr : in word_t; - dout : out word_t - ); - END COMPONENT; - - COMPONENT ram - Generic - ( - word_addr_width : integer - ); - Port - ( - clk : in STD_LOGIC; - we : in STD_LOGIC; - addr : in word_t; - din : in word_t; - dout : out word_t - ); - END COMPONENT; - - constant CLK_PERIOD : time := 10 ns; - - signal rst : std_logic := '1'; - signal clk : std_logic := '1'; - signal cpu_halt : std_logic; - signal irom_data : word_t := (others => '-'); - signal irom_addr : word_t; - signal dmem_din : word_t := (others => '-'); - signal dmem_dout : word_t; - signal dmem_addr : word_t; - signal dmem_we : std_logic; - signal dmem_re : std_logic; - -BEGIN - -uut: mips_top - PORT MAP( - rst => rst, - clk => clk, - halt => cpu_halt, - imem_din => irom_data, - imem_addr => irom_addr, - dmem_we => dmem_we, - dmem_re => dmem_re, - dmem_din => dmem_din, - dmem_dout => dmem_dout, - dmem_addr => dmem_addr - ); - -inst_rom: rom - PORT MAP - ( - clk => clk, - addr => irom_addr, - dout => irom_data - ); - -inst_ram: ram - GENERIC MAP - ( - word_addr_width => 6 - ) - PORT MAP - ( - clk => clk, - we => dmem_we, - addr => dmem_addr, - din => dmem_dout, - dout => dmem_din - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -HLT_GEN: - process(rst, clk) - subtype cnt_t is natural range 0 to 2; - variable cnt : cnt_t; - begin - if rst = '1' then - cnt := cnt_t'high; - cpu_halt <= '0'; - elsif rising_edge(clk) then - cpu_halt <= '0'; - if cnt /= 0 then - cnt := cnt - 1; - else - cnt := cnt_t'high; - cpu_halt <= '1'; - end if; - end if; - end process; - -STIMULUS: process - - begin - --- for i in 0 to instr_name_array'length-1 loop --- fprint(RESULT, L,"%d %s\n", fo(i), instr_name_array(i)); --- end loop; - - wait for 3*CLK_PERIOD; - wait until rising_edge(clk); - rst <= '0'; - wait for 2*CLK_PERIOD; - --- assert false report "Test finished" severity error; - wait; - - end process; - -END; diff --git a/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd b/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd deleted file mode 100644 index f46253b..0000000 --- a/lib/CPUs/MIPS/src/testbench.ROM_ld.vhd +++ /dev/null @@ -1,4222 +0,0 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY icache IS - Port - ( - clk : in STD_LOGIC; - ce : in STD_LOGIC; - addr : in unsigned(31 downto 0); - dout : out unsigned(31 downto 0) - ); -END icache; - -ARCHITECTURE data OF icache IS - - subtype word_t is unsigned(31 downto 0); - type word_array_t is array (0 to 4095) of word_t; - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - - signal word_array : word_array_t := - ( - - X"3C1A1040", -- 00000000 - X"375A040C", -- 00000004 - X"409A6000", -- 00000008 - X"241A0000", -- 0000000C - X"409A6800", -- 00000010 - X"401A7800", -- 00000014 - X"00000000", -- 00000018 - X"409AF800", -- 0000001C - X"3C1A0040", -- 00000020 - X"275A04F4", -- 00000024 - X"03400008", -- 00000028 - X"42000010", -- 0000002C - X"00000000", -- 00000030 - X"00000000", -- 00000034 - X"00000000", -- 00000038 - X"00000000", -- 0000003C - X"00000000", -- 00000040 - X"00000000", -- 00000044 - X"00000000", -- 00000048 - X"00000000", -- 0000004C - X"00000000", -- 00000050 - X"00000000", -- 00000054 - X"00000000", -- 00000058 - X"00000000", -- 0000005C - X"00000000", -- 00000060 - X"00000000", -- 00000064 - X"00000000", -- 00000068 - X"00000000", -- 0000006C - X"00000000", -- 00000070 - X"00000000", -- 00000074 - X"00000000", -- 00000078 - X"00000000", -- 0000007C - X"00000000", -- 00000080 - X"00000000", -- 00000084 - X"00000000", -- 00000088 - X"00000000", -- 0000008C - X"00000000", -- 00000090 - X"00000000", -- 00000094 - X"00000000", -- 00000098 - X"00000000", -- 0000009C - X"00000000", -- 000000A0 - X"00000000", -- 000000A4 - X"00000000", -- 000000A8 - X"00000000", -- 000000AC - X"00000000", -- 000000B0 - X"00000000", -- 000000B4 - X"00000000", -- 000000B8 - X"00000000", -- 000000BC - X"00000000", -- 000000C0 - X"00000000", -- 000000C4 - X"00000000", -- 000000C8 - X"00000000", -- 000000CC - X"00000000", -- 000000D0 - X"00000000", -- 000000D4 - X"00000000", -- 000000D8 - X"00000000", -- 000000DC - X"00000000", -- 000000E0 - X"00000000", -- 000000E4 - X"00000000", -- 000000E8 - X"00000000", -- 000000EC - X"00000000", -- 000000F0 - X"00000000", -- 000000F4 - X"00000000", -- 000000F8 - X"00000000", -- 000000FC - X"00000000", -- 00000100 - X"00000000", -- 00000104 - X"00000000", -- 00000108 - X"00000000", -- 0000010C - X"00000000", -- 00000110 - X"00000000", -- 00000114 - X"00000000", -- 00000118 - X"00000000", -- 0000011C - X"00000000", -- 00000120 - X"00000000", -- 00000124 - X"00000000", -- 00000128 - X"00000000", -- 0000012C - X"00000000", -- 00000130 - X"00000000", -- 00000134 - X"00000000", -- 00000138 - X"00000000", -- 0000013C - X"00000000", -- 00000140 - X"00000000", -- 00000144 - X"00000000", -- 00000148 - X"00000000", -- 0000014C - X"00000000", -- 00000150 - X"00000000", -- 00000154 - X"00000000", -- 00000158 - X"00000000", -- 0000015C - X"00000000", -- 00000160 - X"00000000", -- 00000164 - X"00000000", -- 00000168 - X"00000000", -- 0000016C - X"00000000", -- 00000170 - X"00000000", -- 00000174 - X"00000000", -- 00000178 - X"00000000", -- 0000017C - X"3C010000", -- 00000180 - X"AC3D09A0", -- 00000184 - X"3C1D0000", -- 00000188 - X"27BD09A0", -- 0000018C - X"27BD0004", -- 00000190 - X"AFA80000", -- 00000194 - X"27BD0004", -- 00000198 - X"AFA90000", -- 0000019C - X"27BD0004", -- 000001A0 - X"AFAA0000", -- 000001A4 - X"27BD0004", -- 000001A8 - X"AFAB0000", -- 000001AC - X"27BD0004", -- 000001B0 - X"AFAC0000", -- 000001B4 - X"27BD0004", -- 000001B8 - X"AFBF0000", -- 000001BC - X"400A4000", -- 000001C0 - X"27BD0004", -- 000001C4 - X"AFAA0000", -- 000001C8 - X"400A6000", -- 000001CC - X"27BD0004", -- 000001D0 - X"AFAA0000", -- 000001D4 - X"400A6800", -- 000001D8 - X"27BD0004", -- 000001DC - X"AFAA0000", -- 000001E0 - X"000A5742", -- 000001E4 - X"314B0004", -- 000001E8 - X"400A7000", -- 000001EC - X"27BD0004", -- 000001F0 - X"AFAA0000", -- 000001F4 - X"014B5021", -- 000001F8 - X"27BD0004", -- 000001FC - X"AFAA0000", -- 00000200 - X"3C1A8000", -- 00000204 - X"275A0009", -- 00000208 - X"241B000D", -- 0000020C - X"A35B0000", -- 00000210 - X"3C0B0000", -- 00000214 - X"256B0ADE", -- 00000218 - X"0C10012B", -- 0000021C - X"00000000", -- 00000220 - X"3C0B0000", -- 00000224 - X"256B0AA0", -- 00000228 - X"0C10012B", -- 0000022C - X"00000000", -- 00000230 - X"8FAA0000", -- 00000234 - X"27BDFFFC", -- 00000238 - X"0C1000E3", -- 0000023C - X"00000000", -- 00000240 - X"3C0B0000", -- 00000244 - X"256B0ADE", -- 00000248 - X"0C10012B", -- 0000024C - X"00000000", -- 00000250 - X"3C0B0000", -- 00000254 - X"256B0AAE", -- 00000258 - X"0C10012B", -- 0000025C - X"00000000", -- 00000260 - X"8FAA0000", -- 00000264 - X"27BDFFFC", -- 00000268 - X"0C1000E3", -- 0000026C - X"00000000", -- 00000270 - X"3C0B0000", -- 00000274 - X"256B0ADE", -- 00000278 - X"0C10012B", -- 0000027C - X"00000000", -- 00000280 - X"3C0B0000", -- 00000284 - X"256B0ABA", -- 00000288 - X"0C10012B", -- 0000028C - X"00000000", -- 00000290 - X"8FAA0000", -- 00000294 - X"27BDFFFC", -- 00000298 - X"0C1000E3", -- 0000029C - X"00000000", -- 000002A0 - X"3C0B0000", -- 000002A4 - X"256B0ADE", -- 000002A8 - X"0C10012B", -- 000002AC - X"00000000", -- 000002B0 - X"3C0B0000", -- 000002B4 - X"256B0AC6", -- 000002B8 - X"0C10012B", -- 000002BC - X"00000000", -- 000002C0 - X"8FAA0000", -- 000002C4 - X"27BDFFFC", -- 000002C8 - X"0C1000E3", -- 000002CC - X"00000000", -- 000002D0 - X"3C0B0000", -- 000002D4 - X"256B0ADE", -- 000002D8 - X"0C10012B", -- 000002DC - X"00000000", -- 000002E0 - X"3C0B0000", -- 000002E4 - X"256B0AD2", -- 000002E8 - X"0C10012B", -- 000002EC - X"00000000", -- 000002F0 - X"8FAA0000", -- 000002F4 - X"27BDFFFC", -- 000002F8 - X"0C1000E3", -- 000002FC - X"00000000", -- 00000300 - X"3C0B0000", -- 00000304 - X"256B0ADE", -- 00000308 - X"0C10012B", -- 0000030C - X"00000000", -- 00000310 - X"401A6800", -- 00000314 - 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X"00A40018", -- 00001C08 - X"00661823", -- 00001C0C - X"00031100", -- 00001C10 - X"00431023", -- 00001C14 - X"00021080", -- 00001C18 - X"01021023", -- 00001C1C - X"AE220000", -- 00001C20 - X"00002010", -- 00001C24 - X"00852021", -- 00001C28 - X"00042083", -- 00001C2C - X"00872023", -- 00001C30 - X"000410C0", -- 00001C34 - X"00441023", -- 00001C38 - X"00A22823", -- 00001C3C - X"04A0008B", -- 00001C40 - X"AE230004", -- 00001C44 - X"AE250018", -- 00001C48 - X"05200060", -- 00001C4C - X"241007B2", -- 00001C50 - X"27860978", -- 00001C54 - X"32020003", -- 00001C58 - X"001027C3", -- 00001C5C - X"1440000E", -- 00001C60 - X"00002821", -- 00001C64 - X"3C0351EB", -- 00001C68 - X"3463851F", -- 00001C6C - X"02030018", -- 00001C70 - X"00001810", -- 00001C74 - X"00031943", -- 00001C78 - X"00641823", -- 00001C7C - X"00031040", -- 00001C80 - X"00431021", -- 00001C84 - X"000210C0", -- 00001C88 - X"00431021", -- 00001C8C - X"00021080", -- 00001C90 - X"16020017", -- 00001C94 - X"00000000", -- 00001C98 - X"3C0351EB", -- 00001C9C - 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X"00000000", -- 00003C18 - X"00000000", -- 00003C1C - X"00000000", -- 00003C20 - X"00000000", -- 00003C24 - X"00000000", -- 00003C28 - X"00000000", -- 00003C2C - X"00000000", -- 00003C30 - X"00000000", -- 00003C34 - X"00000000", -- 00003C38 - X"00000000", -- 00003C3C - X"00000000", -- 00003C40 - X"00000000", -- 00003C44 - X"00000000", -- 00003C48 - X"00000000", -- 00003C4C - X"00000000", -- 00003C50 - X"00000000", -- 00003C54 - X"00000000", -- 00003C58 - X"00000000", -- 00003C5C - X"00000000", -- 00003C60 - X"00000000", -- 00003C64 - X"00000000", -- 00003C68 - X"00000000", -- 00003C6C - X"00000000", -- 00003C70 - X"00000000", -- 00003C74 - X"00000000", -- 00003C78 - X"00000000", -- 00003C7C - X"00000000", -- 00003C80 - X"00000000", -- 00003C84 - X"00000000", -- 00003C88 - X"00000000", -- 00003C8C - X"00000000", -- 00003C90 - X"00000000", -- 00003C94 - X"00000000", -- 00003C98 - X"00000000", -- 00003C9C - X"00000000", -- 00003CA0 - X"00000000", -- 00003CA4 - X"00000000", -- 00003CA8 - X"00000000", -- 00003CAC - X"00000000", -- 00003CB0 - X"00000000", -- 00003CB4 - X"00000000", -- 00003CB8 - X"00000000", -- 00003CBC - X"00000000", -- 00003CC0 - X"00000000", -- 00003CC4 - X"00000000", -- 00003CC8 - X"00000000", -- 00003CCC - X"00000000", -- 00003CD0 - X"00000000", -- 00003CD4 - X"00000000", -- 00003CD8 - X"00000000", -- 00003CDC - X"00000000", -- 00003CE0 - X"00000000", -- 00003CE4 - X"00000000", -- 00003CE8 - X"00000000", -- 00003CEC - X"00000000", -- 00003CF0 - X"00000000", -- 00003CF4 - X"00000000", -- 00003CF8 - X"00000000", -- 00003CFC - X"00000000", -- 00003D00 - X"00000000", -- 00003D04 - X"00000000", -- 00003D08 - X"00000000", -- 00003D0C - X"00000000", -- 00003D10 - X"00000000", -- 00003D14 - X"00000000", -- 00003D18 - X"00000000", -- 00003D1C - X"00000000", -- 00003D20 - X"00000000", -- 00003D24 - X"00000000", -- 00003D28 - X"00000000", -- 00003D2C - X"00000000", -- 00003D30 - X"00000000", -- 00003D34 - X"00000000", -- 00003D38 - X"00000000", -- 00003D3C - X"00000000", -- 00003D40 - X"00000000", -- 00003D44 - X"00000000", -- 00003D48 - X"00000000", -- 00003D4C - X"00000000", -- 00003D50 - X"00000000", -- 00003D54 - X"00000000", -- 00003D58 - X"00000000", -- 00003D5C - X"00000000", -- 00003D60 - X"00000000", -- 00003D64 - X"00000000", -- 00003D68 - X"00000000", -- 00003D6C - X"00000000", -- 00003D70 - X"00000000", -- 00003D74 - X"00000000", -- 00003D78 - X"00000000", -- 00003D7C - X"00000000", -- 00003D80 - X"00000000", -- 00003D84 - X"00000000", -- 00003D88 - X"00000000", -- 00003D8C - X"00000000", -- 00003D90 - X"00000000", -- 00003D94 - X"00000000", -- 00003D98 - X"00000000", -- 00003D9C - X"00000000", -- 00003DA0 - X"00000000", -- 00003DA4 - X"00000000", -- 00003DA8 - X"00000000", -- 00003DAC - X"00000000", -- 00003DB0 - X"00000000", -- 00003DB4 - X"00000000", -- 00003DB8 - X"00000000", -- 00003DBC - X"00000000", -- 00003DC0 - X"00000000", -- 00003DC4 - X"00000000", -- 00003DC8 - X"00000000", -- 00003DCC - X"00000000", -- 00003DD0 - X"00000000", -- 00003DD4 - X"00000000", -- 00003DD8 - X"00000000", -- 00003DDC - X"00000000", -- 00003DE0 - X"00000000", -- 00003DE4 - X"00000000", -- 00003DE8 - X"00000000", -- 00003DEC - X"00000000", -- 00003DF0 - X"00000000", -- 00003DF4 - X"00000000", -- 00003DF8 - X"00000000", -- 00003DFC - X"00000000", -- 00003E00 - X"00000000", -- 00003E04 - X"00000000", -- 00003E08 - X"00000000", -- 00003E0C - X"00000000", -- 00003E10 - X"00000000", -- 00003E14 - X"00000000", -- 00003E18 - X"00000000", -- 00003E1C - X"00000000", -- 00003E20 - X"00000000", -- 00003E24 - X"00000000", -- 00003E28 - X"00000000", -- 00003E2C - X"00000000", -- 00003E30 - X"00000000", -- 00003E34 - X"00000000", -- 00003E38 - X"00000000", -- 00003E3C - X"00000000", -- 00003E40 - X"00000000", -- 00003E44 - X"00000000", -- 00003E48 - X"00000000", -- 00003E4C - X"00000000", -- 00003E50 - X"00000000", -- 00003E54 - X"00000000", -- 00003E58 - X"00000000", -- 00003E5C - X"00000000", -- 00003E60 - X"00000000", -- 00003E64 - X"00000000", -- 00003E68 - X"00000000", -- 00003E6C - X"00000000", -- 00003E70 - X"00000000", -- 00003E74 - X"00000000", -- 00003E78 - X"00000000", -- 00003E7C - X"00000000", -- 00003E80 - X"00000000", -- 00003E84 - X"00000000", -- 00003E88 - X"00000000", -- 00003E8C - X"00000000", -- 00003E90 - X"00000000", -- 00003E94 - X"00000000", -- 00003E98 - X"00000000", -- 00003E9C - X"00000000", -- 00003EA0 - X"00000000", -- 00003EA4 - X"00000000", -- 00003EA8 - X"00000000", -- 00003EAC - X"00000000", -- 00003EB0 - X"00000000", -- 00003EB4 - X"00000000", -- 00003EB8 - X"00000000", -- 00003EBC - X"00000000", -- 00003EC0 - X"00000000", -- 00003EC4 - X"00000000", -- 00003EC8 - X"00000000", -- 00003ECC - X"00000000", -- 00003ED0 - X"00000000", -- 00003ED4 - X"00000000", -- 00003ED8 - X"00000000", -- 00003EDC - X"00000000", -- 00003EE0 - X"00000000", -- 00003EE4 - X"00000000", -- 00003EE8 - X"00000000", -- 00003EEC - X"00000000", -- 00003EF0 - X"00000000", -- 00003EF4 - X"00000000", -- 00003EF8 - X"00000000", -- 00003EFC - X"00000000", -- 00003F00 - X"00000000", -- 00003F04 - X"00000000", -- 00003F08 - X"00000000", -- 00003F0C - X"00000000", -- 00003F10 - X"00000000", -- 00003F14 - X"00000000", -- 00003F18 - X"00000000", -- 00003F1C - X"00000000", -- 00003F20 - X"00000000", -- 00003F24 - X"00000000", -- 00003F28 - X"00000000", -- 00003F2C - X"00000000", -- 00003F30 - X"00000000", -- 00003F34 - X"00000000", -- 00003F38 - X"00000000", -- 00003F3C - X"00000000", -- 00003F40 - X"00000000", -- 00003F44 - X"00000000", -- 00003F48 - X"00000000", -- 00003F4C - X"00000000", -- 00003F50 - X"00000000", -- 00003F54 - X"00000000", -- 00003F58 - X"00000000", -- 00003F5C - X"00000000", -- 00003F60 - X"00000000", -- 00003F64 - X"00000000", -- 00003F68 - X"00000000", -- 00003F6C - X"00000000", -- 00003F70 - X"00000000", -- 00003F74 - X"00000000", -- 00003F78 - X"00000000", -- 00003F7C - X"00000000", -- 00003F80 - X"00000000", -- 00003F84 - X"00000000", -- 00003F88 - X"00000000", -- 00003F8C - X"00000000", -- 00003F90 - X"00000000", -- 00003F94 - X"00000000", -- 00003F98 - X"00000000", -- 00003F9C - X"00000000", -- 00003FA0 - X"00000000", -- 00003FA4 - X"00000000", -- 00003FA8 - X"00000000", -- 00003FAC - X"00000000", -- 00003FB0 - X"00000000", -- 00003FB4 - X"00000000", -- 00003FB8 - X"00000000", -- 00003FBC - X"00000000", -- 00003FC0 - X"00000000", -- 00003FC4 - X"00000000", -- 00003FC8 - X"00000000", -- 00003FCC - X"00000000", -- 00003FD0 - X"00000000", -- 00003FD4 - X"00000000", -- 00003FD8 - X"00000000", -- 00003FDC - X"00000000", -- 00003FE0 - X"00000000", -- 00003FE4 - X"00000000", -- 00003FE8 - X"00000000", -- 00003FEC - X"00000000", -- 00003FF0 - X"00000000", -- 00003FF4 - X"00000000", -- 00003FF8 - X"00000000" -- 00003FFC - ); - -begin - -PROM_READ: - process(clk) - begin - if rising_edge(clk) and ce = '1' then - dout <= word_array(to_integer(addr(13 downto 2))); - end if; - end process; - - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; - - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - word_array(to_integer(jtag_ld_addr(11 downto 0))) <= jtag_ld_din; - else - jtag_ld_dout <= word_array(to_integer(jtag_ld_addr(11 downto 0))); - end if; - end if; - end process; - -end data; diff --git a/lib/CPUs/MIPS/tools/insrom.rb b/lib/CPUs/MIPS/tools/insrom.rb deleted file mode 100644 index fdbf1ed..0000000 --- a/lib/CPUs/MIPS/tools/insrom.rb +++ /dev/null @@ -1,46 +0,0 @@ -#!/usr/bin/env ruby - -# ---------------------------------------------------------------------- -# Project: JIPS, a portable 32-bit RISC CPU written in VHDL -# This file: Insertion of code fragments into templates -# -# Copyright (C) 2008 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -arg = $* -rom_filename = arg[0].to_s -tpl_filename = arg[1].to_s - -subst_pattern = "ROM_INSERT_HERE" - -# -------------------------------------------------------- -# Open file -# -------------------------------------------------------- -romfile = File.open(rom_filename, "r") -tplfile = File.open(tpl_filename, "r") -re = Regexp.new(subst_pattern) - -while (line = tplfile.gets) - puts line - line.scan(re).each do |word| - romfile.each do |raw_line| - puts raw_line - end - end -end diff --git a/lib/CPUs/MIPS/tools/irom.vhd.tpl b/lib/CPUs/MIPS/tools/irom.vhd.tpl deleted file mode 100644 index 5ffd6d7..0000000 --- a/lib/CPUs/MIPS/tools/irom.vhd.tpl +++ /dev/null @@ -1,29 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: The ROM file for use in your VHDL design --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - --- ROM_INSERT_HERE - diff --git a/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl b/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl deleted file mode 100644 index 3bd3afb..0000000 --- a/lib/CPUs/MIPS/tools/irom_ld.vhd.tpl +++ /dev/null @@ -1,147 +0,0 @@ -------------------------------------------------------------------------- --- Project: JIPS, a portable 32-bit RISC CPU written in VHDL --- This file: loadable ROM --- --- Copyright (C) 2008 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -library UNISIM; -use UNISIM.VComponents.all; - -ENTITY irom IS - Port ( - clk : in STD_LOGIC; - addr : in inst_addr_t; - dout : out inst_t - ); - -END irom; - -ARCHITECTURE loadable OF irom IS - - -- JASM_ROM_INSERT_HERE - - signal jtag_ld_clk : STD_LOGIC; - signal jtag_ld_we : STD_LOGIC; - signal jtag_ld_addr : unsigned (15 downto 0); - signal jtag_ld_dout : unsigned (31 downto 0); - signal jtag_ld_din : unsigned (31 downto 0); - signal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic; - signal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic; - signal user_regi, user_rego : unsigned (47 downto 0); - constant id : unsigned (47 downto 0) := X"DEAD" & X"BEEF" & "X"BABE"; - -begin - --------------------------------------------------------------------------- --- Virtex-4: JTAG Loader --------------------------------------------------------------------------- - i00_BUFG : BUFG - port map - ( - O => bs_clk1, - I => bs_clk0 - ); - - i01_BUFG : BUFG - port map - ( - O => bs_update1, - I => bs_update0 - ); - - BSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 - generic map - ( - JTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4) - ) - port map - ( - CAPTURE => bs_capture, -- CAPTURE output from TAP controller - DRCK => bs_clk0, -- Data register output for USER functions - RESET => bs_rst, -- Reset output from TAP controller - SEL => bs_sel, -- USER active output - SHIFT => bs_shift, -- SHIFT output from TAP controller - TDI => bs_tdi, -- TDI output from TAP controller - UPDATE => bs_update0, -- UPDATE output from TAP controller - TDO => bs_tdo -- Data input for USER function - ); - - jtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length); - jtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0); - jtag_ld_clk <= bs_update1; - jtag_ld_we <= bs_sel; - -sipo: - process (bs_rst, bs_clk1, bs_tdi, bs_shift) - begin - if bs_rst = '1' then - user_regi <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_regi <= bs_tdi & user_regi(user_regi'left downto 1); - end if; - end if; - end process; - -piso: - process (bs_rst, bs_clk1, bs_shift, user_rego) - begin - bs_tdo <= user_rego(0); - if bs_rst = '1' then - user_rego <= (others => '0'); - elsif rising_edge(bs_clk1) then - if bs_shift = '1' then - user_rego <= user_rego(0) & user_rego(user_rego'left downto 1); - else - user_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout; --- user_rego <= id; - end if; - end if; - end process; - -PROM_WRITE: - process(jtag_ld_clk, jtag_ld_we) - begin - if rising_edge(jtag_ld_clk) then - if jtag_ld_we = '1' then - imem_rom(to_integer(jtag_ld_addr)) <= jtag_ld_din; - else - jtag_ld_dout <= imem_rom(to_integer(jtag_ld_addr)); - end if; - end if; - end process; - --------------------------------------------------------------------------- --- ROM Read/Write --------------------------------------------------------------------------- -PROM_READ: - process(clk) - begin - if rising_edge(clk) then - dout <= imem_rom(to_integer(addr)); - end if; - end process; - --------------------------------------------------------------------------- -end loadable; diff --git a/lib/CPUs/MIPS/tools/make b/lib/CPUs/MIPS/tools/make deleted file mode 100644 index cb50a10..0000000 --- a/lib/CPUs/MIPS/tools/make +++ /dev/null @@ -1,51 +0,0 @@ -#!/bin/sh - -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: rom-file generation for cpu_core -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- -# $Header: /tmp/cvsroot/VHDL/lib/CPUs/MIPS/tools/make,v 1.3 2008-08-23 07:37:52 Jens Exp $ -# ---------------------------------------------------------------------- -TARGET=$2 -DSTDIR=$1 - -JASM_HOME=/cygdrive/w/vhdl/lib/CPUs/JCpu/tools - -$JASM_HOME/jasm.rb $TARGET.jsm - -irom_tcl_snippet="$TARGET.irom.tcl.snip" -irom_vhdl_snippet="$TARGET.irom.vhdl.snip" -irom_ld_vhdl_snippet="$TARGET.irom_ld.vhdl.snip" -xrom_tcl_snippet="$TARGET.xrom.tcl.snip" -xrom_vhdl_snippet="$TARGET.xrom.vhdl.snip" -xrom_ld_vhdl_snippet="$TARGET.xrom_ld.vhdl.snip" - -$JASM_HOME/insrom.rb $irom_vhdl_snippet $JASM_HOME/irom.vhd.tpl >$DSTDIR/$TARGET\_irom.vhdl -$JASM_HOME/insrom.rb $irom_ld_vhdl_snippet $JASM_HOME/irom_ld.vhd.tpl >$DSTDIR/$TARGET\_irom_ld.vhdl - -$JASM_HOME/insrom.rb $xrom_vhdl_snippet $JASM_HOME/xrom.vhd.tpl >$DSTDIR/$TARGET\_xrom.vhdl -$JASM_HOME/insrom.rb $xrom_ld_vhdl_snippet $JASM_HOME/xrom_ld.vhd.tpl >$DSTDIR/$TARGET\_xrom_ld.vhdl - -cat $irom_tcl_snippet > $TARGET.tcl.snip.snip -cat $xrom_tcl_snippet >> $TARGET.tcl.snip.snip -$JASM_HOME/insrom.rb $TARGET.tcl.snip.snip $JASM_HOME/rom.tcl.tpl >$TARGET.tcl - -rm -f *.snip diff --git a/lib/CPUs/MIPS/tools/rom.tcl.tpl b/lib/CPUs/MIPS/tools/rom.tcl.tpl deleted file mode 100644 index 9f5c0dc..0000000 --- a/lib/CPUs/MIPS/tools/rom.tcl.tpl +++ /dev/null @@ -1,61 +0,0 @@ -# ---------------------------------------------------------------------- -# Project: JCPU, a portable 8-bit RISC CPU written in VHDL -# This file: The ROM file for upload to target over JTAG -# -# Copyright (C) 2007 J. Ahrensfeld -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see . -# -# For questions and ideas, please contact the author at jens@jayfield.org -# -# --------------------------------------------------------------------- - -# --------------------------------------------------------------------- -# For Chipscope 9.1 -# --------------------------------------------------------------------- -# Source JTAG/TCL frame work -cd $env(CHIPSCOPE)\\bin\\nt -source csejtag.tcl - -namespace import ::chipscope::* - -# Platform USB Cable -set PLATFORM_USB_CABLE_ARGS [list "port=USB2" "frequency=6000000"] -# frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000" - -# Create session -set handle [::chipscope::csejtag_session create 0] - -# Open JTAG and lock -set open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS] -set lock_result [::chipscope::csejtag_target lock $handle 1000] - -set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT] - -# Get Device ID -set devtype "Virtex-4SX" -set devid 2 -set irlength [::chipscope::csejtag_tap get_irlength $handle $devid] -set idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid] - -set CSE_OP $CSEJTAG_SHIFT_READWRITE -set CSE_ES $CSEJTAG_RUN_TEST_IDLE - -# Write Program -# JASM_ROM_INSERT_HERE - -::chipscope::csejtag_target unlock $handle -::chipscope::csejtag_target close $handle -::chipscope::csejtag_session destroy $handle -exit diff --git a/lib/CPUs/MIPS/tools/src/ramgen.c b/lib/CPUs/MIPS/tools/src/ramgen.c deleted file mode 100644 index a266e35..0000000 --- a/lib/CPUs/MIPS/tools/src/ramgen.c +++ /dev/null @@ -1,125 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "ram" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveRAM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER2 Instruction (b1111000011) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 2\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C3\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveRAM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/lib/CPUs/MIPS/tools/src/romgen.c b/lib/CPUs/MIPS/tools/src/romgen.c deleted file mode 100644 index 6d1ec5f..0000000 --- a/lib/CPUs/MIPS/tools/src/romgen.c +++ /dev/null @@ -1,368 +0,0 @@ -#include -#include -#include -#include - -#define ARCH_NAME "data" -#define ENT_NAME "icache" -#define JTAG_ADDR_WIDTH 16 - -// -------------------------------------------------------------- -void basename(char *pSrc, char *pDst) -{ - int i, size; - - size = strlen(pSrc); - - while(pSrc[size] != '.') - size--; - - for (i=0; i < size; i++) - pDst[i] = pSrc[i]; - - pDst[i] = 0; - -} - -int SaveROM(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tconstant word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "begin\n", ARCH_NAME); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - - return 0; -} - -int SaveROM_V4LD(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, filesize, romsize; - - char tpl[] = {"--------------------------------------------------------------------------\n-- Virtex-4: JTAG Loader\n--------------------------------------------------------------------------\n\ti00_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_clk1,\n I => bs_clk0\n\t);\n\t\n\ti01_BUFG : BUFG\n\tport map\n\t(\n\t\tO => bs_update1,\n I => bs_update0\n\t);\n\n\tBSCAN_VIRTEX4_inst1 : BSCAN_VIRTEX4 \n\tgeneric map\n\t(\n\t\tJTAG_CHAIN => 1 -- Value to set BSCAN site of device. Possible values: (1,2,3 or 4)\n\t)\n\tport map \n\t(\n\t\tCAPTURE => bs_capture, -- CAPTURE output from TAP controller\n\t\tDRCK => bs_clk0, -- Data register output for USER functions\n\t\tRESET => bs_rst, -- Reset output from TAP controller\n\t\tSEL => bs_sel, -- USER active output\n\t\tSHIFT => bs_shift, -- SHIFT output from TAP controller\n\t\tTDI => bs_tdi, -- TDI output from TAP controller\n\t\tUPDATE => bs_update0, -- UPDATE output from TAP controller\n\t\tTDO => bs_tdo -- Data input for USER function\n\t);\n\n\tjtag_ld_addr <= user_regi(user_regi'left downto jtag_ld_dout'length);\n\tjtag_ld_din <= user_regi(jtag_ld_dout'length-1 downto 0);\n\tjtag_ld_clk <= bs_update1;\n\tjtag_ld_we <= bs_sel;\n\t\nsipo:\n\tprocess (bs_rst, bs_clk1, bs_tdi, bs_shift)\n\tbegin\n\t\tif bs_rst = '1' then\n\t\t\tuser_regi <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_regi <= bs_tdi & user_regi(user_regi'left downto 1);\n\t\t\tend if;\n\t\tend if;\n\tend process;\t\n\npiso:\n\tprocess (bs_rst, bs_clk1, bs_shift, user_rego)\n\tbegin\n\t\tbs_tdo <= user_rego(0);\n\t\tif bs_rst = '1' then\n\t\t\tuser_rego <= (others => '0');\n\t\telsif rising_edge(bs_clk1) then\n\t\t\tif bs_shift = '1' then\n\t\t\t\tuser_rego <= user_rego(0) & user_rego(user_rego'left downto 1);\n\t\t\telse\n\t\t\t\tuser_rego <= (user_rego'left downto jtag_ld_dout'length => '0') & jtag_ld_dout;\t\n\t\n\t\t\tend if;\n\t\tend if;\n\tend process;\n\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fprintf(pFileOut, "LIBRARY IEEE;\n"); - fprintf(pFileOut, "USE IEEE.STD_LOGIC_1164.ALL;\n"); - fprintf(pFileOut, "USE IEEE.NUMERIC_STD.ALL;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "library UNISIM;\n"); - fprintf(pFileOut, "use UNISIM.VComponents.all;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "ENTITY %s IS\n", ENT_NAME); - fprintf(pFileOut, "\tPort\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\t\tclk\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\tce\t\t: in STD_LOGIC;\n"); - fprintf(pFileOut, "\t\taddr\t\t: in unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\t\tdout\t\t: out unsigned(%d downto 0)\n", nbits_data-1); - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "END %s;\n", ENT_NAME); - fprintf(pFileOut, "\n"); - - - fprintf(pFileOut, "ARCHITECTURE %s OF %s IS\n", ARCH_NAME, ENT_NAME); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsubtype word_t is unsigned(%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\ttype word_array_t is array (0 to %d) of word_t;\n", romsize/4-1); - - fprintf(pFileOut, "\tsignal jtag_ld_clk\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_we\t\t: STD_LOGIC;\n"); - fprintf(pFileOut, "\tsignal jtag_ld_addr\t\t: unsigned (%d downto 0);\n", JTAG_ADDR_WIDTH-1); - fprintf(pFileOut, "\tsignal jtag_ld_dout\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal jtag_ld_din\t\t: unsigned (%d downto 0);\n", nbits_data-1); - fprintf(pFileOut, "\tsignal bs_rst, bs_sel, bs_shift, bs_tdi, bs_tdo : std_logic;\n"); - fprintf(pFileOut, "\tsignal bs_capture, bs_clk0, bs_clk1, bs_update0, bs_update1 : std_logic;\n"); - fprintf(pFileOut, "\tsignal user_regi, user_rego : unsigned (%d downto 0);\n", 31 + JTAG_ADDR_WIDTH); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "\tsignal word_array : word_array_t :=\n"); - fprintf(pFileOut, "\t(\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - word = 0; - for (; i < romsize; i += sizeof(int)) - { - fprintf(pFileOut, "\t\tX\"%8.8X\"", word); - if (i < (romsize-sizeof(int))) - fprintf(pFileOut, ", -- %8.8X\n", i); - else - fprintf(pFileOut, " -- %8.8X\n", i); - } - fprintf(pFileOut, "\t);\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "begin\n", ARCH_NAME); - - fprintf(pFileOut, "\n"); - fprintf(pFileOut, "PROM_READ:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(clk)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(clk) and ce = '1' then\n"); - fprintf(pFileOut, "\t\t\tdout <= word_array(to_integer(addr(%d downto 2)));\n", nbits_addr+1); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "\n"); - fputs(tpl, pFileOut); - - fprintf(pFileOut, "PROM_WRITE:\n", ARCH_NAME); - fprintf(pFileOut, "\tprocess(jtag_ld_clk, jtag_ld_we)\n"); - fprintf(pFileOut, "\tbegin\n"); - fprintf(pFileOut, "\t\tif rising_edge(jtag_ld_clk) then\n"); - fprintf(pFileOut, "\t\t\tif jtag_ld_we = '1' then\n"); - fprintf(pFileOut, "\t\t\t\tword_array(to_integer(jtag_ld_addr(%d downto 0))) <= jtag_ld_din;\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\telse\n"); - fprintf(pFileOut, "\t\t\t\tjtag_ld_dout <= word_array(to_integer(jtag_ld_addr(%d downto 0)));\n", nbits_addr-1); - fprintf(pFileOut, "\t\t\tend if;\n"); - fprintf(pFileOut, "\t\tend if;\n"); - fprintf(pFileOut, "\tend process;\n"); - fprintf(pFileOut, "\n"); - - fprintf(pFileOut, "end %s;\n", ARCH_NAME); - return 0; -} - -int SaveROM_TCL(char *pFilenameIn, char *pFilenameOut, char *pArchName, char *pEntName, int nbits_addr, int nbits_data) -{ - FILE *pFileIn, *pFileOut; - long start, end; - int i, word, word_addr, filesize, romsize; - char binstr_addr[33]; - char binstr_data[33]; - - char tpl[] = {"# ---------------------------------------------------------------------\n# For Chipscope 9.1\n# ---------------------------------------------------------------------\n# Source JTAG/TCL frame work\ncd $env(CHIPSCOPE)\\\\bin\\\\nt\nsource csejtag.tcl\n\nnamespace import ::chipscope::*\n\n# Platform USB Cable\nset PLATFORM_USB_CABLE_ARGS [list \"port=USB2\" \"frequency=6000000\"]\n# frequency=\"24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000\"\n\n# Create session\nset handle [::chipscope::csejtag_session create 0]\n\n# Open JTAG and lock\nset open_result [::chipscope::csejtag_target open $handle $CSEJTAG_TARGET_PLATFORMUSB 0 $PLATFORM_USB_CABLE_ARGS]\nset lock_result [::chipscope::csejtag_target lock $handle 1000]\n\nset devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]\n\n# Get Device ID\nset devtype \"Virtex-4SX\"\nset devid 2\nset irlength [::chipscope::csejtag_tap get_irlength $handle $devid]\nset idcode [::chipscope::csejtag_tap get_device_idcode $handle $devid]\n\nset CSE_OP $CSEJTAG_SHIFT_READWRITE\nset CSE_ES $CSEJTAG_RUN_TEST_IDLE\n\n# Write Program\n"}; - - pFileIn = fopen(pFilenameIn, "rb"); - if (!pFileIn) - { - fprintf(stderr, "Error opening file %s\n", pFilenameIn); - return 1; - } - - pFileOut = fopen(pFilenameOut, "wb"); - if (!pFileOut) - { - fprintf(stderr, "Error opening file %s\n", pFilenameOut); - return 1; - } - - fseek(pFileIn, 0, SEEK_SET); - start = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_END); - end = ftell(pFileIn); - fseek(pFileIn, 0, SEEK_SET); - - filesize = (end-start); - romsize = (int)pow(2, nbits_addr+2); - - // ------------------------------------------------------------------------- - // Header - - // ------------------------------------------------------------------------- - fputs(tpl, pFileOut); - - // ------------------------------------------------------------------------- - // ROM part - // ------------------------------------------------------------------------- - fprintf(pFileOut, "# Assembled from %s\n", pFilenameIn); - fprintf(pFileOut, "# ---------------------------------------------------------------\n"); - fprintf(pFileOut, "# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA\n"); - fprintf(pFileOut, "# User 1\n"); - fprintf(pFileOut, "set result [::chipscope::csejtag_tap shift_device_ir $handle $devid $CSE_OP $CSE_ES 0 $irlength \"3C2\"]\n\n"); - - word_addr = 0; - for (i=0; i < filesize; i += sizeof(int)) - { - fread(&word, 1, sizeof(int), pFileIn); - fprintf(pFileOut, "::chipscope::csejtag_tap shift_device_dr $handle $devid $CSE_OP $CSE_ES 0 %d \"%4.4X%8.8X\"\n", nbits_data + JTAG_ADDR_WIDTH, word_addr, word); - word_addr++; - } - fprintf(pFileOut, "\n"); - - // ------------------------------------------------------------------------- - // Trailer - // ------------------------------------------------------------------------- - fprintf(pFileOut, "::chipscope::csejtag_target unlock $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_target close $handle\n"); - fprintf(pFileOut, "::chipscope::csejtag_session destroy $handle\n"); - fprintf(pFileOut, "exit\n"); - - return 0; -} - -int main(int argc, char *argv[]) -{ - char *pFilenameIn; - char name_prj[1024]; - char name_rom[1024]; - char name_rom_v4ld[1024]; - char name_rom_tcl[1024]; - - FILE *pFileIn; - int filesize, romsize, nbits_addr, nbits_data; - long start, end; - int word, i; - - if (argc < 2) - { - fprintf(stderr, "Usage: romgen \n"); - return 1; - } - - pFilenameIn = argv[1]; - if (argc == 3) - nbits_addr = atoi(argv[2]); - - - basename(pFilenameIn, name_prj); - sprintf(name_rom, "%s.vhd", name_prj); - sprintf(name_rom_v4ld, "%s_ld.vhd", name_prj); - sprintf(name_rom_tcl, "%s.tcl", name_prj); - - SaveROM(pFilenameIn, name_rom, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_V4LD(pFilenameIn, name_rom_v4ld, ARCH_NAME, ENT_NAME, nbits_addr, 32); - SaveROM_TCL(pFilenameIn, name_rom_tcl, ARCH_NAME, ENT_NAME, nbits_addr, 32); - - - return 0; -} - diff --git a/lib/FIFO/sim/tb_async_fifo_ctrl.fdo b/lib/FIFO/sim/tb_async_fifo_ctrl.fdo deleted file mode 100644 index cfa76ee..0000000 --- a/lib/FIFO/sim/tb_async_fifo_ctrl.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/dpram.vhd" -vcom -explicit -93 "../src/async_fifo_ctrl.vhd" -vcom -explicit -93 "../src/tb_async_fifo_ctrl.vhd" -vsim -t 1ps -lib work tb_async_fifo_ctrl -view wave -do {tb_async_fifo_ctrl.wdo} -view structure -view signals - -run 10us diff --git a/lib/FIFO/sim/tb_async_fifo_ctrl.wdo b/lib/FIFO/sim/tb_async_fifo_ctrl.wdo deleted file mode 100644 index 8f23edb..0000000 --- a/lib/FIFO/sim/tb_async_fifo_ctrl.wdo +++ /dev/null @@ -1,36 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_async_fifo_ctrl/rst -add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_w -add wave -noupdate -format Logic /tb_async_fifo_ctrl/we -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_w -add wave -noupdate -format Logic /tb_async_fifo_ctrl/clk_r -add wave -noupdate -format Logic /tb_async_fifo_ctrl/re -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/ptr_r -add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_empty -add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_empty -add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_almost_full -add wave -noupdate -format Logic /tb_async_fifo_ctrl/fifo_full -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/dout -add wave -noupdate -format Logic /tb_async_fifo_ctrl/uut/inst_gray_counter_w/ce -add wave -noupdate -format Literal -radix hexadecimal /tb_async_fifo_ctrl/uut/bnxt_w -add wave -noupdate -format Literal /tb_async_fifo_ctrl/uut/bcnt_r -add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffw -add wave -noupdate -format Literal -radix decimal /tb_async_fifo_ctrl/uut/diffr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {250000 ps} 0} -configure wave -namecolwidth 190 -configure wave -valuecolwidth 80 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {115874 ps} {612358 ps} diff --git a/lib/FIFO/sim/tb_gray_counter.fdo b/lib/FIFO/sim/tb_gray_counter.fdo deleted file mode 100644 index b619f71..0000000 --- a/lib/FIFO/sim/tb_gray_counter.fdo +++ /dev/null @@ -1,13 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/tb_gray_counter.vhd" -vsim -t 1ps -lib work tb_gray_counter -view wave -do {tb_gray_counter.wdo} -view structure -view signals - -run 1us diff --git a/lib/FIFO/sim/tb_gray_counter.wdo b/lib/FIFO/sim/tb_gray_counter.wdo deleted file mode 100644 index b33112f..0000000 --- a/lib/FIFO/sim/tb_gray_counter.wdo +++ /dev/null @@ -1,25 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_gray_counter/rst -add wave -noupdate -format Logic /tb_gray_counter/ce -add wave -noupdate -format Logic /tb_gray_counter/clk -add wave -noupdate -format Literal /tb_gray_counter/bcnt -add wave -noupdate -format Literal /tb_gray_counter/bnxt -add wave -noupdate -format Literal /tb_gray_counter/gcnt -add wave -noupdate -format Literal /tb_gray_counter/gnxt -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {20898 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {134759 ps} diff --git a/lib/FIFO/sim/tb_sync_fifo_ctrl.fdo b/lib/FIFO/sim/tb_sync_fifo_ctrl.fdo deleted file mode 100644 index fff4902..0000000 --- a/lib/FIFO/sim/tb_sync_fifo_ctrl.fdo +++ /dev/null @@ -1,15 +0,0 @@ -## NOTE: Do not edit this file. -## -vlib work -vcom -explicit -93 "../src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../src/gray_counter.vhd" -vcom -explicit -93 "../src/dpram.vhd" -vcom -explicit -93 "../src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../src/tb_sync_fifo_ctrl.vhd" -vsim -t 1ps -lib work tb_sync_fifo_ctrl -view wave -do {tb_sync_fifo_ctrl.wdo} -view structure -view signals - -run 10us diff --git a/lib/FIFO/sim/tb_sync_fifo_ctrl.wdo b/lib/FIFO/sim/tb_sync_fifo_ctrl.wdo deleted file mode 100644 index 8821953..0000000 --- a/lib/FIFO/sim/tb_sync_fifo_ctrl.wdo +++ /dev/null @@ -1,32 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/rst -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/we -add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_w -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/re -add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/ptr_r -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_empty -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_empty -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_almost_full -add wave -noupdate -format Logic /tb_sync_fifo_ctrl/fifo_full -add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/din -add wave -noupdate -format Literal -radix hexadecimal /tb_sync_fifo_ctrl/dout -add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pw_next -add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/pr_next -add wave -noupdate -format Literal -radix unsigned /tb_sync_fifo_ctrl/uut/diff -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {290000 ps} 0} -configure wave -namecolwidth 190 -configure wave -valuecolwidth 80 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {2166667 ps} diff --git a/lib/FIFO/src/async_fifo_ctrl.vhd b/lib/FIFO/src/async_fifo_ctrl.vhd deleted file mode 100644 index 90fe9be..0000000 --- a/lib/FIFO/src/async_fifo_ctrl.vhd +++ /dev/null @@ -1,244 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -entity async_fifo_ctrl is - Generic ( - addr_width : integer := 3; - almost_full_thresh : integer := 6; - almost_empty_thresh : integer := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - ptr_w : out unsigned (addr_width-1 downto 0); - ptr_r : out unsigned (addr_width-1 downto 0); - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC - ); -end async_fifo_ctrl; - -architecture Behavioral of async_fifo_ctrl is - - signal gcnt_w : unsigned (addr_width downto 0); - signal gcnt2_w : unsigned (addr_width downto 0); - signal bcnt2_aw : unsigned (addr_width downto 0); - signal bcnt_w : unsigned (addr_width downto 0); - signal gnxt_w : unsigned (addr_width downto 0); - signal bnxt_w : unsigned (addr_width downto 0); - signal gcnt_r : unsigned (addr_width downto 0); - signal gcnt2_r : unsigned (addr_width downto 0); - signal bcnt2_ar : unsigned (addr_width downto 0); - signal bcnt_r : unsigned (addr_width downto 0); - signal gnxt_r : unsigned (addr_width downto 0); - signal bnxt_r : unsigned (addr_width downto 0); - - signal empty, full : std_logic; - signal write_inhibit, read_inhibit : std_logic; - signal winc, rinc : std_logic; - - -- synthesis translate_off - signal diffw : signed (addr_width downto 0); - signal diffr : signed (addr_width downto 0); - -- synthesis translate_on - -begin - - ptr_w <= bcnt_w(addr_width-1 downto 0); - ptr_r <= bcnt_r(addr_width-1 downto 0); - winc <= we and (not write_inhibit); - rinc <= re and (not read_inhibit); - fifo_full <= write_inhibit; - fifo_empty <= read_inhibit; - -proc_write_inhibit: - process(rst, clk_w) - begin - if rst = '1' then - write_inhibit <= '0'; - elsif rising_edge(clk_w) then - write_inhibit <= full; - end if; - end process; - -proc_read_inhibit: - process(rst, clk_r) - begin - if rst = '1' then - read_inhibit <= '1'; - elsif rising_edge(clk_r) then - read_inhibit <= empty; - end if; - end process; - -proc_sync_grptr: - process(clk_w) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_w) then - gcnt2_r <= p2; - p2 := p1; - p1 := gcnt_r; - end if; - end process; - -proc_ptr_gwptr: - process(clk_r) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_r) then - gcnt2_w <= p2; - p2 := p1; - p1 := gcnt_w; - end if; - end process; - -proc_status_full: - process(gnxt_w, gcnt2_r) - begin - if (gnxt_w = (not gcnt2_r(gcnt2_r'left downto gcnt2_r'left-1) & gcnt2_r(gcnt2_r'left-2 downto 0))) then - full <= '1'; - else - full <= '0'; - end if; - end process; - -proc_status_empty: - process(gnxt_r, gcnt2_w) - begin - if (gnxt_r = gcnt2_w) then - empty <= '1'; - else - empty <= '0'; - end if; - end process; - -proc_sync_arptr: - process(clk_w) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_w) then - bcnt2_ar <= p2; - p2 := p1; - p1 := bcnt_r; - end if; - end process; - -proc_ptr_awptr: - process(clk_r) - variable p1, p2 : unsigned (addr_width downto 0); - begin - if rising_edge(clk_r) then - bcnt2_aw <= p2; - p2 := p1; - p1 := bcnt_w; - end if; - end process; - -proc_status_almost_full: - process(rst, clk_w) - variable diff : unsigned (addr_width downto 0); - begin - -- synthesis translate_off - diffw <= signed(diff); - -- synthesis translate_on - if rst = '1' then - fifo_afull <= '0'; - diff := (others => '0'); - elsif rising_edge(clk_w) then - if diff >= almost_full_thresh-1 then - fifo_afull <= '1'; - else - fifo_afull <= '0'; - end if; - diff := unsigned(abs(signed(bnxt_w) - signed(bcnt2_ar))); - end if; - end process; - -proc_status_almost_empty: - process(rst, clk_r) - variable diff : unsigned (addr_width downto 0); - begin - -- synthesis translate_off - diffr <= signed(diff); - -- synthesis translate_on - if rst = '1' then - fifo_aempty <= '1'; - diff := (others => '0'); - elsif rising_edge(clk_r) then - if diff <= almost_empty_thresh+1 then - fifo_aempty <= '1'; - else - fifo_aempty <= '0'; - end if; - diff := unsigned(abs(signed(bcnt2_aw) - signed(bnxt_r))); - end if; - end process; - -inst_gray_counter_w : entity work.gray_counter - generic map ( - width => addr_width+1, - init_value => 0 - ) - port map ( - rst => rst, - clk => clk_w, - ce => winc, - bcnt => bcnt_w, - bnxt => bnxt_w, - gcnt => gcnt_w, - gnxt => gnxt_w - ); - -inst_gray_counter_r : entity work.gray_counter - generic map ( - width => addr_width+1, - init_value => 0 - ) - port map ( - rst => rst, - clk => clk_r, - ce => rinc, - bcnt => bcnt_r, - bnxt => bnxt_r, - gcnt => gcnt_r, - gnxt => gnxt_r - ); - -end Behavioral; - diff --git a/lib/FIFO/src/dpram.vhd b/lib/FIFO/src/dpram.vhd deleted file mode 100644 index b8f8565..0000000 --- a/lib/FIFO/src/dpram.vhd +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/dpram.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram; - -architecture Behavioral of dpram is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/FIFO/src/fifo_ctrl_pkg.vhd b/lib/FIFO/src/fifo_ctrl_pkg.vhd deleted file mode 100644 index a8c9c61..0000000 --- a/lib/FIFO/src/fifo_ctrl_pkg.vhd +++ /dev/null @@ -1,46 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/fifo_ctrl_pkg.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package fifo_ctrl_pkg is - - -- Constants - -- Types - - -- Functions - function bin2gray(xb : unsigned) return unsigned; - function gray2bin(xg : unsigned) return unsigned; - -end fifo_ctrl_pkg; - -package body fifo_ctrl_pkg is - - function bin2gray(xb : unsigned) return unsigned is - variable xg : unsigned(xb'left downto xb'right); - begin - - xg(xg'left) := xb(xb'left); - for i in 1 to xb'left loop - xg(xg'left-i) := xb(xb'left-i+1) xor xb(xb'left-i); - end loop; - - return xg; - end bin2gray; - - function gray2bin(xg : unsigned) return unsigned is - variable xb : unsigned(xg'left downto xg'right); - begin - - xb(xb'left) := xg(xg'left); - for i in 1 to xg'left loop - xb(xb'left-i) := xb(xb'left-i+1) xor xg(xg'left-i); - end loop; - - return xb; - end gray2bin; - -end fifo_ctrl_pkg; - diff --git a/lib/FIFO/src/gray_counter.vhd b/lib/FIFO/src/gray_counter.vhd deleted file mode 100644 index eb17fd5..0000000 --- a/lib/FIFO/src/gray_counter.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -entity gray_counter is - Generic ( - width : natural := 3; - init_value : natural := 0 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - ce : in STD_LOGIC; - bcnt : out unsigned (width-1 downto 0); - bnxt : out unsigned (width-1 downto 0); - gcnt : out unsigned (width-1 downto 0); - gnxt : out unsigned (width-1 downto 0) - ); -end gray_counter; - -architecture Behavioral of gray_counter is - - signal cntb : unsigned (width-1 downto 0); - signal nxtb : unsigned (width-1 downto 0); - signal cntg : unsigned (width-1 downto 0); - signal nxtg : unsigned (width-1 downto 0); - -begin - - bnxt <= nxtb; - gnxt <= nxtg; - - process(rst, clk, ce, cntb, nxtb) - begin - if rst = '1' then - cntb <= to_unsigned(init_value, width); - nxtb <= to_unsigned(init_value, width); - cntg <= to_unsigned(init_value, width); - nxtg <= to_unsigned(init_value, width); - bcnt <= to_unsigned(init_value, width); - gcnt <= to_unsigned(init_value, width); - else - if rising_edge(clk) then - bcnt <= nxtb; - gcnt <= nxtg; - cntb <= nxtb; - cntg <= nxtg; - end if; - nxtg <= bin2gray(nxtb); - nxtb <= cntb; - if ce = '1' then - nxtb <= cntb + 1; - end if; - end if; - end process; - -end Behavioral; - diff --git a/lib/FIFO/src/sync_fifo_ctrl.vhd b/lib/FIFO/src/sync_fifo_ctrl.vhd deleted file mode 100644 index ef8661f..0000000 --- a/lib/FIFO/src/sync_fifo_ctrl.vhd +++ /dev/null @@ -1,199 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: The call/return/data stack - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity sync_fifo_ctrl is - Generic ( - addr_width : integer := 3; - almost_full_thresh : integer := 6; - almost_empty_thresh : integer := 2 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - ptr_w : out unsigned (addr_width-1 downto 0); - ptr_r : out unsigned (addr_width-1 downto 0); - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC - ); -end sync_fifo_ctrl; - -architecture Behavioral of sync_fifo_ctrl is - - signal pW, pW_cnt, pW_next : unsigned (addr_width-1 downto 0); - signal pR, pR_cnt, pR_next : unsigned (addr_width-1 downto 0); - signal empty, full : std_logic; - signal pre_empty, pre_full : std_logic; - signal was_write : std_logic; - signal write, read : std_logic; - signal diff : unsigned (addr_width downto 0); - -begin - - read <= '1' when re = '1' and empty = '0' else '0'; - write <= '1' when we = '1' and full = '0' else '0'; - - fifo_full <= full; - fifo_empty <= empty; - - -proc_diff_gen: - process(rst, clk) - begin - if rst = '1' then - diff <= (others => '0'); - elsif rising_edge(clk) then - if write = '1' and read = '0' then - diff <= diff + 1; - elsif write = '0' and read = '1' then - diff <= diff - 1; - end if; - end if; - end process; - -proc_status_almost_full: - process(rst, clk) - begin - if rst = '1' then - fifo_afull <= '0'; - elsif rising_edge(clk) then - if diff >= almost_full_thresh-1 then - fifo_afull <= '1'; - else - fifo_afull <= '0'; - end if; - end if; - end process; - -proc_status_almost_empty: - process(rst, clk) - begin - if rst = '1' then - fifo_aempty <= '1'; - elsif rising_edge(clk) then - if diff <= almost_empty_thresh+1 then - fifo_aempty <= '1'; - else - fifo_aempty <= '0'; - end if; - end if; - end process; - -proc_full_reg: - process(rst, clk) - begin - if rst = '1' then - full <= '0'; - elsif rising_edge(clk) then - full <= pre_full; - end if; - end process; - -proc_empty_reg: - process(rst, clk) - begin - if rst = '1' then - empty <= '1'; - elsif rising_edge(clk) then - empty <= pre_empty; - end if; - end process; - -proc_status_w: - process(was_write, pW_next, pR_next, pW, pR, we, re) - begin - if (pW_next = pR) and (we = '1' or was_write = '1') then - pre_full <= '1'; - else - pre_full <= '0'; - end if; - if (pR_next = pW) and (re = '1' or was_write = '0') then - pre_empty <= '1'; - else - pre_empty <= '0'; - end if; - end process; - -proc_flag_write: - process(rst, clk) - begin - if rst = '1' then - was_write <= '0'; - elsif rising_edge(clk) then - if write = '1' then - was_write <= '1'; - elsif read = '1' then - was_write <= '0'; - end if; - end if; - end process; - -proc_ptr_w: - process(rst, clk, pW, we, full) - begin - if rst = '1' then - pW <= to_unsigned(0, addr_width); - pW_next <= to_unsigned(0, addr_width); - elsif rising_edge(clk) then - if we = '1' then - pW <= pW_next; - end if; - end if; - pW_next <= pW; - if we = '1' and full = '0' then - pW_next <= pW + 1; - end if; - ptr_w <= pW; - end process; - -proc_ptr_r: - process(rst, clk, pR_next, pR, re, empty) - begin - if rst = '1' then - pR <= to_unsigned(0, addr_width); - pR_next <= to_unsigned(0, addr_width); - elsif rising_edge(clk) then - if re = '1' then - pR <= pR_next; - end if; - end if; - pR_next <= pR; - if re = '1' and empty = '0' then - pR_next <= pR + 1; - end if; - ptr_r <= pR_next; - end process; - -end Behavioral; - diff --git a/lib/FIFO/src/tb_async_fifo_ctrl.vhd b/lib/FIFO/src/tb_async_fifo_ctrl.vhd deleted file mode 100644 index 2e95862..0000000 --- a/lib/FIFO/src/tb_async_fifo_ctrl.vhd +++ /dev/null @@ -1,176 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_async_fifo_ctrl IS -END tb_async_fifo_ctrl; - -ARCHITECTURE behavior OF tb_async_fifo_ctrl IS - - --Constants - constant PERIOD_W : time := 10 ns; - constant PERIOD_R : time := 20 ns; - constant ADDR_WIDTH : integer := 3; - - --Inputs - signal rst : STD_LOGIC := '1'; - signal clk_w : STD_LOGIC := '0'; - signal clk_r : STD_LOGIC := '0'; - signal we : STD_LOGIC := '0'; - signal re : STD_LOGIC := '0'; - signal din : unsigned (7 downto 0); - --Outputs - - signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0); - signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0); - signal dout : unsigned (7 downto 0); - signal fifo_full : STD_LOGIC; - signal fifo_empty : STD_LOGIC; - signal fifo_almost_full : STD_LOGIC; - signal fifo_almost_empty : STD_LOGIC; - signal mem_we : STD_LOGIC; - - signal write_en : STD_LOGIC := '0'; - signal read_en : STD_LOGIC := '0'; - - signal wdata : unsigned (7 downto 0) := (others => '0'); - signal rdata : unsigned (7 downto 0) := (others => '0'); - signal rdata2 : unsigned (7 downto 0) := (others => '0'); - -BEGIN - - din <= wdata; - - -- Instantiate the Unit Under Test (UUT) - uut: entity work.async_fifo_ctrl - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - almost_full_thresh => 6, - almost_empty_thresh => 2 - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - inst_dpram: entity work.dpram - GENERIC MAP ( - addr_width => ADDR_WIDTH, - data_width => 8 - ) - PORT MAP( - clka => clk_w, - clkb => clk_r, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => din, - dout_b => dout - ); - - tb_clk_w : PROCESS - BEGIN - clk_w <= not clk_w; - wait for PERIOD_W/2; - END PROCESS; - - tb_clk_r : PROCESS - BEGIN - clk_r <= not clk_r; - wait for PERIOD_R/2; - END PROCESS; - - tb_write : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 5*PERIOD_W; - rst <= '0'; - wait for 5*PERIOD_W; - write_en <= '1'; - wait for 15*PERIOD_W; - write_en <= '0'; - - wait; - - END PROCESS; - - tb_read : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 15*PERIOD_R; - read_en <= '1'; - - wait; - - END PROCESS; - - we <= write_en and not fifo_full; - mem_we <= we; - - tb_w : PROCESS(rst, clk_w) - BEGIN - - if rst = '1' then - wdata <= (others => '0'); - elsif rising_edge(clk_w) then - if we = '1' then - wdata <= wdata + 1; - end if; - end if; - - END PROCESS; - - re <= read_en and not fifo_empty; - - tb_r : PROCESS(rst, clk_r) - BEGIN - - if rst = '1' then - rdata <= (others => '0'); - elsif rising_edge(clk_r) then - rdata2 <= rdata; - if re = '1' then - assert rdata2 = dout report "FIFO read error!" severity failure; - rdata <= rdata + 1; - end if; - end if; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_gray_counter.vhd b/lib/FIFO/src/tb_gray_counter.vhd deleted file mode 100644 index 00380d7..0000000 --- a/lib/FIFO/src/tb_gray_counter.vhd +++ /dev/null @@ -1,83 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_gray_counter --- Module Name: tb_gray_counter.vhd --- Project Name: gray_counter package --- Target Device: --- Tool versions: --- Description: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_gray_counter.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - -LIBRARY WORK; -USE WORK.FIFO_CTRL_PKG.ALL; - -ENTITY tb_gray_counter IS -END tb_gray_counter; - -ARCHITECTURE behavior OF tb_gray_counter IS - - constant PERIOD : time := 10 ns; - constant WIDTH : integer := 3; - - --Signals - signal gcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal bcnt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal gnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal bnxt : unsigned (WIDTH-1 downto 0) := to_unsigned(0, WIDTH); - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal ce : STD_LOGIC := '0'; - -BEGIN - -inst_gray_counter : entity work.gray_counter - generic map (width => WIDTH) - port map ( - rst => rst, - clk => clk, - ce => ce, - bcnt => bcnt, - bnxt => bnxt, - gcnt => gcnt, - gnxt => gnxt - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb_counter : PROCESS - - BEGIN - - wait for 4*PERIOD; - rst <= '0'; - wait for 1*PERIOD; - ce <= '1'; - wait for 3*PERIOD; - ce <= '0'; - wait for 4*PERIOD; - ce <= '1'; - wait for 1*PERIOD; - ce <= '0'; - wait for 1*PERIOD; - ce <= '1'; - - wait; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/FIFO/src/tb_sync_fifo_ctrl.vhd b/lib/FIFO/src/tb_sync_fifo_ctrl.vhd deleted file mode 100644 index 4eb81e3..0000000 --- a/lib/FIFO/src/tb_sync_fifo_ctrl.vhd +++ /dev/null @@ -1,221 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_sync_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_sync_fifo_ctrl IS -END tb_sync_fifo_ctrl; - -ARCHITECTURE behavior OF tb_sync_fifo_ctrl IS - - --Constants - constant PERIOD : time := 10 ns; - constant ADDR_WIDTH : integer := 3; - - --Inputs - signal rst : STD_LOGIC := '1'; - signal clk : STD_LOGIC := '0'; - signal we : STD_LOGIC := '0'; - signal re : STD_LOGIC := '0'; - signal din : unsigned (7 downto 0); - --Outputs - - signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0); - signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0); - signal dout : unsigned (7 downto 0); - signal fifo_full : STD_LOGIC; - signal fifo_empty : STD_LOGIC; - signal fifo_almost_full : STD_LOGIC; - signal fifo_almost_empty : STD_LOGIC; - signal mem_we : STD_LOGIC; - - signal write_en : STD_LOGIC := '0'; - signal read_en : STD_LOGIC := '0'; - - signal wdata : unsigned (7 downto 0) := (others => '0'); - signal rdata : unsigned (7 downto 0) := (others => '0'); - signal rdata2 : unsigned (7 downto 0) := (others => '0'); - -BEGIN - - din <= wdata; - - -- Instantiate the Unit Under Test (UUT) - uut: entity work.sync_fifo_ctrl - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - almost_full_thresh => 6, - almost_empty_thresh => 2 - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - inst_dpram: entity work.dpram - GENERIC MAP ( - addr_width => ADDR_WIDTH, - data_width => 8 - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => din, - dout_b => dout - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb_write : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 5*PERIOD; - rst <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - wait for 7*PERIOD; - write_en <= '1'; - wait for 1*PERIOD; - write_en <= '0'; - wait for 1*PERIOD; - write_en <= '1'; - wait for 1*PERIOD; - write_en <= '0'; - wait for 3*PERIOD; - write_en <= '1'; - wait for 4*PERIOD; - write_en <= '0'; - wait for 17*PERIOD; - write_en <= '1'; - wait for 25*PERIOD; - write_en <= '0'; - - wait; - - END PROCESS; - - tb_read : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 25*PERIOD; - read_en <= '1'; - wait for 25*PERIOD; - read_en <= '0'; - wait for 25*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 5*PERIOD; - read_en <= '1'; - wait for 1*PERIOD; - read_en <= '0'; - wait for 7*PERIOD; - read_en <= '1'; - wait for 15*PERIOD; - read_en <= '0'; - - wait; - - END PROCESS; - - we <= write_en and not fifo_full; - mem_we <= we; - - tb_w : PROCESS(rst, clk) - BEGIN - - if rst = '1' then - wdata <= (others => '0'); - elsif rising_edge(clk) then - if we = '1' then - wdata <= wdata + 1; - end if; - end if; - - END PROCESS; - - re <= read_en and not fifo_empty; - - tb_r : PROCESS(rst, clk) - BEGIN - - if rst = '1' then - rdata <= (others => '0'); - elsif rising_edge(clk) then - rdata2 <= rdata; - if re = '1' then - assert rdata = dout report "FIFO read error!" severity failure; - rdata <= rdata + 1; - end if; - end if; - - END PROCESS; - -END behavior; \ No newline at end of file diff --git a/lib/PCK_FIO-1.16/PCK_FIO.html b/lib/PCK_FIO-1.16/PCK_FIO.html deleted file mode 100644 index 8b8c8c5..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.html +++ /dev/null @@ -1,297 +0,0 @@ - - - - - - VHDL package for formatted file output - - - - -
-

-Name

-PCK_FIO - VHDL package for  formatted file output -

-


-

-Contents

-Usage -
The file output function 'fo' -
Format specifiers -
Special characters -
Things to watch out for -
Methodology notes -
Parametrization -
Test bench -
Known limitations and problems -
Author -

-


-

-Usage

-PCK_FIO is a VHDL package that defines  fprint, a function -for formatted file output. -

After installing the package you can call fprint as follows: -

  fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable. -

The argument Format is the format string, which consists of ``normal'' -substrings which are copied verbatim, and format specifiers, starting with -'%'. -A typical format string looks as follows: -

   "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write -to the file, embedded in fo function calls. There can be 0 to -32 of such arguments. The expressions can be of any type for which an fo -function exists. String expressions can also be called directly. -

-


-

-The file output function 'fo'

-The fo (file output) functions do the trick. They -return a tagged string representation that is meaningful to format specifiers. -Here are some examples: -
  fo (signed'("1100"))   returns "S:1100" 
-  fo (unsigned'("1100")) returns "U:1100" 
-  fo (TRUE)              returns "L:T"
-  fo (127)               returns "I:127"
-The internal behavior of fo is irrelevant to the typical user. -

The fo function is currently overloaded as follows: -

  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
- -
-
- -

-Format specifiers

-The general format of a format specifier is: -
   %[-][n]c
-The optional - sign specifies left justified output; default is -right justified. -

The optional number n specifies a field-width. If it is not specified, -fprint -does something reasonable. -

c is the conversion specifier. Currently the following conversion -specifiers are supported: -

-
-r
- -
-reasonable output format (inspired by Synopsys VSS)
- -
Prints the ``most reasonable'' representation e.g. hex for -unsigned, signed and other bit-like vectors (not preferred for integers)
- -
-b
- -
-bit-oriented output
- -
-d
- -
-decimal output
- -
-s
- -
-string output (e.g. in combination with 'IMAGE for enum types)
- -
-q
- -
-``qualified'' string output (shows internal representation from fo)
- -
-{}
- -
-Iteration operator, used as follows:
- -
-%n{<format-string>}
- -
In this case, n is the iteration count and is mandatory. Iteration -can be nested.
- -
-

-Special characters

-To print a double-quote,  use '""' in the format string (VHDL -convention). To print the special characters, '\', and '%', -escape them with '\'. To prevent '{' and '}' -from being interpreted as opening and closing brackets in iteration strings, -escape them with '\'. -

A newline is specified in the format string by '\n'. -

-


-

-Things to notice

-The fprint function expands into VHDL write and writeline -commands. As in plain VHDL, nothing will be written to the output file -until a writeline is given. Therefore, don't forget to include -'\n' -commands in the format string, or it ``will not work''. -

The preferred format specifier for integers is, naturally, %d. -This calls the VHDL write for integers. If you specify a field -width that is too small, the field will automatically be expanded. If you -use %r for integers, the field is not expanded automatically, which -means that some digits are simply thrown away. This may sometimes be useful -but it is also dangerous. Look at the test bench output for differences -between %d and %r output. -

When using the %d format specifier, the VHDL constraints for -the allowed integer range apply. -

In VHDL, signed/unsigned types have been standardized only relatively -recently, in the package IEEE.numeric_std. The lack of a standard -has caused (and is causing) portability issues. The most popular non-standard -package that defines signed/unsigned is IEEE.std_logic_arith from -Synopsys. PCK_FIO has been developed with this latter package, and still -refers to this package by default. However, PCK_FIO  works with -IEEE.numeric_std -as well. To use IEEE.numeric_std, replace the reference to IEEE.std_logic_arith -in the source code.  This needs to be done consistently in a design -database (e.g. in the PCK_FIO test bench as well). -

-


-

-Methodology notes

-The obvious application for fprint is in test benches, to produce -output files that trace the simulation behavior. -

Another interesting application for fprint is to produce info, -warning and error messages in your models. As it can take arguments, fprint -is much better suited for this task than VHDL's assert or report -statements. Actually fprint produces its own (few) warning messages. -

An advanced usage is the generation of test vectors in a specific format. -Instead of using the fo functions, you can write your own set -of functions that return the symbols of a specific test format in a way -that is understandable to the fprint format specifiers. As an -example, when a high output value should be represented using the symbol -'H' it suffices to write a conversion function that returns "B:H" and call -it in combination with the %b format specifier. -

-


-

-Parametrization

-Prefix and postfix strings for bit-oriented and hex-oriented output are -parameterizable in the packages to accommodate different output styles. -The settings in the distribution are such that hex output is indicated -by the prefix '0x', while  bit output prefix and postfix are empty -strings. -

You can adapt the output style by modifying the following constants -in the package header: -

   -- prefix string for hex output -
  -- VHDL style:    "X""" -
  -- Verilog style: "h'" -
  -- C style:       "0x" -
  constant FIO_h_PRE:  string := "0x"; -

  -- postfix string for hex output -
  -- VHDL style:    """" -
  constant FIO_h_POST: string := ""; -

  -- prefix string for bit vector output -
  -- VHDL style:    "B""" -
  -- Verilog style: "b'" -
  constant FIO_bv_PRE:  string := ""; -

  -- postfix string for bit vector output -
  -- VHDL style:    """" -
  constant FIO_bv_POST: string := ""; -

  -- prefix string for bit output -
  -- VHDL style:    "'" -
  -- Verilog style: "b'" -
  constant FIO_b_PRE:  string := ""; -

  -- postfix string for bit output -
  -- VHDL style:    "'" -
  constant FIO_b_POST: string := ""; -

-


-

-Test bench

-Included in the distribution is a file TB_PCK_FIO.vhd with a test -bench for the PCK_FIO package. The file PCK_FIO.out.gold contains -the expected output. If you run the test bench it should produce the file -PCK_FIO.out -that should be identical to PCK_FIO.out.gold. The source files -should be analyzed in a VHDL library EASICS_PACKAGES. -

A good way to understand fprint is to inspect the test bench -and what it produces. -

-


-

-Known limitations and problems

-This VHDL package is an implementation of a flexible concept. It is likely -to be extended and modified in the future. Backward compatibility is not -guaranteed. Therefore, it is not recommended to give this package the status -of a company-wide standard package (or even worse, a VHDL standard package). -Rather, it should be linked with a particular project (and it can be regarded -as a standard package within that project). -

PCK_FIO is written in standard VHDL Std1076-1987. Nevertheless, some -simulators/versions have problems with the package. The following is an -overview of currently known issues: -
  -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SimulatorPCK_FIO handling
Synopsys VSS 3.5 and earlierIncorrect (all zero) output in compiled mode
Synopsys VSS 97.01OK
Mentor quickhdlOK
Modeltech modelsimOK
Cadence LeapfrogShould work with 4.4.1 -
Mysterious problems have been reported - please run the test bench -and report problems
PCK_FIO and various simulators/versions
- -

Although the package name suggests file IO, it only does file output. -

-


-

-Author

-Jan Decaluwe -

-


- - diff --git a/lib/PCK_FIO-1.16/PCK_FIO.out.gold b/lib/PCK_FIO-1.16/PCK_FIO.out.gold deleted file mode 100644 index dcd183e..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.out.gold +++ /dev/null @@ -1,206 +0,0 @@ -PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO ------------------------------------------ - -This is the result of running the PCK_FIO testbench. -This file should be compared with PCK_FIO.out.gold, which is -the reference output. Any difference indicates a portability -issue or a simulator non-compliance or bug. - - --------------------- --- Basic features -- --------------------- - --- First some auxiliary declarations -> file RESULT: text is out "PCK_FIO.out"; -> variable L: line; -> variable BoolTrue: boolean := TRUE; -> variable BoolFalse: boolean := FALSE; -> variable IntPos: integer := 5678; -> variable BigIntPos: integer := 12345678; -> variable IntNeg: integer := -8765; -> variable BigIntNeg: integer := -87654321; -> variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); -> variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); -> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); -> variable SigPos: signed(6 downto 0) := signed'("0010010"); -> variable SigNeg: signed(6 downto 0) := signed'("1010010"); -> variable BitX: std_logic := 'X'; -> variable Bit1: std_logic := '1'; -> variable Bit0: std_logic := '0'; - - --- fprint call with no arguments -> fprint(RESULT, L, "No arguments.\n);" -No arguments. - --- Special characters need to be escaped -> fprint(RESULT, L, "Special characters: \% \\ " \n"); -Special characters: % \ " - --- Various format specifiers interprete the same object differently -> fprint(RESULT, L, "Format specifiers: %r %d %b %q\n);" -> fo(Uns), fo(Uns), fo(Uns), fo(Uns) -> ); -Format specifiers: 0x52 82 1010010 U:1010010 - --- Format string can be shortened by using the iteration specifier -> fprint(RESULT, L, "Iteration specifier: %4{%r }\n);" -> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) -> ); -Iteration specifier: 0x52 0x12 0x52 0x12 - ------------------------------------- --- Support for bit-oriented types -- ------------------------------------- - --- Reasonable format -> fprint(RESULT, L, "Reasonable format: %9{%r }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Reasonable format: 0x12 0x52 0x12 0x52 0x?? 1 X T F - --- Decimal format -> fprint(RESULT, L, "Decimal format: %7{%d }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Decimal format: 18 82 18 -46 -1 1 -1 1 0 - --- Bit format -> fprint(RESULT, L, "Bit format: %7{%b }\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), -> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) -> ); -Bit format: 0010010 1010010 0010010 1010010 1X10Z10 1 X 1 0 - - --- Alignment --- Template of the call: ( stands for the format specifier) - -> fprint(RESULT, L, "Bitvectors with : %4{|}\n", -> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg) -> ); - --- Results of the call with various format specifiers - -Bitvectors with %1r: 0x52|0x12|0x12|0x52| -Bitvectors with %2r: 0x52|0x12|0x12|0x52| -Bitvectors with %3r: 0x52|0x12|0x12|0x52| -Bitvectors with %4r: 0x52|0x12|0x12|0x52| -Bitvectors with %5r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %6r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %7r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %8r: 0x52| 0x12| 0x12| 0x52| -Bitvectors with %9r: 0x52| 0x12| 0x12| 0x52| - -Bitvectors with %-1r: 0x52|0x12|0x12|0x52| -Bitvectors with %-2r: 0x52|0x12|0x12|0x52| -Bitvectors with %-3r: 0x52|0x12|0x12|0x52| -Bitvectors with %-4r: 0x52|0x12|0x12|0x52| -Bitvectors with %-5r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-6r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-7r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-8r: 0x52 |0x12 |0x12 |0x52 | -Bitvectors with %-9r: 0x52 |0x12 |0x12 |0x52 | - -Bitvectors with %1d: 82|18|18|-46| -Bitvectors with %2d: 82|18|18|-46| -Bitvectors with %3d: 82| 18| 18|-46| -Bitvectors with %4d: 82| 18| 18| -46| -Bitvectors with %5d: 82| 18| 18| -46| -Bitvectors with %6d: 82| 18| 18| -46| -Bitvectors with %7d: 82| 18| 18| -46| -Bitvectors with %8d: 82| 18| 18| -46| -Bitvectors with %9d: 82| 18| 18| -46| - -Bitvectors with %-1d: 82|18|18|-46| -Bitvectors with %-2d: 82|18|18|-46| -Bitvectors with %-3d: 82 |18 |18 |-46| -Bitvectors with %-4d: 82 |18 |18 |-46 | -Bitvectors with %-5d: 82 |18 |18 |-46 | -Bitvectors with %-6d: 82 |18 |18 |-46 | -Bitvectors with %-7d: 82 |18 |18 |-46 | -Bitvectors with %-8d: 82 |18 |18 |-46 | -Bitvectors with %-9d: 82 |18 |18 |-46 | - - -------------------------------- --- Support for integer types -- -------------------------------- - - --- Template of the call: ( stands for the format specifier) - -> fprint(RESULT, L, "Integers with : %4{|}\n", -> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) -> ); - --- Results of the call with various format specifiers - -Integers with %5d: 5678|-8765|12345678|-87654321| -Integers with %6d: 5678| -8765|12345678|-87654321| -Integers with %7d: 5678| -8765|12345678|-87654321| -Integers with %8d: 5678| -8765|12345678|-87654321| -Integers with %9d: 5678| -8765| 12345678|-87654321| -Integers with %10d: 5678| -8765| 12345678| -87654321| - -Integers with %-5d: 5678 |-8765|12345678|-87654321| -Integers with %-6d: 5678 |-8765 |12345678|-87654321| -Integers with %-7d: 5678 |-8765 |12345678|-87654321| -Integers with %-8d: 5678 |-8765 |12345678|-87654321| -Integers with %-9d: 5678 |-8765 |12345678 |-87654321| -Integers with %-10d: 5678 |-8765 |12345678 |-87654321 | - -Integers with %5r: 5678|-8765| 5678|-4321| -Integers with %6r: 5678|- 8765| 45678|-54321| -Integers with %7r: 5678|- 8765| 345678|-654321| -Integers with %8r: 5678|- 8765| 2345678|-7654321| -Integers with %9r: 5678|- 8765| 12345678|-87654321| -Integers with %10r: 5678|- 8765| 12345678|- 87654321| - -Integers with %-5r: 5678|-8765| 1234|-8765| -Integers with %-6r: 5678 |-8765 | 12345|-87654| -Integers with %-7r: 5678 |-8765 | 123456|-876543| -Integers with %-8r: 5678 |-8765 | 1234567|-8765432| -Integers with %-9r: 5678 |-8765 | 12345678|-87654321| -Integers with %-10r: 5678 |-8765 | 12345678 |-87654321 | - - ----------------------- --- Support for time -- ----------------------- --- For portability reasons, time is converted --- into an integer value (of nanoseconds) -> wait for 648 ns -> fprint (RESULT, L, "The time is now %d ns\n", fo(now)); -The time is now 648 ns - ----------------------------------------- --- Erroneous calls and error messages -- ----------------------------------------- - --- Less arguments than formats specifiers -> fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); -82 18 -** Warning: FIO_PrintLastValue: Format specifier beyond last argument -** in format string: "%d %d %d %d \n" -** ------^ - --- Unsupported format specifier -> fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); -0x52 -** Warning: FIO_PrintArg: Unexpected format specifier 'v' -** in format string: "%r %v %r %r\n" -** ----^ -** Assuming 'q' to proceed: V:0010010 0x52 0x12 - - ----------------------------------------- --- Things you wouldn't expect to work -- ----------------------------------------- - --- Nested iteration -> fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); -<<_END__END__END_>><<_END__END__END_>><<_END__END__END_>> diff --git a/lib/PCK_FIO-1.16/PCK_FIO.vhd b/lib/PCK_FIO-1.16/PCK_FIO.vhd deleted file mode 100644 index e5e6a8e..0000000 --- a/lib/PCK_FIO-1.16/PCK_FIO.vhd +++ /dev/null @@ -1,916 +0,0 @@ ----- File: PCK_FIO.vhd ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- ----- ----- Revision history: ----- ----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/PCK_FIO.vhd,v $ ----- $Revision: 1.1 $ ----- $Log: not supported by cvs2svn $ ----- Revision 1.16 1999/04/21 08:28:46 jand ----- Tested with IEEE.numeric_std ----- Small patch for Leapfrog ----- ----- Revision 1.14 1997/07/14 10:16:04 jand ----- prefix/postfix for bits/bitvectors set to empty strings by default ----- ----- Revision 1.13 1997/07/11 17:42:57 jand ----- Corrected Easics address ----- ----- Revision 1.12 1997/07/11 17:38:49 jand ----- Improved prefix/postfix support ----- ----- Revision 1.11 1995/11/15 13:46:02 jand ----- Catched integer'low value in fo for integers ----- ----- Revision 1.10 1995/08/11 16:42:26 jand ----- Reimplemented FIO_FormatExpand as a procedure in an attempt to ----- avoid memory leakage problems in VSS ----- ----- Revision 1.9 1995/08/09 13:47:51 jand ----- Removed array of line trick in fprint for less memory, less ----- CPU time, and more conservatism in general ----- Rearranged FIO_PrintValue call so that fprint remains concise ----- ----- Revision 1.8 1995/08/09 10:32:27 jand ----- Removed fprint_flat to have a single call level ----- Added explicit deallocators of line variables (has strong influence ----- on memory usage in VSS - and possibly CPU time) ----- Redefined 'fo' for type time to make it more portable ----- ----- Revision 1.7 1995/08/07 08:56:04 jand ----- Improved conciseness of fprint argument handling through array of line type ----- ----- Revision 1.6 1995/08/04 18:19:13 jand ----- Increase # arguments from 16 to 32 ----- Corrected bug within fprint 's call to Arg16 ----- Added support for bit format specifier 'b' ----- ----- Revision 1.5 1995/08/02 10:22:37 jand ----- Release 1.1 under GNU ----- ----- Revision 1.4 1995/08/01 11:15:52 jand ----- Added escaping during iteration string read ----- ----- Revision 1.3 1995/08/01 08:23:47 jand ----- Many improvements in robustness, conciseness and coding style ----- ----- Revision 1.2 1995/07/30 16:15:43 jand ----- Improved robustness for release to the world ----- ----- Revision 1.1 1995/07/30 14:21:30 jand ----- Initial revision ----- - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std -use IEEE.std_logic_arith.all; -- the Synopsys one --- use IEEE.numeric_std.all; - -package PCK_FIO is - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - - -package body PCK_FIO is - - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (F: out text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (F: out text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - function fo (Arg: string) return string is - begin - return Arg; - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; diff --git a/lib/PCK_FIO-1.16/README b/lib/PCK_FIO-1.16/README deleted file mode 100644 index 4af4c99..0000000 --- a/lib/PCK_FIO-1.16/README +++ /dev/null @@ -1,72 +0,0 @@ -# $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $ -# $Log: not supported by cvs2svn $ -# Revision 1.3 1999/04/21 08:08:35 jand -# Tested with IEEE.numeric_std -# Small patch for Leapfrog -# -# - - PCK_FIO, Version 1.16 - Copyright (C) 1995, 1999 Easics NV - ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -Contents --------- - -This distribution contains the following files: - - PCK_FIO.vhd: VHDL source of the PCK_FIO package - TB_PCK_FIO.vhd: VHDL source of the testbench for package PCK_FIO - PCK_FIO.out.gold: Certified test bench output - PCK_FIO.html: Manual for PCK_FIO in html format - README: This file - - -Installation ------------- - -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO.vhd into the same library. - -If you want to use IEEE.numeric_std instead of IEEE.std_logic_arith, you need -to edit the source code of the package and the test bench and replace the -package use clause. PCK_FIO works with either of these packages. - -To install the documentation, point your web browser to the file PCK_FIO.html -and bookmark it. - - -Installation check ------------------- - -After installing the test bench, you should run it. The corresponding VHDL -design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB). - -Simulating the test bench should create a file called PCK_FIO.out. This file -should be identical to PCK_FIO.out.gold. Any difference indicates a portability -issue or a simulator non-compliance or bug. diff --git a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd b/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd deleted file mode 100644 index c64d045..0000000 --- a/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd +++ /dev/null @@ -1,504 +0,0 @@ ----- File: TB_PCK_FIO.vhd ----- ----- TBC_PCK_FIO: a test bench for the PCK_FIO package. ----- Copyright (C) 1995, 1999 Easics NV ----- ----- This program is free software; you can redistribute it and/or modify ----- it under the terms of the GNU General Public License as published by ----- the Free Software Foundation; either version 1, or (at your option) ----- any later version. ----- ----- This program is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ----- GNU General Public License for more details. ----- ----- You should have received a copy of the GNU General Public License ----- along with this program; if not, write to the Free Software ----- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 396 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- ----- ----- $Source: /tmp/cvsroot/VHDL/lib/PCK_FIO-1.16/TB_PCK_FIO.vhd,v $ ----- $Revision: 1.1 $ ----- $Log: not supported by cvs2svn $ ----- Revision 1.7 1999/04/21 08:23:53 jand ----- Tested with IEEE.numeric_std ----- Small patch for Leapfrog ----- ----- Revision 1.3 1998/09/29 10:09:44 vhdl ----- to EASICS_PACKAGES ----- ----- Revision 1.2 1998/09/29 09:17:51 vhdl ----- library EASICS_PACKAGES; ----- ----- Revision 1.1 1998/09/29 09:15:44 vhdl ----- Initial revision ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std -use IEEE.std_logic_arith.all; -- the Synopsys one --- use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text is out "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n);""\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n);""\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n);""\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); - - -fprint(RESULT, L, - "\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; diff --git a/lib/PCK_FIO-2002.7/CHANGES b/lib/PCK_FIO-2002.7/CHANGES deleted file mode 100644 index b755a56..0000000 --- a/lib/PCK_FIO-2002.7/CHANGES +++ /dev/null @@ -1,86 +0,0 @@ ----- $Id: CHANGES,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -Changes from version 1.16 to version 2002.07 -============================================ - -PCK_FIO is now distributed under the GNU Lesser General Public Licencse -instead of the ordinary GPL, to better reflect intended usage. - -Cosmetic changes in source code to correct some typos in the testbench output. -A new testbench is also supplied. - -The package now uses IEEE.numeric_std as default. - -URL http://www.easics.com has been made part of address. - -Changed syntax in the PCK_FIO package and its testbench to support VHDL-1993. -Because of backwards-incompatibility, it has been necessary to supply -different sets of files for 1987 and 1993. - -Split the packages into a separate file for the header and a -separate file for the body (in compliance with Easics' guidelines). - -These changes resulted in the files: - -Files for VHDL-1993: --------------------- - PCK_FIO_1993.vhd : the source code of the header file for the package - PCK_FIO_1993_BODY.vhd: the source code of the body of the package - TB_PCK_FIO_1993.vhd: the testbench for the package - -Files for VHDL-1987: --------------------- - PCK_FIO_1987.vhd: the source code of the header file for the package - PCK_FIO_1987_BODY.vhd: the source code of the body of the package - TB_PCK_FIO_1987.vhd: the testbench for the package - -Updated README and PCK_FIO.html to support these changes. - -Adapted package files to support NUL termination of strings. -fo(Arg: string) now prints the string until the first NUL. -Several examples of its use are demonstrated in the supplied testbenches. - -Made cosmetic changes to code to improve readability. - -Acknowledgment --------------- -These changes have been implemented by Peter Geens. - - - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.html b/lib/PCK_FIO-2002.7/PCK_FIO.html deleted file mode 100644 index 6b5fc72..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO.html +++ /dev/null @@ -1,339 +0,0 @@ - - - - - - VHDL package for formatted file output - - - - -
-

-Name

-PCK_FIO - VHDL package for  formatted file output -

-


-

-Contents

-Usage -
The file output function 'fo' -
Format specifiers -
Special characters -
Things to watch out for -
Methodology notes -
Parametrization -
Test bench -
Known limitations and problems -
Author -

-


-

-Usage

-PCK_FIO is a VHDL package that defines  fprint, a function -for formatted file output. -

After installing the package you can call fprint as follows: -

  fprint(F, L, Format, fo(Expr_1), fo(Expr_2), ... fo(Expr_n));
-where F is the filehandle and L is the line variable. -

The argument Format is the format string, which consists of ``normal'' -substrings which are copied verbatim, and format specifiers, starting with -'%'. -A typical format string looks as follows: -

   "Arg1 = %6r, Arg2 = %10d, Arg3 = %-5r\n"
-The remaining arguments are the expressions whose results you want to write -to the file, embedded in fo function calls. There can be 0 to -32 of such arguments. The expressions can be of any type for which an fo -function exists. String expressions can also be called directly. -

-


-

-The file output function 'fo'

-The fo (file output) functions do the trick. They -return a tagged string representation that is meaningful to format specifiers. -Here are some examples: -
  fo (signed'("1100"))   returns "S:1100" 
-  fo (unsigned'("1100")) returns "U:1100" 
-  fo (TRUE)              returns "L:T"
-  fo (127)               returns "I:127"
-The internal behavior of fo is irrelevant to the typical user. -
  -
The fo function is currently overloaded as follows:
- -
  function fo (Arg: unsigned)          return string;
-  function fo (Arg: signed)            return string;
-  function fo (Arg: std_logic_vector)  return string;
-  function fo (Arg: std_ulogic_vector) return string;
-  function fo (Arg: bit_vector)        return string;
-  function fo (Arg: integer)           return string;
-  function fo (Arg: std_ulogic)        return string;
-  function fo (Arg: bit)               return string;
-  function fo (Arg: boolean)           return string; 
-  function fo (Arg: character)         return string;
-  function fo (Arg: string)            return string;
-  function fo (Arg: time)              return string;
- -


To support null-terminated strings, the function fo(Arg: -string) processes Arg up to the first NUL character, -if any. If you want the whole string to be outputted you can just enter -the string as a direct argument in fprint.  See also the -examples in the testbench. -

-
- -

-Format specifiers

-The general format of a format specifier is: -
   %[-][n]c
-The optional - sign specifies left justified output; default is -right justified. -

The optional number n specifies a field-width. If it is not specified, -fprint -does something reasonable. -

c is the conversion specifier. Currently the following conversion -specifiers are supported: -

-
-r
- -
-reasonable output format (inspired by Synopsys VSS)
- -
Prints the ``most reasonable'' representation e.g. hex for -unsigned, signed and other bit-like vectors (not preferred for integers)
- -
-b
- -
-bit-oriented output
- -
-d
- -
-decimal output
- -
-s
- -
-string output (e.g. in combination with 'IMAGE for enum types)
- -
-q
- -
-``qualified'' string output (shows internal representation from fo)
- -
-{}
- -
-Iteration operator, used as follows:
- -
-%n{<format-string>}
- -
In this case, n is the iteration count and is mandatory. Iteration -can be nested.
- -
-

-Special characters

-To print a double quote,  use '""' in the format string (VHDL -convention). To print the special characters, '\', and '%', -escape them with '\'. To prevent '{' and '}' -from being interpreted as opening and closing brackets in iteration strings, -escape them with '\'. -

A newline is specified in the format string by '\n'. -

-


-

-Things to notice

-The fprint function expands into VHDL write and writeline -commands. As in plain VHDL, nothing will be written to the output file -until a writeline is given. Therefore, don't forget to include -'\n' -commands in the format string, or it ``will not work''. -

The preferred format specifier for integers is, naturally, %d. -This calls the VHDL write for integers. If you specify a field -width that is too small, the field will automatically be expanded. If you -use %r for integers, the field is not expanded automatically, which -means that some digits are simply thrown away. This may sometimes be useful -but it is also dangerous. Look at the test bench output for differences -between %d and %r output. -

When using the %d format specifier, the VHDL constraints for -the allowed integer range apply. -

In VHDL, signed/unsigned types have been standardized only relatively -recently, in the package IEEE.numeric_std. The lack of a standard -has caused (and is causing) portability issues. The most popular non-standard -package that defines signed/unsigned is IEEE.std_logic_arith from -Synopsys. PCK_FIO works with both packages,  but refers to the standard -package IEEE.numeric_std by default. To use IEEE.std_logic_arith -instead, replace the reference to IEEE.numeric_std in the source -code.  This needs to be done consistently in a design database (e.g. -in the PCK_FIO test bench as well). -

-


-

-Methodology notes

-The obvious application for fprint is in test benches, to produce -output files that trace the simulation behavior. -

Another interesting application for fprint is to produce info, -warning and error messages in your models. As it can take arguments, fprint -is much better suited for this task than VHDL's assert or report -statements. Actually fprint produces its own (few) warning messages. -

An advanced usage is the generation of test vectors in a specific format. -Instead of using the fo functions, you can write your own set -of functions that return the symbols of a specific test format in a way -that is understandable to the fprint format specifiers. As an -example, when a high output value should be represented using the symbol -'H' it suffices to write a conversion function that returns "B:H" and call -it in combination with the %b format specifier. -

-


-

-Parametrization

-Prefix and postfix strings for bit-oriented and hex-oriented output are -parameterizable in the packages to accommodate different output styles. -The settings in the distribution are such that hex output is indicated -by the prefix '0x', while  bit output prefix and postfix are empty -strings. -

You can adapt the output style by modifying the following constants -in the package header: -

   -- prefix string for hex output -
  -- VHDL style:    "X""" -
  -- Verilog style: "h'" -
  -- C style:       "0x" -
  constant FIO_h_PRE:  string := "0x"; -

  -- postfix string for hex output -
  -- VHDL style:    """" -
  constant FIO_h_POST: string := ""; -

  -- prefix string for bit vector output -
  -- VHDL style:    "B""" -
  -- Verilog style: "b'" -
  constant FIO_bv_PRE:  string := ""; -

  -- postfix string for bit vector output -
  -- VHDL style:    """" -
  constant FIO_bv_POST: string := ""; -

  -- prefix string for bit output -
  -- VHDL style:    "'" -
  -- Verilog style: "b'" -
  constant FIO_b_PRE:  string := ""; -

  -- postfix string for bit output -
  -- VHDL style:    "'" -
  constant FIO_b_POST: string := ""; -

-


-

-Test bench

-Included in the distribution are the files TB_PCK_FIO_1987.vhd and -TB_PCK_FIO_1993 with a test bench,depending on the standard you're -running, for the PCK_FIO package. The file PCK_FIO.out.gold contains -the expected output. If you run the test bench it should produce the file -PCK_FIO.out -that should be identical to PCK_FIO.out.gold. The source files -should be analyzed in a VHDL library EASICS_PACKAGES. -

A good way to understand fprint is to inspect the test bench -and what it produces. -

-


-

-Known limitations and problems

-This VHDL package is an implementation of a flexible concept. It is likely -to be extended and modified in the future. Backward compatibility is not -guaranteed. Therefore, it is not recommended to give this package the status -of a company wide standard package (or even worse, a VHDL standard package). -Rather, it should be linked with a particular project (and it can be regarded -as a standard package within that project). -

PCK_FIO is available in either standard VHDL Std1076-1987 or standard -VHDL Std1076-1993. Nevertheless, some simulators/versions have problems -with the package. The following is an overview of currently known issues: -
  -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PCK_FIO_1987 and various simulators/versions
SimulatorPCK_FIO_1987
Synopsys VSS 3.5 and earlierIncorrect (all zero) output in compiled mode
Synopsys VSS 97.01OK
Synopsys VSS/Scirocco 2000.02Incorrect output in compiled mode, interpreted mode works
Mentor quickhdlOK
Modeltech modelsimOK
Cadence LeapfrogShould work with 4.4.1 -
Mysterious problems have been reported - please run the test bench -and report problems
- -
  -
- - - - - - - - - - - - - - - - - - - - - - - - - -
PCK_FIO_1993 and various simulators/versions
SimulatorPCK_FIO_1993
Synopsys VSS/Scirocco 2000.02Compile errors due to improper handling of files by Synopsys
Synopsys VSS/Scirocco 2000.06works fine
Modeltech modelsim 5.4c and higherOK
- -

Although the package name suggests file IO, it only does file output. -

-


-

-Author

-Jan Decaluwe -

-


- - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold b/lib/PCK_FIO-2002.7/PCK_FIO.out.gold deleted file mode 100644 index 3fcfe4c..0000000 Binary files a/lib/PCK_FIO-2002.7/PCK_FIO.out.gold and /dev/null differ diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd deleted file mode 100644 index d4cf8e6..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1987.vhd +++ /dev/null @@ -1,105 +0,0 @@ ----- $Id: PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -package PCK_FIO is - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd deleted file mode 100644 index 44e42cf..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1987_BODY.vhd +++ /dev/null @@ -1,821 +0,0 @@ ----- $Id: PCK_FIO_1987_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -package body PCK_FIO is - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (F: out text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (F: out text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - -- unsigned to decimal - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - -- signed to decimal - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - -- string to decimal - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - -- boolean (0,1) to decimal - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - -- boolean (T,F) to decimal - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - -- test for end of format string - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (F: out text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (F: out text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - -- auxilary function fgets(Arg: string) - -- gives index until first NUL - -- reads string from 1 to Arg'length - function fgets (Arg: string) return integer is - variable index: integer := Arg'length; - begin - for i in 1 to Arg'length loop - if Arg(i) = NUL then - index := i - 1; - exit; - else - null; - end if; - end loop; - return index; - end fgets; - - function fo (Arg: string) return string is - begin - return Arg(1 to fgets(Arg)); - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; - - - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd deleted file mode 100644 index 9df893e..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd +++ /dev/null @@ -1,108 +0,0 @@ ----- $Id: PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -use STD.TEXTIO.all; - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -package PCK_FIO is - - - -- prefix string for hex output - -- VHDL style: "X""" - -- Verilog style: "h'" - -- C style: "0x" - constant FIO_h_PRE: string := "0x"; - - -- postfix string for hex output - -- VHDL style: """" - constant FIO_h_POST: string := ""; - - -- prefix string for bit vector output - -- VHDL style: "B""" - -- Verilog style: "b'" - constant FIO_bv_PRE: string := ""; - - -- postfix string for bit vector output - -- VHDL style: """" - constant FIO_bv_POST: string := ""; - - -- prefix string for bit output - -- VHDL style: "'" - -- Verilog style: "b'" - constant FIO_b_PRE: string := ""; - - -- postfix string for bit output - -- VHDL style: "'" - constant FIO_b_POST: string := ""; - - -- digit width for the string representation of integers - constant FIO_d_WIDTH: integer := 10; - - -- bit width for the string representation of integers - constant FIO_b_WIDTH: integer := 32; - - -- definition of the NIL string (default value for fprint arguments) - -- fprint stops consuming arguments at the first NIL argument - constant FIO_NIL: string := "\"; - - procedure fprint - (file F: text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ); - - function fo (Arg: unsigned) return string; - function fo (Arg: signed) return string; - function fo (Arg: std_logic_vector) return string; - function fo (Arg: std_ulogic_vector) return string; - function fo (Arg: bit_vector) return string; - function fo (Arg: integer) return string; - function fo (Arg: std_ulogic) return string; - function fo (Arg: bit) return string; - function fo (Arg: boolean) return string; - function fo (Arg: character) return string; - function fo (Arg: string) return string; - function fo (Arg: time) return string; - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive); - -end PCK_FIO; - - - diff --git a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd b/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd deleted file mode 100644 index 3d123f0..0000000 --- a/lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd +++ /dev/null @@ -1,814 +0,0 @@ ----- $Id: PCK_FIO_1993_BODY.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - - package body PCK_FIO is - - -------------------------- - -- FIO Warnings support -- - -------------------------- - - procedure FIO_Warning_Fsbla (file F: text; - L: inout line; - Format: in string; - Pointer: in positive) is - begin - fprint (F, L, "\n** Warning: FIO_PrintLastValue: " & - "Format specifier beyond last argument\n"); - fprint (F, L, "** in format string: ""%s""\n", Format); - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n"); - end FIO_Warning_Fsbla; - - procedure FIO_Warning_Ufs (file F: text; - L: inout line; - Format: in string; - Pointer: in positive; - Char: in character) is - begin - fprint (F, L, "\n** Warning: FIO_PrintArg: " & - "Unexpected format specifier '%r'\n", - fo(Char)); - fprint (F, L, "** in format string: ""%s""\n", Format) ; - fprint (F, L, "** "); - for i in 1 to Pointer-1 loop - fprint (F, L, "-"); - end loop; - fprint (F, L, "^\n** Assuming 'q' to proceed: "); - end FIO_Warning_Ufs; - - - ---------------------------------- - -- bit conversion support -- - ---------------------------------- - - type T_bit_map is array(bit) of character; - - constant C_BIT_MAP: T_bit_map - := ('0', '1'); - - ---------------------------------- - -- std_logic conversion support -- - ---------------------------------- - - type T_std_logic_map is array(std_ulogic) of character; - - constant C_STD_LOGIC_MAP: T_std_logic_map - := ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); - - ------------------------------ - -- Digit conversion support -- - ------------------------------ - - -- types & constants - - subtype S_digit_chars is character range '0' to '9'; - subtype S_digits is integer range 0 to 9 ; - - type T_digit_chars_map is array(S_digit_chars) of S_digits; - - constant C_DIGIT_CHARS_MAP: T_digit_chars_map - := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9); - - type T_digits_map is array(S_digits) of S_digit_chars; - - constant C_DIGITS_MAP: T_digits_map - := ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9'); - - - -------------------------------- - -- Decimal conversion support -- - -------------------------------- - - -- unsigned to decimal - - function U_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - for i in Argument'range loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(-1); - end case; - end loop; - return (Result); - end U_To_d; - - -- signed to decimal - - function S_To_d (Arg: string) return integer is - constant Argument: string(Arg'length downto 1) := Arg; - variable Result: integer := 0; - begin - case Argument(Argument'left) is - when '1' => Result := - 2**(Argument'left-1); - when '0' => Result := 0; - when others => return (integer'low); - end case; - for i in Argument'left-1 downto 1 loop - case Argument(i) is when '1' => Result := 2**(i-1) + Result; - when '0' => null; - when others => return(integer'low); - end case; - end loop; - return (Result); - end S_To_d; - - -- string to decimal - - function I_To_d (Arg: string(1 to FIO_d_WIDTH+1)) return integer is - constant Sign: character := Arg(1); - constant Value: string(Arg'length-1 downto 1) := Arg(2 to Arg'length); - variable Char: character; - variable Result: integer := 0; - begin - Result := 0; - for i in Value'range loop - Result := Result * 10; - Char := Value(i); - if (Char /= ' ') then - Result := Result + C_DIGIT_CHARS_MAP(Char); - end if; - end loop; - case Sign is when '-' => return(-Result); - when others => return(Result); - end case; - end I_To_d; - - -- boolean (0,1) to decimal - - function B_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "1" => return(1); - when "0" => return(0); - when others => return(-1); - end case; - end B_To_d; - - -- boolean (T,F) to decimal - - function L_To_d (Arg: string(1 to 1)) return integer is - begin - case Arg is when "T" => return(1); - when others => return(0); - end case; - end L_To_d; - - - - ---------------------------- - -- Hex conversion support -- - ---------------------------- - - -- Constants & types - - constant C_HEX_CHARS: string(1 to 17) := "0123456789ABCDEF?"; - - -- Function to return Hex index of a nibble - - function U_To_h_Index(Arg: string(4 downto 1)) return integer is - variable Index: integer := 0; - begin - for i in Arg'range loop - case Arg(i) is when '1' => Index := 2**(i-1) + Index; - when '0' => null; - when others => return (17); - end case; - end loop; - return (Index+1); - end U_To_h_Index; - - -- Hex conversion - - function U_To_h (Arg: string) return string is - variable Result: string((Arg'length-1)/4 +1 downto 1); - variable ExtArg: string(Result'length*4 downto 1) := (others => '0'); - begin - ExtArg(Arg'length downto 1) := Arg; - for i in Result'range loop - Result(i) := C_HEX_CHARS(U_To_h_Index( ExtArg(i*4 downto i*4 -3) )); - end loop; - return (FIO_h_PRE & Result & FIO_h_POST); - end U_To_h; - - - - ---------------------------- - -- Bit conversion support -- - ---------------------------- - - function L_To_b (Arg: string(1 to 1)) return string is - variable Result: string(1 to 1); - begin - case Arg is when "T" => Result := "1"; - when others => Result := "0"; - end case; - return(FIO_b_PRE & Result & FIO_b_POST); - end L_To_b; - - - function I_To_b (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - - variable IntValue: integer := I_To_d(Arg); - variable BitValue: string(1 to FIO_b_WIDTH) := (others => ' '); - variable Sign: character := ' '; - constant Blanks: string(1 to FIO_b_WIDTH) := (others => ' '); - variable BitWidth: integer range 0 to FIO_b_WIDTH; - variable MsPos: integer range 1 to BitValue'length; - variable BitValueExtended: string(1 to 2*FIO_b_WIDTH); - - begin - - if (IntValue < 0) then - Sign := '-'; - IntValue := -IntValue; - end if; - - for i in BitValue'reverse_range loop - BitValue(i) := C_DIGITS_MAP(IntValue mod 2); - IntValue := IntValue / 2; - exit when (IntValue = 0); - end loop; - - BitValueExtended := BitValue & Blanks; - - if (Width = 0) or (Width > FIO_b_WIDTH+1) then - BitWidth := FIO_b_WIDTH; - else - BitWidth := Width-1; - end if; - - if (Justified = RIGHT) then - return (FIO_bv_PRE & - Sign & BitValue(BitValue'length-BitWidth+1 to BitValue'length) & - FIO_bv_POST); - else - for i in BitValue'range loop - if BitValue(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (FIO_bv_PRE & - Sign & BitValueExtended(MSPos to MSPos+BitWidth-1) & - FIO_bv_POST); - end if; - - end I_To_b; - - - ----------------------------------- - -- Reasonable conversion support -- - ----------------------------------- - - function I_To_r (Arg: string(1 to FIO_d_WIDTH+1); - Justified: side; - Width: integer) return string is - constant Value: string(1 to FIO_d_WIDTH) := Arg(2 to FIO_d_WIDTH+1); - constant Sign: character := Arg(1); - constant Blanks: string(1 to FIO_d_WIDTH) := (others => ' '); - variable IntWidth: integer range 0 to FIO_d_WIDTH; - variable MsPos: integer range 1 to Value'length; - variable ValueExtended: string(1 to 2*FIO_d_WIDTH) := Value & Blanks; - begin - if (Width = 0) or (Width > FIO_d_WIDTH+1) then - IntWidth := FIO_d_WIDTH; - else - IntWidth := Width-1; - end if; - if (Justified = RIGHT) then - return (Sign & Value(Value'length-IntWidth+1 to Value'length)); - else - for i in Value'range loop - if Value(i) /= ' ' then - MSPos := i; - exit; - end if; - end loop; - return (Sign & ValueExtended(MSPos to MSPos+IntWidth-1)); - end if; - end I_To_r; - - - ------------------------------------------- - -- Reasonable output conversion function -- - ------------------------------------------- - - function ReasonableOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return U_To_h(Value); - when "I:" => - return I_To_r(Value, Justified, Width); - when "B:" | "L:" | "C:" => - return Value; - when others => - return Argument; - end case; - - end ReasonableOutput; - - - ------------------------------------ - -- Bit output conversion function -- - ------------------------------------ - - function BitOutput (Arg: string; - Justified: side; - Width: integer) return string is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:" | "S:" | "V:" => - return (FIO_bv_PRE & Value & FIO_bv_POST); - when "B:" => - -- Value(1 to 1) instead of Value for LeapFrog - return (FIO_b_PRE & Value(1 to 1) & FIO_b_POST); - when "I:" => - return I_To_b(Value, Justified, Width); - when "L:" => - -- Value(1 to 1) instead of Value for LeapFrog - return L_To_b(Value(1 to 1)); - when others => - return Argument; - end case; - - end BitOutput; - - - ------------------------------------------- - -- Decimal output conversion function -- - ------------------------------------------- - - function DecimalOutput (Arg: string) return integer is - constant Argument: string(1 to Arg'length) := Arg; - constant TypeSpec: string (1 to 2) := Argument(1 to 2); - constant Value: string(1 to Arg'length-2) := Argument(3 to Arg'length); - begin - case TypeSpec is - when "U:"| "V:" => - return U_To_d(Value); - when "S:" => - return S_To_d(Value); - when "I:" => - return I_To_d(Value); - when "B:" => - return B_To_d(Value); - when "L:" => - return L_To_d(Value); - when others => - return integer'low; - end case; - - end DecimalOutput; - - - ---------------------------- - -- Atomic print functions -- - ---------------------------- - - -- test for end of format string - - function FIO_EOS (Format: in string; - Pointer: in integer) - return boolean is - begin - return (Pointer > Format'length); - end FIO_EOS; - - - -- Atomic value print function - - procedure FIO_PrintValue (file F: text; - L: inout line; - Format: in string; - Pointer: inout integer; - Last: in boolean := FALSE) is - variable Char: character; - begin - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '\' => - Pointer := Pointer + 1; - exit when (FIO_EOS(Format, Pointer)); - Char := Format(Pointer); - case Char is when 'n' => writeline(F, L); - when others => write(L, Char); - end case; - when '%' => - if Last then - FIO_Warning_Fsbla(F, L, Format, Pointer); - end if; - Pointer := Pointer + 1; - exit; - when others => - write(L, char); - end case; - Pointer := Pointer + 1; - end loop; - end FIO_PrintValue; - - - ---- Atomic argument print function - - procedure FIO_PrintArg (file F: text; - L: inout line; - Format: in string; - Pointer: inout integer; - Arg: in string) is - variable Char: character; - variable Justified: side; - variable Width: integer; - - begin - - FIO_PrintValue(F, L, Format, Pointer); - - Justified := RIGHT; - Width := 0; - while (not FIO_EOS(Format, Pointer)) loop - Char := Format(Pointer); - case Char is - when '-' => - Justified := LEFT; - Pointer := Pointer + 1; - when '0' to '9' => - Width := Width*10 + C_DIGIT_CHARS_MAP(Char); - Pointer := Pointer + 1; - when 'r' => - write(L, ReasonableOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'b' => - write(L, BitOutput(Arg, Justified, Width), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'd' => - write(L, DecimalOutput(Arg), Justified, Width); - Pointer := Pointer + 1; - exit; - when 'q' | 's' => - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - when others => - FIO_Warning_Ufs(F, L, Format, Pointer, Char); - write(L, Arg, Justified, Width); - Pointer := Pointer + 1; - exit; - end case; - end loop; - end FIO_PrintArg; - - - ----------------------------------------------------- - -- The format string iteration expansion procedure -- - ----------------------------------------------------- - - procedure FIO_FormatExpand (FMT: inout line; - Format: in string; - StartPointer: in positive) is - - variable Pointer: positive := StartPointer; - variable TokenStart: positive; - variable IterStringStart: positive; - variable IterStringEnd: positive; - variable IterCount: natural; - variable OpenBrackets: natural; - variable L: line; - - begin - - FORMAT_SEARCH: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- look for format specifier - when '%' => - - -- initialize iteration token search - TokenStart := Pointer; - IterCount := 0; - Pointer := Pointer + 1; - - -- start iteration token search - TOKEN_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - - -- read iteration counter - when '0' to '9' => - IterCount := IterCount*10 + C_DIGIT_CHARS_MAP(Format(Pointer)); - Pointer := Pointer + 1; - - -- expect open bracket - when '{' => - - -- initialize iteration string read - OpenBrackets := 1; - IterStringStart := Pointer + 1; - Pointer := Pointer + 1; - -- quit prematurely when iteration count is 0 - next FORMAT_SEARCH when (IterCount = 0); - - -- start iteration string read - ITER_STRING_READ: while not FIO_EOS(Format, Pointer) loop - - case Format(Pointer) is - -- keep track of open brackets - when '{' => - OpenBrackets := OpenBrackets + 1; - Pointer := Pointer + 1; - -- when closing bracket is found, process iteration string - when '}' => - OpenBrackets := OpenBrackets - 1; - if (OpenBrackets = 0) then - IterStringEnd := Pointer-1; - if (TokenStart /= 1) then - write(L, Format(1 to TokenStart-1)); - end if; - for i in 1 to IterCount loop - write(L, Format(IterStringStart to IterStringEnd)); - end loop; - if (IterStringEnd /= Format'length) then - write(L, Format(IterStringEnd+2 to Format'length)); - end if; - -- call expansion procedure recursively on expanded format - FIO_FormatExpand(FMT, L.all, TokenStart); - deallocate(L); - return; - end if; - Pointer := Pointer + 1; - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - -- read iteration string - when others => - Pointer := Pointer + 1; - - end case; - - end loop ITER_STRING_READ; - - -- stop iteration token search when no opening bracket found - when others => - Pointer := Pointer + 1; - next FORMAT_SEARCH; - - end case; - - end loop TOKEN_READ; - - -- skip escaped characters - when '\' => - Pointer := Pointer + 2; - - -- read other characters - when others => - Pointer := Pointer + 1; - - end case; - - end loop FORMAT_SEARCH; - - write(FMT, Format); - deallocate(L); - - end FIO_FormatExpand; - - - - -------------------------- - -- The fprint procedure -- - -------------------------- - - procedure fprint - (file F: text; - L: inout line; - Format: in string; - A1 , A2 , A3 , A4 , A5 , A6 , A7 , A8 : in string := FIO_NIL; - A9 , A10, A11, A12, A13, A14, A15, A16: in string := FIO_NIL; - A17, A18, A19, A20, A21, A22, A23, A24: in string := FIO_NIL; - A25, A26, A27, A28, A29, A30, A31, A32: in string := FIO_NIL - ) is - - variable Pointer: integer; - variable FMT: line; - - begin - - Pointer := 1; - - FIO_FormatExpand (FMT, Format, Format'low); - - if (A1 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A1 ); - if (A2 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A2 ); - if (A3 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A3 ); - if (A4 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A4 ); - if (A5 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A5 ); - if (A6 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A6 ); - if (A7 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A7 ); - if (A8 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A8 ); - if (A9 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A9 ); - if (A10 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A10); - if (A11 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A11); - if (A12 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A12); - if (A13 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A13); - if (A14 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A14); - if (A15 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A15); - if (A16 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A16); - if (A17 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A17); - if (A18 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A18); - if (A19 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A19); - if (A20 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A20); - if (A21 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A21); - if (A22 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A22); - if (A23 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A23); - if (A24 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A24); - if (A25 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A25); - if (A26 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A26); - if (A27 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A27); - if (A28 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A28); - if (A29 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A29); - if (A30 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A30); - if (A31 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A31); - if (A32 /= FIO_NIL) then FIO_PrintArg(F, L, FMT.all, Pointer, A32); - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - end if; end if; end if; end if; end if; end if; end if; end if; - - FIO_PrintValue(F, L, FMT.all, Pointer, Last => TRUE); - - deallocate(FMT); - - end fprint; - - - ------------------------------------------- - -- Formatted output conversion functions -- - ------------------------------------------- - - function fo (Arg: unsigned) return string is - constant Argument: unsigned(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("U:" & Result); - end fo; - - function fo (Arg: signed) return string is - constant Argument: signed(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("S:" & Result); - end fo; - - function fo (Arg: std_logic_vector) return string is - constant Argument: std_logic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: std_ulogic_vector) return string is - constant Argument: std_ulogic_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_STD_LOGIC_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: bit_vector) return string is - constant Argument: bit_vector(1 to Arg'length) := Arg; - variable Result: string(1 to Arg'length); - begin - for i in Argument'range loop - Result(i) := C_BIT_MAP(Argument(i)); - end loop; - return ("V:" & Result); - end fo; - - function fo (Arg: integer) return string is - variable Argument: integer := Arg; - variable Result: string(1 to FIO_d_WIDTH) := (others => ' '); - variable Sign: character := ' '; - begin - if (Argument < 0) and (Argument /= integer'low) then - Sign := '-'; - Argument := -Argument; - end if; - for i in Result'reverse_range loop - Result(i) := C_DIGITS_MAP(Argument mod 10); - Argument := Argument / 10; - exit when (Argument = 0); - end loop; - return ("I:" & Sign & Result); - end fo; - - function fo (Arg: std_ulogic) return string is - begin - return ("B:" & C_STD_LOGIC_MAP(Arg)); - end fo; - - function fo (Arg: bit) return string is - begin - return ("B:" & C_BIT_MAP(Arg)); - end fo; - - function fo (Arg: boolean) return string is - begin - if (ARG = TRUE) then - return ("L:T"); - else - return ("L:F"); - end if; - end fo; - - function fo (Arg: character) return string is - begin - return ("C:" & Arg); - end fo; - - -- auxilary function fgets(Arg :string) - -- returns index of first NUL in Arg or if no NUL is present just Arg'length - -- goes through Arg from 1 to Arg'length - function fgets (Arg: string) return integer is - variable index: integer := Arg'length; - begin - for i in 1 to Arg'length loop - if Arg(i) = NUL then - index := i - 1; - exit; - else - null; - end if; - end loop; - return index; - end fgets; - - -- returns the Arg string until the first NUL was encountered - -- if fo is used on a string with NUL in it it will stop reading the rest - -- of the string, even if a larger field width has been supplied. fo will - -- then just pad the remaining characters with blanco's - function fo (Arg: string) return string is - begin - return Arg(1 to fgets(Arg)); - end fo; - - function fo (Arg: time) return string is - begin - return fo (integer (Arg / 1 ns)); - end fo; - -end PCK_FIO; - diff --git a/lib/PCK_FIO-2002.7/README b/lib/PCK_FIO-2002.7/README deleted file mode 100644 index b16c6c5..0000000 --- a/lib/PCK_FIO-2002.7/README +++ /dev/null @@ -1,88 +0,0 @@ ----- $Id: README,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - -Version 2002.07 -=============== - -Contents -======== - -This distribution contains the following files: - - PCK_FIO_1987.vhd: VHDL-87 source of the header of the PCK_FIO package - PCK_FIO_1987_BODY.vhd: VHDL-87 source of the body of the PCK_FIO package - PCK_FIO_1993.vhd: VHDL-93 source of the header of the PCK_FIO package - PCK_FIO_1993_BODY.vhd: VHDL-93 source of the body of the PCK_FIO package - TB_PCK_FIO_1987.vhd: VHDL-87 source of the testbench for package PCK_FIO - TB_PCK_FIO_1993.vhd: VHDL-93 source of the testbench for package PCK_FIO - PCK_FIO.out.gold: Certified test bench output - PCK_FIO.html: Manual for PCK_FIO in html format - README: This file - - -Installation -============ - -VHDL-1987 ---------- -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO_1987.vhd and PCK_FIO_1987_BODY.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO_1987.vhd into the same library. - -VHDL-1993 ---------- -To install PCK_FIO, define a VHDL library called EASICS_PACKAGES, and -analyze the VHDL file PCK_FIO_1993.vhd and PCK_FIO_1993_BODY.vhd into this library. - -To install the test bench, analyze TB_PCK_FIO_1993.vhd into the same library. - -Numeric packages ----------------- -If you want to use IEEE.std_logic_arith instead of IEEE.numeric_std, you need -to edit the source code of the package, both header and body, and the test bench -and replace the package use clause. PCK_FIO works with either of these packages. - -Documentation -------------- -To install the documentation, put the file point PCK_FIO.html in a path of -your choosing, point your web browser to it, and bookmark it. - - -Installation check -================== - -After installing the test bench, you should run it. The corresponding VHDL -design unit is EASICS_PACKAGES.TBE_PCK_FIO(TB). - -Simulating the test bench should create a file called PCK_FIO.out. This file -should be identical to PCK_FIO.out.gold. Any difference indicates a portability -issue or a simulator non-compliance or bug. - - - - diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd deleted file mode 100644 index 2e18ff4..0000000 --- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1987.vhd +++ /dev/null @@ -1,531 +0,0 @@ ----- $Id: TB_PCK_FIO_1987.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one - use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text is out "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - constant TempString: string :="ABC" & NUL & "DEF"; -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" & - "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n"");\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); -fprint(RESULT, L, - "\n-------------------------------\n"& - "--Testing string manipulation--\n"& - "-------------------------------\n"); -fprint(RESULT, L, "--testing done using the string TempString : " & """ABC""" - & " & NUL & ""DEF""\n"); --- temp_string: string:="ABC"&NUL&"DEF" --- test for detecting NUL in string -fprint(RESULT, L, "\n--test for NUL ending in strings\n"); -fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n"); -fprint(RESULT, L, fo(TempString)); - --- direct inclusion of string in fprint should give whole string -fprint(RESULT, L, "\n--same without fo,so without NUL testing\n"); -fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n"); -fprint(RESULT, L, TempString & "\n"); - --- influence of given width - -fprint(RESULT, L, "\n--if there are less characters in the given string then" - & " in the width fo will\n"& - "-- pad the remaining with blanco's according to the given justification\n"); -fprint(RESULT, L, "\n--with specified width, justified right,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n"); -fprint(RESULT, L, "%5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width, justified left, using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n"); -fprint(RESULT, L, "%-5s",fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n"); -fprint(RESULT, L, "%9s", TempString); -fprint(RESULT, L, "\n\n-- if the width is smaller then the number" & - " of characters in the string fprint\n" & - "-- will output the string with the minimum of characters needed\n"); -fprint(RESULT, L, "\n--with specified width,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n"); -fprint(RESULT, L, "%2s",fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n"); -fprint(RESULT, L, "%4s", TempString); - - -fprint(RESULT, L, - "\n\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; - - diff --git a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd b/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd deleted file mode 100644 index 0386a11..0000000 --- a/lib/PCK_FIO-2002.7/TB_PCK_FIO_1993.vhd +++ /dev/null @@ -1,536 +0,0 @@ ----- $Id: TB_PCK_FIO_1993.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $ ----- ----- PCK_FIO: a VHDL package for C-style formatted file output ----- Copyright (C) 1995, 2001 Easics NV ----- ----- This library is free software; you can redistribute it and/or ----- modify it under the terms of the GNU Lesser General Public ----- License as published by the Free Software Foundation; either ----- version 2.1 of the License, or (at your option) any later version. ----- ----- This library is distributed in the hope that it will be useful, ----- but WITHOUT ANY WARRANTY; without even the implied warranty of ----- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ----- Lesser General Public License for more details. ----- ----- You should have received a copy of the GNU Lesser General Public ----- License along with this library; if not, write to the Free Software ----- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ----- ----- For suggestions, bug reports, enhancement requests, and info about ----- our design services, you can contact us at the following address: ----- http://www.easics.com ----- Easics NV, Interleuvenlaan 86, B-3001 Leuven, Belgium ----- tel.: +32 16 395 600 fax : +32 16 395 619 ----- e-mail: jand@easics.be (Jan Decaluwe) ----- - - -library IEEE; -use IEEE.std_logic_1164.all; --- signed/unsigned definition: use either std_logic_arith or numeric_std --- use IEEE.std_logic_arith.all; -- the Synopsys one -use IEEE.numeric_std.all; - -use STD.TEXTIO.all; - -library EASICS_PACKAGES; -use EASICS_PACKAGES.PCK_FIO.all; - -entity TBE_PCK_FIO is - -end TBE_PCK_FIO; - -architecture TB of TBE_PCK_FIO is - -begin - -USAGE: process - - file RESULT: text open write_mode is "PCK_FIO.out"; - variable L: line; - variable Pointer: integer; - variable BoolTrue: boolean := TRUE; - variable BoolFalse: boolean := FALSE; - variable IntPos: integer := 5678; - variable BigIntPos: integer := 12345678; - variable IntNeg: integer := -8765; - variable BigIntNeg: integer := -87654321; - variable Uns: unsigned(6 downto 0) := unsigned'("1010010"); - variable Unk: unsigned(6 downto 0) := unsigned'("1X10Z10"); - variable Std: std_logic_vector(6 downto 0) := std_logic_vector'("0010010"); - variable SigPos: signed(6 downto 0) := signed'("0010010"); - variable SigNeg: signed(6 downto 0) := signed'("1010010"); - variable BitX: std_logic := 'X'; - variable Bit1: std_logic := '1'; - variable Bit0: std_logic := '0'; - - variable parameter_1: integer := 1234; - variable parameter_2: integer := 2345; - variable parameter_3: integer := 4567; - - constant TempString: string :="ABC" & NUL & "DEF"; -begin - -fprint(RESULT, L, - "PCK_FIO.out: TESTBENCH OUTPUT FOR PCK_FIO\n" & - "-----------------------------------------\n\n" & - "This is the result of running the PCK_FIO testbench.\n" & - "This file should be compared with PCK_FIO.out.gold, which is\n" & - "the reference output. Any difference indicates a portability\n" & - "issue or a simulator non-compliance or bug.\n\n" - ); - - -fprint(RESULT, L, - "\n--------------------\n" & - "-- Basic features --\n" & - "--------------------\n\n" - ); - -fprint(RESULT, L, - "-- First some auxiliary declarations\n" - ); - -fprint(RESULT, L, - "> file RESULT: text is out ""PCK_FIO.out"";\n" & - "> variable L: line;\n" & - "> variable BoolTrue: boolean := TRUE;\n" & - "> variable BoolFalse: boolean := FALSE;\n" & - "> variable IntPos: integer := 5678;\n" & - "> variable BigIntPos: integer := 12345678;\n" & - "> variable IntNeg: integer := -8765;\n" & - "> variable BigIntNeg: integer := -87654321;\n" & - "> variable Uns: unsigned(6 downto 0) := unsigned'(""1010010"");\n" & - "> variable Unk: unsigned(6 downto 0) := unsigned'(""1X10Z10"");\n" & - "> variable Std: std_logic_vector(6 downto 0) := std_logic_vector'(""0010010"");\n" & - "> variable SigPos: signed(6 downto 0) := signed'(""0010010"");\n" & - "> variable SigNeg: signed(6 downto 0) := signed'(""1010010"");\n" & - "> variable BitX: std_logic := 'X';\n" & - "> variable Bit1: std_logic := '1';\n" & - "> variable Bit0: std_logic := '0';\n" & - "> constant TempString: string := ""ABC"" & NUL & ""DEF"";\n" -); - - -fprint(RESULT, L, - "\n\n-- fprint call with no arguments\n" & - "> fprint(RESULT, L, ""No arguments.\\n"");\n" - ); -fprint(RESULT, L, "No arguments.\n"); - - -fprint(RESULT, L, - "\n-- Special characters need to be escaped\n" & - "> fprint(RESULT, L, ""Special characters: \\\% \\\\ "" \\n"");\n" - ); - -fprint(RESULT, L, "Special characters: \% \\ "" \n"); - - -fprint(RESULT, L, - "\n-- Various format specifiers interprete the same object differently\n" & - "> fprint(RESULT, L, ""Format specifiers: \%r \%d \%b \%q\\n"",\n" & - "> fo(Uns), fo(Uns), fo(Uns), fo(Uns)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Format specifiers: %r %d %b %q\n", - fo(Uns), fo(Uns), fo(Uns), fo(Uns) - ); - -fprint(RESULT, L, - "\n-- Format string can be shortened by using the iteration specifier\n" & - "> fprint(RESULT, L, ""Iteration specifier: \%4{\%r }\\n"",\n" & - "> fo(Uns), fo(SigPos), fo(SigNeg), fo(Std)\n" & - "> );\n" - ); - -fprint(RESULT, L, "Iteration specifier: %4{%r }\n", - fo(Uns), fo(SigPos), fo(SigNeg), fo(Std) - ); -fprint(RESULT, L, - "\n-------------------------------\n"& - "--Testing string manipulation--\n"& - "-------------------------------\n"); -fprint(RESULT, L, "--testing done using the string TempString : " & """ABC""" - & " & NUL & ""DEF""\n"); --- TempString: string:="ABC" & NUL & "DEF" --- test for detecting NUL in string -fprint(RESULT, L ,"\n--test for NUL ending in strings\n"); -fprint(RESULT, L, "> fprint(RESULT, L, fo(TempString));\n"); -fprint(RESULT, L, fo(TempString)); - --- direct inclusion of string in fprint should give whole string -fprint(RESULT, L, "\n--same without fo,so without NUL testing\n"); -fprint(RESULT, L, "> fprint(RESULT, L, TempString);\n"); -fprint(RESULT, L, TempString & "\n"); - --- influence of given width - -fprint(RESULT, L, "\n--if there are less characters in the given string then in the width fo will\n"& - "-- pad the remaining with blanco's according to the given justification\n"); -fprint(RESULT, L, "\n--with specified width, justified right,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%5s"", fo(TempString));\n"); -fprint(RESULT, L, "%5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width, justified left, using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%-5s"", fo(TempString));\n"); -fprint(RESULT, L, "%-5s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%9s"", TempString);\n"); -fprint(RESULT, L, "%9s", TempString); -fprint(RESULT, L, "\n\n-- if the width is smaller then the number of characters in the string fprint\n"& - "-- will output the string with the minimum of characters needed\n"); -fprint(RESULT, L, "\n--with specified width,using fo\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%2s"", fo(TempString));\n"); -fprint(RESULT, L, "%2s", fo(TempString)); -fprint(RESULT, L, "\n--with specified width without fo\n"); -fprint(RESUlT, L, "> fprint(RESULT, L, ""\%4s"", TempString);\n"); -fprint(RESULT, L, "%4s", TempString); - -fprint(RESULT, L, - "\n\n------------------------------------\n" & - "-- Support for bit-oriented types --\n" & - "------------------------------------\n" - ); - -fprint (RESULT, L, "\n-- Reasonable format\n" & - "> fprint(RESULT, L, ""Reasonable format: \%9{\%r }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Reasonable format: %9{%r }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Decimal format\n" & - "> fprint(RESULT, L, ""Decimal format: \%7{\%d }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Decimal format: %9{%d }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint (RESULT, L, "\n-- Bit format\n" & - "> fprint(RESULT, L, ""Bit format: \%7{\%b }\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk),\n" & - "> fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) \n" & - "> );\n" - ); - - -fprint(RESULT, L, "Bit format: %9{%b }\n", - fo(Std), fo(Uns), fo(SigPos), fo(SigNeg), fo(Unk), - fo(Bit1), fo(BitX), fo(BoolTrue), fo(BoolFalse) - ); - -fprint(RESULT, L, - "\n\n" & - "-- Alignment\n-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Bitvectors with : \%4{|}\\n"",\n" & - "> fo(Std), fo(Uns), fo(SigPos), fo(SigNeg)\n" & - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - -fprint(RESULT, L, "Bitvectors with \%1r: %4{%1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2r: %4{%2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3r: %4{%3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4r: %4{%4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5r: %4{%5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6r: %4{%6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7r: %4{%7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8r: %4{%8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9r: %4{%9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1r: %4{%-1r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2r: %4{%-2r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3r: %4{%-3r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4r: %4{%-4r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5r: %4{%-5r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6r: %4{%-6r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7r: %4{%-7r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8r: %4{%-8r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9r: %4{%-9r|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%1d: %4{%1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%2d: %4{%2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%3d: %4{%3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%4d: %4{%4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%5d: %4{%5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%6d: %4{%6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%7d: %4{%7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%8d: %4{%8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%9d: %4{%9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Bitvectors with \%-1d: %4{%-1d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-2d: %4{%-2d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-3d: %4{%-3d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-4d: %4{%-4d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-5d: %4{%-5d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-6d: %4{%-6d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-7d: %4{%-7d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-8d: %4{%-8d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "Bitvectors with \%-9d: %4{%-9d|} \n", - fo(Uns), fo(Std), fo(SigPos), fo(SigNeg) - ); -fprint(RESULT, L, "\n"); - - - -fprint(RESULT, L, - "\n-------------------------------\n" & - "-- Support for integer types --\n" & - "-------------------------------\n" - ); - -fprint(RESULT, L, - "\n\n" & - "-- Template of the call: ( stands for the format specifier)\n" - ); - - -fprint(RESULT, L, "\n" & - "> fprint(RESULT, L, ""Integers with : \%4{|}\\n"",\n" & - "> fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg)\n" & - - "> );\n" - ); - -fprint(RESULT, L, - "\n" & - "-- Results of the call with various format specifiers\n\n" - ); - - -fprint(RESULT, L, "Integers with \%5d: %4{%5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6d: %4{%6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7d: %4{%7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8d: %4{%8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9d: %4{%9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10d: %4{%10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5d: %4{%-5d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6d: %4{%-6d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7d: %4{%-7d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8d: %4{%-8d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9d: %4{%-9d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10d: %4{%-10d|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%5r: %4{%5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%6r: %4{%6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%7r: %4{%7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%8r: %4{%8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%9r: %4{%9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%10r: %4{%10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); -fprint(RESULT, L, "Integers with \%-5r: %4{%-5r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-6r: %4{%-6r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-7r: %4{%-7r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-8r: %4{%-8r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-9r: %4{%-9r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "Integers with \%-10r: %4{%-10r|} \n", - fo(IntPos), fo(IntNeg), fo(BigIntPos), fo(BigIntNeg) - ); -fprint(RESULT, L, "\n"); - - -fprint(RESULT, L, - "\n----------------------\n" & - "-- Support for time --\n" & - "----------------------\n" - ); - -fprint (RESULT, L, "-- For portability reasons, time is converted \n" & - "-- into an integer value (of nanoseconds)\n" - ); -fprint (RESULT, L, "> wait for 648 ns\n"); -fprint (RESULT, L, "> fprint (RESULT, L, ""The time is now \%d ns\\n"", fo(now));\n"); - -wait for 648 ns; - -fprint (RESULT, L, "The time is now %d ns\n", fo(now)); - - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Erroneous calls and error messages --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Less arguments than formats specifiers\n" & - "> fprint(RESULT, L, ""\%d \%d \%d \%d \\n"", fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%d %d %d %d \n", fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, "-- Unsupported format specifier\n" & - "> fprint(RESULT, L, ""\%r \%v \%r \%r\\n"", " & - "fo(Uns), fo(Std), fo(Uns), fo(Std));\n" - ); - -fprint(RESULT, L, "%r %v %r %r\n", fo(Uns), fo(Std), fo(Uns), fo(Std)); - -fprint(RESULT, L, "\n"); - -fprint(RESULT, L, - "\n----------------------------------------\n" & - "-- Things you wouldn't expect to work --\n" & - "----------------------------------------\n" - ); - -fprint(RESULT, L, "\n-- Nested iteration\n"); -fprint(RESULT, L, "> fprint(RESULT, L, ""\%3{<<\%3{_END_}>>}\\n"");\n"); -fprint(RESULT, L, "%3{<<%3{_END_}>>}\n"); - -wait; - -end process USAGE; - -end TB; - - - - - - - - - - - diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 deleted file mode 100644 index c5a4a92..0000000 --- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1987 +++ /dev/null @@ -1,34 +0,0 @@ -### msMakefile generated by vma on Thu Oct 4 17:33:56 CEST 2001 - -ANALYZER = vcom -quiet -nologo -ANALYZER_C = vcom -quiet -nologo -all : \ - bin/tbe_pck_fio/tb.dat \ - bin/tbe_pck_fio/_primary.dat - -# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) -# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO - -bin/tbe_pck_fio/tb.dat \ -bin/tbe_pck_fio/_primary.dat : \ - bin/pck_fio/body.dat \ - bin/pck_fio/_primary.dat \ - TB_PCK_FIO_1987.vhd - ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1987.vhd - - -# Prerequisites for package body EASICS_PACKAGES.PCK_FIO() - -bin/pck_fio/body.dat : \ - bin/pck_fio/_primary.dat \ - PCK_FIO_1987_BODY.vhd - ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1987_BODY.vhd - - -# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO - -bin/pck_fio/_primary.dat : \ - PCK_FIO_1987.vhd - ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1987.vhd - - diff --git a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 b/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 deleted file mode 100644 index 0f9a351..0000000 --- a/lib/PCK_FIO-2002.7/msMakefile.TBE_PCK_FIO_TB.1993 +++ /dev/null @@ -1,34 +0,0 @@ -### msMakefile generated by vma on Thu Oct 4 17:32:23 CEST 2001 - -ANALYZER = vcom -quiet -nologo -93 -ANALYZER_C = vcom -quiet -nologo -93 -all : \ - bin/tbe_pck_fio/tb.dat \ - bin/tbe_pck_fio/_primary.dat - -# Prerequisites for architecture EASICS_PACKAGES.TBE_PCK_FIO(TB) -# Prerequisites for entity EASICS_PACKAGES.TBE_PCK_FIO - -bin/tbe_pck_fio/tb.dat \ -bin/tbe_pck_fio/_primary.dat : \ - bin/pck_fio/body.dat \ - bin/pck_fio/_primary.dat \ - TB_PCK_FIO_1993.vhd - ${ANALYZER_C} -work EASICS_PACKAGES TB_PCK_FIO_1993.vhd - - -# Prerequisites for package body EASICS_PACKAGES.PCK_FIO() - -bin/pck_fio/body.dat : \ - bin/pck_fio/_primary.dat \ - PCK_FIO_1993_BODY.vhd - ${ANALYZER_C} -work EASICS_PACKAGES PCK_FIO_1993_BODY.vhd - - -# Prerequisites for package declaration EASICS_PACKAGES.PCK_FIO - -bin/pck_fio/_primary.dat : \ - PCK_FIO_1993.vhd - ${ANALYZER} -work EASICS_PACKAGES PCK_FIO_1993.vhd - - diff --git a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj b/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj deleted file mode 100644 index ba54b14..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/ise9/sdram_ctrl_top_vhdl.prj +++ /dev/null @@ -1,13 +0,0 @@ -vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_config.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_types.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd" -vhdl work "W:\vhdl\lib\FIFO\src\dpram.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_cmd.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\reset_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\fifo_sync.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\ddr_phy_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\clockgen_virtex4.vhd" -vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_4\src\sdram_ctrl_top.vhd" diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do b/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do deleted file mode 100644 index 16b23bb..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_simprim.do +++ /dev/null @@ -1,6 +0,0 @@ -vlib simprim - -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vcomponents_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_Vpackage_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_SMODEL_mti.vhd -vcom -93 -work simprim F:/Xilinx9/vhdl/src/simprims/simprim_VITAL_mti.vhd diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do b/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do deleted file mode 100644 index d35d8c9..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/compile_unisim.do +++ /dev/null @@ -1,6 +0,0 @@ -vlib unisim - -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vpkg.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vcomp.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_smodel.vhd -vcom -93 -work unisim F:/Xilinx9/vhdl/src/unisims/unisim_vital.vhd diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo deleted file mode 100644 index 7af84ba..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl.wdo} -view wave -view structure -view signals -run 800us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo deleted file mode 100644 index 4a9d3f1..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl.wdo +++ /dev/null @@ -1,93 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/mode_fifo_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/col_fifo_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_in -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_out -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_full -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_re -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/cmd_fifo_we -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {14963876 ps} 0} -configure wave -namecolwidth 184 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {14733925 ps} {15711632 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo deleted file mode 100644 index 4f1cf1c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_fifo.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl_fifo -do {tb_sdr_ctrl_fifo.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo deleted file mode 100644 index 4088038..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_fifo.wdo +++ /dev/null @@ -1,68 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/rst_out -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/inst_sdram_cmd/cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_we_n -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_sdram_ctrl/sd_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_addr -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_busy -add wave -noupdate -format Literal /tb_sdr_ctrl_fifo/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_cmd_we -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_r -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_data_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/u_data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/u_req_rd -add wave -noupdate -divider {Read FIFO} -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/read_fifo_re -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/read_fifo_dout -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/was_write -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pr_next -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/pw_next -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_full -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_read_fifo/inst_sync_fifo_ctrl/fifo_empty -add wave -noupdate -divider {Write FIFO} -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_write_fifo/data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/re -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_write_fifo/fifo_full -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pr_next -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw -add wave -noupdate -format Literal -radix unsigned /tb_sdr_ctrl_fifo/inst_write_fifo/inst_sync_fifo_ctrl/pw_next -add wave -noupdate -divider {Command FIFO} -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl_fifo/inst_command_fifo/data_w -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/we -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/re -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_empty -add wave -noupdate -format Logic /tb_sdr_ctrl_fifo/inst_command_fifo/inst_sync_fifo_ctrl/fifo_full -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {13893123 ps} 0} -configure wave -namecolwidth 172 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {13879998 ps} {13928553 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo deleted file mode 100644 index eee9b52..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_lin_r_rand_w.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_lin_r_rand_w.wdo} -view wave -view structure -view signals -run 1200us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo deleted file mode 100644 index 542c24b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_r_rand_w.wdo +++ /dev/null @@ -1,87 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {21813900 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {21725359 ps} {22204052 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo deleted file mode 100644 index 4716a01..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_lin_w_rand_r.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_lin_w_rand_r.wdo} -view wave -view structure -view signals -run 1200us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo deleted file mode 100644 index 542c24b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_lin_w_rand_r.wdo +++ /dev/null @@ -1,87 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {21813900 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {21725359 ps} {22204052 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo deleted file mode 100644 index 9be2261..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_rand_addr.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_rand_rw.wdo} -view wave -view structure -view signals -run 1000us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo deleted file mode 100644 index eb20b08..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_addr.wdo +++ /dev/null @@ -1,82 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {60573747 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {60552548 ps} {60600861 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo deleted file mode 100644 index c868866..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.fdo +++ /dev/null @@ -1,27 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdr_ctrl_rand_rw.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdr_ctrl -do {tb_sdr_ctrl_rand_rw.wdo} -view wave -view structure -view signals -run 10000us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo deleted file mode 100644 index e3087e6..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdr_ctrl_rand_rw.wdo +++ /dev/null @@ -1,84 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_sdram_cmd/burst_finished -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_in -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_wr -add wave -noupdate -format Literal /tb_sdr_ctrl/u_tag_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/clk -add wave -noupdate -format Logic /tb_sdr_ctrl/rst -add wave -noupdate -format Logic /tb_sdr_ctrl/rst_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_fb -add wave -noupdate -format Analog-Step -height 50 -offset 0.5 -scale 20.0 /tb_sdr_ctrl/efficiency -add wave -noupdate -format Literal /tb_sdr_ctrl/data_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/cycle_cnt -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_we_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cs_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_ras_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cas_n -add wave -noupdate -format Logic /tb_sdr_ctrl/part_cke -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_zen -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_rst -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_p -add wave -noupdate -format Logic /tb_sdr_ctrl/part_clk_n -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dqs -add wave -noupdate -format Literal /tb_sdr_ctrl/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_addr -add wave -noupdate -format Literal /tb_sdr_ctrl/part_ba -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/part_data -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/dqs_drive -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/drive270 -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -divider {Main controller} -add wave -noupdate -format Logic /tb_sdr_ctrl/rw_null_en -add wave -noupdate -format Literal /tb_sdr_ctrl/test_phase -add wave -noupdate -format Literal /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/sd_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_en -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/read_clk -add wave -noupdate -format Logic /tb_sdr_ctrl/clk_out -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal /tb_sdr_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_cmd_we -add wave -noupdate -format Logic /tb_sdr_ctrl/u_busy -add wave -noupdate -format Logic /tb_sdr_ctrl/u_data_vld -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_rd -add wave -noupdate -format Logic /tb_sdr_ctrl/u_req_wr -add wave -noupdate -format Logic /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/sys_clk0 -add wave -noupdate -format Literal -expand /tb_sdr_ctrl/inst_sdram_ctrl/phy_ctrl -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/inst_sdram_ctrl/inst_ddr_phy/data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/ref_data -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_r -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_data_w -add wave -noupdate -format Literal -radix hexadecimal /tb_sdr_ctrl/u_addr -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {16004147 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {15914249 ps} {16324366 ps} diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo deleted file mode 100644 index dbf023a..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.fdo +++ /dev/null @@ -1,28 +0,0 @@ -## NOTE: Do not edit this file. -## - -vlib work -vcom -explicit -93 "../../../FIFO/src/fifo_ctrl_pkg.vhd" -vcom -explicit -93 "../../../misc/dpram_1w2r.vhd" -vcom -explicit -93 "../../../FIFO/src/sync_fifo_ctrl.vhd" -vcom -explicit -93 "../../../misc/utils_pkg.vhd" -vcom -explicit -93 "../src/fifo_sync.vhd" -vcom -explicit -93 "../src/sdram_config.vhd" -vcom -explicit -93 "../src/sdram_types.vhd" -vcom -explicit -93 "../src/reset_virtex4.vhd" -vcom -explicit -93 "../src/clockgen_virtex4.vhd" -vcom -explicit -93 "../src/sdram_cmd.vhd" -vcom -explicit -93 "../src/sdram_ctrl.vhd" -vcom -explicit -93 "../src/ddr_phy_virtex4.vhd" -vcom -explicit -93 "../src/sdram_ctrl_top.vhd" -vcom -explicit -93 "../src/sdram_ctrl_frontend.vhd" -vcom -explicit -93 "../src/mt46v16m16.vhd" -vcom -explicit -93 "../src/tb_sdram_ctrl_frontend.vhd" - -#restart -force -vsim -t 1ps -lib work tb_sdram_ctrl_frontend -do {tb_sdram_ctrl_frontend.wdo} -view wave -view structure -view signals -run 40us diff --git a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo b/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo deleted file mode 100644 index 565f89c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/sim/tb_sdram_ctrl_frontend.wdo +++ /dev/null @@ -1,45 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/addr -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/busy -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/en -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/r_wn -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/din -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/be -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/dout_vld -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/dout_reg -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/clk_out -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cs_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_we_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_ras_n -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/part_cas_n -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_ba -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/part_dm -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_addr -add wave -noupdate -format Literal -radix hexadecimal /tb_sdram_ctrl_frontend/part_data -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_busy -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/u_cmd_we -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl -add wave -noupdate -format Literal /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_cmd/st_sdr -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/inst_sdram_ctrl/inst_sdram_ctrl/sdr_cmd_busy -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/cat_fifo_full -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/write_fifo_full -add wave -noupdate -format Logic /tb_sdram_ctrl_frontend/inst_sdram_ctrl_frontend/read_fifo_full -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 4} {27951315 ps} 0} -configure wave -namecolwidth 172 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {42 us} diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd deleted file mode 100644 index c924c8c..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/clockgen_virtex4.vhd +++ /dev/null @@ -1,240 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Clock generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee, work; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clockgen is - generic - ( - read_phaseshift : integer := 0; - frequency_hz : integer := 100E6 - ); - port - ( - -- Clocks and Reset - rst : in std_logic; -- external async reset, low active - clk_in : in std_logic; -- system clock (e.g. 100MHz), from board - clk_fb_in : in std_logic; -- feedback clock - read_clk0_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 0° - read_clk270_out : out std_logic; -- Clock for DDR-SDRAM data capture, dcm#1 output 270° - sys_clk0_out : out std_logic; -- System clock, dcm#0 output 0° - sys_clk270_out : out std_logic; -- System clock, dcm#0 output 270° - locked_out : out std_logic; -- DCM locked status - error_out : out std_logic -- indicates DCM Errors - ); - -end; - -architecture tech of clockgen is - - constant CLKIN_PER : real := real(1000E6/frequency_hz); - - signal locked : unsigned(1 downto 0); - signal dcm_rst : unsigned(1 downto 0); - signal read_clk0 : std_logic; - signal read_clk270 : std_logic; - signal read_clk0_bufg : std_logic; - signal read_clk270_bufg : std_logic; - signal sys_clk0 : std_logic; - signal sys_clk270 : std_logic; - signal sys_clk0_bufg : std_logic; - signal sys_clk270_bufg : std_logic; - signal dcm1_locked, dcm2_locked : unsigned(2 downto 0); - signal cnt_q : unsigned(4 downto 0); - - type STATE_TYPE is (s0, s1, s2, s3, s4); - signal state_q : STATE_TYPE; - -begin - - read_clk0_out <= read_clk0_bufg; - read_clk270_out <= read_clk270_bufg; - sys_clk0_out <= sys_clk0_bufg; - sys_clk270_out <= sys_clk270_bufg; - -bufg11: bufg - port map - ( - o => sys_clk0_bufg, - i => sys_clk0 - ); - -bufg12: bufg - port map ( - o => sys_clk270_bufg, - i => sys_clk270 - ); - -bufg13: bufg - port map - ( - o => read_clk0_bufg, - i => read_clk0 - ); - -bufg14: bufg - port map ( - o => read_clk270_bufg, - i => read_clk270 - ); - - ------------------------------------------------------------------------------------------------------- - -- Clock generation - ------------------------------------------------------------------------------------------------------- - -inst_DCM_BASE_0 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => sys_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => sys_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(0), -- DCM LOCK status output - CLKFB => clk_fb_in, -- DCM clock feedback - CLKIN => clk_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(0) -- DCM asynchronous reset input - ); - - inst_DCM_BASE_1 : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => 1, -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => 4, -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => CLKIN_PER, -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "FIXED", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_AUTOCALIBRATION => TRUE, -- DCM calibrartion circuitry TRUE/FALSE - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => read_phaseshift, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => read_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => read_clk270, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => open, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => locked(1), -- DCM LOCK status output - CLKFB => read_clk0_bufg, -- DCM clock feedback - CLKIN => clk_fb_in, -- Clock input (from IBUFG, BUFG or DCM) - RST => dcm_rst(1) -- DCM asynchronous reset input - ); - - dcm_rst(1) <= not locked(0); - -dcm_fsm: - process(rst, clk_in) - begin - if rst = '1' then - state_q <= s0; - dcm_rst(0) <= '0'; - cnt_q <= "11111"; - error_out <= '0'; - locked_out <= '0'; - dcm1_locked <= (others => '0'); - dcm2_locked <= (others => '0'); - elsif rising_edge(clk_in) then - case state_q is - when s0 => - state_q <= s1; - - when s1 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '1'; - state_q <= s2; - end if; - - when s2 => - cnt_q <= cnt_q - 1; - if cnt_q = 0 then - dcm_rst(0) <= '0'; - state_q <= s3; - end if; - - when s3 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - state_q <= s4; - error_out <= '0'; - end if; - - when s4 => - if dcm1_locked(2)='1' and dcm2_locked(2)='1' then - locked_out <= '1'; - else - error_out <= '1'; - end if; - end case; - - -- synchronize 'dcm1_locked' - dcm1_locked <= dcm1_locked(1 downto 0) & locked(0); - dcm2_locked <= dcm2_locked(1 downto 0) & locked(1); - - end if; - end process; - -end architecture tech; - - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd deleted file mode 100644 index 1494c9b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/ddr_phy_virtex4.vhd +++ /dev/null @@ -1,370 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: DDR physical layer (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity ddr_phy is - Port ( - sys_rst : in STD_LOGIC; - sys_clk0 : in STD_LOGIC; - sys_clk270 : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - read_clk : in STD_LOGIC; - phy_ctrl : in phy_ctrl_t; - part_ctrl : in part_ctrl_t; - sdr_data_w : in unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - sdr_data_r : out unsigned(SDR_DATA_WIDTH-1 downto 0); - sdr_data_vld : out STD_LOGIC; - sdr_data_req_w : out STD_LOGIC; - sdr_data_req_r : out STD_LOGIC; - part_clk_p : out STD_LOGIC; - part_clk_n : out STD_LOGIC; - part_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - part_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - part_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0); - part_ba : out unsigned(DDR_BANK_WIDTH-1 downto 0); - part_addr : out unsigned(DDR_ADDR_WIDTH-1 downto 0); - part_cs_n : out STD_LOGIC; - part_we_n : out STD_LOGIC; - part_cas_n : out STD_LOGIC; - part_ras_n : out STD_LOGIC; - part_cke : out STD_LOGIC - ); -end ddr_phy; - -architecture tech of ddr_phy is - - signal dqs_drive : std_logic; - signal drive : std_logic; - signal dqs : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_zen : unsigned(DDR_DQS_WIDTH-1 downto 0); - signal dqs_rst : std_logic; - signal ddr_data_w : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal data_reg_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal drive270 : unsigned(DDR_DATA_WIDTH-1 downto 0); - signal part_ctrl_reg : part_ctrl_t; - signal we_reg : std_logic; - signal read_en : std_logic; - - type u_tag_array_t is array (natural range 0 to 4) of user_tag_t; - signal u_tag_pipe : u_tag_array_t; - -begin - ------------------------------------------------------------------------------------------------------------------------------------------------- -utag_pipe: - process(sys_rst, sys_clk0) - begin - if rising_edge(sys_clk0) then - for i in u_tag_pipe'length-1 downto 1 loop - u_tag_pipe(i) <= u_tag_pipe(i-1); - end loop; - if phy_ctrl.utag_we = '1' then - u_tag_pipe(0) <= u_tag_in; - end if; - end if; - end process; - -WE_REGISTER: - process(sys_rst, sys_clk0) - begin - if sys_rst = '1' then - we_reg <= '0'; - elsif rising_edge(sys_clk0) then - we_reg <= phy_ctrl.we; - end if; - end process; - -DATA_DRIVE_GEN: - process(sys_clk0) - begin - if falling_edge(sys_clk0) then - dqs_rst <= not we_reg; - drive <= we_reg; - end if; - end process; - -DQS_DRIVE_GEN: - process(sys_clk0) - variable p : unsigned(1 downto 0); - begin - if rising_edge(sys_clk0) then - if phy_ctrl.drive_en = '1' then - p := (others => '1'); - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - dqs_drive <= p(p'left); - end process; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- SDRAM Clock -ODDR_clk_p : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_p, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '1', -- 1-bit data input (positive edge) - D2 => '0', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - -ODDR_clk_n : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_clk_n, -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => '0', -- 1-bit data input (positive edge) - D2 => '1', -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data OUT DDR-FFs -gen_ddr_data_out: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - ODDR_data : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => ddr_data_w(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_data_w(n + DDR_DATA_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_data_w(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_data_out; - --- Sample tristate on clock90 - process (sys_clk270) - begin - if rising_edge(sys_clk270) then - for n in 0 to DDR_DATA_WIDTH-1 loop - drive270(n) <= drive; - end loop; - end if; - end process; - --- Output mux -out_mux_data: - for n in 0 to DDR_DATA_WIDTH-1 generate - part_data(n) <= ddr_data_w(n) when drive270(n) = '1' else 'Z'; - end generate; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- Data-mask OUT DDR-FFs -gen_ddr_dm_out: - for n in 0 to DDR_DM_WIDTH-1 generate - begin - ODDR_dm : ODDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => part_dm(n), -- 1-bit DDR output - C => sys_clk270, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D1 => sdr_dm(n + DDR_DM_WIDTH), -- 1-bit data input (positive edge) - D2 => sdr_dm(n), -- 1-bit data input (negative edge) - R => '0', -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_ddr_dm_out; - ------------------------------------------------------------------------------------------------------------------------------------------------- --- DQS OUT DDR-FFs -gen_dqs_out: - for n in 0 to DDR_DQS_WIDTH-1 generate - begin - ODDR_dqs : ODDR - generic map - ( - DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE" - INIT => '0', -- Initial value for Q port ('1' or '0') - SRTYPE => "SYNC" -- Reset Type ("ASYNC" or "SYNC") - ) - port map ( - Q => dqs(n), -- 1-bit DDR output - C => sys_clk0, -- 1-bit clock input - CE => '1', -- 1-bit clock enable input - D2 => '0', -- 1-bit data input (positive edge) - D1 => '1', -- 1-bit data input (negative edge) - R => dqs_rst, -- 1-bit reset input - S => '0' -- 1-bit set input - ); - end generate gen_dqs_out; - --- Tristate-Control fuer dqs - process (sys_clk0) is - variable zctrl : boolean; - begin - if rising_edge(sys_clk0) then - if dqs_drive = '1' then - zctrl := false; - else - zctrl := true; - end if; - if zctrl then - dqs_zen <= (others => '1'); - else - dqs_zen <= (others => '0'); - end if; - end if; - end process; - --- Tristate-Buffer fuer dqs -gen_out_mux_dqs: - for n in 0 to DDR_DQS_WIDTH-1 generate - part_dqs(n) <= 'Z' when dqs_zen(n)='1' else dqs(n); - end generate gen_out_mux_dqs; - ------------------------------------------------------------------------------------------------------------------------------------------------- - process (sys_rst, sys_clk0) is - begin - if sys_rst = '1' then - part_ctrl_reg.cmd <= COMMAND(SD_DESELECT); - part_ctrl_reg.ba <= (others=>'0'); - part_ctrl_reg.addr <= (others=>'0'); - part_ctrl_reg.cke <= '0'; - elsif rising_edge(sys_clk0) then - part_ctrl_reg <= part_ctrl; - end if; - end process; - - process (sys_clk0) is - begin - if falling_edge(sys_clk0) then - part_ras_n <= part_ctrl_reg.cmd.ras_n; - part_cas_n <= part_ctrl_reg.cmd.cas_n; - part_we_n <= part_ctrl_reg.cmd.we_n; - part_cs_n <= part_ctrl_reg.cmd.cs_n; - part_ba <= part_ctrl_reg.ba; - part_addr <= part_ctrl_reg.addr; - part_cke <= part_ctrl_reg.cke; - end if; - end process; - ------------------------------------------------------------------ --- READ DATA Processing ------------------------------------------------------------------ -gen_ddr_data_in: - for n in 0 to DDR_DATA_WIDTH-1 generate - begin - IDDR_data : IDDR - generic map - ( - DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" or "SAME_EDGE_PIPELINED" - INIT_Q1 => '0', -- Initial value of Q1: '0' or '1' - INIT_Q2 => '0', -- Initial value of Q2: '0' or '1' - SRTYPE => "SYNC" -- Set/Reset type: "SYNC" or "ASYNC" - ) - port map - ( - Q1 => data_r(n), -- 1-bit output for positive edge of clock - Q2 => data_r(n + DDR_DATA_WIDTH), -- 1-bit output for negative edge of clock - C => read_clk, -- 1-bit clock input - CE => read_en, -- 1-bit clock enable input - D => part_data(n), -- 1-bit DDR data input - R => '0', -- 1-bit reset - S => '0' -- 1-bit set - ); - end generate; - - -data_sample_stage: - process (sys_clk0) - begin - if falling_edge(sys_clk0) then - data_reg_r <= data_r; - end if; - end process; - -misc_flags_and_data_out: - process (sys_rst, sys_clk0) - variable p : unsigned(3 downto 0); - begin - if sys_rst = '1' then - p := (others => '0'); - read_en <= '0'; - sdr_data_vld <= '0'; - sdr_data_req_w <= '0'; - sdr_data_req_r <= '0'; - elsif rising_edge(sys_clk0) then - sdr_data_r <= data_reg_r; - if p(3) = '1' then - u_tag_rd <= u_tag_pipe(4); - end if; - if phy_ctrl.we = '1' then - u_tag_wr <= u_tag_pipe(0); - end if; - sdr_data_req_w <= phy_ctrl.we; - sdr_data_req_r <= phy_ctrl.re; - sdr_data_vld <= p(3); - read_en <= p(1); - if phy_ctrl.re = '1' then - p := p(p'left-1 downto 0) & '1'; - else - p := p(p'left-1 downto 0) & '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd deleted file mode 100644 index 79ce51f..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/fifo_sync.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.fifo_ctrl_pkg.all; - -entity fifo_sync is - Generic ( - addr_width : natural := 4; - data_width : natural := 8; - almost_full_thresh : integer := 12; - almost_empty_thresh : integer := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - we : in STD_LOGIC; - re : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - data_w : in unsigned (data_width-1 downto 0); - data_r : out unsigned (data_width-1 downto 0) - ); -end fifo_sync; - -architecture Behavioral of fifo_sync is - - signal mem_we : STD_LOGIC; - signal ptr_w : unsigned (addr_width-1 downto 0); - signal ptr_r : unsigned (addr_width-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - -begin - - mem_we <= we; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - - inst_sync_fifo_ctrl: entity work.sync_fifo_ctrl - GENERIC MAP - ( - addr_width => addr_width, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk => clk, - we => we, - re => re, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - - inst_dpram_1w1r: entity work.dpram_1w1r_dist - GENERIC MAP ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk, - clkb => clk, - en_a => '1', - en_b => '1', - we_a => mem_we, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => data_w, - dout_b => data_r - ); - -end Behavioral; - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd deleted file mode 100644 index 356bb28..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/mt46v16m16.vhd +++ /dev/null @@ -1,1320 +0,0 @@ ------------------------------------------------------------------------------------------ --- --- File Name: MT46V16M16.VHD --- Version: 2.1 --- Date: January 14th, 2002 --- Model: Behavioral --- Simulator: NCDesktop - http://www.cadence.com --- ModelSim PE - http://www.model.com --- --- Dependencies: None --- --- Author: Son P. Huynh --- Email: sphuynh@micron.com --- Phone: (208) 368-3825 --- Company: Micron Technology, Inc. --- Part Number: MT46V16M16 (4 Mb x 16 x 4 Banks) --- --- Description: Micron 256 Mb SDRAM DDR (Double Data Rate) --- --- Limitation: Doesn't model internal refresh counter --- --- Note: --- --- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY --- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR --- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT. --- --- Copyright (c) 1998 Micron Semiconductor Products, Inc. --- All rights researved --- --- Rev Author Date Changes --- --- ---------------------------- ---------- ------------------------------------- --- 2.1 Son P. Huynh 01/14/2002 - Fix Burst_counter --- Micron Technology, Inc. --- --- 2.0 Son P. Huynh 11/08/2001 - Second release --- Micron Technology, Inc. - Rewrote and remove SHARED VARIABLE --- ------------------------------------------------------------------------------------------ - -LIBRARY IEEE; - USE IEEE.STD_LOGIC_1164.ALL; - USE IEEE.STD_LOGIC_UNSIGNED.ALL; - USE IEEE.STD_LOGIC_ARITH.ALL; - -ENTITY MT46V16M16 IS - GENERIC ( -- Timing for -75Z CL2 - tCK : TIME := 7.500 ns; - tCH : TIME := 3.375 ns; -- 0.45*tCK - tCL : TIME := 3.375 ns; -- 0.45*tCK - tDH : TIME := 0.500 ns; - tDS : TIME := 0.500 ns; - tIH : TIME := 0.900 ns; - tIS : TIME := 0.900 ns; - tMRD : TIME := 15.000 ns; - tRAS : TIME := 40.000 ns; - tRAP : TIME := 20.000 ns; - tRC : TIME := 65.000 ns; - tRFC : TIME := 75.000 ns; - tRCD : TIME := 20.000 ns; - tRP : TIME := 20.000 ns; - tRRD : TIME := 15.000 ns; - tWR : TIME := 15.000 ns; - addr_bits : INTEGER := 13; - data_bits : INTEGER := 16; - cols_bits : INTEGER := 9 - ); - PORT ( - Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - Dqs : INOUT STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - Ba : IN STD_LOGIC_VECTOR (1 DOWNTO 0); - Clk : IN STD_LOGIC; - Clk_n : IN STD_LOGIC; - Cke : IN STD_LOGIC; - Cs_n : IN STD_LOGIC; - Ras_n : IN STD_LOGIC; - Cas_n : IN STD_LOGIC; - We_n : IN STD_LOGIC; - Dm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) - ); -END MT46V16M16; - -ARCHITECTURE behave OF MT46V16M16 IS - -- Array for Read pipeline - TYPE Array_Read_cmnd IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Read_bank IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Read_cols IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Write pipeline - TYPE Array_Write_cmnd IS ARRAY (2 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_bank IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Write_cols IS ARRAY (2 DOWNTO 0) OF STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Array for Auto Precharge - TYPE Array_Read_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Write_precharge IS ARRAY (3 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Count_precharge IS ARRAY (3 DOWNTO 0) OF INTEGER; - - -- Array for Manual Precharge - TYPE Array_A10_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - TYPE Array_Bank_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC_VECTOR (1 DOWNTO 0); - TYPE Array_Cmnd_precharge IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Burst Terminate - TYPE Array_Cmnd_bst IS ARRAY (8 DOWNTO 0) OF STD_LOGIC; - - -- Array for Memory Access - TYPE Array_ram_type IS ARRAY (2**cols_bits - 1 DOWNTO 0) OF STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - TYPE Array_ram_pntr IS ACCESS Array_ram_type; - TYPE Array_ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF Array_ram_pntr; - - -- Data pair - SIGNAL Dq_pair : STD_LOGIC_VECTOR (2 * data_bits - 1 DOWNTO 0); - SIGNAL Dm_pair : STD_LOGIC_VECTOR (3 DOWNTO 0); - - -- Mode Register - SIGNAL Mode_reg : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); - - -- Command Decode Variables - SIGNAL Active_enable, Aref_enable, Burst_term, Ext_mode_enable : STD_LOGIC := '0'; - SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : STD_LOGIC := '0'; - - -- Burst Length Decode Variables - SIGNAL Burst_length_2, Burst_length_4, Burst_length_8, Burst_length_f : STD_LOGIC := '0'; - - -- Cas Latency Decode Variables - SIGNAL Cas_latency_15, Cas_latency_2, Cas_latency_25, Cas_latency_3, Cas_latency_4 : STD_LOGIC := '0'; - - -- Internal Control Signals - SIGNAL Cs_in, Ras_in, Cas_in, We_in : STD_LOGIC := '0'; - - -- System Clock - SIGNAL Sys_clk : STD_LOGIC := '0'; - - -- Dqs buffer - SIGNAL Dqs_out : STD_LOGIC_VECTOR (1 DOWNTO 0) := "ZZ"; - -BEGIN - -- Strip the strength - Cs_in <= To_X01 (Cs_n); - Ras_in <= To_X01 (Ras_n); - Cas_in <= To_X01 (Cas_n); - We_in <= To_X01 (We_n); - - -- Commands Decode - Active_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND We_in; - Aref_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND We_in; - Burst_term <= NOT(Cs_in) AND Ras_in AND Cas_in AND NOT(We_in); - Ext_mode_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND Ba(0) AND NOT(Ba(1)); - Mode_reg_enable <= NOT(Cs_in) AND NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in) AND NOT(Ba(0)) AND NOT(Ba(1)); - Prech_enable <= NOT(Cs_in) AND NOT(Ras_in) AND Cas_in AND NOT(We_in); - Read_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND We_in; - Write_enable <= NOT(Cs_in) AND Ras_in AND NOT(Cas_in) AND NOT(We_in); - - -- Burst Length Decode - Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0); - Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0)); - Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - Burst_length_f <= (Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0); - - -- CAS Latency Decode - Cas_latency_15 <= Mode_reg(6) AND NOT(Mode_reg(5)) AND (Mode_reg(4)); - Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_25 <= Mode_reg(6) AND Mode_reg(5) AND NOT(Mode_reg(4)); - Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4); - Cas_latency_4 <= (Mode_reg(6)) AND NOT(Mode_reg(5)) AND NOT(Mode_reg(4)); - - -- Dqs buffer - Dqs <= Dqs_out; - - -- - -- System Clock - -- - int_clk : PROCESS (Clk, Clk_n) - VARIABLE ClkZ, CkeZ : STD_LOGIC := '0'; - begin - IF Clk = '1' AND Clk_n = '0' THEN - ClkZ := '1'; - CkeZ := Cke; - ELSIF Clk = '0' AND Clk_n = '1' THEN - ClkZ := '0'; - END IF; - Sys_clk <= CkeZ AND ClkZ; - END PROCESS; - - -- - -- Main Process - -- - state_register : PROCESS - -- Precharge Variables - VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : STD_LOGIC := '0'; - - -- Activate Variables - VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : STD_LOGIC := '1'; - - -- Data IO variables - VARIABLE Data_in_enable, Data_out_enable : STD_LOGIC := '0'; - - -- Internal address mux variables - VARIABLE Cols_brst : STD_LOGIC_VECTOR (2 DOWNTO 0); - VARIABLE Prev_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Bank_addr : STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"; - VARIABLE Cols_addr : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - VARIABLE Rows_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B0_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B1_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B2_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - VARIABLE B3_row_addr : STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0); - - -- DLL Reset variables - VARIABLE DLL_enable : STD_LOGIC := '0'; - VARIABLE DLL_reset : STD_LOGIC := '0'; - VARIABLE DLL_done : STD_LOGIC := '0'; - VARIABLE DLL_count : INTEGER := 0; - - -- Timing Check - VARIABLE MRD_chk : TIME := 0 ns; - VARIABLE RFC_chk : TIME := 0 ns; - VARIABLE RRD_chk : TIME := 0 ns; - VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns; - VARIABLE RAP_chk0, RAP_chk1, RAP_chk2, RAP_chk3 : TIME := 0 ns; - VARIABLE RC_chk0, RC_chk1, RC_chk2, RC_chk3 : TIME := 0 ns; - VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns; - VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns; - VARIABLE WR_chk0, WR_chk1, WR_chk2, WR_chk3 : TIME := 0 ns; - - -- Read pipeline variables - VARIABLE Read_cmnd : Array_Read_cmnd; - VARIABLE Read_bank : Array_Read_bank; - VARIABLE Read_cols : Array_Read_cols; - - -- Write pipeline variables - VARIABLE Write_cmnd : Array_Write_cmnd; - VARIABLE Write_bank : Array_Write_bank; - VARIABLE Write_cols : Array_Write_cols; - - -- Auto Precharge variables - VARIABLE Read_precharge : Array_Read_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Write_precharge : Array_Write_precharge := ('0' & '0' & '0' & '0'); - VARIABLE Count_precharge : Array_Count_precharge := ( 0 & 0 & 0 & 0 ); - - -- Manual Precharge variables - VARIABLE A10_precharge : Array_A10_precharge; - VARIABLE Bank_precharge : Array_Bank_precharge; - VARIABLE Cmnd_precharge : Array_Cmnd_precharge; - - -- Burst Terminate variable - VARIABLE Cmnd_bst : Array_Cmnd_bst; - - -- Memory Banks - VARIABLE Bank0 : Array_ram_stor; - VARIABLE Bank1 : Array_ram_stor; - VARIABLE Bank2 : Array_ram_stor; - VARIABLE Bank3 : Array_ram_stor; - - -- Burst Counter - VARIABLE Burst_counter : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0); - - -- Internal Dqs initialize - VARIABLE Dqs_int : STD_LOGIC := '0'; - - -- Data buffer for DM Mask - VARIABLE Data_buf : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z'); - - -- - -- Initialize empty rows - -- - PROCEDURE Init_mem (Bank : STD_LOGIC_VECTOR; Row_index : INTEGER) IS - VARIABLE i, j : INTEGER := 0; - BEGIN - IF Bank = "00" THEN - IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty - Bank0 (Row_index) := NEW Array_ram_type; -- Open new row for access - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank0 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "01" THEN - IF Bank1 (Row_index) = NULL THEN - Bank1 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank1 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "10" THEN - IF Bank2 (Row_index) = NULL THEN - Bank2 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank2 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - ELSIF Bank = "11" THEN - IF Bank3 (Row_index) = NULL THEN - Bank3 (Row_index) := NEW Array_ram_type; - FOR i IN (2**cols_bits - 1) DOWNTO 0 LOOP - FOR j IN (data_bits - 1) DOWNTO 0 LOOP - Bank3 (Row_index) (i) (j) := '0'; - END LOOP; - END LOOP; - END IF; - END IF; - END; - - -- - -- Burst Counter - -- - PROCEDURE Burst_decode IS - VARIABLE Cols_temp : STD_LOGIC_VECTOR (cols_bits - 1 DOWNTO 0) := (OTHERS => '0'); - BEGIN - -- Advance burst counter - Burst_counter := Burst_counter + 1; - - -- Burst Type - IF Mode_reg (3) = '0' THEN - Cols_temp := Cols_addr + 1; - ELSIF Mode_reg (3) = '1' THEN - Cols_temp (2) := Burst_counter (2) XOR Cols_brst (2); - Cols_temp (1) := Burst_counter (1) XOR Cols_brst (1); - Cols_temp (0) := Burst_counter (0) XOR Cols_brst (0); - END IF; - - -- Burst Length - IF Burst_length_2 = '1' THEN - Cols_addr (0) := Cols_temp (0); - ELSIF Burst_length_4 = '1' THEN - Cols_addr (1 DOWNTO 0) := Cols_temp (1 DOWNTO 0); - ELSIF Burst_length_8 = '1' THEN - Cols_addr (2 DOWNTO 0) := Cols_temp (2 DOWNTO 0); - ELSE - Cols_addr := Cols_temp; - END IF; - - -- Data counter - IF Burst_length_2 = '1' THEN - IF Burst_counter >= 2 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_4 = '1' THEN - IF Burst_counter >= 4 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - ELSIF Burst_length_8 = '1' THEN - IF Burst_counter >= 8 THEN - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - ELSIF Data_out_enable = '1' THEN - Data_out_enable := '0'; - END IF; - END IF; - END IF; - END; - - BEGIN - WAIT ON Sys_clk; - - -- - -- Manual Precharge Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- A10 Precharge Pipeline - A10_precharge(0) := A10_precharge(1); - A10_precharge(1) := A10_precharge(2); - A10_precharge(2) := A10_precharge(3); - A10_precharge(3) := A10_precharge(4); - A10_precharge(4) := A10_precharge(5); - A10_precharge(5) := A10_precharge(6); - A10_precharge(6) := A10_precharge(7); - A10_precharge(7) := A10_precharge(8); - A10_precharge(8) := '0'; - - -- Bank Precharge Pipeline - Bank_precharge(0) := Bank_precharge(1); - Bank_precharge(1) := Bank_precharge(2); - Bank_precharge(2) := Bank_precharge(3); - Bank_precharge(3) := Bank_precharge(4); - Bank_precharge(4) := Bank_precharge(5); - Bank_precharge(5) := Bank_precharge(6); - Bank_precharge(6) := Bank_precharge(7); - Bank_precharge(7) := Bank_precharge(8); - Bank_precharge(8) := "00"; - - -- Command Precharge Pipeline - Cmnd_precharge(0) := Cmnd_precharge(1); - Cmnd_precharge(1) := Cmnd_precharge(2); - Cmnd_precharge(2) := Cmnd_precharge(3); - Cmnd_precharge(3) := Cmnd_precharge(4); - Cmnd_precharge(4) := Cmnd_precharge(5); - Cmnd_precharge(5) := Cmnd_precharge(6); - Cmnd_precharge(6) := Cmnd_precharge(7); - Cmnd_precharge(7) := Cmnd_precharge(8); - Cmnd_precharge(8) := '0'; - - -- Terminate Read if same bank or all banks - IF ((Cmnd_precharge (0) = '1') AND - (Bank_precharge (0) = Bank_addr OR A10_precharge (0) = '1') AND - (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Burst Terminate Pipeline - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Burst Terminate pipeline - Cmnd_bst (0) := Cmnd_bst (1); - Cmnd_bst (1) := Cmnd_bst (2); - Cmnd_bst (2) := Cmnd_bst (3); - Cmnd_bst (3) := Cmnd_bst (4); - Cmnd_bst (4) := Cmnd_bst (5); - Cmnd_bst (5) := Cmnd_bst (6); - Cmnd_bst (6) := Cmnd_bst (7); - Cmnd_bst (7) := Cmnd_bst (8); - Cmnd_bst (8) := '0'; - - -- Terminate current Read - IF ((Cmnd_bst (0) = '1') AND (Data_out_enable = '1')) THEN - Data_out_enable := '0'; - END IF; - END IF; - - -- - -- Dq and Dqs Drivers - -- - IF ((Sys_clk'EVENT AND Sys_clk = '0') OR (Sys_clk'EVENT AND Sys_clk = '1')) THEN - -- Read Command Pipeline - Read_cmnd (0) := Read_cmnd (1); - Read_cmnd (1) := Read_cmnd (2); - Read_cmnd (2) := Read_cmnd (3); - Read_cmnd (3) := Read_cmnd (4); - Read_cmnd (4) := Read_cmnd (5); - Read_cmnd (5) := Read_cmnd (6); - Read_cmnd (6) := Read_cmnd (7); - Read_cmnd (7) := Read_cmnd (8); - Read_cmnd (8) := '0'; - - -- Read Bank Pipeline - Read_bank (0) := Read_bank (1); - Read_bank (1) := Read_bank (2); - Read_bank (2) := Read_bank (3); - Read_bank (3) := Read_bank (4); - Read_bank (4) := Read_bank (5); - Read_bank (5) := Read_bank (6); - Read_bank (6) := Read_bank (7); - Read_bank (7) := Read_bank (8); - Read_bank (8) := "00"; - - -- Read Column Pipeline - Read_cols (0) := Read_cols (1); - Read_cols (1) := Read_cols (2); - Read_cols (2) := Read_cols (3); - Read_cols (3) := Read_cols (4); - Read_cols (4) := Read_cols (5); - Read_cols (5) := Read_cols (6); - Read_cols (6) := Read_cols (7); - Read_cols (7) := Read_cols (8); - Read_cols (8) := (OTHERS => '0'); - - -- Initialize Read command - IF Read_cmnd (0) = '1' THEN - Data_out_enable := '1'; - Bank_addr := Read_bank (0); - Cols_addr := Read_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Toggle Dqs during Read command - IF Data_out_enable = '1' THEN - Dqs_int := '0'; - IF Dqs_out = "00" THEN - Dqs_out <= "11"; - ELSIF Dqs_out = "11" THEN - Dqs_out <= "00"; - ELSE - Dqs_out <= "00"; - END IF; - ELSIF Data_out_enable = '0' AND Dqs_int = '0' THEN - Dqs_out <= "ZZ"; - END IF; - - -- Initialize Dqs for Read command - IF Read_cmnd (2) = '1' THEN - IF Data_out_enable = '0' THEN - Dqs_int := '1'; - Dqs_out <= "00"; - END IF; - END IF; - - -- Read Latch - IF Data_out_enable = '1' THEN - -- Initialize Memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Output Data - CASE Bank_addr IS - WHEN "00" => Dq <= Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Dq <= Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Dq <= Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Dq <= Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Increase Burst Counter - Burst_decode; - ELSE - Dq <= (OTHERS => 'Z'); - END IF; - END IF; - - -- - -- Write FIFO and DM Mask Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Write command pipeline - Write_cmnd (0) := Write_cmnd (1); - Write_cmnd (1) := Write_cmnd (2); - Write_cmnd (2) := '0'; - - -- Write command pipeline - Write_bank (0) := Write_bank (1); - Write_bank (1) := Write_bank (2); - Write_bank (2) := "00"; - - -- Write column pipeline - Write_cols (0) := Write_cols (1); - Write_cols (1) := Write_cols (2); - Write_cols (2) := (OTHERS => '0'); - - -- Initialize Write command - IF Write_cmnd (0) = '1' THEN - Data_in_enable := '1'; - Bank_addr := Write_bank (0); - Cols_addr := Write_cols (0); - Cols_brst := Cols_addr (2 DOWNTO 0); - Burst_counter := (OTHERS => '0'); - - -- Row address mux - CASE Bank_addr IS - WHEN "00" => Rows_addr := B0_row_addr; - WHEN "01" => Rows_addr := B1_row_addr; - WHEN "10" => Rows_addr := B2_row_addr; - WHEN OTHERS => Rows_addr := B3_row_addr; - END CASE; - END IF; - - -- Write data - IF Data_in_enable = '1' THEN - -- Initialize memory - Init_mem (Bank_addr, CONV_INTEGER(Rows_addr)); - - -- Write first data - IF Dm_pair (1) = '0' OR Dm_pair (0) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (0) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair ( 7 DOWNTO 0); - END IF; - IF Dm_pair (1) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (15 DOWNTO 8); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- Write second data - IF Dm_pair (3) = '0' OR Dm_pair (2) = '0' THEN - -- Data Buffer - CASE Bank_addr IS - WHEN "00" => Data_buf := Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "01" => Data_buf := Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN "10" => Data_buf := Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - WHEN OTHERS => Data_buf := Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)); - END CASE; - - -- Perform DM Mask - IF Dm_pair (2) = '0' THEN - Data_buf ( 7 DOWNTO 0) := Dq_pair (23 DOWNTO 16); - END IF; - IF Dm_pair (3) = '0' THEN - Data_buf (15 DOWNTO 8) := Dq_pair (31 DOWNTO 24); - END IF; - - -- Write Data - CASE Bank_addr IS - WHEN "00" => Bank0 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "01" => Bank1 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN "10" => Bank2 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - WHEN OTHERS => Bank3 (CONV_INTEGER(Rows_addr)) (CONV_INTEGER(Cols_addr)) := Data_buf; - END CASE; - END IF; - - -- Increase Burst Counter - Burst_decode; - - -- tWR start and tWTR check - IF Dm_pair (3 DOWNTO 2) = "00" OR Dm_pair (1 DOWNTO 0) = "00" THEN - CASE Bank_addr IS - WHEN "00" => WR_chk0 := NOW; - WHEN "01" => WR_chk1 := NOW; - WHEN "10" => WR_chk2 := NOW; - WHEN OTHERS => WR_chk3 := NOW; - END CASE; - - -- tWTR check - ASSERT (Read_enable = '0') - REPORT "tWTR violation during Read" - SEVERITY WARNING; - END IF; - END IF; - END IF; - - -- - -- Auto Precharge Calculation - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Precharge counter - IF Read_precharge (0) = '1' OR Write_precharge (0) = '1' THEN - Count_precharge (0) := Count_precharge (0) + 1; - END IF; - IF Read_precharge (1) = '1' OR Write_precharge (1) = '1' THEN - Count_precharge (1) := Count_precharge (1) + 1; - END IF; - IF Read_precharge (2) = '1' OR Write_precharge (2) = '1' THEN - Count_precharge (2) := Count_precharge (2) + 1; - END IF; - IF Read_precharge (3) = '1' OR Write_precharge (3) = '1' THEN - Count_precharge (3) := Count_precharge (3) + 1; - END IF; - - -- Read with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. BL/2 cycles after command - IF ((Read_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(0) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(0) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(0) >= 4)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW; - Read_precharge(0) := '0'; - END IF; - END IF; - IF ((Read_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(1) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(1) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(1) >= 4)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW; - Read_precharge(1) := '0'; - END IF; - END IF; - IF ((Read_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(2) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(2) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(2) >= 4)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW; - Read_precharge(2) := '0'; - END IF; - END IF; - IF ((Read_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge(3) >= 1) OR - (Burst_length_4 = '1' AND Count_precharge(3) >= 2) OR - (Burst_length_8 = '1' AND Count_precharge(3) >= 4)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW; - Read_precharge(3) := '0'; - END IF; - END IF; - - -- Write with AutoPrecharge Calculation - -- The device start internal precharge when: - -- 1. Meet tRAS requirement - -- 2. Two clock after last burst - -- Since tWR is time base, the model will compensate tRP - IF ((Write_precharge(0) = '1') AND (NOW - RAS_chk0 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (0) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (0) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (0) >= 7)) THEN - Pc_b0 := '1'; - Act_b0 := '0'; - RP_chk0 := NOW - ((2 * tCK) - tWR); - Write_precharge(0) := '0'; - END IF; - END IF; - IF ((Write_precharge(1) = '1') AND (NOW - RAS_chk1 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (1) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (1) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (1) >= 7)) THEN - Pc_b1 := '1'; - Act_b1 := '0'; - RP_chk1 := NOW - ((2 * tCK) - tWR); - Write_precharge(1) := '0'; - END IF; - END IF; - IF ((Write_precharge(2) = '1') AND (NOW - RAS_chk2 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (2) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (2) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (2) >= 7)) THEN - Pc_b2 := '1'; - Act_b2 := '0'; - RP_chk2 := NOW - ((2 * tCK) - tWR); - Write_precharge(2) := '0'; - END IF; - END IF; - IF ((Write_precharge(3) = '1') AND (NOW - RAS_chk3 >= tRAS)) THEN - IF ((Burst_length_2 = '1' AND Count_precharge (3) >= 4) OR - (Burst_length_4 = '1' AND Count_precharge (3) >= 5) OR - (Burst_length_8 = '1' AND Count_precharge (3) >= 7)) THEN - Pc_b3 := '1'; - Act_b3 := '0'; - RP_chk3 := NOW - ((2 * tCK) - tWR); - Write_precharge(3) := '0'; - END IF; - END IF; - END IF; - - -- - -- DLL Counter - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - IF (DLL_Reset = '1' AND DLL_done = '0') THEN - DLL_count := DLL_count + 1; - IF (DLL_count >= 200) THEN - DLL_done := '1'; - END IF; - END IF; - END IF; - - -- - -- Control Logic - -- - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - -- Auto Refresh - IF Aref_enable = '1' THEN - -- Auto Refresh to Auto Refresh - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Auto Refresh" - SEVERITY WARNING; - - -- Precharge to Auto Refresh - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All banks must be Precharge before Auto Refresh" - SEVERITY WARNING; - - -- Record current tRFC time - RFC_chk := NOW; - END IF; - - -- Extended Load Mode Register - IF Ext_mode_enable = '1' THEN - IF (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') THEN - IF (Addr (0) = '0') THEN - DLL_enable := '1'; - ELSE - DLL_enable := '0'; - END IF; - END IF; - - -- Precharge to EMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Extended Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Extended Load Register" - SEVERITY WARNING; - - -- LMR/EMR to EMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Extended Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Load Mode Register - IF Mode_reg_enable = '1' THEN - -- Register mode - Mode_reg <= Addr; - - -- DLL Reset - IF (DLL_enable = '1' AND Addr (8) = '1') THEN - DLL_reset := '1'; - DLL_done := '0'; - DLL_count := 0; - ELSIF (DLL_enable = '1' AND DLL_reset = '0' AND Addr (8) = '0') THEN - ASSERT (FALSE) - REPORT "DLL is ENABLE: DLL RESET is require" - SEVERITY WARNING; - ELSIF (DLL_enable = '0' AND Addr (8) = '1') THEN - ASSERT (FALSE) - REPORT "DLL is DISABLE: DLL RESET will be ignored" - SEVERITY WARNING; - END IF; - - -- Precharge to LMR - ASSERT (Pc_b0 = '1' AND Pc_b1 = '1' AND Pc_b2 = '1' AND Pc_b3 = '1') - REPORT "All bank must be Precharged before Load Mode Register" - SEVERITY WARNING; - - -- Precharge to EMR - ASSERT ((NOW - RP_chk0 >= tRP) AND (NOW - RP_chk1 >= tRP) AND - (NOW - RP_chk2 >= tRP) AND (NOW - RP_chk3 >= tRP)) - REPORT "tRP violation during Load Mode Register" - SEVERITY WARNING; - - -- LMR/ELMR to LMR - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid Burst Length - ASSERT ((Addr (2 DOWNTO 0) = "001") OR -- BL = 2 - (Addr (2 DOWNTO 0) = "010") OR -- BL = 4 - (Addr (2 DOWNTO 0) = "011")) -- BL = 8 - REPORT "Invalid Burst Length during Load Mode Register" - SEVERITY WARNING; - - -- Check for invalid CAS Latency - ASSERT ((Addr (6 DOWNTO 4) = "010") OR -- CL = 2.0 - (Addr (6 DOWNTO 4) = "110")) -- CL = 2.5 - REPORT "Invalid CAS Latency during Load Mode Register" - SEVERITY WARNING; - - -- Record current tMRD time - MRD_chk := NOW; - END IF; - - -- Active Block (latch Bank and Row Address) - IF Active_enable = '1' THEN - -- Activate an OPEN bank can corrupt data - ASSERT ((Ba = "00" AND Act_b0 = '0') OR - (Ba = "01" AND Act_b1 = '0') OR - (Ba = "10" AND Act_b2 = '0') OR - (Ba = "11" AND Act_b3 = '0')) - REPORT "Bank is already activated - data can be corrupted" - SEVERITY WARNING; - - -- Activate Bank 0 - IF Ba = "00" AND Pc_b0 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk0 >= tRC) - REPORT "tRC violation during Activate Bank 0" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk0 >= tRP) - REPORT "tRP violation during Activate Bank 0" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b0 := '1'; - Pc_b0 := '0'; - B0_row_addr := Addr; - RC_chk0 := NOW; - RCD_chk0 := NOW; - RAS_chk0 := NOW; - RAP_chk0 := NOW; - END IF; - - -- Activate Bank 1 - IF Ba = "01" AND Pc_b1 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk1 >= tRC) - REPORT "tRC violation during Activate Bank 1" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk1 >= tRP) - REPORT "tRP violation during Activate Bank 1" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b1 := '1'; - Pc_b1 := '0'; - B1_row_addr := Addr; - RC_chk1 := NOW; - RCD_chk1 := NOW; - RAS_chk1 := NOW; - RAP_chk1 := NOW; - END IF; - - -- Activate Bank 2 - IF Ba = "10" AND Pc_b2 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk2 >= tRC) - REPORT "tRC violation during Activate Bank 2" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk2 >= tRP) - REPORT "tRP violation during Activate Bank 2" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b2 := '1'; - Pc_b2 := '0'; - B2_row_addr := Addr; - RC_chk2 := NOW; - RCD_chk2 := NOW; - RAS_chk2 := NOW; - RAP_chk2 := NOW; - END IF; - - -- Activate Bank 3 - IF Ba = "11" AND Pc_b3 = '1' THEN - -- Activate to Activate (same bank) - ASSERT (NOW - RC_chk3 >= tRC) - REPORT "tRC violation during Activate Bank 3" - SEVERITY WARNING; - - -- Precharge to Active - ASSERT (NOW - RP_chk3 >= tRP) - REPORT "tRP violation during Activate Bank 3" - SEVERITY WARNING; - - -- Record Variables for checking violation - Act_b3 := '1'; - Pc_b3 := '0'; - B3_row_addr := Addr; - RC_chk3 := NOW; - RCD_chk3 := NOW; - RAS_chk3 := NOW; - RAP_chk3 := NOW; - END IF; - - -- Activate Bank A to Activate Bank B - IF (Prev_bank /= Ba) THEN - ASSERT (NOW - RRD_chk >= tRRD) - REPORT "tRRD violation during Activate" - SEVERITY WARNING; - END IF; - - -- AutoRefresh to Activate - ASSERT (NOW - RFC_chk >= tRFC) - REPORT "tRFC violation during Activate" - SEVERITY WARNING; - - -- Record Variables for Checking Violation - RRD_chk := NOW; - Prev_bank := Ba; - END IF; - - -- Precharge Block - Consider NOP if bank already precharged or in process of precharging - IF Prech_enable = '1' THEN - -- EMR or LMR to Precharge - ASSERT (NOW - MRD_chk >= tMRD) - REPORT "tMRD violation during Precharge" - SEVERITY WARNING; - - -- Precharge Bank 0 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "00")) AND Act_b0 = '1') THEN - Act_b0 := '0'; - Pc_b0 := '1'; - RP_chk0 := NOW; - - -- Activate to Precharge bank 0 - ASSERT (NOW - RAS_chk0 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk0 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 1 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "01")) AND Act_b1 = '1') THEN - Act_b1 := '0'; - Pc_b1 := '1'; - RP_chk1 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk1 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk1 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 2 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "10")) AND Act_b2 = '1') THEN - Act_b2 := '0'; - Pc_b2 := '1'; - RP_chk2 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk2 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk2 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Precharge Bank 3 - IF ((Addr (10) = '1' OR (Addr (10) = '0' AND Ba = "11")) AND Act_b3 = '1') THEN - Act_b3 := '0'; - Pc_b3 := '1'; - RP_chk3 := NOW; - - -- Activate to Precharge - ASSERT (NOW - RAS_chk3 >= tRAS) - REPORT "tRAS violation during Precharge" - SEVERITY WARNING; - - -- tWR violation check for Write - ASSERT (NOW - WR_chk3 >= tWR) - REPORT "tWR violation during Precharge" - SEVERITY WARNING; - END IF; - - -- Pipeline for READ - IF CAS_latency_15 = '1' THEN - A10_precharge (3) := Addr(10); - Bank_precharge (3) := Ba; - Cmnd_precharge (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - A10_precharge (4) := Addr(10); - Bank_precharge (4) := Ba; - Cmnd_precharge (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - A10_precharge (5) := Addr(10); - Bank_precharge (5) := Ba; - Cmnd_precharge (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - A10_precharge (6) := Addr(10); - Bank_precharge (6) := Ba; - Cmnd_precharge (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - A10_precharge (8) := Addr(10); - Bank_precharge (8) := Ba; - Cmnd_precharge (8) := '1'; - END IF; - END IF; - - -- Burst Terminate - IF Burst_term = '1' THEN - -- Pipeline for Read - IF CAS_latency_15 = '1' THEN - Cmnd_bst (3) := '1'; - ELSIF CAS_latency_2 = '1' THEN - Cmnd_bst (4) := '1'; - ELSIF CAS_latency_25 = '1' THEN - Cmnd_bst (5) := '1'; - ELSIF CAS_latency_3 = '1' THEN - Cmnd_bst (6) := '1'; - ELSIF CAS_latency_4 = '1' THEN - Cmnd_bst (8) := '1'; - END IF; - - -- Terminate Write - ASSERT (Data_in_enable = '0') - REPORT "It's illegal to Burst Terminate a Write" - SEVERITY WARNING; - - -- Terminate Read with Auto Precharge - ASSERT (Read_precharge (0) = '0' AND Read_precharge (1) = '0' AND - Read_precharge (2) = '0' AND Read_precharge (3) = '0') - REPORT "It's illegal to Burst Terminate a Read with Auto Precharge" - SEVERITY WARNING; - END IF; - - -- Read Command - IF Read_enable = '1' THEN - -- CAS Latency Pipeline - IF Cas_latency_15 = '1' THEN - Read_cmnd (3) := '1'; - Read_bank (3) := Ba; - Read_cols (3) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_2 = '1' THEN - Read_cmnd (4) := '1'; - Read_bank (4) := Ba; - Read_cols (4) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_25 = '1' THEN - Read_cmnd (5) := '1'; - Read_bank (5) := Ba; - Read_cols (5) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_3 = '1' THEN - Read_cmnd (6) := '1'; - Read_bank (6) := Ba; - Read_cols (6) := Addr (8 DOWNTO 0); - ELSIF Cas_latency_4 = '1' THEN - Read_cmnd (8) := '1'; - Read_bank (8) := Ba; - Read_cols (8) := Addr (8 DOWNTO 0); - END IF; - - -- Write to Read: Terminate Write Immediately - IF Data_in_enable = '1' THEN - Data_in_enable := '0'; - END IF; - - -- Interrupting a Read with Auto Precharge (same bank only) - ASSERT (Read_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Read with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Read - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Read" - SEVERITY WARNING; - - -- Activate to Read without Auto Precharge - IF Addr (10) = '0' THEN - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Read" - SEVERITY WARNING; - END IF; - - -- Activate to Read with Auto Precharge - IF Addr (10) = '1' THEN - ASSERT ((Ba = "00" AND NOW - RAP_chk0 >= tRAP) OR - (Ba = "01" AND NOW - RAP_chk1 >= tRAP) OR - (Ba = "10" AND NOW - RAP_chk2 >= tRAP) OR - (Ba = "11" AND NOW - RAP_chk3 >= tRAP)) - REPORT "tRAP violation during Read" - SEVERITY WARNING; - END IF; - - -- Auto precharge - IF Addr (10) = '1' THEN - Read_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - - -- DLL Check - IF (DLL_reset = '1') THEN - ASSERT (DLL_done = '1') - REPORT "DLL RESET not complete" - SEVERITY WARNING; - END IF; - END IF; - - -- Write Command - IF Write_enable = '1' THEN - -- Pipeline for Write - Write_cmnd (2) := '1'; - Write_bank (2) := Ba; - Write_cols (2) := Addr (8 DOWNTO 0); - - -- Interrupting a Write with Auto Precharge (same bank only) - ASSERT (Write_precharge(CONV_INTEGER(Ba)) = '0') - REPORT "It's illegal to interrupt a Write with Auto Precharge" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND Act_b0 = '1') OR - (Ba = "01" AND Act_b1 = '1') OR - (Ba = "10" AND Act_b2 = '1') OR - (Ba = "11" AND Act_b3 = '1')) - REPORT "Bank is not Activated for Write" - SEVERITY WARNING; - - -- Activate to Write - ASSERT ((Ba = "00" AND NOW - RCD_chk0 >= tRCD) OR - (Ba = "01" AND NOW - RCD_chk1 >= tRCD) OR - (Ba = "10" AND NOW - RCD_chk2 >= tRCD) OR - (Ba = "11" AND NOW - RCD_chk3 >= tRCD)) - REPORT "tRCD violation during Write" - SEVERITY WARNING; - - -- Auto precharge - IF Addr (10) = '1' THEN - Write_precharge (Conv_INTEGER(Ba)) := '1'; - Count_precharge (Conv_INTEGER(Ba)) := 0; - END IF; - END IF; - END IF; - END PROCESS; - - -- - -- Dqs Receiver - -- - dqs_rcvrs : PROCESS - VARIABLE Dm_temp : STD_LOGIC_VECTOR (1 DOWNTO 0); - VARIABLE Dq_temp : STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0); - BEGIN - WAIT ON Dqs; - -- Latch data at posedge Dqs - IF Dqs'EVENT AND Dqs (1) = '1' AND Dqs (0) = '1' THEN - Dq_temp := Dq; - Dm_temp := Dm; - END IF; - -- Latch data at negedge Dqs - IF Dqs'EVENT AND Dqs (1) = '0' AND Dqs (0) = '0' THEN - Dq_pair <= (Dq & Dq_temp); - Dm_pair <= (Dm & Dm_temp); - END IF; - END PROCESS; - - -- - -- Setup timing checks - -- - Setup_check : PROCESS - BEGIN - WAIT ON Sys_clk; - IF Sys_clk'EVENT AND Sys_clk = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIS) - REPORT "CKE Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIS) - REPORT "CS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIS) - REPORT "CAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIS) - REPORT "RAS# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIS) - REPORT "WE# Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIS) - REPORT "ADDR Setup time violation -- tIS" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIS) - REPORT "BA Setup time violation -- tIS" - SEVERITY WARNING; - END IF; - END PROCESS; - - -- - -- Hold timing checks - -- - Hold_check : PROCESS - BEGIN - WAIT ON Sys_clk'DELAYED (tIH); - IF Sys_clk'DELAYED (tIH) = '1' THEN - ASSERT(Cke'LAST_EVENT >= tIH) - REPORT "CKE Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cs_n'LAST_EVENT >= tIH) - REPORT "CS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Cas_n'LAST_EVENT >= tIH) - REPORT "CAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ras_n'LAST_EVENT >= tIH) - REPORT "RAS# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(We_n'LAST_EVENT >= tIH) - REPORT "WE# Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Addr'LAST_EVENT >= tIH) - REPORT "ADDR Hold time violation -- tIH" - SEVERITY WARNING; - ASSERT(Ba'LAST_EVENT >= tIH) - REPORT "BA Hold time violation -- tIH" - SEVERITY WARNING; - END IF; - END PROCESS; - -END behave; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd deleted file mode 100644 index 4f799c5..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/reset_virtex4.vhd +++ /dev/null @@ -1,111 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Reset generator (Virtex-4 specific) --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; - -Library UNISIM; -use UNISIM.vcomponents.all; - -entity reset is - port - ( - clk : in std_logic; - rst_in : in std_logic; - rst_out : out std_logic - ); -end; - -architecture tech of reset is - - signal rst : std_logic; - signal shift_pipe : std_logic_vector(3 downto 0); - attribute KEEP : string; - attribute KEEP of shift_pipe : signal is "TRUE"; - -begin - - rst <= shift_pipe(0); - -bufg_reset: bufg - port map - ( - o => rst_out, - i => rst - ); - -fdp0: fdp - generic map - ( - init => '1' - ) - port map - ( - d => rst_in, - c => clk, - pre => '0', - q => shift_pipe(3) - ); - -fdp1: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(3), - c => clk, - pre => '0', - q => shift_pipe(2) - ); - -fdp2: fdp - generic map - ( - init => '1' - ) - port map - ( - d => shift_pipe(2), - c => clk, - pre => '0', - q => shift_pipe(1) - ); - -fdp3: fdp - generic map - ( - init => '1' - ) - port map - ( - - d => shift_pipe(1), - c => clk, - pre => '0', - q => shift_pipe(0) - ); - -end tech; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd deleted file mode 100644 index a50b6e8..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_cmd.vhd +++ /dev/null @@ -1,269 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM command controller --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_cmd is - Generic (BL : natural := 2); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - enable : in STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - phy_ctrl : out phy_ctrl_t; - cmd : in sdr_cmd_t; - cmd_we : in STD_LOGIC; - cmd_ack : out STD_LOGIC; - col_addr : in col_addr_t; - mode_word : in mode_word_t; - sdr_cmd_ctrl : out sdr_cmd_lines_t; - sdr_addr : out sdr_addr_t; - sdr_ba : out sdr_ba_t - ); -end sdram_cmd; - -architecture behaviour of sdram_cmd is - - signal st_sdr, st_sdr_next : sdr_state_t; - - signal cc_preset : natural range 0 to 10; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal burst_preset : natural range 0 to 3; - signal burst_load_en : std_logic; - signal burst_finished : std_logic; - -begin - - u_tag_out <= u_tag_in; - ------------------------------------------------------------------------------------------- - -fsm_sdr_state: - process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr) - begin - st_sdr_next <= st_sdr; - sdr_cmd_ctrl <= COMMAND(SD_NOP); - - cc_load_en <= '0'; - cc_preset <= TIMING(cmd); - burst_load_en <= '0'; - cmd_ack <= '0'; - burst_preset <= BL/2-1; - phy_ctrl.re <= '0'; - phy_ctrl.drive_en <= '0'; - phy_ctrl.we <= '0'; - phy_ctrl.utag_we <= '0'; - sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right); - sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1); - - case st_sdr is - when PWR_DOWN => - sdr_cmd_ctrl <= COMMAND(SD_DESELECT); - if enable = '1' then - st_sdr_next <= IDLE; - end if; - - when PRECHARGE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when MODE => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when IDLE => - if cmd_we = '1' then - cmd_ack <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL); - when SD_LMR => - st_sdr_next <= MODE; - when SD_ACT => - st_sdr_next <= ROW_ACT; - when SD_AR => - st_sdr_next <= AUTO_REF; - when others => null; - end case; - end if; - - when ROW_ACT => - if cycle_finished = '1' then - if cmd_we = '1' then - cmd_ack <= '1'; - burst_load_en <= '1'; - cc_load_en <= '1'; - cc_preset <= TIMING(cmd); - sdr_cmd_ctrl <= COMMAND(cmd); - case cmd is - when SD_PRE => - st_sdr_next <= PRECHARGE; - when SD_READ => - phy_ctrl.utag_we <= '1'; - st_sdr_next <= READ; - sdr_addr(col_addr_t'range) <= col_addr; - when SD_WRITE => - phy_ctrl.utag_we <= '1'; - phy_ctrl.drive_en <= '1'; - st_sdr_next <= WRITE; - sdr_addr(col_addr_t'range) <= col_addr; - when others => null; - end case; - end if; - end if; - - when WRITE => - phy_ctrl.drive_en <= '1'; - phy_ctrl.we <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_WRITE then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - phy_ctrl.drive_en <= '0'; - cc_load_en <= '1'; - cc_preset <= TIMING(SD_WRITE)+1; - st_sdr_next <= ROW_ACT; - end if; - end if; - - when READ => - phy_ctrl.re <= '1'; - if burst_finished = '1' then - if cmd_we = '1' and cmd = SD_READ then - sdr_addr(col_addr_t'range) <= col_addr; - cmd_ack <= '1'; - burst_load_en <= '1'; - sdr_cmd_ctrl <= COMMAND(cmd); - phy_ctrl.utag_we <= '1'; - else - cc_load_en <= '1'; - cc_preset <= TIMING(SD_READ); - st_sdr_next <= ROW_ACT; - end if; - end if; - - when WRITE_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when READ_A => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when BURST_STOP => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when SELF_REF => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when PRE_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when ACT_PWR_DOWN => -- not implemented yet - cmd_ack <= '1'; - st_sdr_next <= IDLE; - - when AUTO_REF => - if cycle_finished = '1' then - st_sdr_next <= IDLE; - end if; - - when others => - st_sdr_next <= IDLE; - end case; - - end process; - -fsm_sdr_state_next: - process (rst, clk) - begin - if rst = '1' then - st_sdr <= PWR_DOWN; - elsif rising_edge(clk) then - st_sdr <= st_sdr_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - variable cycle_cnt : natural range 0 to 10; - begin - if rst = '1' then - cycle_cnt := 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt := cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt := cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -burst_counter: - process (rst, clk) - variable burst_cnt : natural range 0 to 3; - begin - if rst = '1' then - burst_cnt := 0; - elsif rising_edge(clk) then - burst_finished <= '0'; - if burst_load_en = '1' then - burst_cnt := burst_preset; - elsif burst_cnt /= 0 then - burst_cnt := burst_cnt - 1; - end if; - if burst_cnt = 0 then - burst_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd deleted file mode 100644 index b62e085..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_config.vhd +++ /dev/null @@ -1,74 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: User SDRAM component adjustments --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -package sdram_config is - - constant DDR_DATA_WIDTH : positive := 16; -- External DDR-SDRAM Module data bus width - constant DDR_ADDR_WIDTH : positive := 13; -- number of address lines to DDR-SDRAM Device/Module - constant DDR_BANK_WIDTH : positive := 2; -- Number of BANK address lines of external DDR-SDRAM - constant DDR_ROW_ADDR_WIDTH : positive := 13; -- - constant DDR_COL_ADDR_WIDTH : positive := 9; -- - - constant LMR_REG_BASE : natural := 0; - constant LMR_REG_EXTENDED : natural := 1; - constant LMR_OP_NORMAL : natural := 0; - constant LMR_OP_RES_DLL : natural := 2; - constant LMR_BT_SEQ : natural := 0; - constant LMR_BT_ILVD : natural := 1; - constant LMR_BL2 : natural := 1; - constant LMR_BL4 : natural := 2; - constant LMR_BL8 : natural := 3; - constant LMR_CL2 : natural := 2; - constant LMR_CL3 : natural := 3; - constant LMR_CL2_5 : natural := 6; - - -- DDR SDRAM Hardware defined constants - constant BIT_AUTO_PRE : positive := 10; -- bit-position in column address for auto precharge (see Data Sheet) - constant BIT_PRE_ALL : positive := 10; -- bit-position in column address for precharge all (see Data Sheet) - constant ENABLE_PRE_ALL : std_logic := '1'; - constant ENABLE_AUTO_PRE : std_logic := '0'; - - -- DDR-SDR TIMING constants ------------------------------------------------------------------ - -- After REFRESH_CLOCKS a refresh cycle is necessary, 64ms / 8192 = max every 7.8125 us refesh - constant REFRESH_INTERVAL : real := 7.8125; -- us - - -- These values are for your SDRAM part (see datasheet) - constant TCAS : positive := 2; -- CAS latency [clocks] - constant TRP : positive := 2; -- precharge command period - constant TRAS : positive := 4; -- active to precharge delay - constant TRFC : positive := 8; -- auto refresh command period - constant TMRD : positive := 2; -- load mode register command cylce time - constant TRCD : positive := 2; -- active to read or write delay ! - constant TWR : positive := 2; -- write recovery time - - constant PWR_UP_WAIT : natural := 1; -- µs - - subtype user_tag_t is unsigned(3 downto 0); - - ---------------------------------------------------------------------------------------------- - -end sdram_config; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd deleted file mode 100644 index dbb5b80..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl.vhd +++ /dev/null @@ -1,487 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: SDRAM main controller and user I/F --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity sdram_ctrl is - Generic - ( - f_sysclk : natural := 100E6; - BL : natural := 2 - ); - Port ( - rst : in STD_LOGIC; - clk : in STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_out : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - col_addr : out col_addr_t; - sdr_cmd_busy : in STD_LOGIC; - sdr_cmd : out sdr_cmd_t; - sdr_cmd_we : out STD_LOGIC; - sdr_mode : out mode_word_t; - sdr_cke : out STD_LOGIC - ); -end sdram_ctrl; - -architecture behaviour of sdram_ctrl is - - constant LMR_BURST_LEN : natural := NextExpBaseTwo(BL); - - type ctrl_state_t is (RESET, POWER_WAIT, INIT, INIT_WAIT, USER_READY, USER_WRITE_PRE, USER_WRITE_ACT, USER_WRITE, USER_READ_PRE, USER_READ_ACT, USER_READ, REFRESH); - signal st_ctrl, st_ctrl_next : ctrl_state_t; - - constant PWR_UP_CLOCK_INTERVAL : natural := PWR_UP_WAIT*(f_sysclk/1E6); - signal pwr_up_cnt : natural range 0 to PWR_UP_CLOCK_INTERVAL-1; - signal pwr_up_cnt_rst : std_logic; - signal pwr_up_finished : std_logic; - - signal cycle_cnt : natural range 0 to 255; - signal cc_preset : natural range 0 to 255; - signal cc_load_en : std_logic; - signal cycle_finished : std_logic; - - signal seq_cnt : natural range 0 to 31; - signal seq_rst_en : std_logic; - signal seq_cnt_en : std_logic; - - constant REFRESH_CLOCK_INTERVAL : natural := natural(REFRESH_INTERVAL*real(f_sysclk)/1.0E6); - signal refresh_cnt : natural range 0 to REFRESH_CLOCK_INTERVAL-1; - signal refresh_request : std_logic; - signal refresh_cnt_rst : std_logic; - - signal addr_reg_load_en : std_logic; - - signal u_tag_reg : user_tag_t; - signal bank_addr_reg : bank_addr_t; - signal row_addr_reg : row_addr_t; - signal col_addr_reg : col_addr_t; - - signal u_bank_addr : bank_addr_t; - signal u_row_addr : row_addr_t; - signal u_col_addr : col_addr_t; - - signal act_request : std_logic; - signal act_request_set : std_logic; - signal act_request_clr : std_logic; - - type init_seq_rom_t is array (0 to 14) of init_seq_t; - - constant init_seq_rom : init_seq_rom_t := - ( - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_EXTENDED, 2) & "0000000000010", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_RES_DLL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_PRE, - mode_word => "000010000000000", - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_AR, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ), - ( - cmd => SD_LMR, - mode_word => to_unsigned(LMR_REG_BASE, 2) & to_unsigned(LMR_OP_NORMAL, 6) & to_unsigned(LMR_CL2, 3) & '0' & to_unsigned(LMR_BURST_LEN, 3), - wait_cycle => 200 - ), - ( - cmd => SD_NOP, - mode_word => (others => '0'), - wait_cycle => 0 - ) - - ); - -begin - - u_row_addr <= u_addr(user_addr_t'left downto user_addr_t'left-row_addr_t'length+1); - u_bank_addr <= u_addr(user_addr_t'left-row_addr_t'length downto user_addr_t'left-row_addr_t'length-bank_addr_t'length+1); - u_col_addr <= u_addr(user_addr_t'left-row_addr_t'length-bank_addr_t'length downto 0); - ------------------------------------------------------------------------------------------- -fsm_ctrl_state: - process (st_ctrl, u_tag_in, u_tag_reg, u_cmd, u_cmd_we, sdr_cmd_busy, pwr_up_finished, seq_cnt, cycle_finished, u_bank_addr, u_row_addr, bank_addr_reg, row_addr_reg, u_col_addr, col_addr_reg, refresh_request, act_request) - begin - - u_busy <= '1'; - pwr_up_cnt_rst <= '0'; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - cc_load_en <= '0'; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - sdr_cmd_we <= '0'; - sdr_mode <= bank_addr_reg & row_addr_reg; - col_addr <= col_addr_reg; - sdr_cke <= '1'; - seq_cnt_en <= '0'; - seq_rst_en <= '0'; - addr_reg_load_en <= '0'; - refresh_cnt_rst <= '0'; - act_request_set <= '0'; - act_request_clr <= '0'; - u_tag_out <= u_tag_reg; - - st_ctrl_next <= st_ctrl; - case st_ctrl is - when RESET => - sdr_cke <= '0'; - pwr_up_cnt_rst <= '1'; - st_ctrl_next <= POWER_WAIT; - - when POWER_WAIT => - sdr_cke <= '0'; - if pwr_up_finished = '1' then - seq_rst_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when INIT => - sdr_mode <= init_seq_rom(seq_cnt).mode_word; - sdr_cmd <= init_seq_rom(seq_cnt).cmd; - cc_preset <= init_seq_rom(seq_cnt).wait_cycle; - if seq_cnt = init_seq_rom_t'high then - act_request_set <= '1'; - refresh_cnt_rst <= '1'; - st_ctrl_next <= USER_READY; - elsif sdr_cmd_busy = '0' then - cc_load_en <= '1'; - sdr_cmd_we <= '1'; - st_ctrl_next <= INIT_WAIT; - end if; - - when INIT_WAIT => - if sdr_cmd_busy = '0' and cycle_finished = '1' then - seq_cnt_en <= '1'; - st_ctrl_next <= INIT; - end if; - - when USER_READY => - if sdr_cmd_busy = '0' then - if refresh_request = '1' then - sdr_mode(BIT_PRE_ALL) <= '1'; - sdr_cmd_we <= '1'; - sdr_cmd <= SD_PRE; - st_ctrl_next <= REFRESH; - else - u_busy <= '0'; - if u_cmd_we = '1' then - case u_cmd is - when UCMD_NOP => - sdr_cmd <= SD_NOP; - when UCMD_LMR => - sdr_cmd <= SD_NOP; - when UCMD_WRITE => - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - addr_reg_load_en <= '1'; - act_request_clr <= '1'; - sdr_cmd <= SD_WRITE; - if (u_row_addr /= row_addr_reg) or act_request = '1' then - st_ctrl_next <= USER_WRITE_PRE; - elsif (u_bank_addr /= bank_addr_reg) then - if ENABLE_PRE_ALL = '1' then - st_ctrl_next <= USER_WRITE_ACT; - else - st_ctrl_next <= USER_WRITE_PRE; - end if; - elsif sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - else - st_ctrl_next <= USER_WRITE; - end if; - when UCMD_READ => - col_addr <= u_col_addr; - u_tag_out <= u_tag_in; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - addr_reg_load_en <= '1'; - act_request_clr <= '1'; - sdr_cmd <= SD_READ; - if (u_row_addr /= row_addr_reg) or act_request = '1' then - st_ctrl_next <= USER_READ_PRE; - elsif (u_bank_addr /= bank_addr_reg) then - if ENABLE_PRE_ALL = '1' then - st_ctrl_next <= USER_READ_ACT; - else - st_ctrl_next <= USER_READ_PRE; - end if; - elsif sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - else - st_ctrl_next <= USER_READ; - end if; - when others => null; - end case; - end if; - end if; - end if; - - when USER_WRITE_PRE => - sdr_cmd <= SD_PRE; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE_ACT; - end if; - - when USER_WRITE_ACT => - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_WRITE; - end if; - - when USER_WRITE => - sdr_cmd <= SD_WRITE; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when USER_READ_PRE => - sdr_cmd <= SD_PRE; - sdr_mode(BIT_PRE_ALL) <= ENABLE_PRE_ALL; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ_ACT; - end if; - - when USER_READ_ACT => - sdr_cmd <= SD_ACT; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READ; - end if; - - when USER_READ => - sdr_cmd <= SD_READ; - sdr_mode(BIT_AUTO_PRE) <= ENABLE_AUTO_PRE; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - end if; - - when REFRESH => - sdr_cmd <= SD_AR; - if sdr_cmd_busy = '0' then - sdr_cmd_we <= '1'; - st_ctrl_next <= USER_READY; - refresh_cnt_rst <= '1'; - act_request_set <= '1'; - end if; - - when others => - st_ctrl_next <= RESET; - end case; - - end process; - -fsm_ctrl_state_next: - process (rst, clk) - begin - if rst = '1' then - st_ctrl <= RESET; - elsif rising_edge(clk) then - st_ctrl <= st_ctrl_next; - end if; - end process; - ------------------------------------------------------------------------------------------- -act_request_register: - process (rst, clk) - begin - if rst = '1' then - act_request <= '1'; - elsif rising_edge(clk) then - if act_request_set = '1' then - act_request <= '1'; - elsif act_request_clr = '1' then - act_request <= '0'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -user_addr_register: - process (rst, clk) - begin - if rst = '1' then - bank_addr_reg <= (others => '0'); - row_addr_reg <= (others => '0'); - col_addr_reg <= (others => '0'); - u_tag_reg <= (others => '0'); - elsif rising_edge(clk) then - if addr_reg_load_en = '1' then - bank_addr_reg <= u_bank_addr; - row_addr_reg <= u_row_addr; - col_addr_reg <= u_col_addr; - u_tag_reg <= u_tag_in; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -power_up_counter: - process (rst, clk) - begin - if rst = '1' then - pwr_up_cnt <= 0; - pwr_up_finished <= '0'; - elsif rising_edge(clk) then - pwr_up_finished <= '0'; - if pwr_up_cnt_rst = '1' then - pwr_up_cnt <= PWR_UP_CLOCK_INTERVAL-1; - else - if pwr_up_cnt /= 0 then - pwr_up_cnt <= pwr_up_cnt - 1; - else - pwr_up_finished <= '1'; - end if; - end if; - end if; - end process; - - ------------------------------------------------------------------------------------------- -refresh_counter: - process (rst, clk) - begin - if rst = '1' then - refresh_cnt <= 0; - refresh_request <= '0'; - elsif rising_edge(clk) then - refresh_request <= '0'; - if refresh_cnt_rst = '1' then - refresh_cnt <= REFRESH_CLOCK_INTERVAL-1; - else - if refresh_cnt /= 0 then - refresh_cnt <= refresh_cnt - 1; - else - refresh_request <= '1'; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -cycle_counter: - process (rst, clk) - begin - if rst = '1' then - cycle_cnt <= 0; - cycle_finished <= '0'; - elsif rising_edge(clk) then - cycle_finished <= '0'; - if cc_load_en = '1' then - cycle_cnt <= cc_preset; - elsif cycle_cnt /= 0 then - cycle_cnt <= cycle_cnt - 1; - else - cycle_finished <= '1'; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -seq_counter: - process (rst, clk) - begin - if rst = '1' then - seq_cnt <= 0; - elsif rising_edge(clk) then - if seq_rst_en = '1' then - seq_cnt <= 0; - elsif seq_cnt_en = '1' then - if seq_cnt /= init_seq_rom_t'high then - seq_cnt <= seq_cnt + 1; - end if; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- -end behaviour; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd deleted file mode 100644 index 98dea2a..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_frontend.vhd +++ /dev/null @@ -1,277 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_frontend is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - read_phaseshift : integer := 0; - fifo_depth : integer := 4 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; - sys_clk_fb : in STD_LOGIC; - - -- User interface - busy : out STD_LOGIC; - en : in STD_LOGIC; - r_wn : in STD_LOGIC; - be : in unsigned(SDR_DM_WIDTH-1 downto 0); - addr : in user_addr_t; - din : in unsigned(SDR_DATA_WIDTH-1 downto 0); - dout : out unsigned(SDR_DATA_WIDTH-1 downto 0); - dout_re : in STD_LOGIC; - dout_vld : out STD_LOGIC; - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_frontend; - -architecture struct of sdram_ctrl_frontend is - - -- Number of user data words for simulation - signal rst_out : std_logic; - signal clk_out : std_logic; - - signal u_addr : user_addr_t; - signal u_tag_in : user_tag_t; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t; - signal u_cmd_we : std_logic; - signal u_busy : std_logic; - signal u_data_w : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_dm : unsigned(SDR_DM_WIDTH-1 downto 0); - signal u_data_r : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - - constant CAT_FIFO_WIDTH : integer := user_cmd_t'length + user_tag_t'length + DDR_ROW_ADDR_WIDTH + DDR_BANK_WIDTH + DDR_COL_ADDR_WIDTH; - signal cat_fifo_din : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_dout : unsigned(CAT_FIFO_WIDTH-1 downto 0); - signal cat_fifo_re : std_logic; - signal cat_fifo_we : std_logic; - signal cat_fifo_full : std_logic; - signal cat_fifo_empty : std_logic; --- signal cat_fifo_almost_full : std_logic; --- signal cat_fifo_almost_empty : std_logic; - - signal write_fifo_din : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_dout : unsigned(SDR_DATA_WIDTH+SDR_DM_WIDTH-1 downto 0); - signal write_fifo_re : std_logic; - signal write_fifo_we : std_logic; - signal write_fifo_full : std_logic; - signal write_fifo_empty : std_logic; --- signal write_fifo_almost_full : std_logic; --- signal write_fifo_almost_empty : std_logic; - - signal read_fifo_din : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_dout : unsigned(SDR_DATA_WIDTH-1 downto 0); - signal read_fifo_re : std_logic; - signal read_fifo_we : std_logic; - signal read_fifo_full : std_logic; - signal read_fifo_empty : std_logic; --- signal read_fifo_almost_full : std_logic; --- signal read_fifo_almost_empty : std_logic; - - alias cmd_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_in is cat_fifo_din(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - alias cmd_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-1 downto CAT_FIFO_WIDTH-user_cmd_t'length); - alias tag_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-1 downto CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length); - alias addr_fifo_out is cat_fifo_dout(CAT_FIFO_WIDTH-user_cmd_t'length-user_tag_t'length-1 downto 0); - alias write_fifo_dm_in is write_fifo_din(write_fifo_din'length-1 downto write_fifo_din'length-SDR_DM_WIDTH); - alias write_fifo_data_in is write_fifo_din(write_fifo_din'length-SDR_DM_WIDTH-1 downto 0); - alias write_fifo_dm_out is write_fifo_dout(write_fifo_dout'length-1 downto write_fifo_dout'length-SDR_DM_WIDTH); - alias write_fifo_data_out is write_fifo_dout(write_fifo_dout'length-SDR_DM_WIDTH-1 downto 0); - -begin - - -- Instantiate synchronous FIFO - inst_cat_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => CAT_FIFO_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => cat_fifo_we, - re => cat_fifo_re, - fifo_full => cat_fifo_full, - fifo_empty => cat_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cat_fifo_din, - data_r => cat_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH + SDR_DM_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => fifo_depth, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BL, - read_phaseshift => read_phaseshift, - f_sysclk => f_sysclk - ) - Port map - ( - - sys_rst_in => sys_rst_in, - sys_clk_in => sys_clk_in, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => sys_clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => open, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => sd_clk_p, - sd_clk_n => sd_clk_n, - sd_cke => sd_cke, - sd_cs_n => sd_cs_n, - sd_cas_n => sd_cas_n, - sd_ras_n => sd_ras_n, - sd_we_n => sd_we_n, - sd_addr => sd_addr, - sd_ba => sd_ba, - sd_dm => sd_dm, - sd_dqs => sd_dqs, - sd_data => sd_data - - ); - ------------------------------------------------------------------------------------------- - sys_rst_out <= rst_out; - sys_clk_out <= clk_out; - - busy <= cat_fifo_full or write_fifo_full or read_fifo_full; - write_fifo_we <= en and not r_wn and not write_fifo_full and not cat_fifo_full and not read_fifo_full; - write_fifo_data_in <= din; - write_fifo_dm_in <= not be; - cat_fifo_we <= en and not cat_fifo_full and not write_fifo_full and not read_fifo_full; - cmd_fifo_in <= UCMD_WRITE when r_wn = '0' else UCMD_READ; - addr_fifo_in <= addr; - tag_fifo_in <= (others=>'0'); - dout <= read_fifo_dout; - dout_vld <= not read_fifo_empty; - - u_cmd_we <= (not cat_fifo_empty) and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - u_dm <= write_fifo_dm_out; - u_tag_in <= tag_fifo_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cat_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_data_out; - read_fifo_re <= (not read_fifo_empty) and dout_re; - read_fifo_we <= u_data_vld; - read_fifo_din <= u_data_r; - - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd deleted file mode 100644 index ba9ee71..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_ctrl_top.vhd +++ /dev/null @@ -1,285 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Top-level put all together --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; - -entity sdram_ctrl_top is - Generic - ( - BL : natural := 2; - f_sysclk : natural := 100E6; - read_phaseshift : integer := 0 - ); - Port - ( - sys_rst_in : in STD_LOGIC; - sys_clk_in : in STD_LOGIC; - sys_rst_out : out STD_LOGIC; - sys_clk_out : out STD_LOGIC; - sys_clk_fb : in STD_LOGIC; - - -- User interface - u_data_vld : out STD_LOGIC; - u_data_req_w : out STD_LOGIC; - u_data_req_r : out STD_LOGIC; - u_busy : out STD_LOGIC; - u_tag_in : in user_tag_t; - u_tag_rd : out user_tag_t; - u_tag_wr : out user_tag_t; - u_addr : in user_addr_t; - u_cmd : in user_cmd_t; - u_cmd_we : in STD_LOGIC; - u_data_wr : in unsigned(SDR_DATA_WIDTH-1 downto 0); - u_dm : in unsigned(SDR_DM_WIDTH-1 downto 0); - u_data_rd : out unsigned(SDR_DATA_WIDTH-1 downto 0); - - -- SDRAM signals - sd_clk_p : out STD_LOGIC; - sd_clk_n : out STD_LOGIC; - sd_cke : out STD_LOGIC; - sd_cs_n : out STD_LOGIC; - sd_cas_n : out STD_LOGIC; - sd_ras_n : out STD_LOGIC; - sd_we_n : out STD_LOGIC; - sd_addr : out sdr_addr_t; - sd_ba : out sdr_ba_t; - sd_dm : out unsigned(DDR_DM_WIDTH-1 downto 0); - sd_dqs : inout unsigned(DDR_DQS_WIDTH-1 downto 0); - sd_data : inout unsigned(DDR_DATA_WIDTH-1 downto 0) - - ); -end sdram_ctrl_top; - -architecture rtl of sdram_ctrl_top is - - signal clk0 : std_logic; - signal clk270 : std_logic; - signal read_clk270 : std_logic; - - signal phy_ctrl : phy_ctrl_t; - - signal u_tag : user_tag_t; - signal sd_cmd_in : sdr_cmd_t; - signal sd_cmd : sdr_cmd_t; - signal sd_cmd_we : std_logic; - signal cmd_ctrl : sdr_cmd_lines_t; - signal cke : std_logic; - signal ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - signal addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - - -- Clock generator - - signal cg_rst : std_logic; - signal cg_read_clk0 : std_logic; - signal cg_read_clk270 : std_logic; - signal cg_sys_clk0 : std_logic; - signal cg_sys_clk270 : std_logic; - signal cg_locked : std_logic; - signal cg_error : std_logic; - signal ctrl_rst : std_logic; - signal part_ctrl : part_ctrl_t; - - -- SD command FIFO - - constant CMD_FIFO_ADDR_WIDTH : positive := 2; - constant CMD_FIFO_DATA_WIDTH : positive := user_tag_t'length + 4 + mode_word_t'length + col_addr_t'length; - signal cmd_fifo_din : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_dout : unsigned(CMD_FIFO_DATA_WIDTH-1 downto 0); - signal cmd_fifo_re : std_logic; - signal cmd_fifo_we : std_logic; - signal cmd_fifo_full : std_logic; - signal cmd_fifo_empty : std_logic; - - alias tag_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_in is cmd_fifo_din(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - - alias tag_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length); - alias cmd_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4); - alias mode_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-1 downto CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length); - alias col_fifo_out is cmd_fifo_dout(CMD_FIFO_DATA_WIDTH-user_tag_t'length-4-mode_word_t'length-1 downto 0); - -begin - - --------------------------------- - clk0 <= cg_sys_clk0; - clk270 <= cg_sys_clk270; - read_clk270 <= cg_read_clk270; - cg_rst <= not cg_locked; - - --------------------------------- - sys_clk_out <= cg_sys_clk0; - sys_rst_out <= ctrl_rst; - - --------------------------------- - part_ctrl.cmd <= cmd_ctrl; - part_ctrl.ba <= ba; - part_ctrl.addr <= addr; - part_ctrl.cke <= cke; - - --------------------------------- - sd_cmd_we <= not cmd_fifo_empty; - cmd_fifo_in <= to_unsigned(sd_cmd_in, 4); - sd_cmd <= sdr_cmd_t(to_integer(cmd_fifo_out)); - - --------------------------------- - inst_reset: entity work.reset - port map - ( - clk => clk0, - rst_in => cg_rst, - rst_out => ctrl_rst - ); - - inst_clockgen : entity work.clockgen - generic map - ( - read_phaseshift => read_phaseshift, - frequency_hz => f_sysclk - ) - port map - ( - rst => sys_rst_in, - clk_in => sys_clk_in, - clk_fb_in => sys_clk_fb, - read_clk0_out => cg_read_clk0, - read_clk270_out => cg_read_clk270, - sys_clk0_out => cg_sys_clk0, - sys_clk270_out => cg_sys_clk270, - locked_out => cg_locked, - error_out => cg_error - ); - - -- Main controller - inst_sdram_ctrl : entity work.sdram_ctrl - Generic map - ( - f_sysclk => 100E6, - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => clk0, - u_busy => u_busy, - u_tag_in => u_tag_in, - u_tag_out => tag_fifo_in, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_addr => u_addr, - sdr_cmd_busy => cmd_fifo_full, - sdr_cmd => sd_cmd_in, - sdr_cmd_we => cmd_fifo_we, - col_addr => col_fifo_in, - sdr_mode => mode_fifo_in, - sdr_cke => cke - ); - - -- Instantiate synchronous FIFO - inst_sd_cmd_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => CMD_FIFO_ADDR_WIDTH, - data_width => CMD_FIFO_DATA_WIDTH, - almost_full_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1), - almost_empty_thresh => 2**(CMD_FIFO_ADDR_WIDTH-1) - ) - PORT MAP - ( - rst => ctrl_rst, - clk => clk0, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => open, - fifo_aempty => open, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- DDR SDRAM command fsm - inst_sdram_cmd : entity work.sdram_cmd - Generic map - ( - BL => BL - ) - Port map - ( - rst => ctrl_rst, - clk => clk0, - u_tag_in => tag_fifo_out, - u_tag_out => u_tag, - phy_ctrl => phy_ctrl, - enable => cke, - cmd => sd_cmd, - cmd_we => sd_cmd_we, - cmd_ack => cmd_fifo_re, - sdr_cmd_ctrl => cmd_ctrl, - col_addr => col_fifo_out, - mode_word => mode_fifo_out, - sdr_ba => ba, - sdr_addr => addr - ); - - -- DDR phy - inst_ddr_phy : entity work.ddr_phy - Port map - ( - sys_rst => ctrl_rst, - sys_clk0 => clk0, - sys_clk270 => clk270, - u_tag_in => u_tag, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - read_clk => read_clk270, - phy_ctrl => phy_ctrl, - part_ctrl => part_ctrl, - sdr_data_req_w => u_data_req_w, - sdr_data_req_r => u_data_req_r, - sdr_data_w => u_data_wr, - sdr_dm => u_dm, - sdr_data_r => u_data_rd, - sdr_data_vld => u_data_vld, - part_clk_p => sd_clk_p, - part_clk_n => sd_clk_n, - part_addr => sd_addr, - part_ba => sd_ba, - part_dm => sd_dm, - part_dqs => sd_dqs, - part_data => sd_data, - part_cs_n => sd_cs_n, - part_we_n => sd_we_n, - part_cas_n => sd_cas_n, - part_ras_n => sd_ras_n, - part_cke => sd_cke - ); - -end architecture rtl; - diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd deleted file mode 100644 index d235d75..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/sdram_types.vhd +++ /dev/null @@ -1,133 +0,0 @@ -------------------------------------------------------------------------- --- Project: SDRAM controller --- This file: Type definitions --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.sdram_config.all; - -package sdram_types is - - ----------------------------------------------------------------------------------------- - -- Table of Timing Parameters as a function of operation - - -- Derived constants from sdram_config - - constant DDR_DQS_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of data strobe lines - constant DDR_DM_WIDTH : positive := DDR_DATA_WIDTH / 8; -- Number of Data Mask Lines - constant SDR_DATA_WIDTH : positive := 2*DDR_DATA_WIDTH; -- - constant SDR_DM_WIDTH : positive := 2*DDR_DM_WIDTH; -- - - subtype user_cmd_t is unsigned(1 downto 0); - constant UCMD_NOP : user_cmd_t := "00"; - constant UCMD_READ : user_cmd_t := "01"; - constant UCMD_WRITE : user_cmd_t := "10"; - constant UCMD_LMR : user_cmd_t := "11"; - - subtype sdr_cmd_t is natural range 0 to 9; - constant SD_DESELECT : sdr_cmd_t := 0; - constant SD_NOP : sdr_cmd_t := 1; - constant SD_LMR : sdr_cmd_t := 2; - constant SD_ACT : sdr_cmd_t := 3; - constant SD_READ : sdr_cmd_t := 4; - constant SD_WRITE : sdr_cmd_t := 5; - constant SD_PRE : sdr_cmd_t := 6; - constant SD_BST : sdr_cmd_t := 7; - constant SD_AR : sdr_cmd_t := 8; - constant SD_SR : sdr_cmd_t := 9; - - type sdr_state_t is (PWR_DOWN, PRECHARGE, MODE, IDLE, ROW_ACT, WRITE, WRITE_A, READ, READ_A, BURST_STOP, SELF_REF, AUTO_REF, PRE_PWR_DOWN, ACT_PWR_DOWN); - subtype user_addr_t is unsigned(DDR_BANK_WIDTH+DDR_ROW_ADDR_WIDTH+DDR_COL_ADDR_WIDTH-1 downto 0); - subtype sdr_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype sdr_ba_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype mode_word_t is unsigned(DDR_ADDR_WIDTH+DDR_BANK_WIDTH-1 downto 0); - - subtype bank_addr_t is unsigned(DDR_BANK_WIDTH-1 downto 0); - subtype row_addr_t is unsigned(DDR_ADDR_WIDTH-1 downto 0); - subtype col_addr_t is unsigned(8 downto 0); - - subtype cycle_cnt_t is natural range 0 to 10; - - type phy_ctrl_t is - record - drive_en : std_logic; - re : std_logic; - we : std_logic; - utag_we : std_logic; - end record phy_ctrl_t; - - type sdr_cmd_lines_t is - record - cs_n : std_logic; - ras_n : std_logic; - cas_n : std_logic; - we_n : std_logic; - end record sdr_cmd_lines_t; - - type part_ctrl_t is - record - cmd : sdr_cmd_lines_t; - ba : unsigned(DDR_BANK_WIDTH-1 downto 0); - addr : unsigned(DDR_ADDR_WIDTH-1 downto 0); - cke : std_logic; - end record part_ctrl_t; - - type part_cmd_array_t is array (sdr_cmd_t) of sdr_cmd_lines_t; - constant COMMAND : part_cmd_array_t := - -- command cs_n ras_qn cas_qn we_qn - ( SD_DESELECT => ( '1', '1', '1', '1'), - SD_NOP => ( '0', '1', '1', '1'), - SD_LMR => ( '0', '0', '0', '0'), - SD_ACT => ( '0', '0', '1', '1'), - SD_READ => ( '0', '1', '0', '1'), - SD_WRITE => ( '0', '1', '0', '0'), - SD_PRE => ( '0', '0', '1', '0'), - SD_BST => ( '0', '1', '1', '0'), - SD_AR => ( '0', '0', '0', '1'), - SD_SR => ( '0', '0', '0', '1') - ); - - type part_timing_array_t is array (sdr_cmd_t) of cycle_cnt_t; - constant TIMING : part_timing_array_t := - -- command cycle_cnt - ( SD_DESELECT => ( 0 ), - SD_NOP => ( 0 ), - SD_LMR => ( TMRD-1 ), - SD_ACT => ( TRCD-1 ), - SD_READ => ( TCAS-1 ), - SD_WRITE => ( TWR-1 ), - SD_PRE => ( TRP-1 ), - SD_BST => ( 0 ), - SD_AR => ( TRFC-1 ), - SD_SR => ( TRFC-1 ) - ); - - type init_seq_t is - record - cmd : sdr_cmd_t; - mode_word : mode_word_t; - wait_cycle : natural; - end record init_seq_t; - -end sdram_types; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd deleted file mode 100644 index cc18253..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl.vhd +++ /dev/null @@ -1,332 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - u_addr_preset <= X"000000"; - u_addr_end <= X"008000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 1 - u_addr_preset <= X"400000"; - u_addr_end <= X"408000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - u_addr_preset <= X"000000"; - u_addr_end <= X"008000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 1 - u_addr_preset <= X"400000"; - u_addr_end <= X"408000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd deleted file mode 100644 index 6a2a9da..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_fifo.vhd +++ /dev/null @@ -1,416 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdr_ctrl_fifo is -end; - -architecture struct of tb_sdr_ctrl_fifo is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - - signal cmd_fifo_din : unsigned(25 downto 0) := (others => '0'); - signal cmd_fifo_dout : unsigned(25 downto 0) := (others => '0'); - signal cmd_fifo_re : std_logic := '0'; - signal cmd_fifo_we : std_logic := '0'; - signal cmd_fifo_full : std_logic := '0'; - signal cmd_fifo_empty : std_logic := '0'; - signal cmd_fifo_almost_full : std_logic := '0'; - signal cmd_fifo_almost_empty : std_logic := '0'; - - signal write_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal write_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal write_fifo_re : std_logic := '0'; - signal write_fifo_we : std_logic := '0'; - signal write_fifo_full : std_logic := '0'; - signal write_fifo_empty : std_logic := '0'; - signal write_fifo_almost_full : std_logic := '0'; - signal write_fifo_almost_empty : std_logic := '0'; - - signal read_fifo_din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal read_fifo_dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal read_fifo_re : std_logic := '0'; - signal read_fifo_we : std_logic := '0'; - signal read_fifo_full : std_logic := '0'; - signal read_fifo_empty : std_logic := '0'; - signal read_fifo_almost_full : std_logic := '0'; - signal read_fifo_almost_empty : std_logic := '0'; - - signal write_start : std_logic := '1'; - signal read_start : std_logic := '1'; - - alias cmd_fifo_in is cmd_fifo_din(25 downto 24); - alias addr_fifo_in is cmd_fifo_din(23 downto 0); - alias cmd_fifo_out is cmd_fifo_dout(25 downto 24); - alias addr_fifo_out is cmd_fifo_dout(23 downto 0); - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- Instantiate synchronous FIFO - inst_command_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2+24 - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => cmd_fifo_we, - re => cmd_fifo_re, - fifo_full => cmd_fifo_full, - fifo_empty => cmd_fifo_empty, - fifo_afull => cmd_fifo_almost_full, - fifo_aempty => cmd_fifo_almost_empty, - data_w => cmd_fifo_din, - data_r => cmd_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_write_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => write_fifo_we, - re => write_fifo_re, - fifo_full => write_fifo_full, - fifo_empty => write_fifo_empty, - fifo_afull => write_fifo_almost_full, - fifo_aempty => write_fifo_almost_empty, - data_w => write_fifo_din, - data_r => write_fifo_dout - ); - - -- Instantiate synchronous FIFO - inst_read_fifo: entity work.fifo_sync - GENERIC MAP - ( - addr_width => 8, - data_width => 2*DDR_DATA_WIDTH - ) - PORT MAP - ( - rst => rst_out, - clk => clk_out, - we => read_fifo_we, - re => read_fifo_re, - fifo_full => read_fifo_full, - fifo_empty => read_fifo_empty, - fifo_afull => read_fifo_almost_full, - fifo_aempty => read_fifo_almost_empty, - data_w => read_fifo_din, - data_r => read_fifo_dout - ); - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - u_cmd_we <= (not cmd_fifo_empty) and write_start and (not u_busy); - u_cmd <= cmd_fifo_out; - u_addr <= addr_fifo_out; - - write_fifo_re <= u_req_wr and (not write_fifo_empty); - cmd_fifo_re <= u_cmd_we; - u_data_w <= write_fifo_dout; - read_fifo_re <= (not read_fifo_empty) and read_start; - read_fifo_we <= u_data_vld; - read_fifo_din <= u_data_r; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait for 4*CLK_PERIOD; - wait until rising_edge(clk_out) and rst_out='0'; - - write_fifo_we <= '1'; - cmd_fifo_we <= '1'; - write_fifo_din <= X"01020304"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000000"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"05060708"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000002"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"00001111"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000004"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"22223333"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000006"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"44445555"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000008"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"66667777"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000a"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"88889999"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000c"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"AAAABBBB"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00000e"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"CCCCDDDD"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000010"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"EEEEFFFF"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000012"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_we <= '0'; - --- wait until rising_edge(clk_out) and u_busy='0'; --- write_start <= '1'; --- wait until rising_edge(clk_out) and write_fifo_empty='1'; - - write_fifo_we <= '1'; - cmd_fifo_we <= '1'; - write_fifo_din <= X"01234567"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000014"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000014"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"89ABCDEF"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000016"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"11223344"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000018"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000010"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"55667788"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00001a"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"99990000"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"00001c"; - - wait until rising_edge(clk_out); - write_fifo_we <= '1'; - write_fifo_din <= X"AAAA5555"; - cmd_fifo_in <= UCMD_WRITE; - addr_fifo_in <= X"000020"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000000"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000018"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"00001A"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"00001C"; - - wait until rising_edge(clk_out); - cmd_fifo_in <= UCMD_READ; - addr_fifo_in <= X"000020"; - - wait until rising_edge(clk_out); - write_fifo_we <= '0'; - cmd_fifo_we <= '0'; - - wait for 40*CLK_PERIOD; - read_start <= '1'; - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd deleted file mode 100644 index 3ab72bd..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_r_rand_w.vhd +++ /dev/null @@ -1,318 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal lin_addr : user_addr_t := (others => '0'); - signal rand_gen : unsigned(7 downto 0) := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' and u_tag_rd = "0000" then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - end if; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' and u_tag_wr = "0000" then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - lin_addr <= u_addr_preset; - rand_gen <= X"80"; - elsif u_addr_cnt_en = '1' then - lin_addr <= lin_addr + BURST_LEN; - if rand_gen(rand_gen'left) = '1' then - rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010"; - else - rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left); - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= "000" & rw_null_en; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0'; - u_addr <= (rand_gen(7) and (not rw_null_en)) & lin_addr(lin_addr'left-1 downto 0); - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_write_en <= '1'; - rw_null_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - rw_null_en <= '1'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_WRITE; - end if; - rw_null_en <= '0'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_read_en <= '1'; - rw_null_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - rw_null_en <= '1'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_READ; - end if; - rw_null_en <= '0'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd deleted file mode 100644 index 312d2a8..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_lin_w_rand_r.vhd +++ /dev/null @@ -1,316 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal lin_addr : user_addr_t := (others => '0'); - signal rand_gen : unsigned(7 downto 0) := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' and u_tag_rd = "0000" then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - end if; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' and u_tag_wr = "0000" then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - lin_addr <= u_addr_preset; - rand_gen <= X"80"; - elsif u_addr_cnt_en = '1' then - lin_addr <= lin_addr + BURST_LEN; - if rand_gen(rand_gen'left) = '1' then - rand_gen <= (rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left)) xor "10010010"; - else - rand_gen <= rand_gen(rand_gen'left-1 downto 0) & rand_gen(rand_gen'left); - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= "000" & rw_null_en; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (lin_addr /= u_addr_end)) else '0'; - u_addr <= (rand_gen(7) and (rw_null_en)) & lin_addr(lin_addr'left-1 downto 0); - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - rw_null_en <= '0'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_READ; - end if; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"000000"; - u_addr_end <= X"010000"-BURST_LEN; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while lin_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - rw_null_en <= '0'; - if rand_gen(3) = '0' and rand_gen(4) = '0' and rand_gen(5) = '0' and rand_gen(6) = '0' then - if rand_gen(1) = '1' or rand_gen(7) = '1' then - u_cmd <= UCMD_WRITE; - end if; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd deleted file mode 100644 index e20e4af..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_addr.vhd +++ /dev/null @@ -1,315 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 8; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"5E2330"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - wait until rising_edge(clk_out) and u_req_wr='0'; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"5E2330"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - u_cmd <= UCMD_READ; - u_read_en <= '1'; - while u_addr /= u_addr_end loop - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd deleted file mode 100644 index 26c8b9b..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdr_ctrl_rand_rw.vhd +++ /dev/null @@ -1,329 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.sdram_config.all; -use work.sdram_types.all; -use work.utils_pkg.all; - -entity tb_sdr_ctrl is -end; - -architecture struct of tb_sdr_ctrl is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal u_addr : user_addr_t := (others => '0'); - signal u_tag_in : user_tag_t := "0000"; - signal u_tag_rd : user_tag_t; - signal u_tag_wr : user_tag_t; - signal u_cmd : user_cmd_t := UCMD_NOP; - signal u_cmd_we : std_logic := '0'; - signal u_busy : std_logic; - signal u_data_w : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_dm : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "0000"; - signal u_data_r : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal u_data_vld : std_logic; - signal u_req_wr : std_logic; - signal u_req_rd : std_logic; - signal u_read_en : std_logic := '0'; - signal u_write_en : std_logic := '0'; - signal rw_null_en : std_logic := '0'; - signal u_addr_cnt_en : std_logic := '0'; - signal u_addr_load : std_logic := '0'; - signal u_addr_preset : user_addr_t := (others => '0'); - signal u_addr_end : user_addr_t := (others => '0'); - signal ref_data : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - type test_phase_t is (IDLE, PART_INIT, WRITE_SINGLE, WRITE_MULTI, READ_SINGLE, READ_MULTI, FINISHED); - signal test_phase : test_phase_t := IDLE; - - type u_addr_mode_t is (MONOTONIC, RANDOM); - signal u_addr_mode : u_addr_mode_t := MONOTONIC; - signal cycle_cnt : natural := 1; - signal data_cnt : natural := 0; - signal efficiency : real := 0.0; - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl : entity work.sdram_ctrl_top - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - -- User interface - u_data_vld => u_data_vld, - u_data_req_w => u_req_wr, - u_data_req_r => u_req_rd, - u_tag_in => u_tag_in, - u_tag_rd => u_tag_rd, - u_tag_wr => u_tag_wr, - u_busy => u_busy, - u_addr => u_addr, - u_cmd => u_cmd, - u_cmd_we => u_cmd_we, - u_data_wr => u_data_w, - u_data_rd => u_data_r, - u_dm => u_dm, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - ------------------------------------------------------------------------------------------- - -R_DATA_COMPARE: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_data_vld='1' then - if u_read_en = '1' then - assert (ref_data = u_data_r) report "Error on read!" severity failure; - end if; - for i in 0 to DDR_DATA_WIDTH/4-1 loop - ref_data((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_read_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - ref_data <= (others => '0'); - end if; - end if; - end process; - -W_DATA_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_req_wr = '1' then - for i in 0 to DDR_DATA_WIDTH/4-1 loop - u_data_w((i+1)*DDR_DATA_WIDTH/2-1 downto i*DDR_DATA_WIDTH/2) <= last_data + i + 1; - end loop; - last_data := last_data + DDR_DATA_WIDTH/4; - elsif u_write_en = '0' and rw_null_en = '0' then - last_data := (others => '0'); - u_data_w <= (others => '0'); - end if; - end if; - end process; - -ADDR_GEN: - process(clk_out) - variable last_data : unsigned(7 downto 0) := (others => '0'); - begin - if rising_edge(clk_out) then - if u_addr_load = '1' then - u_addr <= u_addr_preset; - elsif u_addr_cnt_en = '1' then - if u_addr_mode = MONOTONIC then - u_addr <= u_addr + BURST_LEN; - else - if u_addr(u_addr'left) = '1' then - if BURST_LEN = 2 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "10000000000010001010100"; - elsif BURST_LEN = 4 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "1000000000010011010110"; - elsif BURST_LEN = 8 then - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)) <= (u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)) & u_addr(u_addr'left)) xor "100000000001011110100"; - end if; - else - u_addr(u_addr'left downto NextExpBaseTwo(BURST_LEN)-1) <= u_addr(u_addr'left-1 downto NextExpBaseTwo(BURST_LEN)-1) & u_addr(u_addr'left); - end if; - end if; - end if; - end if; - end process; - -performance_count: - process(clk_out) - begin - if rising_edge(clk_out) then - if u_write_en = '1' or u_read_en = '1' then - cycle_cnt <= cycle_cnt + 1; - if u_req_wr = '1' or u_req_rd = '1' then - data_cnt <= data_cnt + 1; - end if; - else - cycle_cnt <= 1; - data_cnt <= 0; - end if; - end if; - end process; - - u_tag_in <= ("00" & u_write_en & u_read_en) when ((u_addr = X"333C98" or u_addr = X"000100") and u_cmd_we = '1') else "0000"; - - efficiency <= real(data_cnt)/real(cycle_cnt); - u_cmd_we <= (u_write_en or u_read_en or rw_null_en) and (not u_busy); - u_addr_cnt_en <= '1' when (u_cmd_we = '1' and (u_addr /= u_addr_end)) else '0'; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait until rising_edge(clk_out) and u_busy='0'; - wait for 137*CLK_PERIOD; - - -- Bank 0 - test_phase <= WRITE_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"646808"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - while u_addr /= u_addr_end loop - u_cmd <= UCMD_WRITE; - u_write_en <= '1'; - rw_null_en <= '0'; - if u_addr(20) = '0' then - u_cmd <= UCMD_READ; - u_write_en <= '0'; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_write_en <= '0'; - rw_null_en <= '0'; - wait for 200*CLK_PERIOD; - - wait until rising_edge(clk_out) and u_busy='0'; - -- Bank 0 - test_phase <= READ_MULTI; - u_addr_preset <= X"800000"; - if BURST_LEN = 2 then - u_addr_end <= X"646808"; - elsif BURST_LEN = 4 then - u_addr_end <= X"7DEDD0"; - elsif BURST_LEN = 8 then - u_addr_end <= X"5666B0"; - end if; - u_addr_load <= '1'; - wait until rising_edge(clk_out); - u_addr_load <= '0'; - wait until rising_edge(clk_out); - u_addr_mode <= RANDOM; - while u_addr /= u_addr_end loop - u_cmd <= UCMD_READ; - u_read_en <= '1'; - rw_null_en <= '0'; - if u_addr(20) = '0' then - u_cmd <= UCMD_WRITE; - u_read_en <= '0'; - rw_null_en <= '1'; - end if; - wait until rising_edge(clk_out); - end loop; - u_read_en <= '0'; - rw_null_en <= '0'; - wait until rising_edge(clk_out) and u_data_vld='0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd b/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd deleted file mode 100644 index 95ffa58..0000000 --- a/lib/SDRAM/ddr_sdr_v1_4/src/tb_sdram_ctrl_frontend.vhd +++ /dev/null @@ -1,385 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: cpu_embedded using cpu_core and rom --- --- Copyright (C) 2007 J. Ahrensfeld --- --- This program is free software: you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation, either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program. If not, see . --- --- For questions and ideas, please contact the author at jens@jayfield.org --- --------------------------------------------------------------------------- - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -use work.fifo_ctrl_pkg.all; -use work.sdram_config.all; -use work.sdram_types.all; - -entity tb_sdram_ctrl_frontend is -end; - -architecture struct of tb_sdram_ctrl_frontend is - - -- Number of user data words for simulation - constant CLK_PERIOD : time := 10 ns; - constant BURST_LEN : natural := 2; - - signal rst : std_logic := '1'; - signal clk : std_logic := '0'; - signal rst_out : std_logic; - signal clk_out : std_logic; - signal clk_fb : std_logic; - signal part_clk_p : std_logic; - signal part_clk_n : std_logic; - signal part_cke : std_logic; - signal part_cs_n : std_logic; - signal part_we_n : std_logic; - signal part_ras_n : std_logic; - signal part_cas_n : std_logic; - signal part_ba : unsigned(DDR_BANK_WIDTH-1 downto 0) := (others => '0'); - signal part_dm : unsigned(DDR_DM_WIDTH-1 downto 0) := (others => '0'); - signal part_dqs : unsigned(DDR_DQS_WIDTH-1 downto 0) := (others => '0'); - signal part_addr : unsigned(DDR_ADDR_WIDTH-1 downto 0) := (others => '0'); - signal part_data : unsigned(DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - - signal addr : user_addr_t := (others => '0'); - signal r_wn : std_logic := '0'; - signal en : std_logic := '0'; - signal busy : std_logic; - signal din : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal be : unsigned(2*DDR_DM_WIDTH-1 downto 0) := "1111"; - signal dout : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - signal dout_vld : std_logic; - signal dout_re : std_logic; - signal dout_reg : unsigned(2*DDR_DATA_WIDTH-1 downto 0) := (others => '0'); - -begin - - clk_fb <= part_clk_p after 1 ns; - - -- DDR SDRAM Controller Core - inst_sdram_ctrl_frontend : entity work.sdram_ctrl_frontend - Generic map - ( - BL => BURST_LEN, - read_phaseshift => 0, - f_sysclk => 100E6, - fifo_depth => 4 - ) - Port map - ( - - sys_rst_in => rst, - sys_clk_in => clk, - - sys_rst_out => rst_out, - sys_clk_out => clk_out, - sys_clk_fb => clk_fb, - - busy => busy, - en => en, - r_wn => r_wn, - be => be, - addr => addr, - din => din, - dout => dout, - dout_re => dout_re, - dout_vld => dout_vld, - - -- SDRAM signals - sd_clk_p => part_clk_p, - sd_clk_n => part_clk_n, - sd_cke => part_cke, - sd_cs_n => part_cs_n, - sd_cas_n => part_cas_n, - sd_ras_n => part_ras_n, - sd_we_n => part_we_n, - sd_addr => part_addr, - sd_ba => part_ba, - sd_dm => part_dm, - sd_dqs => part_dqs, - sd_data => part_data - - ); - - -- MICRON DDR SDRAM Simulation Model - i_mt46v16m16_0 : entity work.mt46v16m16 - port map ( - dq => std_logic_vector(part_data), - dqs => std_logic_vector(part_dqs), - addr => std_logic_vector(part_addr), - ba => std_logic_vector(part_ba), - clk => part_clk_p, - clk_n => part_clk_n, - cke => part_cke, - cs_n => part_cs_n, - ras_n => part_ras_n, - cas_n => part_cas_n, - we_n => part_we_n, - dm => std_logic_vector(part_dm) - ); - -CLK_GEN: process - begin - wait for CLK_PERIOD/2; - clk <= not clk; - end process; - -read_register: - process(clk_out) - begin - if rising_edge(clk_out) then - if dout_vld = '1' then - dout_reg <= dout; - end if; - end if; - end process; - ------------------------------------------------------------------------------------------- - dout_re <= dout_vld; - - process - begin - - -- Write MAX_WORDS to DDR SDRAM Controller - wait for 4*CLK_PERIOD; - rst <= '0'; - - wait for 4*CLK_PERIOD; - wait until rising_edge(clk_out) and rst_out='0'; - - for i in 0 to 999 loop - en <= '1'; - r_wn <= '0'; - din <= to_unsigned(i, 32); - addr <= to_unsigned(2*i, 24); - wait until rising_edge(clk_out) and busy = '0'; - end loop; - - for i in 0 to 999 loop - en <= '1'; - r_wn <= '1'; - din <= to_unsigned(i, 32); - addr <= to_unsigned(2*i, 24); - wait until rising_edge(clk_out) and busy = '0'; - end loop; - - en <= '1'; - r_wn <= '0'; - din <= X"01020304"; - addr <= X"000000"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"05060708"; - addr <= X"000002"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"00001111"; - addr <= X"000004"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"22223333"; - addr <= X"000006"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"44445555"; - addr <= X"000008"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"66667777"; - addr <= X"00000a"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"88889999"; - addr <= X"00000c"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAABBBB"; - addr <= X"00000e"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCCDDDD"; - addr <= X"000010"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"EEEEFFFF"; - addr <= X"000012"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"FFFFFFFF"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"87CCCCCC"; - be <= "1000"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CC65CCCC"; - be <= "0100"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCC43CC"; - be <= "0010"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"89ABCDEF"; - addr <= X"000016"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"CCCCCC21"; - be <= "0001"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"55555555"; - be <= "1010"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAAAAAA"; - be <= "0101"; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '1'; - addr <= X"000014"; - - wait until rising_edge(clk_out) and busy = '0'; - be <= "1111"; - en <= '1'; - r_wn <= '0'; - din <= X"11223344"; - addr <= X"000018"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000010"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"55667788"; - addr <= X"00001a"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"99990000"; - addr <= X"00001c"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '1'; - r_wn <= '0'; - din <= X"AAAA5555"; - addr <= X"000020"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000000"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000018"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"00001A"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"00001C"; - - wait until rising_edge(clk_out) and busy = '0'; - r_wn <= '1'; - addr <= X"000020"; - - wait until rising_edge(clk_out) and busy = '0'; - en <= '0'; - - wait; - - end process; - -end architecture struct; diff --git a/lib/VGA_ctrl/src/char_gen.vhd b/lib/VGA_ctrl/src/char_gen.vhd deleted file mode 100644 index 5d82fc9..0000000 --- a/lib/VGA_ctrl/src/char_gen.vhd +++ /dev/null @@ -1,546 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: char_gen - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity char_gen is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72; - - -- User supplied parameters - CHARACTER_SCALE : natural := 1; - CHAR_ROM_SIZE_X : natural := 8; -- Pixels - CHAR_ROM_SIZE_Y : natural := 16; -- Pixels - CHAR_ROM_DEPTH : natural := 256; -- Chars - MAX_CHAR_PER_LINE : natural := 32; -- Chars - MAX_LINE_PER_FRAME : natural := 16; -- Chars - CHAR_SPACING_X : natural := 0; -- Pixels - CHAR_SPACING_Y : natural := 0; -- Pixels - SCREEN_OFFSET_X : natural := 16; -- Pixels - SCREEN_OFFSET_Y : natural := 16 -- Pixels - ); - Port - ( - -- System signals - rst : in std_logic; - vga_clk : in std_logic; - sys_clk : in std_logic; - ce : in std_logic; - frame_pulse : in std_logic; - - - -- Host Signals - clr_screen : in std_logic; - clr_line : in std_logic; - ascii_data : in unsigned(7 downto 0); - ascii_data_we : in std_logic; - ascii_posy_we : in std_logic; - ascii_posx_we : in std_logic; - ready : out std_logic; - - -- Control signals - pos_x : in natural range 0 to tsvga.ts_h.ncyc_scan-1; - pos_y : in natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- Output - char_draw_en : out std_logic - - ); -end char_gen; - -architecture Behavioral of char_gen is - - constant A_RAM_ADDR_WIDTH : integer := 12; - constant A_RAM_DATA_WIDTH : integer := 8; - - type offset_rom_t is array (0 to MAX_LINE_PER_FRAME-1) of unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - - - - function gen_offset_rom(num_char_per_line, num_lines : natural) return offset_rom_t is - variable result : offset_rom_t; - - variable offset : unsigned(A_RAM_ADDR_WIDTH-1 downto 0) := (others => '0'); - begin - for i in 0 to num_lines-1 loop - result(i) := offset; - offset := offset + to_unsigned(num_char_per_line, A_RAM_ADDR_WIDTH-1); - end loop; - return result; - end gen_offset_rom; - - constant offset_rom : offset_rom_t := gen_offset_rom(MAX_CHAR_PER_LINE, MAX_LINE_PER_FRAME); - - -- Calculated parameters - type cg_state_t is (cg_init, cg_ready, cg_clr_line, cg_clr_screen); - signal s, sn : cg_state_t; - - constant CELL_SIZE_X : natural := (CHAR_ROM_SIZE_X+CHAR_SPACING_X)*CHARACTER_SCALE; - constant CELL_SIZE_Y : natural := (CHAR_ROM_SIZE_Y+CHAR_SPACING_Y)*CHARACTER_SCALE; - constant CHAR_SIZE_X : natural := CHAR_ROM_SIZE_X*CHARACTER_SCALE; - constant CHAR_SIZE_Y : natural := CHAR_ROM_SIZE_Y*CHARACTER_SCALE; - - signal line_offset : natural range 0 to MAX_LINE_PER_FRAME-1; - signal cell_x_cnt : natural range 0 to MAX_CHAR_PER_LINE-1; - signal cell_y_cnt : natural range 0 to MAX_LINE_PER_FRAME-1; - signal char_x_cnt : natural range 0 to CELL_SIZE_X-1; - signal char_y_cnt : natural range 0 to CELL_SIZE_Y-1; - signal char_rom_row : unsigned(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto 0); - signal char_rom_addr : unsigned(NextExpBaseTwo(CHAR_ROM_DEPTH*CHAR_ROM_SIZE_Y)-1 downto 0); - signal char_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0); - signal char_reg : unsigned((CHARACTER_SCALE*CHAR_ROM_SIZE_X)-1 downto 0); - - signal a_addr_rd : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal a_addr_wr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal a_data_rd : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_data_wr : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_ram_we : std_logic; - signal a_cnt : natural range 0 to 2**A_RAM_ADDR_WIDTH-1; - signal a_cnt_rst : std_logic; - signal a_cnt_en : std_logic; - signal csr_posx_reg : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posy_reg : natural range 0 to MAX_LINE_PER_FRAME-1; - signal a_data_reg : unsigned(A_RAM_DATA_WIDTH-1 downto 0); - signal a_data_we : std_logic; - signal csr_posx_overflow : std_logic; - signal csr_posx_cnt_din : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posx_cnt_set : std_logic; - signal csr_posx_cnt_en : std_logic; - signal csr_posy_overflow : std_logic; - signal csr_posy_cnt_din : natural range 0 to MAX_LINE_PER_FRAME-1; - signal csr_posy_cnt_set : std_logic; - signal csr_posy_cnt_en : std_logic; - - signal line_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - signal char_addr : unsigned(A_RAM_ADDR_WIDTH-1 downto 0); - - -- Visible Cursor - constant CURSOR_BLINK_INTERVAL : natural := tsvga.nfps/2; - - type cursor_rom_t is array (0 to 2*CHAR_ROM_SIZE_Y-1) of unsigned (CHAR_ROM_SIZE_X-1 downto 0); - constant cursor_rom : cursor_rom_t := - ( - -- Cursor off - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "00000000", - "11111111", - "11111111", - "11111111", - - -- Cursor on - "00000000", - "00000000", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "11111111", - "00000000", - "00000000", - "00000000" - - ); - signal cursor_rom_addr : unsigned(NextExpBaseTwo(2*CHAR_ROM_SIZE_Y)-1 downto 0); - signal cursor_rom_data : unsigned(CHAR_ROM_SIZE_X-1 downto 0); - signal cursor_visible : std_logic; - signal cursor_cnt : natural range 0 to CURSOR_BLINK_INTERVAL-1; - signal csr_posx_synced : natural range 0 to MAX_CHAR_PER_LINE-1; - signal csr_posy_synced : natural range 0 to MAX_LINE_PER_FRAME-1; - - -- Scrolling - signal scroll_offset : natural range 0 to MAX_CHAR_PER_LINE-1; - signal scroll_active : std_logic; - - -begin - - a_addr_rd <= to_unsigned(cell_x_cnt, a_addr_rd'length) + offset_rom(line_offset); - line_addr <= offset_rom(csr_posy_reg); - char_addr <= to_unsigned(csr_posx_reg, char_addr'length); - char_rom_addr <= a_data_rd & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1)); - cursor_rom_addr <= cursor_visible & char_rom_row(NextExpBaseTwo(CHAR_SIZE_Y)-1 downto (CHARACTER_SCALE-1)); - - inst_char_rom : entity work.char_rom - PORT MAP - ( - CLK => vga_clk, - ADDR => char_rom_addr, - DATA => char_rom_data - ); - - inst_ascii_ram: entity work.dpram - GENERIC MAP ( - addr_width => A_RAM_ADDR_WIDTH, - data_width => A_RAM_DATA_WIDTH - ) - PORT MAP( - clka => sys_clk, - clkb => vga_clk, - en_a => '1', - en_b => '1', - we_a => a_ram_we, - addr_a => a_addr_wr, - addr_b => a_addr_rd, - din_a => a_data_wr, - dout_b => a_data_rd - ); - - --------------------------------------------------------------------------------------------- - --- ASCII RAM control - --------------------------------------------------------------------------------------------- - asci_ram_fsm: - process (s, a_cnt, clr_line, clr_screen, a_data_we, a_data_reg, char_addr, line_addr) - begin - sn <= s; - a_cnt_rst <= '0'; - a_cnt_en <= '0'; - a_ram_we <= '0'; - a_data_wr <= a_data_reg; - a_addr_wr <= char_addr + line_addr; - ready <= '0'; - - case s is - - when cg_init => - sn <= cg_clr_screen; - a_cnt_rst <= '1'; - when cg_ready => - ready <= '1'; - a_ram_we <= a_data_we; - if clr_screen = '1' then - a_cnt_rst <= '1'; - sn <= cg_clr_screen; - elsif clr_line = '1' then - a_cnt_rst <= '1'; - sn <= cg_clr_line; - end if; - when cg_clr_line => - a_ram_we <= '1'; - a_cnt_en <= '1'; - a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH); - a_addr_wr <= to_unsigned(a_cnt + to_integer(line_addr), A_RAM_ADDR_WIDTH); - if a_cnt = MAX_CHAR_PER_LINE-1 then - sn <= cg_ready; - end if; - when cg_clr_screen => - a_ram_we <= '1'; - a_cnt_en <= '1'; - a_data_wr <= to_unsigned(0, A_RAM_DATA_WIDTH); - a_addr_wr <= to_unsigned(a_cnt, A_RAM_ADDR_WIDTH); - if a_cnt = (2**A_RAM_ADDR_WIDTH-1) then - sn <= cg_ready; - end if; - - when others => - sn <= cg_ready; - - end case; - end process; - - asci_ram_fsm_next: process (rst, sys_clk) - begin - if rst = '1' then - s <= cg_init; - elsif rising_edge(sys_clk) then - s <= sn; - end if; - end process; - - --------------------------------------------------------------------------------------------- - asci_ram_cnt: process (rst, sys_clk) - begin - if rst = '1' then - a_cnt <= 0; - elsif rising_edge(sys_clk) then - if a_cnt_rst = '1' then - a_cnt <= 0; - elsif a_cnt_en = '1' then - if a_cnt < (2**A_RAM_ADDR_WIDTH-1) then - a_cnt <= a_cnt + 1; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - asci_addr_reg: process (rst, sys_clk) - begin - if rst = '1' then - csr_posx_cnt_en <= '0'; - csr_posx_cnt_set <= '0'; - csr_posy_cnt_en <= '0'; - csr_posy_cnt_set <= '0'; - a_data_reg <= (others => '0'); - a_data_we <= '0'; - elsif rising_edge(sys_clk) then - a_data_we <= '0'; - csr_posx_cnt_en <= '0'; - csr_posx_cnt_set <= '0'; - csr_posy_cnt_en <= '0'; - csr_posy_cnt_set <= '0'; - if ascii_posy_we = '1' then - csr_posy_cnt_din <= to_integer(ascii_data); - csr_posy_cnt_set <= '1'; - elsif ascii_posx_we = '1' then - csr_posx_cnt_din <= to_integer(ascii_data); - csr_posx_cnt_set <= '1'; - elsif ascii_data_we = '1' then - if ascii_data < X"20" then - if ascii_data = X"0D" then - csr_posx_cnt_din <= 0; - csr_posx_cnt_set <= '1'; - elsif ascii_data = X"0A" then - csr_posy_cnt_en <= '1'; - end if; - else - a_data_reg <= ascii_data - X"20"; - a_data_we <= '1'; - csr_posx_cnt_en <= '1'; - end if; - end if; - end if; - end process; - - asci_csr_posx_counter: - process (rst, sys_clk) - begin - if rst = '1' then - csr_posx_reg <= 0; - csr_posx_overflow <= '0'; - elsif rising_edge(sys_clk) then - csr_posx_overflow <= '0'; - if csr_posx_cnt_set = '1' then - csr_posx_reg <= csr_posx_cnt_din; - elsif csr_posx_cnt_en = '1' then - if csr_posx_reg < MAX_CHAR_PER_LINE-1 then - csr_posx_reg <= csr_posx_reg + 1; - else - csr_posx_reg <= 0; - csr_posx_overflow <= '1'; - end if; - end if; - end if; - end process; - - asci_csr_posy_counter: - process (rst, sys_clk) - begin - if rst = '1' then - csr_posy_reg <= 0; - csr_posy_overflow <= '0'; - elsif rising_edge(sys_clk) then - csr_posy_overflow <= '0'; - if csr_posy_cnt_set = '1' then - csr_posy_reg <= csr_posy_cnt_din; - elsif csr_posy_cnt_en = '1' or csr_posx_overflow = '1' then - if csr_posy_reg < MAX_LINE_PER_FRAME-1 then - csr_posy_reg <= csr_posy_reg + 1; - else - csr_posy_reg <= 0; - csr_posy_overflow <= '1'; - end if; - end if; - end if; - end process; - - scroll_gen: process (rst, sys_clk) - begin - if rst = '1' then - scroll_offset <= 0; - scroll_active <= '0'; - elsif rising_edge(sys_clk) then - if clr_screen = '1' then - scroll_offset <= 0; - scroll_active <= '0'; - elsif csr_posy_overflow = '1' then - scroll_active <= '1'; - scroll_offset <= 1; - end if; - if (csr_posy_cnt_en = '1' or csr_posx_overflow = '1') and scroll_active = '1' then - scroll_offset <= scroll_offset + 1; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - --- Cursor generator - --------------------------------------------------------------------------------------------- - proc_sync_csr_posx: - process(vga_clk) - variable p1, p2 : natural range 0 to MAX_CHAR_PER_LINE-1; - begin - if rising_edge(vga_clk) then - csr_posx_synced <= p2; - p2 := p1; - p1 := csr_posx_reg; - end if; - end process; - - proc_sync_csr_posy: - process(vga_clk) - variable p1, p2 : natural range 0 to MAX_LINE_PER_FRAME-1; - begin - if rising_edge(vga_clk) then - csr_posy_synced <= p2; - p2 := p1; - p1 := csr_posy_reg; - end if; - end process; - - csr_blink_cnt: process (rst, vga_clk) - begin - if rst = '1' then - cursor_cnt <= 0; - cursor_visible <= '0'; - elsif rising_edge(vga_clk) then - if frame_pulse = '1' then - if cursor_cnt < CURSOR_BLINK_INTERVAL-1 then - cursor_cnt <= cursor_cnt + 1; - else - cursor_cnt <= 0; - cursor_visible <= not cursor_visible; - end if; - end if; - end if; - end process; - - cursor_rom_read: process (vga_clk) - begin - if rising_edge(vga_clk) then - cursor_rom_data <= (others => '0'); - if (cell_x_cnt = csr_posx_synced) and (line_offset = csr_posy_synced) then - cursor_rom_data <= cursor_rom(to_integer(cursor_rom_addr)); - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - --- Character generator - --------------------------------------------------------------------------------------------- - char_rom_ctrl: process (vga_clk) - begin - if rising_edge(vga_clk) then - char_rom_row <= to_unsigned(char_y_cnt, char_rom_row'length); - end if; - end process; - - --------------------------------------------------------------------------------------------- - char_reg_ctrl: process (vga_clk) - begin - if rising_edge(vga_clk) and ce = '1' then - if char_x_cnt = 2 then -- +2 delay for ASCII-RAM access and CHAR-ROM access - for i in 0 to CHAR_ROM_SIZE_X-1 loop - for j in 0 to CHARACTER_SCALE-1 loop - char_reg(i*CHARACTER_SCALE + j) <= char_rom_data(i) xor cursor_rom_data(i); - end loop; - end loop; - else - char_reg <= char_reg(char_reg'left-1 downto 0) & '0'; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- - cg_ctrl: process (rst, vga_clk) - variable enable_x : std_logic; - variable enable_y : std_logic; - variable char_en : std_logic; - variable char_en2 : std_logic; - begin - - if (rst = '1') then - enable_x := '0'; - enable_y := '0'; - line_offset <= 0; - cell_x_cnt <= 0; - cell_y_cnt <= 0; - char_x_cnt <= 0; - char_y_cnt <= 0; - char_en := '0'; - elsif rising_edge(vga_clk) and ce = '1' then - char_draw_en <= char_en2 and char_reg(char_reg'left); - char_en2 := char_en; - char_en := '0'; - if pos_y = SCREEN_OFFSET_Y then - enable_y := '1'; - cell_y_cnt <= 0; - char_x_cnt <= 0; - line_offset <= scroll_offset; - end if; - if pos_x = SCREEN_OFFSET_X and enable_y = '1' then - enable_x := '1'; - cell_x_cnt <= 0; - char_x_cnt <= 0; - elsif enable_x = '1' and enable_y = '1' then - if char_x_cnt < CELL_SIZE_X-1 then - char_x_cnt <= char_x_cnt + 1; - else - char_x_cnt <= 0; - if cell_x_cnt < MAX_CHAR_PER_LINE-1 then - cell_x_cnt <= cell_x_cnt + 1; - else - enable_x := '0'; - if char_y_cnt < CELL_SIZE_Y-1 then - char_y_cnt <= char_y_cnt + 1; - else - char_y_cnt <= 0; - if cell_y_cnt < MAX_LINE_PER_FRAME-1 then - cell_y_cnt <= cell_y_cnt + 1; - else - enable_y := '0'; - end if; - if line_offset < MAX_LINE_PER_FRAME-1 then - line_offset <= line_offset + 1; - else - line_offset <= 0; - end if; - end if; - end if; - end if; - if (char_x_cnt < CHAR_SIZE_X) and (char_y_cnt < CHAR_SIZE_Y) then - char_en := '1'; - end if; - end if; - end if; - end process; - - --------------------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/VGA_ctrl/src/clkgen_virtex4.vhd b/lib/VGA_ctrl/src/clkgen_virtex4.vhd deleted file mode 100644 index 0b58baf..0000000 --- a/lib/VGA_ctrl/src/clkgen_virtex4.vhd +++ /dev/null @@ -1,105 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_ctrl_core - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. -Library UNISIM; -use UNISIM.vcomponents.all; - -entity clkgen is - Generic - ( - sys_freq : integer := 100E6; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - rst : in std_logic; - clk : in std_logic; - vga_clk : out std_logic; - dcm_locked : out std_logic - ); -end clkgen; - -architecture tech of clkgen is - - signal vga_clk0 : std_logic; - signal dcm_clk0 : std_logic; - signal dcm_clk_fb : std_logic; - - begin - - -- Compnent instantiation - DCM_VGA_CLK_inst : DCM_BASE - generic map ( - CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 - -- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 - CLKFX_DIVIDE => DCM_FREQ_D(sys_freq, tsvga.f_pxl_clk), -- Can be any interger from 1 to 32 - CLKFX_MULTIPLY => DCM_FREQ_M(sys_freq, tsvga.f_pxl_clk), -- Can be any integer from 2 to 32 - CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature - CLKIN_PERIOD => DCM_PERIOD(sys_freq), -- Specify period of input clock in ns from 1.25 to 1000.00 - CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift mode of NONE or FIXED - CLK_FEEDBACK => "1X", -- Specify clock feedback of NONE or 1X - DCM_PERFORMANCE_MODE => "MAX_SPEED", -- Can be MAX_SPEED or MAX_RANGE - DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or - -- an integer from 0 to 15 - DFS_FREQUENCY_MODE => "LOW", -- LOW or HIGH frequency mode for frequency synthesis - DLL_FREQUENCY_MODE => "LOW", -- LOW, HIGH, or HIGH_SER frequency mode for DLL - DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE - FACTORY_JF => X"F0F0", -- FACTORY JF Values Suggested to be set to X"F0F0" - PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 1023 - STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM LOCK, TRUE/FALSE - port map ( - CLK0 => dcm_clk0, -- 0 degree DCM CLK ouptput - CLK180 => open, -- 180 degree DCM CLK output - CLK270 => open, -- 270 degree DCM CLK output - CLK2X => open, -- 2X DCM CLK output - CLK2X180 => open, -- 2X, 180 degree DCM CLK out - CLK90 => open, -- 90 degree DCM CLK output - CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) - CLKFX => vga_clk0, -- DCM CLK synthesis out (M/D) - CLKFX180 => open, -- 180 degree CLK synthesis out - LOCKED => dcm_locked, -- DCM LOCK status output - CLKFB => dcm_clk_fb, -- DCM clock feedback - CLKIN => clk, -- Clock input (from IBUFG, BUFG or DCM) - RST => rst -- DCM asynchronous reset input - ); - - BUFG_dcm_clk_fb : BUFG - port map - ( - O => dcm_clk_fb, -- Clock buffer output - I => dcm_clk0 -- Clock buffer input - ); - - BUFG_vga_clk : BUFG - port map - ( - O => vga_clk, -- Clock buffer output - I => vga_clk0 -- Clock buffer input - ); - - -end tech; diff --git a/lib/VGA_ctrl/src/dpram.vhd b/lib/VGA_ctrl/src/dpram.vhd deleted file mode 100644 index b6c5419..0000000 --- a/lib/VGA_ctrl/src/dpram.vhd +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram; - -architecture Behavioral of dpram is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) - begin - if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; - end if; -end process; - -process (clkb) - begin - if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; - end if; -end process; - - -end Behavioral; - diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff deleted file mode 100644 index a1d2353..0000000 Binary files a/lib/VGA_ctrl/src/fonts/Fixedsys_8x15.bff and /dev/null differ diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff deleted file mode 100644 index b5c16cc..0000000 Binary files a/lib/VGA_ctrl/src/fonts/Fixedsys_8x16.bff and /dev/null differ diff --git a/lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff b/lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff deleted file mode 100644 index 158e99f..0000000 Binary files a/lib/VGA_ctrl/src/fonts/Fixedsys_9x16.bff and /dev/null differ diff --git a/lib/VGA_ctrl/src/fonts/System_16x16.bff b/lib/VGA_ctrl/src/fonts/System_16x16.bff deleted file mode 100644 index 4ca2523..0000000 Binary files a/lib/VGA_ctrl/src/fonts/System_16x16.bff and /dev/null differ diff --git a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd b/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd deleted file mode 100644 index 5a544d0..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_c64.vhd +++ /dev/null @@ -1,540 +0,0 @@ --- generated with romgen v3.0 by MikeJ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0000 - x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0008 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0010 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0018 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0020 - x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0028 - x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0030 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0038 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0040 - x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0048 - x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0050 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0058 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0060 - x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0068 - x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0070 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0078 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0080 - x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0088 - x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0090 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0098 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x00A0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x00A8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0 - x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x00B8 - x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x00C0 - x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8 - x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x00D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x00E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0108 - x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0118 - x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0120 - x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0128 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130 - x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148 - x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0150 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178 - x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0180 - x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0188 - x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0190 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198 - x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x01A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8 - x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0 - x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x01B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0 - x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x01C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x01F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200 - x"08",x"1C",x"3E",x"7F",x"7F",x"1C",x"3E",x"00", -- 0x0208 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0210 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0218 - x"00",x"00",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0220 - x"00",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0228 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"00",x"00", -- 0x0230 - x"30",x"30",x"30",x"30",x"30",x"30",x"30",x"30", -- 0x0238 - x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C",x"0C", -- 0x0240 - x"00",x"00",x"00",x"E0",x"F0",x"38",x"18",x"18", -- 0x0248 - x"18",x"18",x"1C",x"0F",x"07",x"00",x"00",x"00", -- 0x0250 - x"18",x"18",x"38",x"F0",x"E0",x"00",x"00",x"00", -- 0x0258 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FF",x"FF", -- 0x0260 - x"C0",x"E0",x"70",x"38",x"1C",x"0E",x"07",x"03", -- 0x0268 - x"03",x"07",x"0E",x"1C",x"38",x"70",x"E0",x"C0", -- 0x0270 - x"FF",x"FF",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0278 - x"FF",x"FF",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0280 - x"00",x"3C",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"00", -- 0x0290 - x"36",x"7F",x"7F",x"7F",x"3E",x"1C",x"08",x"00", -- 0x0298 - x"60",x"60",x"60",x"60",x"60",x"60",x"60",x"60", -- 0x02A0 - x"00",x"00",x"00",x"07",x"0F",x"1C",x"18",x"18", -- 0x02A8 - x"C3",x"E7",x"7E",x"3C",x"3C",x"7E",x"E7",x"C3", -- 0x02B0 - x"00",x"3C",x"7E",x"66",x"66",x"7E",x"3C",x"00", -- 0x02B8 - x"18",x"18",x"66",x"66",x"18",x"18",x"3C",x"00", -- 0x02C0 - x"06",x"06",x"06",x"06",x"06",x"06",x"06",x"06", -- 0x02C8 - x"08",x"1C",x"3E",x"7F",x"3E",x"1C",x"08",x"00", -- 0x02D0 - x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x02D8 - x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x02E0 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02E8 - x"00",x"00",x"03",x"3E",x"76",x"36",x"36",x"00", -- 0x02F0 - x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0328 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0330 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0338 - x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0340 - x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350 - x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0358 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360 - x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378 - x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0380 - x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0390 - x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0398 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8 - x"03",x"03",x"03",x"03",x"03",x"03",x"FF",x"FF", -- 0x03D0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0 - x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x03E8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 - x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0400 - x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0408 - x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0410 - x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0418 - x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0420 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430 - x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0438 - x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0440 - x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0448 - x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0450 - x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0458 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460 - x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0468 - x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0470 - x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0478 - x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0480 - x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0488 - x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0490 - x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0498 - x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0 - x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x04A8 - x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x04B0 - x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x04B8 - x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x04C0 - x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8 - x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x04D0 - x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8 - x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x04E0 - x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8 - x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x04F0 - x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x04F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500 - x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0508 - x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0510 - x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0518 - x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0520 - x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0528 - x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0530 - x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0538 - x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0540 - x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0548 - x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0550 - x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0560 - x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0568 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570 - x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0578 - x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0580 - x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0588 - x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0590 - x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0598 - x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x05A0 - x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x05A8 - x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x05B0 - x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8 - x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x05C0 - x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x05C8 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x05D0 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x05D8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0 - x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x05E8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0 - x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x05F8 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0600 - x"F7",x"E3",x"C1",x"80",x"80",x"E3",x"C1",x"FF", -- 0x0608 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0610 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0618 - x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0620 - x"FF",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF", -- 0x0630 - x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF",x"CF", -- 0x0638 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0640 - x"FF",x"FF",x"FF",x"1F",x"0F",x"C7",x"E7",x"E7", -- 0x0648 - x"E7",x"E7",x"E3",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0650 - x"E7",x"E7",x"C7",x"0F",x"1F",x"FF",x"FF",x"FF", -- 0x0658 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"00",x"00", -- 0x0660 - x"3F",x"1F",x"8F",x"C7",x"E3",x"F1",x"F8",x"FC", -- 0x0668 - x"FC",x"F8",x"F1",x"E3",x"C7",x"8F",x"1F",x"3F", -- 0x0670 - x"00",x"00",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0678 - x"00",x"00",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0680 - x"FF",x"C3",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"FF", -- 0x0690 - x"C9",x"80",x"80",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x0698 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"9F", -- 0x06A0 - x"FF",x"FF",x"FF",x"F8",x"F0",x"E3",x"E7",x"E7", -- 0x06A8 - x"3C",x"18",x"81",x"C3",x"C3",x"81",x"18",x"3C", -- 0x06B0 - x"FF",x"C3",x"81",x"99",x"99",x"81",x"C3",x"FF", -- 0x06B8 - x"E7",x"E7",x"99",x"99",x"E7",x"E7",x"C3",x"FF", -- 0x06C0 - x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x06C8 - x"F7",x"E3",x"C1",x"80",x"C1",x"E3",x"F7",x"FF", -- 0x06D0 - x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x06D8 - x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x06E0 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x06E8 - x"FF",x"FF",x"FC",x"C1",x"89",x"C9",x"C9",x"FF", -- 0x06F0 - x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0728 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0730 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0738 - x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0740 - x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750 - x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0758 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760 - x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0768 - x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0770 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778 - x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0780 - x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0788 - x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0790 - x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0798 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"00",x"00", -- 0x07D0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0 - x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x07E8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0", -- 0x07F8 - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0800 - x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0808 - x"00",x"60",x"60",x"7C",x"66",x"66",x"7C",x"00", -- 0x0810 - x"00",x"00",x"3C",x"60",x"60",x"60",x"3C",x"00", -- 0x0818 - x"00",x"06",x"06",x"3E",x"66",x"66",x"3E",x"00", -- 0x0820 - x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0828 - x"00",x"0E",x"18",x"3E",x"18",x"18",x"18",x"00", -- 0x0830 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"7C", -- 0x0838 - x"00",x"60",x"60",x"7C",x"66",x"66",x"66",x"00", -- 0x0840 - x"00",x"18",x"00",x"38",x"18",x"18",x"3C",x"00", -- 0x0848 - x"00",x"06",x"00",x"06",x"06",x"06",x"06",x"3C", -- 0x0850 - x"00",x"60",x"60",x"6C",x"78",x"6C",x"66",x"00", -- 0x0858 - x"00",x"38",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0860 - x"00",x"00",x"66",x"7F",x"7F",x"6B",x"63",x"00", -- 0x0868 - x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0870 - x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0878 - x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0880 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"06", -- 0x0888 - x"00",x"00",x"7C",x"66",x"60",x"60",x"60",x"00", -- 0x0890 - x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0898 - x"00",x"18",x"7E",x"18",x"18",x"18",x"0E",x"00", -- 0x08A0 - x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x08A8 - x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x08B0 - x"00",x"00",x"63",x"6B",x"7F",x"3E",x"36",x"00", -- 0x08B8 - x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x08C0 - x"00",x"00",x"66",x"66",x"66",x"3E",x"0C",x"78", -- 0x08C8 - x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x08D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x08D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x08E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x08E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x08F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"18",x"18",x"18",x"18",x"00",x"00",x"18",x"00", -- 0x0908 - x"66",x"66",x"66",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"66",x"66",x"FF",x"66",x"FF",x"66",x"66",x"00", -- 0x0918 - x"18",x"3E",x"60",x"3C",x"06",x"7C",x"18",x"00", -- 0x0920 - x"62",x"66",x"0C",x"18",x"30",x"66",x"46",x"00", -- 0x0928 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0930 - x"06",x"0C",x"18",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0940 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0948 - x"00",x"66",x"3C",x"FF",x"3C",x"66",x"00",x"00", -- 0x0950 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0960 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0970 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0978 - x"3C",x"66",x"6E",x"76",x"66",x"66",x"3C",x"00", -- 0x0980 - x"18",x"18",x"38",x"18",x"18",x"18",x"7E",x"00", -- 0x0988 - x"3C",x"66",x"06",x"0C",x"30",x"60",x"7E",x"00", -- 0x0990 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0998 - x"06",x"0E",x"1E",x"66",x"7F",x"06",x"06",x"00", -- 0x09A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x09A8 - x"3C",x"66",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x09B0 - x"7E",x"66",x"0C",x"18",x"18",x"18",x"18",x"00", -- 0x09B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x09C0 - x"3C",x"66",x"66",x"3E",x"06",x"66",x"3C",x"00", -- 0x09C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x09D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x09D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x09E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x09E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x09F0 - x"3C",x"66",x"06",x"0C",x"18",x"00",x"18",x"00", -- 0x09F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0A00 - x"18",x"3C",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A08 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0A10 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0A18 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0A20 - x"7E",x"60",x"60",x"78",x"60",x"60",x"7E",x"00", -- 0x0A28 - x"7E",x"60",x"60",x"78",x"60",x"60",x"60",x"00", -- 0x0A30 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0A38 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0A40 - x"3C",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0A48 - x"1E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0A50 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0A58 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0A60 - x"63",x"77",x"7F",x"6B",x"63",x"63",x"63",x"00", -- 0x0A68 - x"66",x"76",x"7E",x"7E",x"6E",x"66",x"66",x"00", -- 0x0A70 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0A78 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0A80 - x"3C",x"66",x"66",x"66",x"66",x"3C",x"0E",x"00", -- 0x0A88 - x"7C",x"66",x"66",x"7C",x"78",x"6C",x"66",x"00", -- 0x0A90 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0A98 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x0AA0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0AA8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x0AB0 - x"63",x"63",x"63",x"6B",x"7F",x"77",x"63",x"00", -- 0x0AB8 - x"66",x"66",x"3C",x"18",x"3C",x"66",x"66",x"00", -- 0x0AC0 - x"66",x"66",x"66",x"3C",x"18",x"18",x"18",x"00", -- 0x0AC8 - x"7E",x"06",x"0C",x"18",x"30",x"60",x"7E",x"00", -- 0x0AD0 - x"18",x"18",x"18",x"FF",x"FF",x"18",x"18",x"18", -- 0x0AD8 - x"C0",x"C0",x"30",x"30",x"C0",x"C0",x"30",x"30", -- 0x0AE0 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0AE8 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0AF0 - x"33",x"99",x"CC",x"66",x"33",x"99",x"CC",x"66", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0B08 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0B10 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0B20 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0B28 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0B30 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B38 - x"00",x"00",x"00",x"00",x"CC",x"CC",x"33",x"33", -- 0x0B40 - x"CC",x"99",x"33",x"66",x"CC",x"99",x"33",x"66", -- 0x0B48 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0B50 - x"18",x"18",x"18",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B58 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0B60 - x"18",x"18",x"18",x"1F",x"1F",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0B78 - x"00",x"00",x"00",x"1F",x"1F",x"18",x"18",x"18", -- 0x0B80 - x"18",x"18",x"18",x"FF",x"FF",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"FF",x"FF",x"18",x"18",x"18", -- 0x0B90 - x"18",x"18",x"18",x"F8",x"F8",x"18",x"18",x"18", -- 0x0B98 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0BA0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0BA8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0BB0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0BC8 - x"01",x"03",x"06",x"6C",x"78",x"70",x"60",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x0BD8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"18",x"18",x"18",x"F8",x"F8",x"00",x"00",x"00", -- 0x0BE8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x0BF8 - x"C3",x"99",x"91",x"91",x"9F",x"99",x"C3",x"FF", -- 0x0C00 - x"FF",x"FF",x"C3",x"F9",x"C1",x"99",x"C1",x"FF", -- 0x0C08 - x"FF",x"9F",x"9F",x"83",x"99",x"99",x"83",x"FF", -- 0x0C10 - x"FF",x"FF",x"C3",x"9F",x"9F",x"9F",x"C3",x"FF", -- 0x0C18 - x"FF",x"F9",x"F9",x"C1",x"99",x"99",x"C1",x"FF", -- 0x0C20 - x"FF",x"FF",x"C3",x"99",x"81",x"9F",x"C3",x"FF", -- 0x0C28 - x"FF",x"F1",x"E7",x"C1",x"E7",x"E7",x"E7",x"FF", -- 0x0C30 - x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"83", -- 0x0C38 - x"FF",x"9F",x"9F",x"83",x"99",x"99",x"99",x"FF", -- 0x0C40 - x"FF",x"E7",x"FF",x"C7",x"E7",x"E7",x"C3",x"FF", -- 0x0C48 - x"FF",x"F9",x"FF",x"F9",x"F9",x"F9",x"F9",x"C3", -- 0x0C50 - x"FF",x"9F",x"9F",x"93",x"87",x"93",x"99",x"FF", -- 0x0C58 - x"FF",x"C7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0C60 - x"FF",x"FF",x"99",x"80",x"80",x"94",x"9C",x"FF", -- 0x0C68 - x"FF",x"FF",x"83",x"99",x"99",x"99",x"99",x"FF", -- 0x0C70 - x"FF",x"FF",x"C3",x"99",x"99",x"99",x"C3",x"FF", -- 0x0C78 - x"FF",x"FF",x"83",x"99",x"99",x"83",x"9F",x"9F", -- 0x0C80 - x"FF",x"FF",x"C1",x"99",x"99",x"C1",x"F9",x"F9", -- 0x0C88 - x"FF",x"FF",x"83",x"99",x"9F",x"9F",x"9F",x"FF", -- 0x0C90 - x"FF",x"FF",x"C1",x"9F",x"C3",x"F9",x"83",x"FF", -- 0x0C98 - x"FF",x"E7",x"81",x"E7",x"E7",x"E7",x"F1",x"FF", -- 0x0CA0 - x"FF",x"FF",x"99",x"99",x"99",x"99",x"C1",x"FF", -- 0x0CA8 - x"FF",x"FF",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0CB0 - x"FF",x"FF",x"9C",x"94",x"80",x"C1",x"C9",x"FF", -- 0x0CB8 - x"FF",x"FF",x"99",x"C3",x"E7",x"C3",x"99",x"FF", -- 0x0CC0 - x"FF",x"FF",x"99",x"99",x"99",x"C1",x"F3",x"87", -- 0x0CC8 - x"FF",x"FF",x"81",x"F3",x"E7",x"CF",x"81",x"FF", -- 0x0CD0 - x"C3",x"CF",x"CF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x0CD8 - x"F3",x"ED",x"CF",x"83",x"CF",x"9D",x"03",x"FF", -- 0x0CE0 - x"C3",x"F3",x"F3",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x0CE8 - x"FF",x"E7",x"C3",x"81",x"E7",x"E7",x"E7",x"E7", -- 0x0CF0 - x"FF",x"EF",x"CF",x"80",x"80",x"CF",x"EF",x"FF", -- 0x0CF8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D00 - x"E7",x"E7",x"E7",x"E7",x"FF",x"FF",x"E7",x"FF", -- 0x0D08 - x"99",x"99",x"99",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D10 - x"99",x"99",x"00",x"99",x"00",x"99",x"99",x"FF", -- 0x0D18 - x"E7",x"C1",x"9F",x"C3",x"F9",x"83",x"E7",x"FF", -- 0x0D20 - x"9D",x"99",x"F3",x"E7",x"CF",x"99",x"B9",x"FF", -- 0x0D28 - x"C3",x"99",x"C3",x"C7",x"98",x"99",x"C0",x"FF", -- 0x0D30 - x"F9",x"F3",x"E7",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0D38 - x"F3",x"E7",x"CF",x"CF",x"CF",x"E7",x"F3",x"FF", -- 0x0D40 - x"CF",x"E7",x"F3",x"F3",x"F3",x"E7",x"CF",x"FF", -- 0x0D48 - x"FF",x"99",x"C3",x"00",x"C3",x"99",x"FF",x"FF", -- 0x0D50 - x"FF",x"E7",x"E7",x"81",x"E7",x"E7",x"FF",x"FF", -- 0x0D58 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0D60 - x"FF",x"FF",x"FF",x"81",x"FF",x"FF",x"FF",x"FF", -- 0x0D68 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0D70 - x"FF",x"FC",x"F9",x"F3",x"E7",x"CF",x"9F",x"FF", -- 0x0D78 - x"C3",x"99",x"91",x"89",x"99",x"99",x"C3",x"FF", -- 0x0D80 - x"E7",x"E7",x"C7",x"E7",x"E7",x"E7",x"81",x"FF", -- 0x0D88 - x"C3",x"99",x"F9",x"F3",x"CF",x"9F",x"81",x"FF", -- 0x0D90 - x"C3",x"99",x"F9",x"E3",x"F9",x"99",x"C3",x"FF", -- 0x0D98 - x"F9",x"F1",x"E1",x"99",x"80",x"F9",x"F9",x"FF", -- 0x0DA0 - x"81",x"9F",x"83",x"F9",x"F9",x"99",x"C3",x"FF", -- 0x0DA8 - x"C3",x"99",x"9F",x"83",x"99",x"99",x"C3",x"FF", -- 0x0DB0 - x"81",x"99",x"F3",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0DB8 - x"C3",x"99",x"99",x"C3",x"99",x"99",x"C3",x"FF", -- 0x0DC0 - x"C3",x"99",x"99",x"C1",x"F9",x"99",x"C3",x"FF", -- 0x0DC8 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"FF",x"FF", -- 0x0DD0 - x"FF",x"FF",x"E7",x"FF",x"FF",x"E7",x"E7",x"CF", -- 0x0DD8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x0DE0 - x"FF",x"FF",x"81",x"FF",x"81",x"FF",x"FF",x"FF", -- 0x0DE8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x0DF0 - x"C3",x"99",x"F9",x"F3",x"E7",x"FF",x"E7",x"FF", -- 0x0DF8 - x"FF",x"FF",x"FF",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0E00 - x"E7",x"C3",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E08 - x"83",x"99",x"99",x"83",x"99",x"99",x"83",x"FF", -- 0x0E10 - x"C3",x"99",x"9F",x"9F",x"9F",x"99",x"C3",x"FF", -- 0x0E18 - x"87",x"93",x"99",x"99",x"99",x"93",x"87",x"FF", -- 0x0E20 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0E28 - x"81",x"9F",x"9F",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0E30 - x"C3",x"99",x"9F",x"91",x"99",x"99",x"C3",x"FF", -- 0x0E38 - x"99",x"99",x"99",x"81",x"99",x"99",x"99",x"FF", -- 0x0E40 - x"C3",x"E7",x"E7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0E48 - x"E1",x"F3",x"F3",x"F3",x"F3",x"93",x"C7",x"FF", -- 0x0E50 - x"99",x"93",x"87",x"8F",x"87",x"93",x"99",x"FF", -- 0x0E58 - x"9F",x"9F",x"9F",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0E60 - x"9C",x"88",x"80",x"94",x"9C",x"9C",x"9C",x"FF", -- 0x0E68 - x"99",x"89",x"81",x"81",x"91",x"99",x"99",x"FF", -- 0x0E70 - x"C3",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0E78 - x"83",x"99",x"99",x"83",x"9F",x"9F",x"9F",x"FF", -- 0x0E80 - x"C3",x"99",x"99",x"99",x"99",x"C3",x"F1",x"FF", -- 0x0E88 - x"83",x"99",x"99",x"83",x"87",x"93",x"99",x"FF", -- 0x0E90 - x"C3",x"99",x"9F",x"C3",x"F9",x"99",x"C3",x"FF", -- 0x0E98 - x"81",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0EA0 - x"99",x"99",x"99",x"99",x"99",x"99",x"C3",x"FF", -- 0x0EA8 - x"99",x"99",x"99",x"99",x"99",x"C3",x"E7",x"FF", -- 0x0EB0 - x"9C",x"9C",x"9C",x"94",x"80",x"88",x"9C",x"FF", -- 0x0EB8 - x"99",x"99",x"C3",x"E7",x"C3",x"99",x"99",x"FF", -- 0x0EC0 - x"99",x"99",x"99",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x0EC8 - x"81",x"F9",x"F3",x"E7",x"CF",x"9F",x"81",x"FF", -- 0x0ED0 - x"E7",x"E7",x"E7",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0ED8 - x"3F",x"3F",x"CF",x"CF",x"3F",x"3F",x"CF",x"CF", -- 0x0EE0 - x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7",x"E7", -- 0x0EE8 - x"CC",x"CC",x"33",x"33",x"CC",x"CC",x"33",x"33", -- 0x0EF0 - x"CC",x"66",x"33",x"99",x"CC",x"66",x"33",x"99", -- 0x0EF8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F00 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0F08 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0F18 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0F20 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0F28 - x"33",x"33",x"CC",x"CC",x"33",x"33",x"CC",x"CC", -- 0x0F30 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F38 - x"FF",x"FF",x"FF",x"FF",x"33",x"33",x"CC",x"CC", -- 0x0F40 - x"33",x"66",x"CC",x"99",x"33",x"66",x"CC",x"99", -- 0x0F48 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0F50 - x"E7",x"E7",x"E7",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F58 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0F60 - x"E7",x"E7",x"E7",x"E0",x"E0",x"FF",x"FF",x"FF", -- 0x0F68 - x"FF",x"FF",x"FF",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F70 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0F78 - x"FF",x"FF",x"FF",x"E0",x"E0",x"E7",x"E7",x"E7", -- 0x0F80 - x"E7",x"E7",x"E7",x"00",x"00",x"FF",x"FF",x"FF", -- 0x0F88 - x"FF",x"FF",x"FF",x"00",x"00",x"E7",x"E7",x"E7", -- 0x0F90 - x"E7",x"E7",x"E7",x"07",x"07",x"E7",x"E7",x"E7", -- 0x0F98 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0FA0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x0FA8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0FB0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FB8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0FC0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x0FC8 - x"FE",x"FC",x"F9",x"93",x"87",x"8F",x"9F",x"FF", -- 0x0FD0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x0FD8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0FE0 - x"E7",x"E7",x"E7",x"07",x"07",x"FF",x"FF",x"FF", -- 0x0FE8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x0FF0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"F0" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd b/lib/VGA_ctrl/src/fonts/char_rom_data.vhd deleted file mode 100644 index c52e7f7..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_data.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"7C",x"40",x"7C",x"44",x"7C",x"0C",x"0C",x"7C", -- 0x0000 - x"3C",x"24",x"7E",x"62",x"62",x"62",x"62",x"00", -- 0x0008 - x"7C",x"24",x"3E",x"32",x"32",x"32",x"7E",x"00", -- 0x0010 - x"7E",x"42",x"40",x"60",x"60",x"62",x"7E",x"00", -- 0x0018 - x"7E",x"22",x"22",x"32",x"32",x"32",x"7E",x"00", -- 0x0020 - x"7E",x"40",x"40",x"78",x"60",x"60",x"7E",x"00", -- 0x0028 - x"7E",x"40",x"40",x"78",x"60",x"60",x"60",x"00", -- 0x0030 - x"7E",x"42",x"40",x"6E",x"62",x"62",x"7E",x"00", -- 0x0038 - x"42",x"42",x"42",x"7E",x"62",x"62",x"62",x"00", -- 0x0040 - x"10",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x0048 - x"02",x"02",x"02",x"06",x"06",x"46",x"3C",x"00", -- 0x0050 - x"42",x"44",x"48",x"7E",x"62",x"62",x"62",x"00", -- 0x0058 - x"40",x"40",x"40",x"60",x"60",x"60",x"7E",x"00", -- 0x0060 - x"66",x"5A",x"42",x"62",x"62",x"62",x"62",x"00", -- 0x0068 - x"72",x"4A",x"4A",x"6A",x"6A",x"6A",x"66",x"00", -- 0x0070 - x"7E",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x0078 - x"7E",x"42",x"42",x"7E",x"60",x"60",x"60",x"00", -- 0x0080 - x"7E",x"42",x"42",x"62",x"6A",x"64",x"7A",x"00", -- 0x0088 - x"7E",x"42",x"42",x"7E",x"64",x"62",x"62",x"00", -- 0x0090 - x"7E",x"42",x"40",x"7E",x"06",x"46",x"7E",x"00", -- 0x0098 - x"7C",x"10",x"10",x"18",x"18",x"18",x"18",x"00", -- 0x00A0 - x"42",x"42",x"42",x"62",x"62",x"62",x"7E",x"00", -- 0x00A8 - x"42",x"42",x"42",x"24",x"24",x"18",x"18",x"00", -- 0x00B0 - x"62",x"62",x"62",x"62",x"42",x"5A",x"66",x"00", -- 0x00B8 - x"42",x"24",x"18",x"7C",x"62",x"62",x"62",x"00", -- 0x00C0 - x"42",x"42",x"42",x"3C",x"18",x"18",x"18",x"00", -- 0x00C8 - x"7E",x"02",x"1C",x"60",x"60",x"60",x"7E",x"00", -- 0x00D0 - x"3C",x"20",x"20",x"30",x"30",x"30",x"3C",x"00", -- 0x00D8 - x"18",x"20",x"20",x"78",x"60",x"60",x"7C",x"00", -- 0x00E0 - x"3C",x"04",x"04",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x00E8 - x"08",x"1C",x"2A",x"08",x"08",x"08",x"08",x"00", -- 0x00F0 - x"00",x"20",x"40",x"FE",x"40",x"20",x"00",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"1C",x"1C",x"1C",x"00",x"1C",x"00", -- 0x0108 - x"36",x"36",x"12",x"12",x"00",x"00",x"00",x"00", -- 0x0110 - x"24",x"24",x"7E",x"34",x"7E",x"34",x"34",x"00", -- 0x0118 - x"08",x"3E",x"28",x"3E",x"1A",x"3E",x"18",x"00", -- 0x0120 - x"70",x"52",x"74",x"08",x"1E",x"2A",x"4E",x"00", -- 0x0128 - x"78",x"48",x"30",x"70",x"6A",x"64",x"7A",x"00", -- 0x0130 - x"38",x"38",x"08",x"08",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"10",x"20",x"30",x"30",x"10",x"0C",x"00", -- 0x0140 - x"30",x"08",x"04",x"0C",x"0C",x"08",x"30",x"00", -- 0x0148 - x"08",x"2A",x"1C",x"3E",x"1C",x"2A",x"08",x"00", -- 0x0150 - x"00",x"08",x"08",x"3E",x"3E",x"0C",x"0C",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"1C",x"1C",x"04",x"04", -- 0x0160 - x"00",x"00",x"00",x"7E",x"7E",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"02",x"04",x"08",x"10",x"20",x"40",x"00", -- 0x0178 - x"7E",x"42",x"46",x"6A",x"72",x"62",x"7E",x"00", -- 0x0180 - x"38",x"08",x"08",x"18",x"18",x"18",x"3C",x"00", -- 0x0188 - x"7E",x"42",x"02",x"7E",x"60",x"60",x"7E",x"00", -- 0x0190 - x"3E",x"02",x"02",x"1E",x"06",x"06",x"7E",x"00", -- 0x0198 - x"40",x"40",x"44",x"44",x"7E",x"0C",x"0C",x"00", -- 0x01A0 - x"3E",x"20",x"20",x"3E",x"06",x"46",x"7E",x"00", -- 0x01A8 - x"7E",x"40",x"40",x"7E",x"62",x"62",x"7E",x"00", -- 0x01B0 - x"7E",x"42",x"04",x"08",x"18",x"18",x"18",x"00", -- 0x01B8 - x"3C",x"24",x"24",x"7E",x"62",x"62",x"7E",x"00", -- 0x01C0 - x"7E",x"42",x"42",x"7E",x"06",x"06",x"7E",x"00", -- 0x01C8 - x"00",x"00",x"18",x"00",x"18",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"1C",x"00",x"1C",x"1C",x"04",x"04", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"7E",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"7E",x"42",x"02",x"3E",x"30",x"00",x"30",x"00", -- 0x01F8 - x"00",x"00",x"00",x"00",x"FF",x"00",x"00",x"00", -- 0x0200 - x"18",x"3C",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x0208 - x"10",x"10",x"10",x"10",x"10",x"10",x"10",x"10", -- 0x0210 - x"00",x"00",x"00",x"FF",x"00",x"00",x"00",x"00", -- 0x0218 - x"00",x"00",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x0220 - x"00",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0228 - x"00",x"00",x"00",x"00",x"00",x"FF",x"00",x"00", -- 0x0230 - x"20",x"20",x"20",x"20",x"20",x"20",x"20",x"20", -- 0x0238 - x"04",x"04",x"04",x"04",x"04",x"04",x"04",x"04", -- 0x0240 - x"00",x"00",x"00",x"C0",x"30",x"10",x"08",x"08", -- 0x0248 - x"10",x"10",x"08",x"0C",x"03",x"00",x"00",x"00", -- 0x0250 - x"08",x"08",x"10",x"30",x"C0",x"00",x"00",x"00", -- 0x0258 - x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"FF", -- 0x0260 - x"80",x"40",x"20",x"10",x"08",x"04",x"02",x"01", -- 0x0268 - x"01",x"02",x"04",x"08",x"10",x"20",x"40",x"80", -- 0x0270 - x"FF",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0278 - x"FF",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0280 - x"3C",x"7E",x"7E",x"7E",x"7E",x"7E",x"3C",x"00", -- 0x0288 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"00", -- 0x0290 - x"24",x"7E",x"7E",x"7E",x"3C",x"18",x"18",x"00", -- 0x0298 - x"40",x"40",x"40",x"40",x"40",x"40",x"40",x"40", -- 0x02A0 - x"00",x"00",x"00",x"03",x"0C",x"08",x"10",x"10", -- 0x02A8 - x"81",x"42",x"24",x"18",x"18",x"24",x"42",x"81", -- 0x02B0 - x"3C",x"7E",x"66",x"42",x"66",x"7E",x"3C",x"00", -- 0x02B8 - x"18",x"18",x"7E",x"7E",x"18",x"18",x"7E",x"00", -- 0x02C0 - x"02",x"02",x"02",x"02",x"02",x"02",x"02",x"02", -- 0x02C8 - x"00",x"18",x"3C",x"7E",x"7E",x"3C",x"18",x"00", -- 0x02D0 - x"08",x"08",x"08",x"FF",x"08",x"08",x"08",x"08", -- 0x02D8 - x"C0",x"30",x"C0",x"30",x"C0",x"30",x"C0",x"30", -- 0x02E0 - x"08",x"08",x"08",x"08",x"08",x"08",x"08",x"08", -- 0x02E8 - x"00",x"00",x"7C",x"24",x"64",x"64",x"66",x"00", -- 0x02F0 - x"FF",x"7F",x"3F",x"1F",x"0F",x"07",x"03",x"01", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0308 - x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0310 - x"FF",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"FF", -- 0x0320 - x"80",x"80",x"80",x"80",x"80",x"80",x"80",x"80", -- 0x0328 - x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33", -- 0x0330 - x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0338 - x"00",x"00",x"00",x"00",x"CC",x"33",x"CC",x"33", -- 0x0340 - x"FF",x"FE",x"FC",x"F8",x"F0",x"E0",x"C0",x"80", -- 0x0348 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0350 - x"08",x"08",x"08",x"0F",x"08",x"08",x"08",x"08", -- 0x0358 - x"00",x"00",x"00",x"00",x"0F",x"0F",x"0F",x"0F", -- 0x0360 - x"08",x"08",x"08",x"0F",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"F8",x"08",x"08",x"08",x"08", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"FF",x"FF", -- 0x0378 - x"00",x"00",x"00",x"0F",x"08",x"08",x"08",x"08", -- 0x0380 - x"08",x"08",x"08",x"FF",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"FF",x"08",x"08",x"08",x"08", -- 0x0390 - x"08",x"08",x"08",x"F8",x"08",x"08",x"08",x"08", -- 0x0398 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x03A0 - x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x03A8 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x03B0 - x"FF",x"FF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"FF",x"FF",x"FF", -- 0x03C8 - x"01",x"01",x"01",x"01",x"01",x"01",x"01",x"FF", -- 0x03D0 - x"00",x"00",x"00",x"00",x"F0",x"F0",x"F0",x"F0", -- 0x03D8 - x"0F",x"0F",x"0F",x"0F",x"00",x"00",x"00",x"00", -- 0x03E0 - x"08",x"08",x"08",x"F8",x"00",x"00",x"00",x"00", -- 0x03E8 - x"F0",x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00", -- 0x03F0 - x"F0",x"F0",x"F0",x"F0",x"0F",x"0F",x"0F",x"0F", -- 0x03F8 - x"83",x"BF",x"83",x"BB",x"83",x"F3",x"F3",x"83", -- 0x0400 - x"C3",x"DB",x"81",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0408 - x"83",x"DB",x"C1",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0410 - x"81",x"BD",x"BF",x"9F",x"9F",x"9D",x"81",x"FF", -- 0x0418 - x"81",x"DD",x"DD",x"CD",x"CD",x"CD",x"81",x"FF", -- 0x0420 - x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"81",x"FF", -- 0x0428 - x"81",x"BF",x"BF",x"87",x"9F",x"9F",x"9F",x"FF", -- 0x0430 - x"81",x"BD",x"BF",x"91",x"9D",x"9D",x"81",x"FF", -- 0x0438 - x"BD",x"BD",x"BD",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0440 - x"EF",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x0448 - x"FD",x"FD",x"FD",x"F9",x"F9",x"B9",x"C3",x"FF", -- 0x0450 - x"BD",x"BB",x"B7",x"81",x"9D",x"9D",x"9D",x"FF", -- 0x0458 - x"BF",x"BF",x"BF",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x0460 - x"99",x"A5",x"BD",x"9D",x"9D",x"9D",x"9D",x"FF", -- 0x0468 - x"8D",x"B5",x"B5",x"95",x"95",x"95",x"99",x"FF", -- 0x0470 - x"81",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x0478 - x"81",x"BD",x"BD",x"81",x"9F",x"9F",x"9F",x"FF", -- 0x0480 - x"81",x"BD",x"BD",x"9D",x"95",x"9B",x"85",x"FF", -- 0x0488 - x"81",x"BD",x"BD",x"81",x"9B",x"9D",x"9D",x"FF", -- 0x0490 - x"81",x"BD",x"BF",x"81",x"F9",x"B9",x"81",x"FF", -- 0x0498 - x"83",x"EF",x"EF",x"E7",x"E7",x"E7",x"E7",x"FF", -- 0x04A0 - x"BD",x"BD",x"BD",x"9D",x"9D",x"9D",x"81",x"FF", -- 0x04A8 - x"BD",x"BD",x"BD",x"DB",x"DB",x"E7",x"E7",x"FF", -- 0x04B0 - x"9D",x"9D",x"9D",x"9D",x"BD",x"A5",x"99",x"FF", -- 0x04B8 - x"BD",x"DB",x"E7",x"83",x"9D",x"9D",x"9D",x"FF", -- 0x04C0 - x"BD",x"BD",x"BD",x"C3",x"E7",x"E7",x"E7",x"FF", -- 0x04C8 - x"81",x"FD",x"E3",x"9F",x"9F",x"9F",x"81",x"FF", -- 0x04D0 - x"C3",x"DF",x"DF",x"CF",x"CF",x"CF",x"C3",x"FF", -- 0x04D8 - x"E7",x"DF",x"DF",x"87",x"9F",x"9F",x"83",x"FF", -- 0x04E0 - x"C3",x"FB",x"FB",x"F3",x"F3",x"F3",x"C3",x"FF", -- 0x04E8 - x"F7",x"E3",x"D5",x"F7",x"F7",x"F7",x"F7",x"FF", -- 0x04F0 - x"FF",x"DF",x"BF",x"01",x"BF",x"DF",x"FF",x"FF", -- 0x04F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0500 - x"E7",x"E7",x"E3",x"E3",x"E3",x"FF",x"E3",x"FF", -- 0x0508 - x"C9",x"C9",x"ED",x"ED",x"FF",x"FF",x"FF",x"FF", -- 0x0510 - x"DB",x"DB",x"81",x"CB",x"81",x"CB",x"CB",x"FF", -- 0x0518 - x"F7",x"C1",x"D7",x"C1",x"E5",x"C1",x"E7",x"FF", -- 0x0520 - x"8F",x"AD",x"8B",x"F7",x"E1",x"D5",x"B1",x"FF", -- 0x0528 - x"87",x"B7",x"CF",x"8F",x"95",x"9B",x"85",x"FF", -- 0x0530 - x"C7",x"C7",x"F7",x"F7",x"FF",x"FF",x"FF",x"FF", -- 0x0538 - x"F3",x"EF",x"DF",x"CF",x"CF",x"EF",x"F3",x"FF", -- 0x0540 - x"CF",x"F7",x"FB",x"F3",x"F3",x"F7",x"CF",x"FF", -- 0x0548 - x"F7",x"D5",x"E3",x"C1",x"E3",x"D5",x"F7",x"FF", -- 0x0550 - x"FF",x"F7",x"F7",x"C1",x"C1",x"F3",x"F3",x"FF", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x0560 - x"FF",x"FF",x"FF",x"81",x"81",x"FF",x"FF",x"FF", -- 0x0568 - x"FF",x"FF",x"FF",x"FF",x"FF",x"E7",x"E7",x"FF", -- 0x0570 - x"FF",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"FF", -- 0x0578 - x"81",x"BD",x"B9",x"95",x"8D",x"9D",x"81",x"FF", -- 0x0580 - x"C7",x"F7",x"F7",x"E7",x"E7",x"E7",x"C3",x"FF", -- 0x0588 - x"81",x"BD",x"FD",x"81",x"9F",x"9F",x"81",x"FF", -- 0x0590 - x"C1",x"FD",x"FD",x"E1",x"F9",x"F9",x"81",x"FF", -- 0x0598 - x"BF",x"BF",x"BB",x"BB",x"81",x"F3",x"F3",x"FF", -- 0x05A0 - x"C1",x"DF",x"DF",x"C1",x"F9",x"B9",x"81",x"FF", -- 0x05A8 - x"81",x"BF",x"BF",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05B0 - x"81",x"BD",x"FB",x"F7",x"E7",x"E7",x"E7",x"FF", -- 0x05B8 - x"C3",x"DB",x"DB",x"81",x"9D",x"9D",x"81",x"FF", -- 0x05C0 - x"81",x"BD",x"BD",x"81",x"F9",x"F9",x"81",x"FF", -- 0x05C8 - x"FF",x"FF",x"E7",x"FF",x"E7",x"E7",x"FF",x"FF", -- 0x05D0 - x"FF",x"FF",x"E3",x"FF",x"E3",x"E3",x"FB",x"FB", -- 0x05D8 - x"F1",x"E7",x"CF",x"9F",x"CF",x"E7",x"F1",x"FF", -- 0x05E0 - x"FF",x"FF",x"81",x"FF",x"81",x"81",x"FF",x"FF", -- 0x05E8 - x"8F",x"E7",x"F3",x"F9",x"F3",x"E7",x"8F",x"FF", -- 0x05F0 - x"81",x"BD",x"FD",x"C1",x"CF",x"FF",x"CF",x"FF", -- 0x05F8 - x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF", -- 0x0600 - x"E7",x"C3",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x0608 - x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF",x"EF", -- 0x0610 - x"FF",x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0618 - x"FF",x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0620 - x"FF",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0628 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF",x"FF", -- 0x0630 - x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF",x"DF", -- 0x0638 - x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB",x"FB", -- 0x0640 - x"FF",x"FF",x"FF",x"3F",x"CF",x"EF",x"F7",x"F7", -- 0x0648 - x"EF",x"EF",x"F7",x"F3",x"FC",x"FF",x"FF",x"FF", -- 0x0650 - x"F7",x"F7",x"EF",x"CF",x"3F",x"FF",x"FF",x"FF", -- 0x0658 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"00", -- 0x0660 - x"7F",x"BF",x"DF",x"EF",x"F7",x"FB",x"FD",x"FE", -- 0x0668 - x"FE",x"FD",x"FB",x"F7",x"EF",x"DF",x"BF",x"7F", -- 0x0670 - x"00",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0678 - x"00",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0680 - x"C3",x"81",x"81",x"81",x"81",x"81",x"C3",x"FF", -- 0x0688 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"FF", -- 0x0690 - x"DB",x"81",x"81",x"81",x"C3",x"E7",x"E7",x"FF", -- 0x0698 - x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF",x"BF", -- 0x06A0 - x"FF",x"FF",x"FF",x"FC",x"F3",x"F7",x"EF",x"EF", -- 0x06A8 - x"7E",x"BD",x"DB",x"E7",x"E7",x"DB",x"BD",x"7E", -- 0x06B0 - x"C3",x"81",x"99",x"BD",x"99",x"81",x"C3",x"FF", -- 0x06B8 - x"E7",x"E7",x"81",x"81",x"E7",x"E7",x"81",x"FF", -- 0x06C0 - x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD",x"FD", -- 0x06C8 - x"FF",x"E7",x"C3",x"81",x"81",x"C3",x"E7",x"FF", -- 0x06D0 - x"F7",x"F7",x"F7",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x06D8 - x"3F",x"CF",x"3F",x"CF",x"3F",x"CF",x"3F",x"CF", -- 0x06E0 - x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7",x"F7", -- 0x06E8 - x"FF",x"FF",x"83",x"DB",x"9B",x"9B",x"99",x"FF", -- 0x06F0 - x"00",x"80",x"C0",x"E0",x"F0",x"F8",x"FC",x"FE", -- 0x06F8 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0700 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0708 - x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0718 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00", -- 0x0720 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0728 - x"33",x"CC",x"33",x"CC",x"33",x"CC",x"33",x"CC", -- 0x0730 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0738 - x"FF",x"FF",x"FF",x"FF",x"33",x"CC",x"33",x"CC", -- 0x0740 - x"00",x"01",x"03",x"07",x"0F",x"1F",x"3F",x"7F", -- 0x0748 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0750 - x"F7",x"F7",x"F7",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0758 - x"FF",x"FF",x"FF",x"FF",x"F0",x"F0",x"F0",x"F0", -- 0x0760 - x"F7",x"F7",x"F7",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x0768 - x"FF",x"FF",x"FF",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0770 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00", -- 0x0778 - x"FF",x"FF",x"FF",x"F0",x"F7",x"F7",x"F7",x"F7", -- 0x0780 - x"F7",x"F7",x"F7",x"00",x"FF",x"FF",x"FF",x"FF", -- 0x0788 - x"FF",x"FF",x"FF",x"00",x"F7",x"F7",x"F7",x"F7", -- 0x0790 - x"F7",x"F7",x"F7",x"07",x"F7",x"F7",x"F7",x"F7", -- 0x0798 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x07A0 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F", -- 0x07A8 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x07B0 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07B8 - x"00",x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x07C0 - x"FF",x"FF",x"FF",x"FF",x"FF",x"00",x"00",x"00", -- 0x07C8 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"00", -- 0x07D0 - x"FF",x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F", -- 0x07D8 - x"F0",x"F0",x"F0",x"F0",x"FF",x"FF",x"FF",x"FF", -- 0x07E0 - x"F7",x"F7",x"F7",x"07",x"FF",x"FF",x"FF",x"FF", -- 0x07E8 - x"0F",x"0F",x"0F",x"0F",x"FF",x"FF",x"FF",x"FF", -- 0x07F0 - x"0F",x"0F",x"0F",x"0F",x"F0",x"F0",x"F0",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd b/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd deleted file mode 100644 index 95a9bd1..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_datasoft.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0000 - x"08",x"14",x"14",x"22",x"3E",x"41",x"41",x"80", -- 0x0008 - x"FC",x"42",x"42",x"7C",x"42",x"42",x"42",x"FC", -- 0x0010 - x"3C",x"46",x"40",x"40",x"40",x"40",x"46",x"3C", -- 0x0018 - x"FC",x"42",x"42",x"42",x"42",x"42",x"42",x"FC", -- 0x0020 - x"FC",x"46",x"50",x"70",x"50",x"40",x"46",x"FC", -- 0x0028 - x"FC",x"46",x"50",x"70",x"50",x"40",x"40",x"E0", -- 0x0030 - x"3C",x"46",x"40",x"4E",x"44",x"44",x"44",x"3C", -- 0x0038 - x"EE",x"44",x"44",x"7C",x"44",x"44",x"44",x"EE", -- 0x0040 - x"1C",x"08",x"08",x"08",x"08",x"08",x"08",x"1C", -- 0x0048 - x"1C",x"08",x"08",x"08",x"08",x"08",x"C8",x"70", -- 0x0050 - x"E6",x"48",x"50",x"60",x"50",x"48",x"44",x"EE", -- 0x0058 - x"E0",x"40",x"40",x"40",x"40",x"40",x"46",x"FC", -- 0x0060 - x"C6",x"6C",x"6C",x"54",x"54",x"44",x"44",x"EE", -- 0x0068 - x"CE",x"64",x"64",x"54",x"54",x"4C",x"4C",x"E6", -- 0x0070 - x"3C",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x0078 - x"FC",x"42",x"42",x"7C",x"40",x"40",x"40",x"E0", -- 0x0080 - x"3C",x"42",x"42",x"42",x"42",x"4A",x"46",x"3D", -- 0x0088 - x"FC",x"42",x"42",x"7C",x"50",x"48",x"44",x"EE", -- 0x0090 - x"3C",x"42",x"40",x"20",x"1C",x"02",x"C2",x"7C", -- 0x0098 - x"FE",x"92",x"10",x"10",x"10",x"10",x"10",x"38", -- 0x00A0 - x"E7",x"42",x"42",x"42",x"42",x"42",x"42",x"3C", -- 0x00A8 - x"E7",x"42",x"42",x"42",x"42",x"42",x"24",x"18", -- 0x00B0 - x"C3",x"41",x"5D",x"49",x"49",x"55",x"63",x"41", -- 0x00B8 - x"EE",x"44",x"28",x"10",x"10",x"28",x"44",x"EE", -- 0x00C0 - x"EE",x"44",x"44",x"28",x"10",x"10",x"10",x"38", -- 0x00C8 - x"FE",x"84",x"08",x"7C",x"24",x"40",x"82",x"FE", -- 0x00D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"10",x"10",x"10",x"10",x"10",x"00",x"10",x"10", -- 0x0108 - x"CC",x"44",x"44",x"22",x"00",x"00",x"00",x"00", -- 0x0110 - x"77",x"22",x"FF",x"22",x"22",x"FF",x"22",x"77", -- 0x0118 - x"10",x"3E",x"50",x"3C",x"12",x"12",x"7C",x"10", -- 0x0120 - x"87",x"42",x"04",x"08",x"10",x"20",x"44",x"E2", -- 0x0128 - x"3C",x"66",x"3C",x"38",x"67",x"66",x"3F",x"00", -- 0x0130 - x"1E",x"08",x"3C",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0E",x"12",x"60",x"40",x"40",x"60",x"12",x"0E", -- 0x0140 - x"70",x"48",x"06",x"02",x"02",x"06",x"48",x"70", -- 0x0148 - x"42",x"24",x"99",x"7E",x"99",x"24",x"42",x"00", -- 0x0150 - x"08",x"08",x"08",x"7F",x"08",x"08",x"08",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"03",x"06",x"0C",x"18",x"30",x"60",x"00", -- 0x0178 - x"7C",x"82",x"82",x"82",x"82",x"82",x"82",x"7C", -- 0x0180 - x"10",x"30",x"50",x"10",x"10",x"10",x"10",x"7C", -- 0x0188 - x"7C",x"C2",x"02",x"1C",x"60",x"80",x"86",x"FC", -- 0x0190 - x"7C",x"C2",x"02",x"1C",x"02",x"02",x"C2",x"7C", -- 0x0198 - x"08",x"18",x"28",x"48",x"FE",x"08",x"08",x"3E", -- 0x01A0 - x"FE",x"80",x"80",x"FC",x"02",x"02",x"C2",x"7C", -- 0x01A8 - x"7C",x"86",x"80",x"FC",x"82",x"82",x"82",x"7C", -- 0x01B0 - x"7E",x"C2",x"04",x"08",x"10",x"10",x"10",x"7C", -- 0x01B8 - x"7C",x"82",x"82",x"7C",x"82",x"82",x"82",x"7C", -- 0x01C0 - x"7C",x"82",x"82",x"7E",x"02",x"02",x"C2",x"7C", -- 0x01C8 - x"00",x"00",x"18",x"00",x"00",x"18",x"00",x"00", -- 0x01D0 - x"00",x"00",x"18",x"00",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0E",x"18",x"30",x"60",x"30",x"18",x"0E",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"70",x"18",x"0C",x"06",x"0C",x"18",x"70",x"00", -- 0x01F0 - x"3C",x"62",x"02",x"04",x"08",x"08",x"00",x"08", -- 0x01F8 - x"3C",x"66",x"6E",x"6E",x"60",x"62",x"3C",x"00", -- 0x0200 - x"FE",x"FE",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0208 - x"FE",x"FE",x"C6",x"FC",x"C6",x"C6",x"FE",x"FE", -- 0x0210 - x"FE",x"FE",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0218 - x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0220 - x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"FE",x"FE", -- 0x0228 - x"FE",x"FE",x"C0",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0230 - x"FE",x"FE",x"C0",x"DE",x"C6",x"C6",x"FE",x"FE", -- 0x0238 - x"C6",x"C6",x"C6",x"FE",x"C6",x"C6",x"C6",x"C6", -- 0x0240 - x"18",x"18",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x0248 - x"18",x"18",x"18",x"18",x"18",x"18",x"78",x"78", -- 0x0250 - x"C6",x"C6",x"DC",x"F0",x"D8",x"CC",x"C6",x"C6", -- 0x0258 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FE",x"FE", -- 0x0260 - x"FE",x"FE",x"D6",x"D6",x"D6",x"D6",x"D6",x"D6", -- 0x0268 - x"E6",x"E6",x"F6",x"D6",x"D6",x"DE",x"CE",x"CE", -- 0x0270 - x"FE",x"FE",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x0278 - x"FE",x"FE",x"C6",x"FE",x"C0",x"C0",x"C0",x"C0", -- 0x0280 - x"FE",x"FE",x"C6",x"C6",x"C6",x"CE",x"FE",x"FF", -- 0x0288 - x"FE",x"FE",x"C6",x"FE",x"D8",x"D8",x"C6",x"C6", -- 0x0290 - x"FE",x"FE",x"C0",x"FE",x"06",x"06",x"FE",x"FE", -- 0x0298 - x"FE",x"FE",x"18",x"18",x"18",x"18",x"18",x"18", -- 0x02A0 - x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"FE", -- 0x02A8 - x"C6",x"C6",x"C6",x"C6",x"C6",x"C6",x"FE",x"7C", -- 0x02B0 - x"D6",x"D6",x"D6",x"D6",x"D6",x"D6",x"FE",x"FE", -- 0x02B8 - x"C6",x"C6",x"6C",x"38",x"38",x"6C",x"C6",x"C6", -- 0x02C0 - x"C6",x"C6",x"C6",x"FE",x"06",x"06",x"FE",x"FE", -- 0x02C8 - x"FE",x"FE",x"0E",x"18",x"30",x"E0",x"FE",x"FE", -- 0x02D0 - x"3C",x"30",x"30",x"30",x"30",x"30",x"3C",x"00", -- 0x02D8 - x"0C",x"12",x"30",x"7C",x"30",x"62",x"FC",x"00", -- 0x02E0 - x"3C",x"0C",x"0C",x"0C",x"0C",x"0C",x"3C",x"00", -- 0x02E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x02F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"07",x"1F",x"3F",x"3F",x"7F", -- 0x0370 - x"00",x"00",x"00",x"E0",x"E0",x"E0",x"E0",x"E0", -- 0x0378 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"03",x"1F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0408 - x"FC",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"0F", -- 0x0410 - x"00",x"80",x"E0",x"F8",x"F8",x"FE",x"FE",x"FE", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"07",x"07", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"F8",x"FE", -- 0x0428 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"7F", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"C0",x"C0", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"1F",x"7F", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"E0",x"F8", -- 0x0468 - x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7F",x"7F", -- 0x0470 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"FF",x"FF", -- 0x0478 - x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC", -- 0x0480 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0488 - x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F1", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"7F",x"FF", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"80",x"E0", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"0F",x"3F", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"F0",x"F0", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0508 - x"03",x"01",x"01",x"01",x"01",x"01",x"01",x"01", -- 0x0510 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0518 - x"07",x"07",x"07",x"00",x"00",x"07",x"0F",x"3F", -- 0x0520 - x"FE",x"FF",x"FF",x"7F",x"3F",x"FF",x"FF",x"FF", -- 0x0528 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F", -- 0x0530 - x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"03", -- 0x0538 - x"7F",x"7F",x"7F",x"07",x"03",x"7F",x"FF",x"FF", -- 0x0540 - x"E0",x"F0",x"F1",x"F1",x"F3",x"F3",x"F3",x"F1", -- 0x0548 - x"7F",x"FF",x"FF",x"FC",x"F0",x"F0",x"F0",x"F8", -- 0x0550 - x"C0",x"C1",x"C1",x"03",x"03",x"03",x"03",x"03", -- 0x0558 - x"FF",x"FF",x"FF",x"FF",x"F8",x"F0",x"F0",x"F0", -- 0x0560 - x"FC",x"FE",x"FE",x"FF",x"7F",x"3F",x"3F",x"3F", -- 0x0568 - x"7F",x"7F",x"7F",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0570 - x"FF",x"FF",x"FF",x"0F",x"0F",x"0F",x"0F",x"0F", -- 0x0578 - x"FC",x"FC",x"FC",x"C0",x"C0",x"C0",x"C0",x"C0", -- 0x0580 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0588 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0590 - x"FF",x"FF",x"FF",x"F3",x"F1",x"F1",x"F1",x"F1", -- 0x0598 - x"F0",x"F0",x"F8",x"F9",x"F9",x"F9",x"F9",x"F9", -- 0x05A0 - x"7F",x"FF",x"FF",x"FC",x"F8",x"F8",x"F8",x"F8", -- 0x05A8 - x"F0",x"F0",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"3C",x"42",x"B9",x"A5",x"B9",x"A9",x"A5",x"42", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0608 - x"01",x"01",x"03",x"0F",x"7F",x"7F",x"7F",x"7F", -- 0x0610 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FC",x"FC", -- 0x0618 - x"3F",x"7F",x"7E",x"7C",x"7E",x"7F",x"3F",x"3F", -- 0x0620 - x"FF",x"FF",x"3F",x"3F",x"3F",x"BF",x"BF",x"BF", -- 0x0628 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"1F", -- 0x0630 - x"03",x"07",x"07",x"07",x"07",x"F7",x"F3",x"F3", -- 0x0638 - x"FF",x"FF",x"E3",x"C3",x"E3",x"FB",x"FB",x"FB", -- 0x0640 - x"F1",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0",x"F0", -- 0x0648 - x"FC",x"FE",x"7F",x"3F",x"1F",x"0F",x"07",x"03", -- 0x0650 - x"03",x"03",x"83",x"C3",x"E3",x"F1",x"F1",x"F0", -- 0x0658 - x"F0",x"F0",x"F0",x"F0",x"F8",x"FF",x"FF",x"FF", -- 0x0660 - x"3F",x"3F",x"3F",x"3F",x"7F",x"FE",x"FE",x"FC", -- 0x0668 - x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E",x"7E", -- 0x0670 - x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"0F",x"07", -- 0x0678 - x"C0",x"C0",x"C0",x"C0",x"C0",x"FC",x"FC",x"FC", -- 0x0680 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0688 - x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3",x"F3", -- 0x0690 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0698 - x"F9",x"F9",x"F9",x"F9",x"F9",x"F8",x"F8",x"F8", -- 0x06A0 - x"F8",x"F8",x"F8",x"F8",x"FC",x"FF",x"FF",x"7F", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"FC",x"FC",x"FC", -- 0x06B0 - x"3C",x"00",x"00",x"00",x"78",x"FC",x"FC",x"FC", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"7F",x"7F",x"7F",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"F0",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"0F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"BF",x"BF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"1F",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"F0",x"F0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"FB",x"7B",x"03",x"01",x"00",x"00",x"00",x"00", -- 0x0740 - x"F0",x"F8",x"FE",x"FF",x"FF",x"FF",x"3F",x"07", -- 0x0748 - x"03",x"07",x"1F",x"FF",x"FF",x"FF",x"FE",x"F0", -- 0x0750 - x"F0",x"F0",x"E0",x"E0",x"C0",x"80",x"00",x"00", -- 0x0758 - x"7F",x"1F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"F8",x"E0",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"7E",x"7E",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"07",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"07",x"07",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"F3",x"F3",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"F1",x"F1",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"F8",x"F8",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"3F",x"0F",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"FC",x"FC",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"FC",x"78",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd b/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd deleted file mode 100644 index ce977b6..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_demo_maker_m.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"3C",x"66",x"6E",x"6A",x"6E",x"60",x"3C",x"00", -- 0x0000 - x"00",x"00",x"3C",x"06",x"3E",x"66",x"3E",x"00", -- 0x0008 - x"60",x"60",x"7C",x"66",x"66",x"66",x"7C",x"00", -- 0x0010 - x"00",x"00",x"3C",x"66",x"60",x"66",x"3C",x"00", -- 0x0018 - x"06",x"06",x"3E",x"66",x"66",x"66",x"3E",x"00", -- 0x0020 - x"00",x"00",x"3C",x"66",x"7E",x"60",x"3C",x"00", -- 0x0028 - x"1C",x"30",x"30",x"7C",x"30",x"30",x"30",x"00", -- 0x0030 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"3C", -- 0x0038 - x"60",x"60",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0040 - x"18",x"00",x"38",x"18",x"18",x"18",x"3C",x"00", -- 0x0048 - x"18",x"00",x"38",x"18",x"18",x"18",x"18",x"70", -- 0x0050 - x"60",x"60",x"66",x"6C",x"78",x"6C",x"66",x"00", -- 0x0058 - x"38",x"18",x"18",x"18",x"18",x"18",x"3C",x"00", -- 0x0060 - x"00",x"00",x"36",x"7F",x"6B",x"6B",x"63",x"00", -- 0x0068 - x"00",x"00",x"7C",x"66",x"66",x"66",x"66",x"00", -- 0x0070 - x"00",x"00",x"3C",x"66",x"66",x"66",x"3C",x"00", -- 0x0078 - x"00",x"00",x"7C",x"66",x"66",x"7C",x"60",x"60", -- 0x0080 - x"00",x"00",x"3E",x"66",x"66",x"3E",x"06",x"07", -- 0x0088 - x"00",x"00",x"6C",x"76",x"60",x"60",x"60",x"00", -- 0x0090 - x"00",x"00",x"3E",x"60",x"3C",x"06",x"7C",x"00", -- 0x0098 - x"30",x"30",x"7C",x"30",x"30",x"30",x"1C",x"00", -- 0x00A0 - x"00",x"00",x"66",x"66",x"66",x"66",x"3E",x"00", -- 0x00A8 - x"00",x"00",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x00B0 - x"00",x"00",x"63",x"6B",x"6B",x"7F",x"36",x"00", -- 0x00B8 - x"00",x"00",x"66",x"3C",x"18",x"3C",x"66",x"00", -- 0x00C0 - x"00",x"00",x"66",x"66",x"66",x"3E",x"06",x"3C", -- 0x00C8 - x"00",x"00",x"7E",x"0C",x"18",x"30",x"7E",x"00", -- 0x00D0 - x"7C",x"60",x"60",x"60",x"60",x"60",x"7C",x"00", -- 0x00D8 - x"1C",x"36",x"30",x"7C",x"30",x"30",x"7E",x"00", -- 0x00E0 - x"3E",x"06",x"06",x"06",x"06",x"06",x"3E",x"00", -- 0x00E8 - x"00",x"18",x"3C",x"7E",x"18",x"18",x"18",x"18", -- 0x00F0 - x"00",x"10",x"30",x"7F",x"7F",x"30",x"10",x"00", -- 0x00F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0100 - x"18",x"18",x"18",x"18",x"18",x"00",x"18",x"00", -- 0x0108 - x"6C",x"6C",x"6C",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"36",x"36",x"7F",x"36",x"7F",x"36",x"36",x"00", -- 0x0118 - x"0C",x"3F",x"68",x"3E",x"0B",x"7E",x"18",x"00", -- 0x0120 - x"60",x"66",x"0C",x"18",x"30",x"66",x"06",x"00", -- 0x0128 - x"38",x"6C",x"6C",x"38",x"6D",x"66",x"3B",x"00", -- 0x0130 - x"0C",x"18",x"30",x"00",x"00",x"00",x"00",x"00", -- 0x0138 - x"0C",x"18",x"30",x"30",x"30",x"18",x"0C",x"00", -- 0x0140 - x"30",x"18",x"0C",x"0C",x"0C",x"18",x"30",x"00", -- 0x0148 - x"00",x"18",x"7E",x"3C",x"7E",x"18",x"00",x"00", -- 0x0150 - x"00",x"18",x"18",x"7E",x"18",x"18",x"00",x"00", -- 0x0158 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"30", -- 0x0160 - x"00",x"00",x"00",x"7E",x"00",x"00",x"00",x"00", -- 0x0168 - x"00",x"00",x"00",x"00",x"00",x"18",x"18",x"00", -- 0x0170 - x"00",x"06",x"0C",x"18",x"30",x"60",x"00",x"00", -- 0x0178 - x"3C",x"66",x"6E",x"7E",x"76",x"66",x"3C",x"00", -- 0x0180 - x"18",x"38",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0188 - x"3C",x"66",x"06",x"0C",x"18",x"30",x"7E",x"00", -- 0x0190 - x"3C",x"66",x"06",x"1C",x"06",x"66",x"3C",x"00", -- 0x0198 - x"0C",x"1C",x"3C",x"6C",x"7E",x"0C",x"0C",x"00", -- 0x01A0 - x"7E",x"60",x"7C",x"06",x"06",x"66",x"3C",x"00", -- 0x01A8 - x"1C",x"30",x"60",x"7C",x"66",x"66",x"3C",x"00", -- 0x01B0 - x"7E",x"06",x"0C",x"18",x"30",x"30",x"30",x"00", -- 0x01B8 - x"3C",x"66",x"66",x"3C",x"66",x"66",x"3C",x"00", -- 0x01C0 - x"3C",x"66",x"66",x"3E",x"06",x"0C",x"38",x"00", -- 0x01C8 - x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"00", -- 0x01D0 - x"00",x"00",x"18",x"18",x"00",x"18",x"18",x"30", -- 0x01D8 - x"0C",x"18",x"30",x"60",x"30",x"18",x"0C",x"00", -- 0x01E0 - x"00",x"00",x"7E",x"00",x"7E",x"00",x"00",x"00", -- 0x01E8 - x"30",x"18",x"0C",x"06",x"0C",x"18",x"30",x"00", -- 0x01F0 - x"3C",x"66",x"0C",x"18",x"18",x"00",x"18",x"00", -- 0x01F8 - x"00",x"00",x"00",x"FF",x"FF",x"00",x"00",x"00", -- 0x0200 - x"3C",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0208 - x"7C",x"66",x"66",x"7C",x"66",x"66",x"7C",x"00", -- 0x0210 - x"3C",x"66",x"60",x"60",x"60",x"66",x"3C",x"00", -- 0x0218 - x"78",x"6C",x"66",x"66",x"66",x"6C",x"78",x"00", -- 0x0220 - x"7E",x"60",x"60",x"7C",x"60",x"60",x"7E",x"00", -- 0x0228 - x"7E",x"60",x"60",x"7C",x"60",x"60",x"60",x"00", -- 0x0230 - x"3C",x"66",x"60",x"6E",x"66",x"66",x"3C",x"00", -- 0x0238 - x"66",x"66",x"66",x"7E",x"66",x"66",x"66",x"00", -- 0x0240 - x"7E",x"18",x"18",x"18",x"18",x"18",x"7E",x"00", -- 0x0248 - x"3E",x"0C",x"0C",x"0C",x"0C",x"6C",x"38",x"00", -- 0x0250 - x"66",x"6C",x"78",x"70",x"78",x"6C",x"66",x"00", -- 0x0258 - x"60",x"60",x"60",x"60",x"60",x"60",x"7E",x"00", -- 0x0260 - x"63",x"77",x"7F",x"6B",x"6B",x"63",x"63",x"00", -- 0x0268 - x"66",x"66",x"76",x"7E",x"6E",x"66",x"66",x"00", -- 0x0270 - x"3C",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x0278 - x"7C",x"66",x"66",x"7C",x"60",x"60",x"60",x"00", -- 0x0280 - x"3C",x"66",x"66",x"66",x"6A",x"6C",x"36",x"00", -- 0x0288 - x"7C",x"66",x"66",x"7C",x"6C",x"66",x"66",x"00", -- 0x0290 - x"3C",x"66",x"60",x"3C",x"06",x"66",x"3C",x"00", -- 0x0298 - x"7E",x"18",x"18",x"18",x"18",x"18",x"18",x"00", -- 0x02A0 - x"66",x"66",x"66",x"66",x"66",x"66",x"3C",x"00", -- 0x02A8 - x"66",x"66",x"66",x"66",x"66",x"3C",x"18",x"00", -- 0x02B0 - x"63",x"63",x"6B",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0300 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0308 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0310 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0318 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0320 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0328 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0330 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0338 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0340 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0348 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0350 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0358 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0360 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0368 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0370 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0378 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0380 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0388 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0390 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd deleted file mode 100644 index 3b60051..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x15.vhd +++ /dev/null @@ -1,4383 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 033 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "00111100", -- | #### | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 034 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 035 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00110110", -- | ## ## | 04 - "01111111", -- | #######| 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "00110110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 036 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00011000", -- | ## | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 037 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01110000", -- | ### | 02 - "11011000", -- |## ## | 03 - "11011010", -- |## ## # | 04 - "01110110", -- | ### ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01101110", -- | ## ### | 09 - "01011011", -- | # ## ##| 10 - "00011011", -- | ## ##| 11 - "00001110", -- | ### | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 038 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "11111111", -- |########| 13 - "00000000", -- | | 14 - -- ASCII 039 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 040 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 041 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 042 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00110110", -- | ## ## | 05 - "00011100", -- | ### | 06 - "01111111", -- | #######| 07 - "00011100", -- | ### | 08 - "00110110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 043 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 044 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - -- ASCII 045 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 046 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 047 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "01100000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 048 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110011", -- | ## ##| 04 - "00110111", -- | ## ###| 05 - "00110111", -- | ## ###| 06 - "00110011", -- | ## ##| 07 - "00111011", -- | ### ##| 08 - "00111011", -- | ### ##| 09 - "00110011", -- | ## ##| 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 049 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011100", -- | ### | 04 - "01111100", -- | ##### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 050 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 051 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00011100", -- | ### | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 052 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "00110110", -- | ## ## | 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 053 --------------- - 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"01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 133 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 134 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 135 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 136 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 137 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 138 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - "01111110", -- | ###### | 06 - "01111110", -- | ###### | 07 - "01111110", -- | ###### | 08 - "01111110", -- | ###### | 09 - "01111110", -- | ###### | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 139 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01111110", -- | ###### | 04 - "01111110", -- | ###### | 05 - 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"00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01111000", -- | #### | 05 - "00011000", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 240 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00011000", -- | ## | 04 - "01101100", -- | ## ## | 05 - "00011110", -- | #### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 241 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - 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"00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 246 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 247 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 248 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01101110", -- | ## ### | 07 - "01111110", -- | ###### | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 249 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 250 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 251 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 252 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 253 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 254 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - -- ASCII 255 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - -- ASCII 256 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 257 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 258 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 259 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 260 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 261 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 262 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 263 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 264 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 265 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 266 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 267 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 268 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 269 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 270 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 271 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 272 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 273 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 274 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 275 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 276 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 277 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 278 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 279 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 280 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 281 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 282 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 283 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 284 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 285 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 286 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- ASCII 287 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - -- Padding --------------- - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000", -- Padded - "00000000" -- Padded - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd deleted file mode 100644 index e46151c..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_8x16.vhd +++ /dev/null @@ -1,4382 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 033 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "00111100", -- | #### | 05 - "00111100", -- | #### | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 034 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100110", -- | ## ## | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 035 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110110", -- | ## ## | 03 - "00110110", -- | ## ## | 04 - "01111111", -- | #######| 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "00110110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00110110", -- | ## ## | 10 - "00110110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 036 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00011000", -- | ## | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100000", -- | ## | 05 - "00110000", -- | ## | 06 - "00011000", -- | ## | 07 - "00001100", -- | ## | 08 - "00000110", -- | ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00011000", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 037 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01110000", -- | ### | 02 - "11011000", -- |## ## | 03 - "11011010", -- |## ## # | 04 - "01110110", -- | ### ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00110000", -- | ## | 08 - "01101110", -- | ## ### | 09 - "01011011", -- | # ## ##| 10 - "00011011", -- | ## ##| 11 - "00001110", -- | ### | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 038 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "11111111", -- |########| 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 039 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 040 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "00110000", -- | ## | 07 - "00110000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00001100", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 041 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00011000", -- | ## | 11 - "00011000", -- | ## | 12 - "00110000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 042 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00110110", -- | ## ## | 05 - "00011100", -- | ### | 06 - "01111111", -- | #######| 07 - "00011100", -- | ### | 08 - "00110110", -- | ## ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 043 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011000", -- | ## | 05 - "00011000", -- | ## | 06 - "01111110", -- | ###### | 07 - "00011000", -- | ## | 08 - "00011000", -- | ## | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 044 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 045 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 046 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 047 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "01100000", -- | ## | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 048 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011110", -- | #### | 03 - "00110011", -- | ## ##| 04 - "00110111", -- | ## ###| 05 - "00110111", -- | ## ###| 06 - "00110011", -- | ## ##| 07 - "00111011", -- | ### ##| 08 - "00111011", -- | ### ##| 09 - "00110011", -- | ## ##| 10 - "00011110", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 049 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00001100", -- | ## | 03 - "00011100", -- | ### | 04 - "01111100", -- | ##### | 05 - "00001100", -- | ## | 06 - "00001100", -- | ## | 07 - "00001100", -- | ## | 08 - "00001100", -- | ## | 09 - "00001100", -- | ## | 10 - "00001100", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 050 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00001100", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 051 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00000110", -- | ## | 06 - "00011100", -- | ### | 07 - "00000110", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 052 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00110000", -- | ## | 03 - "00110000", -- | ## | 04 - "00110110", -- | ## ## | 05 - "00110110", -- | ## ## | 06 - "00110110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01111111", -- | #######| 09 - "00000110", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 053 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "00000110", -- | ## | 08 - "00000110", -- | ## | 09 - "00001100", -- | ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 054 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011100", -- | ### | 03 - "00011000", -- | ## | 04 - "00110000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 055 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "00000110", -- | ## | 04 - "00001100", -- | ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00110000", -- | ## | 09 - "00110000", -- | ## | 10 - "00110000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 056 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01110110", -- | ### ## | 06 - "00111100", -- | #### | 07 - "01101110", -- | ## ### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 057 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "00111110", -- | ##### | 08 - "00001100", -- | ## | 09 - "00011000", -- | ## | 10 - "00111000", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 058 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 059 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00011100", -- | ### | 05 - "00011100", -- | ### | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00011100", -- | ### | 10 - "00011100", -- | ### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 060 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000110", -- | ## | 03 - "00001100", -- | ## | 04 - "00011000", -- | ## | 05 - "00110000", -- | ## | 06 - "01100000", -- | ## | 07 - "00110000", -- | ## | 08 - "00011000", -- | ## | 09 - "00001100", -- | ## | 10 - "00000110", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 061 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "01111110", -- | ###### | 06 - "00000000", -- | | 07 - "01111110", -- | ###### | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 062 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "00110000", -- | ## | 04 - "00011000", -- | ## | 05 - "00001100", -- | ## | 06 - "00000110", -- | ## | 07 - "00001100", -- | ## | 08 - "00011000", -- | ## | 09 - "00110000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 063 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "00001100", -- | ## | 06 - "00011000", -- | ## | 07 - "00011000", -- | ## | 08 - "00000000", -- | | 09 - "00011000", -- | ## | 10 - "00011000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 064 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "11000011", -- |## ##| 04 - "11000011", -- |## ##| 05 - "11001111", -- |## ####| 06 - "11011011", -- |## ## ##| 07 - "11011011", -- |## ## ##| 08 - "11001111", -- |## ####| 09 - "11000000", -- |## | 10 - "01111111", -- | #######| 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 065 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00011000", -- | ## | 03 - "00111100", -- | #### | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01111110", -- | ###### | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01100110", -- | ## ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 066 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111100", -- | ##### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01111100", -- | ##### | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 067 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - "01100110", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100000", -- | ## | 06 - "01100000", -- | ## | 07 - "01100000", -- | ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 068 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111000", -- | #### | 03 - "01101100", -- | ## ## | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01101100", -- | ## ## | 10 - "01111000", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 069 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01111110", -- | ###### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 070 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01111110", -- | ###### | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01100000", -- | ## | 06 - "01111100", -- | ##### | 07 - "01100000", -- | ## | 08 - "01100000", -- | ## | 09 - "01100000", -- | ## | 10 - "01100000", -- | ## | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 071 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00111100", -- | #### | 03 - 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-- ASCII 243 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 244 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 245 --------------- - "00000000", -- | | 00 - "01110001", -- | ### #| 01 - "11011011", -- |## ## ##| 02 - "10001110", -- |# ### | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 246 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "00111100", -- | #### | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 247 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00011000", -- | ## | 04 - "00011000", -- | ## | 05 - "00000000", -- | | 06 - "01111110", -- | ###### | 07 - "00000000", -- | | 08 - "00011000", -- | ## | 09 - "00011000", -- | ## | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 248 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00111110", -- | ##### | 05 - "01100110", -- | ## ## | 06 - "01101110", -- | ## ### | 07 - "01111110", -- | ###### | 08 - "01110110", -- | ### ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 249 --------------- - "00000000", -- | | 00 - "01110000", -- | ### | 01 - "00110000", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 250 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 251 --------------- - "00000000", -- | | 00 - "00011000", -- | ## | 01 - "00111100", -- | #### | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 252 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111110", -- | ##### | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 253 --------------- - "00000000", -- | | 00 - "00001110", -- | ### | 01 - "00001100", -- | ## | 02 - "00011000", -- | ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 254 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "01100000", -- | ## | 03 - "01100000", -- | ## | 04 - "01100000", -- | ## | 05 - "01111100", -- | ##### | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "01111100", -- | ##### | 11 - "01100000", -- | ## | 12 - "01100000", -- | ## | 13 - "01100000", -- | ## | 14 - "00000000", -- | | 15 - -- ASCII 255 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "01100110", -- | ## ## | 02 - "01100110", -- | ## ## | 03 - "00000000", -- | | 04 - "01100110", -- | ## ## | 05 - "01100110", -- | ## ## | 06 - "01100110", -- | ## ## | 07 - "01100110", -- | ## ## | 08 - "01100110", -- | ## ## | 09 - "01100110", -- | ## ## | 10 - "00111100", -- | #### | 11 - "00001100", -- | ## | 12 - "00011000", -- | ## | 13 - "11110000", -- |#### | 14 - "00000000", -- | | 15 - -- ASCII 256 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 257 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 258 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 259 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 260 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 261 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 262 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 263 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 264 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 265 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 266 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 267 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 268 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 269 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 270 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 271 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 272 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 273 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 274 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 275 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 276 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 277 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 278 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 279 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 280 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 281 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 282 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 283 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 284 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 285 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 286 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "00000000", -- | | 12 - "00000000", -- | | 13 - "00000000", -- | | 14 - "00000000", -- | | 15 - -- ASCII 287 --------------- - "00000000", -- | | 00 - "00000000", -- | | 01 - "00000000", -- | | 02 - "00000000", -- | | 03 - "00000000", -- | | 04 - "00000000", -- | | 05 - "00000000", -- | | 06 - "00000000", -- | | 07 - "00000000", -- | | 08 - "00000000", -- | | 09 - "00000000", -- | | 10 - "00000000", -- | | 11 - "11111111", -- |########| 12 - "11111111", -- |########| 13 - "11111111", -- |########| 14 - "00000000" -- | | 15 - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd deleted file mode 100644 index 9b32d16..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_fixedsys_9x16.vhd +++ /dev/null @@ -1,4351 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(8 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(8 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 033 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000110000", -- | ## | 03 - "001111000", -- | #### | 04 - "001111000", -- | #### | 05 - "001111000", -- | #### | 06 - "000110000", -- | ## | 07 - "000110000", -- | ## | 08 - "000000000", -- | | 09 - "000110000", -- | ## | 10 - "000110000", -- | ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 034 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011001100", -- | ## ## | 03 - "011001100", -- | ## ## | 04 - "011001100", -- | ## ## | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 035 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "001101100", -- | ## ## | 03 - "001101100", -- | ## ## | 04 - "011111110", -- | ####### | 05 - "001101100", -- | ## ## | 06 - "001101100", -- | ## ## | 07 - "001101100", -- | ## ## | 08 - "011111110", -- | ####### | 09 - "001101100", -- | ## ## | 10 - "001101100", -- | ## ## | 11 - "000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 036 --------------- - "000000000", -- | | 00 - "000110000", -- | ## | 01 - "000110000", -- | ## | 02 - "001111000", -- | #### | 03 - "011001100", -- | ## ## | 04 - "011000000", -- | ## | 05 - "001100000", -- | ## | 06 - "000110000", -- | ## | 07 - "000011000", -- | ## | 08 - "000001100", -- | ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000110000", -- | ## | 12 - "000110000", -- | ## | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 037 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011100000", -- | ### | 02 - "110110000", -- |## ## | 03 - "110110100", -- |## ## # | 04 - "011101100", -- | ### ## | 05 - "000011000", -- | ## | 06 - "000110000", -- | ## | 07 - "001100000", -- | ## | 08 - "011011100", -- | ## ### | 09 - "010110110", -- | # ## ## | 10 - "000110110", -- | ## ## | 11 - "000011100", -- | ### | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 038 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "000000000", -- | | 03 - "000000000", -- | | 04 - "000000000", -- | | 05 - "000000000", -- | | 06 - "000000000", -- | | 07 - "000000000", -- | | 08 - "000000000", -- | | 09 - "000000000", -- | | 10 - "000000000", -- | | 11 - "000000000", -- | | 12 - "111111110", -- |######## | 13 - "000000000", -- | | 14 - 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"000000000", -- | | 12 - "000000000", -- | | 13 - "000000000", -- | | 14 - "000000000", -- | | 15 - -- ASCII 253 --------------- - "000000000", -- | | 00 - "000011100", -- | ### | 01 - "000011000", -- | ## | 02 - "000110000", -- | ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- ASCII 254 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "000000000", -- | | 02 - "011000000", -- | ## | 03 - "011000000", -- | ## | 04 - "011000000", -- | ## | 05 - "011111000", -- | ##### | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "011111000", -- | ##### | 11 - "011000000", -- | ## | 12 - "011000000", -- | ## | 13 - "011000000", -- | ## | 14 - "000000000", -- | | 15 - -- ASCII 255 --------------- - "000000000", -- | | 00 - "000000000", -- | | 01 - "011001100", -- | ## ## | 02 - "011001100", -- | ## ## | 03 - "000000000", -- | | 04 - "011001100", -- | ## ## | 05 - "011001100", -- | ## ## | 06 - "011001100", -- | ## ## | 07 - "011001100", -- | ## ## | 08 - "011001100", -- | ## ## | 09 - "011001100", -- | ## ## | 10 - "001111000", -- | #### | 11 - "000011000", -- | ## | 12 - "000110000", -- | ## | 13 - "111100000", -- |#### | 14 - "000000000", -- | | 15 - -- Padding --------------- - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - 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"000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000", -- Padded - "000000000" -- Padded - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd b/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd deleted file mode 100644 index d50d36f..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_system_16x16.vhd +++ /dev/null @@ -1,4382 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port - ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(15 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(15 downto 0); - constant ROM : ROM_ARRAY := - ( - -- ASCII 032 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 033 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0000000000000000", -- | | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 034 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100110000000000", -- |## ## | 03 - "1100110000000000", -- |## ## | 04 - "1100110000000000", -- |## ## | 05 - "1100110000000000", -- |## ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 035 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011011000000000", -- | ## ## | 03 - "0011011000000000", -- | ## ## | 04 - "0111111100000000", -- | ####### | 05 - "0011011000000000", -- | ## ## | 06 - "0011011000000000", -- | ## ## | 07 - "0110110000000000", -- | ## ## | 08 - "0110110000000000", -- | ## ## | 09 - "1111111000000000", -- |####### | 10 - "0110110000000000", -- | ## ## | 11 - "0110110000000000", -- | ## ## | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 036 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0001100000000000", -- | ## | 03 - "0011110000000000", -- | #### | 04 - "0110011000000000", -- | ## ## | 05 - "0110011000000000", -- | ## ## | 06 - "0110000000000000", -- | ## | 07 - "0011110000000000", -- | #### | 08 - "0000011000000000", -- | ## | 09 - "0000011000000000", -- | ## | 10 - "0110011000000000", -- | ## ## | 11 - "0011110000000000", -- | #### | 12 - "0001100000000000", -- | ## | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 037 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0111000001100000", -- | ### ## | 03 - "1101100011000000", -- |## ## ## | 04 - "1101100110000000", -- |## ## ## | 05 - "1101101100000000", -- |## ## ## | 06 - "0111011000000000", -- | ### ## | 07 - "0000110111000000", -- | ## ### | 08 - "0001101101100000", -- | ## ## ## | 09 - "0011001101100000", -- | ## ## ## | 10 - "0110001101100000", -- | ## ## ## | 11 - "1100000111000000", -- |## ### | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 038 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "1111000000000000", -- |#### | 14 - "0000000000000000", -- | | 15 - -- ASCII 039 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0110000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 040 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "0011000000000000", -- | ## | 15 - -- ASCII 041 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "1100000000000000", -- |## | 03 - "0110000000000000", -- | ## | 04 - "0110000000000000", -- | ## | 05 - "0110000000000000", -- | ## | 06 - "0110000000000000", -- | ## | 07 - "0110000000000000", -- | ## | 08 - "0110000000000000", -- | ## | 09 - "0110000000000000", -- | ## | 10 - "0110000000000000", -- | ## | 11 - "0110000000000000", -- | ## | 12 - "0110000000000000", -- | ## | 13 - "0110000000000000", -- | ## | 14 - "1100000000000000", -- |## | 15 - -- ASCII 042 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0011000000000000", -- | ## | 03 - "1111110000000000", -- |###### | 04 - "0011000000000000", -- | ## | 05 - "0111100000000000", -- | #### | 06 - "0100100000000000", -- | # # | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 043 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0001100000000000", -- | ## | 05 - "0001100000000000", -- | ## | 06 - "0001100000000000", -- | ## | 07 - "0111111000000000", -- | ###### | 08 - "0001100000000000", -- | ## | 09 - "0001100000000000", -- | ## | 10 - "0001100000000000", -- | ## | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 044 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - 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"0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 257 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 258 --------------- - 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"0000000000000000", -- | | 15 - -- ASCII 260 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 261 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 262 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 263 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 264 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 265 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 266 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 267 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 268 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 269 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 270 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 271 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 272 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 273 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 274 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 275 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 276 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 277 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 278 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 279 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 280 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 281 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 282 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 283 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 284 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 285 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 286 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000", -- | | 15 - -- ASCII 287 --------------- - "0000000000000000", -- | | 00 - "0000000000000000", -- | | 01 - "0000000000000000", -- | | 02 - "0000000000000000", -- | | 03 - "0000000000000000", -- | | 04 - "0000000000000000", -- | | 05 - "0000000000000000", -- | | 06 - "0000000000000000", -- | | 07 - "0000000000000000", -- | | 08 - "0000000000000000", -- | | 09 - "0000000000000000", -- | | 10 - "0000000000000000", -- | | 11 - "0000000000000000", -- | | 12 - "0000000000000000", -- | | 13 - "0000000000000000", -- | | 14 - "0000000000000000" -- | | 15 - ); -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; - -end RTL; - diff --git a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd b/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd deleted file mode 100644 index f5bbcc5..0000000 --- a/lib/VGA_ctrl/src/fonts/char_rom_the_goonies.vhd +++ /dev/null @@ -1,539 +0,0 @@ -library ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity char_rom is - port ( - CLK : in std_logic; - ADDR : in unsigned(11 downto 0); - DATA : out unsigned(7 downto 0) - ); -end; - -architecture RTL of char_rom is - - - type ROM_ARRAY is array(0 to 4095) of unsigned(7 downto 0); - constant ROM : ROM_ARRAY := ( - x"00",x"00",x"01",x"03",x"07",x"0F",x"0F",x"0F", -- 0x0000 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0008 - x"00",x"00",x"E0",x"F0",x"F8",x"FC",x"FC",x"FC", -- 0x0010 - x"00",x"00",x"01",x"07",x"1F",x"3F",x"7F",x"7F", -- 0x0018 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0020 - x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0028 - x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0030 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"8F", -- 0x0038 - x"00",x"00",x"C3",x"E3",x"F1",x"F1",x"F1",x"F1", -- 0x0040 - x"00",x"00",x"F8",x"FC",x"FE",x"FE",x"FE",x"FE", -- 0x0048 - x"00",x"00",x"1F",x"1F",x"0F",x"0F",x"0F",x"0F", -- 0x0050 - x"00",x"00",x"81",x"C3",x"E2",x"E2",x"E2",x"E2", -- 0x0058 - x"00",x"00",x"FC",x"06",x"FA",x"72",x"DA",x"FA", -- 0x0060 - x"00",x"00",x"03",x"0F",x"3F",x"7F",x"7F",x"7F", -- 0x0068 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"C7", -- 0x0070 - x"00",x"00",x"E0",x"F0",x"F8",x"F8",x"F8",x"F8", -- 0x0078 - x"00",x"00",x"07",x"1F",x"7F",x"FF",x"FF",x"FF", -- 0x0080 - x"00",x"00",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0088 - x"00",x"00",x"80",x"C0",x"C0",x"E0",x"E0",x"F0", -- 0x0090 - x"00",x"00",x"3F",x"3F",x"06",x"06",x"06",x"06", -- 0x0098 - x"00",x"00",x"D8",x"D8",x"18",x"1F",x"1F",x"18", -- 0x00A0 - x"00",x"00",x"DF",x"DF",x"D8",x"DE",x"DE",x"D8", -- 0x00A8 - x"00",x"00",x"80",x"80",x"00",x"00",x"00",x"00", -- 0x00B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x00F8 - x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"1F",x"3F", -- 0x0100 - x"C1",x"C0",x"C0",x"C0",x"C0",x"C0",x"C0",x"80", -- 0x0108 - x"FC",x"F8",x"F0",x"00",x"00",x"00",x"00",x"00", -- 0x0110 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0118 - x"FF",x"C3",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0120 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0128 - x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0130 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"07", -- 0x0138 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0140 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0148 - x"0F",x"0F",x"0F",x"8F",x"8F",x"8F",x"DF",x"FF", -- 0x0150 - x"E3",x"E3",x"E1",x"E0",x"E1",x"E1",x"E1",x"E3", -- 0x0158 - x"56",x"8E",x"FC",x"00",x"FF",x"FE",x"FE",x"FC", -- 0x0160 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0168 - x"83",x"03",x"03",x"0F",x"3F",x"FF",x"FF",x"FC", -- 0x0170 - x"F8",x"F8",x"F8",x"F8",x"F0",x"C0",x"00",x"00", -- 0x0178 - x"FF",x"FF",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0180 - x"E7",x"87",x"07",x"07",x"07",x"00",x"00",x"FF", -- 0x0188 - x"F0",x"F0",x"F0",x"E0",x"80",x"00",x"00",x"80", -- 0x0190 - x"06",x"06",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0198 - x"18",x"18",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A0 - x"DF",x"DF",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01A8 - x"80",x"80",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x01F8 - x"3F",x"3F",x"3F",x"3F",x"3F",x"3F",x"7F",x"7F", -- 0x0200 - x"80",x"80",x"80",x"83",x"87",x"87",x"07",x"06", -- 0x0208 - x"00",x"1C",x"7C",x"FC",x"FC",x"FC",x"F0",x"F0", -- 0x0210 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0218 - x"03",x"03",x"03",x"03",x"03",x"03",x"03",x"03", -- 0x0220 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0228 - x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE",x"FE", -- 0x0230 - x"07",x"07",x"07",x"07",x"07",x"07",x"07",x"0F", -- 0x0238 - x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1",x"F1", -- 0x0240 - x"FF",x"FF",x"FF",x"FF",x"FE",x"FC",x"FC",x"FC", -- 0x0248 - x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"7F",x"7F", -- 0x0250 - x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3", -- 0x0258 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FC", -- 0x0260 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0268 - x"F0",x"C0",x"03",x"07",x"07",x"07",x"03",x"01", -- 0x0270 - x"18",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0278 - x"FF",x"FF",x"FF",x"FC",x"E0",x"06",x"1E",x"FE", -- 0x0280 - x"FF",x"FF",x"FF",x"0F",x"07",x"07",x"07",x"07", -- 0x0288 - x"C0",x"C0",x"E0",x"E0",x"F0",x"F0",x"F0",x"F0", -- 0x0290 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0298 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x02F8 - x"7F",x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F", -- 0x0300 - x"00",x"00",x"00",x"80",x"FF",x"FF",x"FF",x"FF", -- 0x0308 - x"F0",x"78",x"7C",x"FC",x"FC",x"F8",x"F0",x"E0", -- 0x0310 - x"7F",x"7F",x"7F",x"7F",x"3F",x"1F",x"0F",x"07", -- 0x0318 - x"8F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0320 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F0",x"E0",x"C0", -- 0x0328 - x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"7F",x"3F", -- 0x0330 - x"1F",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0338 - x"F1",x"F1",x"F1",x"F1",x"E1",x"C1",x"81",x"03", -- 0x0340 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"FE",x"FF", -- 0x0348 - x"7F",x"3F",x"3F",x"3F",x"3F",x"1F",x"1F",x"1F", -- 0x0350 - x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"E3",x"C7", -- 0x0358 - x"FC",x"FC",x"FC",x"FC",x"FC",x"FC",x"F8",x"F0", -- 0x0360 - x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F",x"7F", -- 0x0368 - x"01",x"03",x"07",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0370 - x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8",x"F8", -- 0x0378 - x"FE",x"FE",x"FE",x"FF",x"FF",x"7F",x"1F",x"07", -- 0x0380 - x"07",x"07",x"0F",x"FF",x"FF",x"FF",x"FF",x"FF", -- 0x0388 - x"F0",x"F0",x"F0",x"F0",x"FF",x"EF",x"C3",x"83", -- 0x0390 - x"00",x"00",x"00",x"00",x"DB",x"DF",x"1F",x"1B", -- 0x0398 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x03F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0400 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0408 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0410 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0418 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0420 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0428 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0430 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0438 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0440 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0448 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0450 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0458 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0460 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0468 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0470 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0478 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0480 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0488 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0490 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0498 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x04F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0500 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0508 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0510 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0518 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0520 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0528 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0530 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0538 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0540 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0548 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0550 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0558 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0560 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0568 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0570 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0578 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0580 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0588 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0590 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0598 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x05F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0600 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0608 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0610 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0618 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0620 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0628 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0630 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0638 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0640 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0648 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0650 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0658 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0660 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0668 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0670 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0678 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0680 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0688 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0690 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0698 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x06F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0700 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0708 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0710 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0718 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0720 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0728 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0730 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0738 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0740 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0748 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0750 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0758 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0760 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0768 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0770 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0778 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0780 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0788 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0790 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0798 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x07F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0800 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0808 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0810 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0818 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0820 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0828 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0830 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0838 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0840 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0848 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0850 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0858 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0860 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0868 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0870 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0878 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0880 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0888 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0890 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0898 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x08F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0900 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0908 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0910 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0918 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0920 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0928 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0930 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0938 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0940 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0948 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0950 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0958 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0960 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0968 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0970 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0978 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0980 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0988 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0990 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0998 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09A8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09B8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09C8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09D8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09E8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x09F8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0A98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0AF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0B98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0BF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0C98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0CF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0D98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0DF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0E98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0ED8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0EF8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F00 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F08 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F10 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F18 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F20 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F28 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F30 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F38 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F40 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F48 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F50 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F58 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F60 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F68 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F70 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F78 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F80 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F88 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F90 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0F98 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FA8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FB8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FC8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FD8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FE8 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", -- 0x0FF0 - x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00" -- 0x0FF8 - ); - -begin - - p_rom : process - begin - wait until rising_edge(CLK); - DATA <= ROM(to_integer(unsigned(ADDR))); - end process; -end RTL; diff --git a/lib/VGA_ctrl/src/fonts/make_rom.bat b/lib/VGA_ctrl/src/fonts/make_rom.bat deleted file mode 100644 index 9cfa61b..0000000 --- a/lib/VGA_ctrl/src/fonts/make_rom.bat +++ /dev/null @@ -1,6 +0,0 @@ -@echo off - -bff2rom fixedsys_8x15.bff y >char_rom_fixedsys_8x15.vhd -bff2rom fixedsys_8x16.bff y >char_rom_fixedsys_8x16.vhd -bff2rom fixedsys_9x16.bff y >char_rom_fixedsys_9x16.vhd -bff2rom System_16x16.bff y >char_rom_system_16x16.vhd diff --git a/lib/VGA_ctrl/src/linefifo.vhd b/lib/VGA_ctrl/src/linefifo.vhd deleted file mode 100644 index 4336ede..0000000 --- a/lib/VGA_ctrl/src/linefifo.vhd +++ /dev/null @@ -1,121 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity linefifo is - Generic - ( - depth : natural := 64; - almost_full_thresh : natural := 60; - almost_empty_thresh : natural := 4 - ); - Port - ( - rst : in STD_LOGIC; - clk_w : in STD_LOGIC; - clk_r : in STD_LOGIC; - we_w : in STD_LOGIC; - re_r : in STD_LOGIC; - fifo_full : out STD_LOGIC; - fifo_empty : out STD_LOGIC; - fifo_afull : out STD_LOGIC; - fifo_aempty : out STD_LOGIC; - color_w : in color_t; - color_r : out color_t - ); -end linefifo; - -architecture Behavioral of linefifo is - - constant data_width : integer := 8; - constant addr_width : integer := NextExpBaseTwo(depth); - - signal buf_we_w : STD_LOGIC; - signal ptr_w : unsigned (ADDR_WIDTH-1 downto 0); - signal ptr_r : unsigned (ADDR_WIDTH-1 downto 0); - signal full : STD_LOGIC; - signal empty : STD_LOGIC; - signal almost_full : STD_LOGIC; - signal almost_empty : STD_LOGIC; - -begin - - buf_we_w <= we_w; - fifo_full <= full; - fifo_empty <= empty; - fifo_afull <= almost_full; - fifo_aempty <= almost_empty; - -gen_line: - for c in color_range_t generate - begin - inst_dpram: entity work.dpram - GENERIC MAP - ( - addr_width => addr_width, - data_width => data_width - ) - PORT MAP( - clka => clk_w, - clkb => clk_r, - en_a => '1', - en_b => '1', - we_a => buf_we_w, - addr_a => ptr_w, - addr_b => ptr_r, - din_a => color_w(c), - dout_b => color_r(c) - ); - end generate; - - inst_fifo_ctrl: entity work.async_fifo_ctrl - GENERIC MAP - ( - addr_width => ADDR_WIDTH, - almost_full_thresh => almost_full_thresh, - almost_empty_thresh => almost_empty_thresh - ) - PORT MAP - ( - rst => rst, - clk_w => clk_w, - clk_r => clk_r, - we => we_w, - re => re_r, - ptr_w => ptr_w, - ptr_r => ptr_r, - fifo_full => full, - fifo_empty => empty, - fifo_afull => almost_full, - fifo_aempty => almost_empty - - ); - -end Behavioral; - diff --git a/lib/VGA_ctrl/src/vga_backend.vhd b/lib/VGA_ctrl/src/vga_backend.vhd deleted file mode 100644 index 2994eec..0000000 --- a/lib/VGA_ctrl/src/vga_backend.vhd +++ /dev/null @@ -1,223 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_backend - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_backend is - Generic - ( - sys_freq : integer := 100E6; - fifo_depth : integer := 2048; - fifo_almost_full_thresh : natural := 2000; - fifo_almost_empty_thresh : natural := 48; - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - -- System signals - sys_rst : in std_logic; - sys_clk : in std_logic; - vga_ready : out std_logic; - - -- Buffered channel (Graphics plane) - color_in : in color_t; - color_fifo_we : in std_logic; - color_fifo_full : out std_logic; - color_fifo_afull : out std_logic; - - -- Direct channel (Character plane) - direct_color_in : in color_t; - direct_draw_en : in std_logic; - - -- Status signals - stat_hsync : out std_logic; - stat_vsync : out std_logic; - stat_hready : out std_logic; - stat_vready : out std_logic; - stat_hscan : out std_logic; - stat_vscan : out std_logic; - stat_hpos : out natural range 0 to tsvga.ts_h.ncyc_scan-1; - stat_vpos : out natural range 0 to tsvga.ts_v.ncyc_scan-1; - - -- VGA domain signals - vga_clk_out : out std_logic; - vga_color_out : out color_t; - vga_blank_n : out std_logic; - vga_sync_n : out std_logic; - vga_hsync : out std_logic; - vga_vsync : out std_logic - ); -end vga_backend; - -architecture Behavioral of vga_backend is - - signal scan_enable : std_logic; - signal fifo_full : std_logic; - signal fifo_empty : std_logic; - signal fifo_almost_empty : std_logic; - signal fifo_almost_full : std_logic; - signal is_scan : std_logic; - signal is_hscan : std_logic; - signal is_vscan : std_logic; - signal hsync : std_logic; - signal vsync : std_logic; - signal hready : std_logic; - signal vready : std_logic; - signal color : color_t; - signal vga_clk : std_logic; - signal dcm_locked : std_logic; - signal rst : std_logic; - -begin - - vga_clk_out <= vga_clk; - vga_ready <= dcm_locked; - - inst_clkgen: entity work.clkgen - GENERIC MAP - ( - sys_freq => sys_freq, - tsvga => tsvga - ) - PORT MAP - ( - rst => sys_rst, - clk => sys_clk, - vga_clk => vga_clk, - dcm_locked => dcm_locked - ); - - inst_vga_timing: entity work.vga_timing - GENERIC MAP - ( - tsvga => tsvga - ) - PORT MAP - ( - sys_rst => sys_rst, - vga_clk => vga_clk, - vga_ce => dcm_locked, - sync_h => hsync, - sync_v => vsync, - scan_pos_h => stat_hpos, - scan_pos_v => stat_vpos, - is_scan_h => is_hscan, - is_scan_v => is_vscan, - scan_rdy_h => hready, - scan_rdy_v => vready - ); - - inst_linefifo: entity work.linefifo - GENERIC MAP - ( - depth => fifo_depth, - almost_full_thresh => fifo_almost_full_thresh, - almost_empty_thresh => fifo_almost_empty_thresh - ) - PORT MAP( - rst => sys_rst, - clk_w => sys_clk, - clk_r => vga_clk, - we_w => color_fifo_we, - re_r => is_scan, - color_w => color_in, - color_r => color, - fifo_full => fifo_full, - fifo_empty => fifo_empty, - fifo_afull => fifo_almost_full, - fifo_aempty => fifo_almost_empty - - ); - - --------------------------------------------------------------------------------------------- - rst <= not dcm_locked; - stat_hsync <= hsync; - stat_vsync <= vsync; - stat_hscan <= is_hscan; - stat_vscan <= is_vscan; - stat_hready <= hready; - stat_vready <= vready; - - vga_blank_n <= '1'; - vga_sync_n <= '0'; - is_scan <= is_hscan and is_vscan and scan_enable; - - color_fifo_full <= fifo_full; - color_fifo_afull <= fifo_almost_full; - - --------------------------------------------------------------------------------------------- - proc_vga_start: - process (rst, vga_clk) - begin - if rst = '1' then - scan_enable <= '0'; - elsif rising_edge(vga_clk) then - if vsync = '1' then - if fifo_empty = '0' then - scan_enable <= '1'; - else - scan_enable <= '0'; - end if; - end if; - end if; - end process; - - proc_vga_color_out: - process (rst, vga_clk) - variable do_scan : std_logic; - begin - if rst = '1' then - do_scan := '0'; - elsif rising_edge(vga_clk) then - vga_color_out <= (X"00", X"00", X"00"); - if do_scan = '1' then - if direct_draw_en = '1' then - vga_color_out <= direct_color_in; - else - vga_color_out <= color; - end if; - end if; - do_scan := is_scan; - end if; - end process; - - --------------------------------------------------------------------------------------------- - proc_vga_sync_out: - process (rst, vga_clk) - variable hsync_r : std_logic; - variable vsync_r : std_logic; - begin - if rst = '1' then - vga_hsync <= tsvga.ts_h.sync_polarity; - vga_vsync <= tsvga.ts_v.sync_polarity; - hsync_r := tsvga.ts_h.sync_polarity; - vsync_r := tsvga.ts_v.sync_polarity; - elsif rising_edge(vga_clk) then - vga_hsync <= hsync_r; - vga_vsync <= vsync_r; - hsync_r := hsync xor (not tsvga.ts_h.sync_polarity); - vsync_r := vsync xor (not tsvga.ts_v.sync_polarity); - end if; - end process; - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_sync.vhd b/lib/VGA_ctrl/src/vga_sync.vhd deleted file mode 100644 index 56e4384..0000000 --- a/lib/VGA_ctrl/src/vga_sync.vhd +++ /dev/null @@ -1,127 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:15:39 10/21/05 --- Design Name: --- Module Name: fsm_scan - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_sync is - Generic - ( - ts : scan_timespec_t := (4,2,1,3,'0') - ); - Port - ( - rst : in std_logic; - clk : in std_logic; - ce : in std_logic; - pos : out natural range 0 to ts.ncyc_scan-1; - sync : out std_logic; - is_scan : out std_logic; - rdy_scan : out std_logic - ); - end vga_sync; - -architecture Behavioral of vga_sync is - - type timing_state_t is (st_init, st_scan, st_front, st_sync, st_back); - - -- Counter - signal state, next_state : timing_state_t; - signal count_srst : std_logic; - signal count : natural range 0 to ts.ncyc_scan-1; - -begin - - pos <= count; - ---------------------------------------------------------------------------------------------- -counter: - process (clk) - begin - if rising_edge(clk) then - if ce = '1' then - if count_srst = '1' then - count <= 0; - else - count <= count + 1; - end if; - end if; - end if; - end process; - ---------------------------------------------------------------------------------------------- -SYNC_TIMING: -process (state, count) - begin - count_srst <= '0'; - rdy_scan <= '0'; - is_scan <= '0'; - sync <= '0'; - - next_state <= state; --default is to stay in current state - - case (state) is - - when st_init => - count_srst <= '1'; - next_state <= st_front; - when st_front => - if count = ts.ncyc_porch_front - 1 then - count_srst <= '1'; - next_state <= st_sync; - end if; - when st_sync => - sync <= '1'; - if count = ts.ncyc_sync_pulse - 1 then - count_srst <= '1'; - next_state <= st_back; - end if; - when st_back => - if count = ts.ncyc_porch_back - 1 then - count_srst <= '1'; - next_state <= st_scan; - end if; - when st_scan => - is_scan <= '1'; - if count = ts.ncyc_scan - 1 then - count_srst <= '1'; - rdy_scan <= '1'; - next_state <= st_front; - end if; - when others => - next_state <= st_init; - - end case; - end process; - -SYNC_TIMING_NEXT: - process (rst, clk) - begin - if rst = '1' then - state <= st_init; - elsif rising_edge(clk) and ce = '1' then - state <= next_state; - end if; - end process; - ---------------------------------------------------------------------------------------------- -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_timing.vhd b/lib/VGA_ctrl/src/vga_timing.vhd deleted file mode 100644 index c110652..0000000 --- a/lib/VGA_ctrl/src/vga_timing.vhd +++ /dev/null @@ -1,102 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 11:25:45 10/15/05 --- Design Name: --- Module Name: vga_ctrl_core - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -use work.vga_types.all; - -entity vga_timing is - Generic - ( - tsvga : vga_timespec_t := ts_vga_800_600_72 - ); - Port - ( - sys_rst : in std_logic; - vga_clk : in std_logic; - vga_ce : in std_logic; - sync_h : out std_logic; - sync_v : out std_logic; - scan_pos_h : out natural range 0 to tsvga.ts_h.ncyc_scan-1; - scan_pos_v : out natural range 0 to tsvga.ts_v.ncyc_scan-1; - is_scan_h : out std_logic; - is_scan_v : out std_logic; - scan_rdy_h : out std_logic; - scan_rdy_v : out std_logic - ); -end vga_timing; - -architecture Behavioral of vga_timing is - - --------------------------------------------------------------------------------------------- - signal is_scan_h_i : std_logic; - signal is_scan_v_i : std_logic; - signal scan_rdy_h_i : std_logic; - signal scan_rdy_v_i : std_logic; - signal sync_h_i : std_logic; - signal sync_v_i : std_logic; - - --------------------------------------------------------------------------------------------- -begin - - is_scan_h <= is_scan_h_i; - is_scan_v <= is_scan_v_i; - scan_rdy_h <= scan_rdy_h_i; - scan_rdy_v <= scan_rdy_v_i; - sync_h <= sync_h_i; - sync_v <= sync_v_i; - - --------------------------------------------------------------------------------------------- - inst_vga_sync_h: entity work.vga_sync - GENERIC MAP - ( - ts => tsvga.ts_h - ) - PORT MAP - ( - rst => sys_rst, - clk => vga_clk, - ce => vga_ce, - pos => scan_pos_h, - sync => sync_h_i, - is_scan => is_scan_h_i, - rdy_scan => scan_rdy_h_i - ); - - inst_vga_sync_v: entity work.vga_sync - GENERIC MAP - ( - ts => tsvga.ts_v - ) - PORT MAP - ( - rst => sys_rst, - clk => vga_clk, - ce => scan_rdy_h_i, - pos => scan_pos_v, - sync => sync_v_i, - is_scan => is_scan_v_i, - rdy_scan => scan_rdy_v_i - ); - ---------------------------------------------------------------------------------------------- - -end Behavioral; diff --git a/lib/VGA_ctrl/src/vga_types.vhd b/lib/VGA_ctrl/src/vga_types.vhd deleted file mode 100644 index 44cecbd..0000000 --- a/lib/VGA_ctrl/src/vga_types.vhd +++ /dev/null @@ -1,213 +0,0 @@ --- Package File Template --- --- Purpose: This package defines supplemental types, subtypes, --- constants, and functions - - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -package vga_types is - - -- Constants - - -- Types - type color_range_t is (r, g, b); - type color_t is array (color_range_t) of unsigned(7 downto 0); - - type scan_timespec_t is - record - ncyc_scan : integer; - ncyc_porch_front : integer; - ncyc_sync_pulse : integer; - ncyc_porch_back : integer; - sync_polarity : std_logic; - end record; - - type vga_timespec_t is - record - f_pxl_clk : integer; - nfps : integer; - ts_h : scan_timespec_t; - ts_v : scan_timespec_t; - end record; - - ----------------------------------------------------------------------- - -- Common timimg specifications - ----------------------------------------------------------------------- - -- For test bench (not for H/W use) - constant ts_vga_testbench : vga_timespec_t := - ( - f_pxl_clk => 100E6, - nfps => 6, - ts_h => (8,5,2,3,'0'), - ts_v => (6,4,2,3,'0') - ); - - -- 640 x 480 @ 60 Hz (not recommended) - constant ts_vga_640_480_60 : vga_timespec_t := - ( - f_pxl_clk => 25175000, - nfps => 60, - ts_h => (640,16,96,48,'0'), - ts_v => (480,11,2,31,'0') - ); - - -- 640 x 480 @ 72 Hz (not recommended) - constant ts_vga_640_480_72 : vga_timespec_t := - ( - f_pxl_clk => 31500000, - nfps => 72, - ts_h => (640,24,40,128,'0'), - ts_v => (480,9,3,28,'0') - ); - - -- 800 x 600 @ 60 Hz (OK) - constant ts_vga_800_600_60 : vga_timespec_t := - ( - f_pxl_clk => 40000000, - nfps => 60, - ts_h => (800,40,128,88,'0'), - ts_v => (600,1,4,23,'0') - ); - - -- 800 x 600 @ 72 Hz (OK) - constant ts_vga_800_600_72 : vga_timespec_t := - ( - f_pxl_clk => 50000000, - nfps => 72, - ts_h => (800,56,120,64,'0'), - ts_v => (600,37,6,23,'0') - ); - - -- 1024 x 768 @ 60 Hz (Noisy) - constant ts_vga_1024_768_60 : vga_timespec_t := - ( - f_pxl_clk => 65000000, - nfps => 60, - ts_h => (1024,24,136,160,'0'), - ts_v => (768,3,6,29,'0') - ); - - -- 1024 x 768 @ 70 Hz (OK) - constant ts_vga_1024_768_70 : vga_timespec_t := - ( - f_pxl_clk => 75000000, - nfps => 70, - ts_h => (1024,24,136,144,'0'), - ts_v => (768,3,6,29,'0') - ); - - -- 1280 x 1024 @ 70 Hz (Noisy) - constant ts_vga_1280_1024_70 : vga_timespec_t := - ( - f_pxl_clk => 125000000, - nfps => 70, - ts_h => (1280,16,176,192,'0'), - ts_v => (1024,3,3,42,'0') - ); - - -- 1280 x 1024 @ 72 Hz (OK) - constant ts_vga_1280_1024_72 : vga_timespec_t := - ( - f_pxl_clk => 130000000, - nfps => 72, - ts_h => (1280,32,160,224,'0'), - ts_v => (1024,2,2,33,'0') - ); - - -- Functions - function NextPowerOfTwo(x : natural) return natural; - function NextExpBaseTwo(x : natural) return natural; - function GCD(a, b : natural) return natural; - function LCM(a, b : natural) return natural; - function DCM_PERIOD(f_sys_hz : natural) return real; - function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural; - function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural; - -end vga_types; - - -package body vga_types is - - function NextExpBaseTwo(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end NextExpBaseTwo; - - function NextPowerOfTwo(x : natural) return natural is - begin - - return 2**NextExpBaseTwo(x); - end NextPowerOfTwo; - - function GCD(a, b : natural) return natural is - variable aa : natural; - variable bb : natural; - begin - aa := a; - bb := b; - while bb /= 0 loop - if aa > bb then - aa := aa - bb; - else - bb := bb - aa; - end if; - end loop; - - return aa; - - end GCD; - - function LCM(a, b : natural) return natural is - begin - - return (a * b)/GCD(a, b); - - end LCM; - - function DCM_FREQ_M(f_sys_hz, f_vga_hz : natural) return natural is - variable f_sys_mhz : natural; - variable f_vga_mhz : natural; - variable m : natural; - begin - f_sys_mhz := f_sys_hz/1E6; - f_vga_mhz := f_vga_hz/1E6; - m := f_vga_mhz/GCD(f_sys_mhz, f_vga_mhz); - - if m = 1 then - m := 2; - end if; - - return m; - - end DCM_FREQ_M; - - function DCM_FREQ_D(f_sys_hz, f_vga_hz : natural) return natural is - variable f_sys_mhz : natural; - variable f_vga_mhz : natural; - variable m : natural; - variable d : natural; - begin - m := DCM_FREQ_M(f_sys_hz, f_vga_hz); - f_sys_mhz := f_sys_hz/1E6; - f_vga_mhz := f_vga_hz/1E6; - d := m*f_sys_mhz/f_vga_mhz; - - return d; - - end DCM_FREQ_D; - - function DCM_PERIOD(f_sys_hz : natural) return real is - begin - - return 1.0E9/real(f_sys_hz); - - end DCM_PERIOD; - - -end vga_types; - - diff --git a/lib/filter/sim/eval_lowpass.m b/lib/filter/sim/eval_lowpass.m deleted file mode 100644 index ccac021..0000000 --- a/lib/filter/sim/eval_lowpass.m +++ /dev/null @@ -1,37 +0,0 @@ -function eval_filter(N) -omega_lp = 0.15 -omega_hp = 0.05 - -omega_bp_m = 0.02; -bw2_bp = 0.02; - -lp = lowpass(N, omega_lp, 1.0); -coef_lp = hann(N)'.*lp./sum(lp.^2); - -hp = lowpass(N, 0.5-omega_hp, 1.0).*cos(pi*(0:N-1)); -coef_hp = hp./sum(hp.^2).*hann(N)'; - -bp = lowpass(N, bw2_bp/2, 1.0).*cos(2*pi*omega_bp_m*(0:N-1)); -coef_bp = bp./sum(bp.^2).*hann(N)'; - -abs_lp = 20*log10(abs(fft(coef_lp))); -abs_hp = 20*log10(abs(fft(coef_hp))); -abs_bp = 20*log10(abs(fft(coef_bp))); - -close all; -plot((0:N/2)/N, abs_lp(1:N/2+1));grid; -figure -plot((0:N/2)/N, abs_hp(1:N/2+1));grid; -figure -plot((0:N/2)/N, abs_bp(1:N/2+1));grid; - -figure -plot((0:N-1), coef_lp);grid; -figure -plot((0:N-1), coef_hp);grid; -figure -plot((0:N-1), coef_bp);grid; - -mean_lp = mean(coef_lp-mean(coef_lp)) -mean_hp = mean(coef_hp) -mean_bp = mean(coef_bp) diff --git a/lib/filter/sim/lowpass.m b/lib/filter/sim/lowpass.m deleted file mode 100644 index 292964d..0000000 --- a/lib/filter/sim/lowpass.m +++ /dev/null @@ -1,20 +0,0 @@ -function coef = lowpass(N, omega, scale) - -phi = 0; -dphi = 2*omega; -if (mod(N, 2) == 0) - M = N/2; - for i=0:M-1, - phi = phi + dphi; - coef(M+i+1) = scale*sinc(phi); - coef(M-i-1+1) = coef(M+i+1); - end; -else - M = (N-1)/2; - for i=1:M, - phi = phi + dphi; - coef(M+i+1) = scale*sinc(phi); - coef(M-i+1) = coef(M+i+1); - end; - coef(M+1) = scale*Sinc(0.0); -end; diff --git a/lib/filter/sim/tb_fir_iterative.fdo b/lib/filter/sim/tb_fir_iterative.fdo deleted file mode 100644 index d4f35ff..0000000 --- a/lib/filter/sim/tb_fir_iterative.fdo +++ /dev/null @@ -1,16 +0,0 @@ -vlib work -vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_stage_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/fir_iterative_pkg.vhd" -vcom -explicit -93 "../src/fir_iterative.vhd" -vcom -explicit -93 "../src/tb_fir_iterative.vhd" -vsim -t 1ps -lib work tb_fir_iterative -do {tb_fir_iterative.wdo} -view wave -view structure -view signals -run 20us diff --git a/lib/filter/sim/tb_fir_iterative.wdo b/lib/filter/sim/tb_fir_iterative.wdo deleted file mode 100644 index 1832c4e..0000000 --- a/lib/filter/sim/tb_fir_iterative.wdo +++ /dev/null @@ -1,86 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Literal /tb_fir_iterative/xi -add wave -noupdate -format Literal /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_clr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/fir_stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/cnt_reset -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xmem -add wave -noupdate -divider {Xmem Dual} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/srst -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/h_addr -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/ready -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_din -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/xo -add wave -noupdate -format Literal /tb_fir_iterative/coeffs -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_w -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/xtap_cnt_r -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/htap_cnt -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/xi -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_iterative/yo -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/stage_en -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/y_valid -add wave -noupdate -format Logic /tb_fir_iterative/y_valid -add wave -noupdate -format Analog-Step -radix decimal -scale 0.00061037000000000005 /tb_fir_iterative/uut_fir_iterative/y_dout -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/x_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/new_round -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/x_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/h_din -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/y_stage -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/ymem -add wave -noupdate -divider {FIR Stage} -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/clk -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/in_valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out_clr -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/h_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_in -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/xin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/hin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/yin -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/prod -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/x_out -add wave -noupdate -format Literal -radix hexadecimal /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/y_out -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/valid -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/p_valid -add wave -noupdate -format Literal /tb_fir_iterative/uut_fir_iterative/s -add wave -noupdate -format Logic /tb_fir_iterative/uut_fir_iterative/inst_fir_stage/out_valid -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1892287 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {1750644 ps} {2771198 ps} diff --git a/lib/filter/sim/tb_fir_parallel b/lib/filter/sim/tb_fir_parallel deleted file mode 100644 index f784c1a..0000000 Binary files a/lib/filter/sim/tb_fir_parallel and /dev/null differ diff --git a/lib/filter/sim/tb_fir_parallel.fdo b/lib/filter/sim/tb_fir_parallel.fdo deleted file mode 100644 index 9e15809..0000000 --- a/lib/filter/sim/tb_fir_parallel.fdo +++ /dev/null @@ -1,16 +0,0 @@ -vlib work -vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_stage_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/fir_parallel_pkg.vhd" -vcom -explicit -93 "../src/fir_parallel.vhd" -vcom -explicit -93 "../src/tb_fir_parallel.vhd" -vsim -t 1ps -lib work tb_fir_parallel -do {tb_fir_parallel.wdo} -view wave -view structure -view signals -run 1000us diff --git a/lib/filter/sim/tb_fir_parallel.wdo b/lib/filter/sim/tb_fir_parallel.wdo deleted file mode 100644 index f0e20ce..0000000 --- a/lib/filter/sim/tb_fir_parallel.wdo +++ /dev/null @@ -1,29 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_parallel/clk -add wave -noupdate -format Logic /tb_fir_parallel/srst -add wave -noupdate -format Logic /tb_fir_parallel/in_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/x_in -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/y_out -add wave -noupdate -format Logic /tb_fir_parallel/out_valid -add wave -noupdate -format Logic /tb_fir_parallel/fileout_enable -add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/xi -add wave -noupdate -format Analog-Interpolated -scale 10.0 /tb_fir_parallel/yo -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/coeff_in -add wave -noupdate -format Literal -radix decimal /tb_fir_parallel/uut_fir_parallel/h -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {19450000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {25152750 ps} diff --git a/lib/filter/sim/tb_fir_results.m b/lib/filter/sim/tb_fir_results.m deleted file mode 100644 index 75a542c..0000000 --- a/lib/filter/sim/tb_fir_results.m +++ /dev/null @@ -1,10 +0,0 @@ -% Read data -function tb_fir_results() -fir = TEXTREAD('fir.txt')'; - -N= length(fir); - -% Output -close all; -plot(0:N-1, fir); grid; - diff --git a/lib/filter/sim/tb_fir_stage.fdo b/lib/filter/sim/tb_fir_stage.fdo deleted file mode 100644 index 9b4379d..0000000 --- a/lib/filter/sim/tb_fir_stage.fdo +++ /dev/null @@ -1,14 +0,0 @@ -vlib work -vcom -explicit -93 "../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/filter_pkg.vhd" -vcom -explicit -93 "../src/fir_stage_pkg.vhd" -vcom -explicit -93 "../src/fir_stage.vhd" -vcom -explicit -93 "../src/tb_fir_stage.vhd" -vsim -t 1ps -lib work tb_fir_stage -do {tb_fir_stage.wdo} -view wave -view structure -view signals -run 2us diff --git a/lib/filter/sim/tb_fir_stage.wdo b/lib/filter/sim/tb_fir_stage.wdo deleted file mode 100644 index 916de83..0000000 --- a/lib/filter/sim/tb_fir_stage.wdo +++ /dev/null @@ -1,31 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_fir_stage/clk -add wave -noupdate -format Logic /tb_fir_stage/srst -add wave -noupdate -divider Input -add wave -noupdate -format Logic /tb_fir_stage/in_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x_in -add wave -noupdate -format Literal /tb_fir_stage/xi -add wave -noupdate -divider Output -add wave -noupdate -format Logic /tb_fir_stage/out_valid -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y_out -add wave -noupdate -format Analog-Step -scale 10.0 /tb_fir_stage/yo -add wave -noupdate -divider {Stage signals} -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/x -add wave -noupdate -format Literal -radix decimal /tb_fir_stage/y -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {1655000 ps} 0} -configure wave -namecolwidth 140 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {2100 ns} diff --git a/lib/filter/src/filter_pkg.vhd b/lib/filter/src/filter_pkg.vhd deleted file mode 100644 index 22be814..0000000 --- a/lib/filter/src/filter_pkg.vhd +++ /dev/null @@ -1,227 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use IEEE.MATH_REAL.ALL; - -------------------------------------------------------------------------------- -package filter_pkg is - - constant pi : real := 3.141592653589793e+000; - type real_array_t is array (natural range <>) of real; - - function FilterCoef_Lowpass (N : positive; omega, amp : real) return real_array_t; - function FilterCoef_Highpass (N : positive; omega, amp : real) return real_array_t; - function FilterCoef_Bandpass (N : positive; bw2, omega_m, amp : real) return real_array_t; - function FilterCoef_Delta (N:positive; delay:natural; amp:real) return real_array_t; - function Window_Hamming (x : real_array_t) return real_array_t; - function Window_VonHann (x : real_array_t) return real_array_t; - function Window_Blackman (x : real_array_t) return real_array_t; - function Sinc (x : real) return real; - function FilterEnergy (x : real_array_t) return real; - function FilterMean (x : real_array_t) return real; - function FilterScale (x : real_array_t; scale : real) return real_array_t; - function FilterTestCoef (N : positive) return real_array_t; - function NextPowerOfTwo(x : real) return natural; - -end; -- package filter_pkg; - -------------------------------------------------------------------------------- -package body filter_pkg is - - function Prototype_Lowpass (N : positive; omega : real) return real_array_t is - variable res : real_array_t(0 to N-1); - variable M : positive; - variable phi : real := 0.0; - variable dphi : real := 2.0*pi*omega; - begin - if (N mod 2) = 0 then - M := N/2; - for i in 0 to M-1 loop - phi := phi + dphi; - res(M+i) := Sinc(phi); - res(M-i-1) := res(M+i); - end loop; - else - M := (N-1)/2; - for i in 1 to M loop - phi := phi + dphi; - res(M+i) := Sinc(phi); - res(M-i) := res(M+i); - end loop; - res(M) := Sinc(0.0); - end if; - return res; - - end Prototype_Lowpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Lowpass (N : positive; omega, amp : real) return real_array_t is - variable lp : real_array_t(0 to N-1); - begin - lp := Prototype_Lowpass(N, omega); - - return Window_VonHann(FilterScale(lp, amp/FilterEnergy(lp))); - - end FilterCoef_Lowpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Highpass (N : positive; omega, amp : real) return real_array_t is - variable lp, res : real_array_t(0 to N-1); - variable phi : real := 0.0; - variable dphi : real := pi; - begin - lp := Prototype_Lowpass(N, 0.5-omega); - - for i in 0 to N-1 loop - res(i) := lp(i) * cos(phi); - phi := phi + dphi; - end loop; - - return Window_VonHann(FilterScale(res, amp/FilterEnergy(lp))); - - end FilterCoef_Highpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Bandpass (N : positive; bw2, omega_m, amp : real) return real_array_t is - variable lp, res, mean, sum : real_array_t(0 to N-1); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi*omega_m; - begin - lp := Prototype_Lowpass(N, bw2/2.0); - - for i in 0 to N-1 loop - res(i) := lp(i) * cos(phi); - phi := phi + dphi; - end loop; - - return Window_VonHann(FilterScale(res, amp/FilterEnergy(lp))); - - end FilterCoef_Bandpass; - - ------------------------------------------------------------------------------- - function FilterCoef_Delta (N:positive; delay:natural; amp:real) return real_array_t is - variable res : real_array_t(0 to N-1); - begin - for i in 0 to N-1 loop - res(i) := 0.0; - end loop; - res(delay) := amp; - - return res; - - end FilterCoef_Delta; - - ------------------------------------------------------------------------------- - function FilterTestCoef (N : positive) return real_array_t is - variable phi : real := 0.0; - variable dphi : real := 1.0/real(N); - variable res : real_array_t(0 to N-1); - begin - for i in 0 to N-1 loop - res(i) := phi; - phi := phi + dphi; - end loop; - return res; - - end FilterTestCoef; - - ------------------------------------------------------------------------------- - function Window_Hamming (x : real_array_t) return real_array_t is - variable res : real_array_t(x'range); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := x(i) * (0.54 - 0.46*(cos(phi))); - phi := phi + dphi; - end loop; - return res; - - end Window_Hamming; - - ------------------------------------------------------------------------------- - function Window_VonHann (x : real_array_t) return real_array_t is - variable res : real_array_t(x'range); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := 0.5 * x(i) * (1.0 - (cos(phi))); - phi := phi + dphi; - end loop; - return res; - - end Window_VonHann; - - ------------------------------------------------------------------------------- - function Window_Blackman (x : real_array_t) return real_array_t is - variable res : real_array_t(0 to x'length-1); - variable phi : real := 0.0; - variable dphi : real := 2.0*pi/real(x'length-1); - begin - for i in x'range loop - res(i) := x(i) * (0.42 - 0.5*cos(phi) + 0.08*cos(2.0*phi)); - phi := phi + dphi; - end loop; - return res; - - end Window_Blackman; - - ------------------------------------------------------------------------------- - function Sinc (x : real) return real is - variable res : real := 1.0; - begin - if x /= 0.0 then - res := sin(x)/x; - end if; - - return res; - - end Sinc; - - ------------------------------------------------------------------------------- - function FilterScale (x : real_array_t; scale : real) return real_array_t is - variable res : real_array_t(x'range); - begin - for i in x'range loop - res(i) := scale * x(i); - end loop; - - return res; - - end FilterScale; - - ------------------------------------------------------------------------------- - function FilterEnergy (x : real_array_t) return real is - variable res : real := 0.0; - begin - for i in x'range loop - res := res + x(i)*x(i); - end loop; - - return res; - - end FilterEnergy; - - ------------------------------------------------------------------------------- - function FilterMean (x : real_array_t) return real is - variable res : real := 0.0; - begin - for i in x'range loop - res := res + x(i); - end loop; - - return res/real(x'length); - - end FilterMean; - - ------------------------------------------------------------------------------- - function NextPowerOfTwo(x : real) return natural is - begin - return integer(ceil(log2(x))); - - end NextPowerOfTwo; - -------------------------------------------------------------------------------- -end; -- package filter_pkg; diff --git a/lib/filter/src/fir_iterative.vhd b/lib/filter/src/fir_iterative.vhd deleted file mode 100644 index 24805fd..0000000 --- a/lib/filter/src/fir_iterative.vhd +++ /dev/null @@ -1,352 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_parallel - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.fir_stage_pkg.all; -use work.fir_iterative_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_iterative is -Generic -( - ntaps : integer := 33; - nbits_in : integer := 12; - nbits_in_frac : integer := 11; - nbits_stages : integer := 13; - nbits_stages_frac : integer := 11; - nbits_out : integer := 12; - nbits_out_frac : integer := 11; - fir_mode : fir_iterative_mode_t := normal; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - h_din : in sfixed; - h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0); - ready : out std_logic; - x_valid : in std_logic; - x_din : in sfixed; - y_dout_valid : out std_logic; - y_dout : out sfixed -); -end fir_iterative; - -architecture Behavioral of fir_iterative is - -------------------------------------------------------------------------------- - -- Component Declaration for FIR stage - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed; - y_out_clr : in std_logic - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - constant fir_stage_mode : fir_stage_mode_t := transposed; - constant ntaps_is_even : boolean := (ntaps mod 2) = 0; - constant h_addr_bits : integer := taps_nbits(ntaps, fir_mode); - - subtype in_t is sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - subtype stage_t is sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low); - - type state_t is (init, idle, start, proc, p1, p2, output); - signal s, sn : state_t; - signal x_stage, xo, y_stage : stage_t; - signal stage_en, cnt_en, new_round : std_logic; - - subtype tap_cnt_t is natural range 0 to ntaps-1; - signal htap_cnt : tap_cnt_t; - signal xtap_cnt_w : tap_cnt_t; - signal xtap_cnt_r : tap_cnt_t; - signal stage_valid, clr_xmem, valid, fir_stage_clr, fir_stage_en, cnt_reset : std_logic; - subtype tap_range_t is natural range 0 to ntaps_addr(ntaps, fir_mode)-1; - signal h_addr : tap_range_t; - signal xmem_din, xmem_dout : in_t; - signal xmem_we, y_valid : std_logic; - - type xmem_t is array (0 to ntaps-1) of in_t; - signal xmem : xmem_t; - signal y_out_reg : stage_t; - signal y_reg_valid : std_logic; - - ------------------------------------------------------------------------------- -begin - - h_addr_out <= to_unsigned(h_addr, h_addr_bits); - x_stage <= resize(xmem_dout, x_stage, false, false); - - ---------------------------------------- - process (clk) - begin - if rising_edge(clk) then - y_reg_valid <= '0'; - if srst = '1' then - y_out_reg <= to_sfixed(0, sproto(nbits_out, nbits_out_frac)); - elsif y_valid = '1' then - y_out_reg <= y_stage; - y_reg_valid <= '1'; - end if; - end if; - end process; - - process (clk) - begin - if rising_edge(clk) then - y_dout_valid <= '0'; - if srst = '1' then - y_dout <= to_sfixed(0, sproto(nbits_out, nbits_out_frac)); - elsif y_reg_valid = '1' then - y_dout <= resize(y_out_reg, sproto(nbits_out, nbits_out_frac), rounding, saturating); - y_dout_valid <= '1'; - end if; - end if; - end process; - - ---------------------------------------- - proc_xmem_rw: process (clk) - begin - if rising_edge(clk) then - if xmem_we = '1' then - xmem(xtap_cnt_w) <= xmem_din; - end if; - xmem_dout <= xmem(xtap_cnt_r); - end if; - end process; - - ---------------------------------------- - proc_xmem_dinmux: process(new_round, clr_xmem, x_din, xmem_dout) - begin - xmem_din <= to_sfixed(0, xmem_din); - if new_round = '1' and clr_xmem = '0' then - xmem_din <= sfixed(x_din); - end if; - end process; - - ---------------------------------------- - proc_xmem_pointer: process(clk, new_round ,clr_xmem) - begin - xmem_we <= clr_xmem or new_round; - if rising_edge(clk) then - if srst = '1' then - xtap_cnt_w <= tap_cnt_t'high; - elsif xmem_we = '1' then - if xtap_cnt_w /= tap_cnt_t'low then - xtap_cnt_w <= xtap_cnt_w - 1; - else - xtap_cnt_w <= tap_cnt_t'high; - end if; - end if; - end if; - end process; - - ---------------------------------------- - proc_h_addr: process(htap_cnt) - begin - if fir_mode = symmetric then - if ntaps_is_even then - if htap_cnt > ntaps/2-1 then - h_addr <= ntaps - htap_cnt - 1; - else - h_addr <= htap_cnt; - end if; - else - if htap_cnt > (ntaps-1)/2 then - h_addr <= ntaps - htap_cnt - 1; - else - h_addr <= htap_cnt; - end if; - end if; - else - h_addr <= htap_cnt; - end if; - end process; - - ---------------------------------------- - proc_tap_counter: process(cnt_reset, clk, htap_cnt, xtap_cnt_r, xtap_cnt_w, cnt_en) - begin - if rising_edge(clk) then - if cnt_reset = '1' then - htap_cnt <= tap_cnt_t'low; - xtap_cnt_r <= xtap_cnt_w; - elsif cnt_en = '1' then - if htap_cnt /= tap_cnt_t'high then - htap_cnt <= htap_cnt + 1; - else - htap_cnt <= tap_cnt_t'low; - end if; - if xtap_cnt_r /= tap_cnt_t'high then - xtap_cnt_r <= xtap_cnt_r + 1; - else - xtap_cnt_r <= tap_cnt_t'low; - end if; - end if; - end if; - end process; - - ---------------------------------------- - proc_valid_out: process(srst, clk, valid, new_round) - variable val_pipe : unsigned(4 downto 0); - variable ctrl_pipe : unsigned(2 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - ctrl_pipe := (others => '0'); - fir_stage_en <= '0'; - fir_stage_clr <= '0'; - else - ctrl_pipe := ctrl_pipe(ctrl_pipe'left-1 downto ctrl_pipe'right) & new_round; - fir_stage_en <= stage_en; - fir_stage_clr <= ctrl_pipe(2); - end if; - end if; - cnt_reset <= new_round; - end process; - - ---------------------------------------- - proc_fsm: process(s, x_valid, htap_cnt, xtap_cnt_w) - begin - clr_xmem <= '0'; - new_round <= '0'; - cnt_en <= '0'; - ready <= '0'; - valid <= '0'; - sn <= s; - stage_en <= '0'; - y_valid <= '0'; - - case s is - when init => - clr_xmem <= '1'; - if xtap_cnt_w = tap_cnt_t'low then - sn <= idle; - end if; - - when idle => - ready <= '1'; - if x_valid = '1' then - sn <= start; - end if; - - when start => - new_round <= '1'; - sn <= proc; - - when proc => - stage_en <= '1'; - cnt_en <= '1'; - if htap_cnt = tap_cnt_t'high then - sn <= p1; - end if; - - when p1 => - sn <= p2; - - when p2 => - sn <= output; - ready <= '1'; - - when output => - sn <= idle; - y_valid <= '1'; - ready <= '1'; - if x_valid = '1' then - sn <= start; - end if; - - when others => null; - end case; - end process; - - proc_fsm_next: process(srst, clk, sn) - begin - if rising_edge(clk) then - if srst = '1' then - s <= init; - else - s <= sn; - end if; - end if; - end process; - - ---------------------------------------- - inst_fir_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => true, - has_pipe_reg => true, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => fir_stage_en, - x_in => x_stage, - y_in => y_stage, - h_in => h_din, - out_valid => stage_valid, - x_out => xo, - y_out_clr => fir_stage_clr, - y_out => y_stage - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - -end Behavioral; diff --git a/lib/filter/src/fir_iterative_pkg.vhd b/lib/filter/src/fir_iterative_pkg.vhd deleted file mode 100644 index 3d71626..0000000 --- a/lib/filter/src/fir_iterative_pkg.vhd +++ /dev/null @@ -1,45 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -use ieee.numeric_std.all; -use work.fixed_pkg.all; -use work.filter_pkg.all; - -------------------------------------------------------------------------------- -package fir_iterative_pkg is - - type fir_iterative_mode_t is (normal, symmetric); - - function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer; - function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer; - -end; -- package fir_iterative_pkg; - -------------------------------------------------------------------------------- -package body fir_iterative_pkg is - - function taps_nbits(ntaps : integer; mode : fir_iterative_mode_t) return integer is - variable res : integer; - begin - res := NextPowerOfTwo(real(ntaps_addr(ntaps, mode))); - return res; - end taps_nbits; - - function ntaps_addr(ntaps : integer; mode : fir_iterative_mode_t) return integer is - constant ntaps_is_even : boolean := (ntaps mod 2) = 0; - variable res : integer := ntaps; - begin - if mode = symmetric then - if ntaps_is_even then - res := ntaps/2; - else - res := (ntaps-1)/2 + 1; - end if; - end if; - return res; - end ntaps_addr; - -end; -- package fir_iterative_pkg; - -------------------------------------------------------------------------------- diff --git a/lib/filter/src/fir_parallel.vhd b/lib/filter/src/fir_parallel.vhd deleted file mode 100644 index a46dba9..0000000 --- a/lib/filter/src/fir_parallel.vhd +++ /dev/null @@ -1,208 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_parallel - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.fir_stage_pkg.all; -use work.fir_parallel_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_parallel is -Generic -( - ntaps : integer := 33; - nbits_in : integer := 12; - nbits_in_frac : integer := 11; - nbits_stages : integer := 13; - nbits_stages_frac : integer := 11; - nbits_out : integer := 12; - nbits_out_frac : integer := 11; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - fir_mode : fir_parallel_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - h_in : in sfixed_array_t; - in_valid : in std_logic; - d_in : in sfixed; - out_valid : out std_logic; - d_out : out sfixed -); -end fir_parallel; - -architecture Behavioral of fir_parallel is - -------------------------------------------------------------------------------- - -- Component Declaration for FIR stage - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - type coeff_array_t is array (natural range <>) of sfixed(SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac)); - type stages_array_t is array (natural range <>) of sfixed(SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac)); - - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - constant fir_stage_mode : fir_stage_mode_t := transposed; - - SIGNAL x_out : sfixed(SFix_high(nbits_out, nbits_out_frac) downto SFix_low(nbits_out, nbits_out_frac)); - - SIGNAL x : stages_array_t(0 to ntaps-2); - SIGNAL y : stages_array_t(0 to ntaps-2); - SIGNAL h : coeff_array_t(0 to ntaps-1); - - ------------------------------------------------------------------------------- -begin - - -- Assign coefficients - assign_coeffs: - for i in 0 to ntaps-1 generate - h(i) <= to_sfixed(h_in, i); - end generate; - - ---------------------------------------- - -- Instantiate the FIR stages - ---------------------------------------- - uut_first_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => d_in, - y_in => zero_in, - h_in => h(ntaps-1), - out_valid => out_valid, - x_out => x(0), - y_out => y(0) - ); - - ---------------------------------------- - gen_stages: - for i in 1 to ntaps-2 generate - uut_stages: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(i-1), - y_in => y(i-1), - h_in => h(ntaps-i-1), - out_valid => open, - x_out => x(i), - y_out => y(i) - ); - end generate; - - ---------------------------------------- - uut_last_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_stage_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(ntaps-2), - y_in => y(ntaps-2), - h_in => h(0), - out_valid => open, - x_out => x_out, - y_out => d_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - -end Behavioral; diff --git a/lib/filter/src/fir_parallel_pkg.vhd b/lib/filter/src/fir_parallel_pkg.vhd deleted file mode 100644 index 1f8c44c..0000000 --- a/lib/filter/src/fir_parallel_pkg.vhd +++ /dev/null @@ -1,76 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use work.fixed_pkg.all; -use work.filter_pkg.all; - -------------------------------------------------------------------------------- -package fir_parallel_pkg is - - type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - - type fir_parallel_mode_t is (transposed, transposed_sym, systolic, systolic_sym); - - function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t; - function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t; - - -- Slicing functions for unconstrained array types - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed; - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed; - -end; -- package fir_parallel_pkg; - -------------------------------------------------------------------------------- -package body fir_parallel_pkg is - - function to_sfixed_array(x : real_array_t; proto : sfixed) return sfixed_array_t is - variable res : sfixed_array_t(0 to x'length-1, proto'range); - variable tt : sfixed(proto'range); - begin - for i in x'range loop - tt := to_sfixed(x(i), proto); - for j in proto'range loop - res(i,j) := tt(j); - end loop; - end loop; - return res; - end to_sfixed_array; - - --------------------------------------------------------------------------- - function to_sfixed_array(x : real_array_t; nbits, nbits_int : integer) return sfixed_array_t is - variable p : sfixed(SFix_high(nbits, nbits_int) downto SFix_low(nbits, nbits_int)); - begin - return to_sfixed_array(x, p); - end to_sfixed_array; - - ------------------------------------------------------------------------------- - -- ufixed <= ufixed_array(i) - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed is - variable dst : ufixed(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_ufixed; - - ------------------------------------------------------------------------------- - -- sfixed <= sfixed_array(i) - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed is - variable dst : sfixed(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_sfixed; - -end; -- package fir_parallel_pkg; - -------------------------------------------------------------------------------- diff --git a/lib/filter/src/fir_stage.vhd b/lib/filter/src/fir_stage.vhd deleted file mode 100644 index c8c4a7c..0000000 --- a/lib/filter/src/fir_stage.vhd +++ /dev/null @@ -1,150 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: fir_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.fir_stage_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity fir_stage is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - fir_mode : fir_stage_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed; - y_out_clr : in std_logic -); -end fir_stage; - -architecture Behavioral of fir_stage is - -signal xin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal yin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal hin : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal prod : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg_y: process(clk) - begin - if rising_edge(clk) then - if srst = '1' or y_out_clr = '1' then - yin <= to_sfixed(0, yin); - else - yin <= resize(y_in, yin); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_in_reg_hx: process(srst, clk, in_valid, x_in, h_in) - variable p : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - xin <= to_sfixed(0, xin); - hin <= to_sfixed(0, hin); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - xin <= resize(x_in, xin); - hin <= resize(h_in, hin); - end if; - end if; - end if; - else - xin <= resize(x_in, xin); - hin <= resize(h_in, hin); - valid <= in_valid; - end if; - x_out <= resize(x_in, p); - - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, xin, hin) - variable p : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - p := resize(xin * hin, p); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - prod <= to_sfixed(0, prod); - p_valid <= '0'; - else - prod <= p; - p_valid <= valid; - end if; - end if; - else - prod <= p; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, prod, yin) - variable yout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - yout := resize(yin + prod, yout, rounding, saturating); --- if rising_edge(clk) then --- if srst = '1' or y_out_clr = '1' then --- y_out <= to_sfixed(0, yout); --- out_valid <= '0'; --- else --- y_out <= yout; --- out_valid <= p_valid; --- end if; --- end if; - out_valid <= p_valid; - y_out <= yout; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/filter/src/fir_stage_pkg.vhd b/lib/filter/src/fir_stage_pkg.vhd deleted file mode 100644 index 8bccba2..0000000 --- a/lib/filter/src/fir_stage_pkg.vhd +++ /dev/null @@ -1,38 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use work.fixed_pkg.all; - -package fir_stage_pkg is - -type fir_stage_mode_t is (transposed, systolic); - - ------------------------------------------------------------- - -- Constructor helpers - -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range); - function uproto (nbits : integer; nbits_frac : integer) return ufixed; - - -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range); - function sproto (nbits : integer; nbits_frac : integer) return sfixed; - -end; -- package fir_stage_pkg; - -package body fir_stage_pkg is - - ------------------------------------------------------------- - -- Constuctor helpers - function uproto (nbits : integer; nbits_frac : integer) return ufixed is - constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0'); - begin - return result(nbits-nbits_frac-1 downto -nbits_frac); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_frac : integer) return sfixed is - constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0'); - begin - return result(nbits-nbits_frac downto -nbits_frac+1); - end sproto; - -end; -- package fir_stage_pkg; diff --git a/lib/filter/src/tb_fir_iterative.vhd b/lib/filter/src/tb_fir_iterative.vhd deleted file mode 100644 index 2621a05..0000000 --- a/lib/filter/src/tb_fir_iterative.vhd +++ /dev/null @@ -1,231 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.filter_pkg.all; -use work.fir_stage_pkg.all; -use work.fir_iterative_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_iterative IS - Generic ( - ntaps : integer := 11; - nbits_in : integer := 15; - nbits_in_frac : integer := 15; - nbits_stages : integer := 15; - nbits_stages_frac : integer := 15; - nbits_out : integer := 15; - nbits_out_frac : integer := 15; - fir_mode : fir_iterative_mode_t := symmetric; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_iterative; - -ARCHITECTURE behavior OF tb_fir_iterative IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_iterative - GENERIC - ( - ntaps : integer; - nbits_in : integer; - nbits_in_frac : integer; - nbits_stages : integer; - nbits_stages_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - fir_mode : fir_iterative_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - h_din : in sfixed; - h_addr_out : out unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0); - ready : out std_logic; - x_valid : in std_logic; - x_din : in sfixed; - y_dout_valid : out std_logic; - y_dout : out sfixed - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - --Constants - constant nsamples : integer := 32; - - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL x_valid : std_logic := '0'; - SIGNAL h_din : sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low); - SIGNAL x_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL y_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL y_valid : std_logic; - SIGNAL ready : std_logic; - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients --- SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Delta(ntaps, 10, 0.999)(0 to ntaps_addr(ntaps, fir_mode)-1); - SIGNAL coeffs : real_array_t(0 to ntaps_addr(ntaps, fir_mode)-1) := FilterCoef_Bandpass(ntaps, 0.25, 0.125, 1.0)(0 to ntaps_addr(ntaps, fir_mode)-1); --- SIGNAL coeffs : real_array_t(0 to ntaps-1) := FilterTestCoef(ntaps); - signal x_input : real_array_t(0 to nsamples-1) := - ( - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.9999, - -0.0000, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0, - 0.0 - - ); - type ymem_t is array (0 to nsamples-1) of sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - signal ymem : ymem_t; - - signal y_cnt : integer ; - SIGNAL xi, yo : real := 0.0; - SIGNAL h_addr : unsigned(taps_nbits(ntaps, fir_mode)-1 downto 0); - - -- file I/O - subtype sample_t is integer range -32768 to 32767; - type file_t is file of sample_t; - - ------------------------------------------------------------------------------- -BEGIN - - xi <= to_real(x_din); - yo <= to_real(y_dout); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_fir_iterative: fir_iterative - GENERIC MAP - ( - ntaps => ntaps, - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_stages => nbits_stages, - nbits_stages_frac => nbits_stages_frac, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - h_din => h_din, - h_addr_out => h_addr, - ready => ready, - x_valid => x_valid, - x_din => x_din, - y_dout_valid => y_valid, - y_dout => y_dout - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - for i in 0 to nsamples-1 loop - if i = nsamples/2 then - wait for 43*PERIOD; - end if; - ------------------------------------------ - wait until rising_edge(clk) and ready = '1'; - x_din <= to_sfixed(x_input(i), x_din); - x_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_valid <= '0'; - end loop; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - process(srst, clk, y_valid) - begin - if rising_edge(clk) then - h_din <= to_sfixed(coeffs(to_integer(h_addr)), h_din); - if srst = '1' then - y_cnt <= 0; - - elsif y_valid = '1' then - ymem(y_cnt) <= y_dout; - y_cnt <= y_cnt + 1; - end if; - end if; - end process; - -END; diff --git a/lib/filter/src/tb_fir_parallel.vhd b/lib/filter/src/tb_fir_parallel.vhd deleted file mode 100644 index bb87e21..0000000 --- a/lib/filter/src/tb_fir_parallel.vhd +++ /dev/null @@ -1,189 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.fir_parallel_pkg.all; -use work.filter_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_parallel IS - Generic ( - ntaps : integer := 33; - nbits_in : integer := 15; - nbits_in_frac : integer := 15; - nbits_stages : integer := 16; - nbits_stages_frac : integer := 15; - nbits_out : integer := 15; - nbits_out_frac : integer := 15; - has_in_reg : boolean := false; - has_pipe_reg : boolean := true; - has_out_reg : boolean := false; - fir_mode : fir_parallel_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_parallel; - -ARCHITECTURE behavior OF tb_fir_parallel IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_parallel - GENERIC - ( - ntaps : integer; - nbits_in : integer; - nbits_in_frac : integer; - nbits_stages : integer; - nbits_stages_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_parallel_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - h_in : in sfixed_array_t; - in_valid : in std_logic; - d_in : in sfixed; - out_valid : out std_logic; - d_out : out sfixed - ); - END COMPONENT; - - ------------------------------------------------------------------------------- - --Constants - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_in : sfixed(SFix_high(nbits_in, nbits_in_frac) downto SFix_low(nbits_in, nbits_in_frac)); - - --Outputs - SIGNAL y_out : sfixed(SFix_high(nbits_out, nbits_out_frac) downto SFix_low(nbits_out, nbits_out_frac)); - SIGNAL out_valid : std_logic := '0'; - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients - SIGNAL coeff_in : sfixed_array_t(0 to ntaps-1, SFix_high(nbits_stages, nbits_stages_frac) downto SFix_low(nbits_stages, nbits_stages_frac)) := to_sfixed_array(FilterCoef_Lowpass(ntaps, 0.125, 0.125), nbits_stages, nbits_stages_frac); - - SIGNAL xi, yo : real := 0.0; - - -- file I/O - subtype sample_t is integer range -32768 to 32767; - type file_t is file of sample_t; - - ------------------------------------------------------------------------------- -BEGIN - - xi <= to_real(x_in); - yo <= to_real(y_out); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_fir_parallel: fir_parallel - GENERIC MAP - ( - ntaps => ntaps, - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_stages => nbits_stages, - nbits_stages_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - h_in => coeff_in, - in_valid => in_valid, - d_in => x_in, - out_valid => out_valid, - d_out => y_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - file fi : file_t open read_mode is "wav_in.dat"; - variable si : sample_t; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - while not endfile(fi) loop - read(fi, si); - x_in <= to_sfixed(to_signed(si, 16)); - in_valid <= '1'; - wait for PERIOD; - wait until rising_edge(clk); - end loop; - ------------------------------------------ - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file fo : file_t open write_mode is "wav_out.dat"; - variable so : sample_t; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - so := to_integer(y_out); - write(fo, so); - end if; - - END PROCESS; - -END; diff --git a/lib/filter/src/tb_fir_stage.vhd b/lib/filter/src/tb_fir_stage.vhd deleted file mode 100644 index 159f13a..0000000 --- a/lib/filter/src/tb_fir_stage.vhd +++ /dev/null @@ -1,268 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_fir_stage --- Module Name: tb_fir_stage.vhd --- Project Name: fir_stage --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.fir_stage_pkg.all; -use work.filter_pkg.all; - -use work.PCK_FIO.all; - -ENTITY tb_fir_stage IS - Generic ( - ntaps : integer := 33; - nbits_in : integer := 24; - nbits_in_frac : integer := 23; - nbits_stages : integer := 25; - nbits_stages_frac : integer := 23; - nbits_out : integer := 24; - nbits_out_frac : integer := 22; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := false; - fir_mode : fir_stage_mode_t := transposed; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_fir_stage; - -ARCHITECTURE behavior OF tb_fir_stage IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT fir_stage - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - fir_mode : fir_stage_mode_t; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_in : in sfixed; - y_in : in sfixed; - h_in : in sfixed; - out_valid : out std_logic; - x_out : out sfixed; - y_out : out sfixed - ); - END COMPONENT; - - type stages_t is array (natural range <>) of sfixed(sproto(nbits_stages, nbits_stages_frac)'high downto sproto(nbits_stages, nbits_stages_frac)'low); - - --Constants - constant PERIOD : time := 10 ns; - constant zero_in : sfixed := to_sfixed(0, nbits_in, nbits_in_frac); - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL x_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL y_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL out_valid : std_logic := '0'; - - SIGNAL x : stages_t(0 to ntaps-2); - SIGNAL y : stages_t(0 to ntaps-2); - - SIGNAL fileout_enable : std_logic := '1'; - - -- Test coefficients - function to_sfixed(x_real : real_array_t) return stages_t is - variable res : stages_t(x_real'range); - begin - for i in x_real'range loop - res(i) := to_sfixed(x_real(i), res(i), true, true); - end loop; - - return res; - end to_sfixed; - - constant h : stages_t(0 to ntaps-1) := to_sfixed(FilterCoef_Lowpass(ntaps, 0.25, 1.0)); - - SIGNAL xi, yo : real := 0.0; - -BEGIN - - xi <= to_real(x_in); - yo <= to_real(y_out); - - ---------------------------------------- - -- Instantiate the Unit Under Test (UUT) - ---------------------------------------- - uut_first_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x_in, - y_in => zero_in, - h_in => h(ntaps-1), - out_valid => out_valid, - x_out => x(0), - y_out => y(0) - ); - - ---------------------------------------- - gen_stages: - for i in 1 to ntaps-2 generate - uut_stages: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_stages, - nbits_out_frac => nbits_stages_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => false, - saturating => false - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(i-1), - y_in => y(i-1), - h_in => h(ntaps-i-1), - out_valid => open, - x_out => x(i), - y_out => y(i) - ); - end generate; - - ---------------------------------------- - uut_last_stage: fir_stage - GENERIC MAP - ( - nbits_in => nbits_stages, - nbits_in_frac => nbits_stages_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - fir_mode => fir_mode, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_in => x(ntaps-2), - y_in => y(ntaps-2), - h_in => h(0), - out_valid => open, - x_out => x_out, - y_out => y_out - ); - - ---------------------------------------- - -- Finished instantiation - ---------------------------------------- - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - - x_in <= to_sfixed(0.0, x_in); - - wait until rising_edge(clk); - in_valid <= '1'; - - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - - wait for 20*PERIOD; - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(1.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - wait until rising_edge(clk); - x_in <= to_sfixed(0.0, x_in); - - wait for 150*PERIOD; - - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file RESULT_FIR: text open write_mode is "fir.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - fprint(RESULT_FIR, L,"%s\n", REAL'image(yo)); - end if; - - END PROCESS; - -END; diff --git a/lib/fix_std/fix_std.vhd b/lib/fix_std/fix_std.vhd deleted file mode 100644 index 6397ebc..0000000 --- a/lib/fix_std/fix_std.vhd +++ /dev/null @@ -1,1007 +0,0 @@ ---------------------------------------------------------------------- --- --- Package fix_std --- Fixed point arithmetic based on numeric_std --- ---------------------------------------------------------------------- --- --- This document describes a VHDL package of definitions and subprograms --- intended to support the use of fixed-point arithmetic in test benches --- and synthesisable designs. This document and the package it describes --- are made freely available to the HDL design community without warranty --- of any kind. You are welcome to make use of this information for your --- own private study and in your own designs. If you make use of the --- package, you accept sole responsibility for its fitness for purpose --- and its suitability in your application. You are free to modify the --- package in any way, and to record your contribution to it, but this --- notice must appear in a prominent place in any modified or derived --- version of the package or its supporting documentation. --- --- The author wishes to thank his employer Doulos Ltd for making --- available the facilities used to develop, test and distribute this --- package. However, Doulos Ltd accepts no responsibility for the --- package's contents and cannot support it in any way. --- ---------------------------------------------------------------------- --- Revision information: --- --- Version 0.1 06-May-2003 --- Alpha version, for review --- No division operators are provided, pending detailed --- consultation on their functionality. --- Some subprogram implementations are unnecessarily inefficient. --- Version 0.2 11-Jun-2003 --- Fixes aiming to make the package portable across all synthesis tools: --- * Removed deferred constants, made them package constants --- * Removed all variable initialisations in procedures, made them --- procedural initialisations in the code ---------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package fix_std is - - -------------------------------------------------------------------- - - -- Integer subtype specifying legal values for a bit index. - -- At present it's restricted to 'natural' to conform with - -- the behaviour of mainstream synthesis tools. For simulation, - -- or in the future when synthesis tools are able to cope, it - -- would be possible to change this subtype to be the full - -- integer range, thus allowing negative subscripts for - -- fraction bits. - -- - subtype Fix_Subscr is natural; - - -- Fixed-point offset, the bit number (subscript) used for - -- the bit in a UFix or SFix vector having binary weight 2^0 - -- (the units bit). - -- - constant FixP: Fix_Subscr := 100; - - -- Type declarations for the basic unsigned and signed fixed point - -- data types: - -- - type UFix is array (Fix_Subscr range <>) of std_logic; - type SFix is array (Fix_Subscr range <>) of std_logic; - - -- Type declarations for control of rounding and overflow modes: - -- - type Fix_Rounding_Mode is ( - clip_LS, -- Throw away unwanted least significant bits - towards_zero, -- Round towards zero - same as clip_LS for UFix - to_nearest -- Round to nearest. Exact halves round up. - ); - type Fix_Overflow_Mode is ( - clip_MS, -- Throw away unwanted most significant bits - saturate -- Saturate overflow to nearest representable value - ); - - -- Defaults for these modes: - -- - constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS; - constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS; - - -------------------------------------------------------------------- - - --------------------------- - -- E. Extraction functions - --------------------------- - - -- E.1. Return the integral part of a UFix value - function Int(U: UFix) return UFix; - - -- E.2. Return the fractional part of a UFix value - function Frac(U: UFix) return UFix; - - -- E.3. Return the integral part of a SFix value - function Int(S: SFix) return SFix; - - -- E.4. Return the fractional part of a SFix value - function Frac(S: SFix) return UFix; - - -- E.5. Widen a SFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(S: SFix) return SFix; - - -- E.6. Widen a UFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(U: UFix) return UFix; - - --------------------------- - -- T. Conversion functions - --------------------------- - - -- T.1 to T.8: Unsigned conversions - -- - -- T.1. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.2. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.3. Conversion from integer to UFix. Provide number of - -- integer bits and number of fraction bits. Note that - -- negative input is tolerated! - -- - function to_UFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.4. Conversion from unsigned to UFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting UFix. - -- - function to_UFix( - N : unsigned; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix; - - -- T.5. Conversion from unsigned to UFix. Automatically set the - -- range of the resulting UFix to match the unsigned value, - -- as an integral UFix value with no fraction bits. - -- - function to_UFix( N : unsigned ) return UFix; - - -- T.6. Conversion from UFix to unsigned. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_unsigned( - N : UFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned; - - -- T.7. Conversion from UFix to unsigned. Caller specifies - -- required number of bits in unsigned result. - -- - function to_unsigned( - N : UFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned; - - -- T.8. Conversion from UFix to integer. Up to 31 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer; - - - -- T.9 to T.16: Signed conversions - -- - -- T.9. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.10. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.11. Conversion from integer to SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.12. Conversion from signed to SFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting SFix. - -- - function to_SFix( - N : signed; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix; - - -- T.13. Conversion from signed to SFix. Automatically set the - -- range of the resulting SFix to match the signed value, - -- as an integral SFix value with no fraction bits. - -- - function to_SFix( N : signed ) return SFix; - - -- T.14. Conversion from SFix to signed. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_signed( - N : SFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed; - - -- T.15. Conversion from SFix to signed. Caller specifies - -- required number of bits in signed result. - -- - function to_signed( - N : SFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed; - - -- T.16. Conversion from SFix to integer. Up to 32 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer; - - -- T.17. Conversion from UFix to SFix. This simply adds - -- an extra more significant bit, set to zero. - -- - function to_SFix(U: UFix) return SFix; - - ---------------------------------- - -- V. Copy-to-variable procedures - ---------------------------------- - - -- Range-aware copying of an expression into a variable. The - -- ranges of destination variable and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- V.1 to V.5: Copy an expression into a UFix variable - -- - - -- V.1. Copy UFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - -- - -- V.2. Copy SFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.3. Copy UNSIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.4. Copy SIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.5. Copy integer to UFix - -- - procedure Copy_V( - target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.6 to V.10: Copy an expression into a SFix variable - -- - - -- V.6. Copy UFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.7. Copy SFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.8. Copy UNSIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.9. Copy SIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- V.10. Copy integer to SFix - -- - procedure Copy_V( - target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - - -------------------------------- - -- S. Copy-to-signal procedures - -------------------------------- - -- - -- Range-aware copying of an expression into a signal. The - -- ranges of destination signal and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- S.1 to S.5: Copy an expression into a UFix signal - -- - - -- S.1. Copy UFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.1. Copy SFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.3. Copy UNSIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.4. Copy SIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.5. Copy integer to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.6 to S.10: Copy an expression into a SFix signal - -- - - -- S.6. Copy UFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.7. Copy SFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.8. Copy UNSIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.9. Copy SIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - -- S.10. Copy integer to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ); - - - ------------------------------------------------------------------ - -- A. Arithmetic operations involving UFix, SFix and other - -- numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- - -- IMPORTANT NOTE: - -- Arithmetic operators return a result that is wide enough - -- and precise enough so that no information is lost. THIS IS - -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std. - -- In the detailed description that follow, "scaling" means - -- the numerical value (weight) of the least significant bit - -- in a fixed-point value. - -- - -- ADDITION returns a result whose least significant bit - -- is the same as the least significant bit in either operand, - -- and whose most significant bit is one position higher than - -- the most significant bit in either operand. Addition of - -- two operands having the same bounds therefore results in - -- a growth of one bit at the most significant end. - -- - -- SUBTRACTION where one or both operands are signed behaves - -- in the same way as addition. Subtraction where both operands - -- are unsigned returns a result whose most significant bit - -- position is the same as the most significant bit in either - -- operand, and whose least significant bit is the same as the - -- least significant bit in either operand. - -- - -- MULTIPLICATION returns a result whose width is the sum of - -- the widths of its two operands, and whose scaling is the - -- product of its two operands' scalings. - -- - -- UNARY NEGATION always gives a result having one more - -- significant bit than the operand. - -- - -- ABSOLUTE VALUE always gives a result having exactly the - -- same subtype as its operand. - -- - -- In binary operations where one operand is a fixed-point type - -- and the other is an integer numeric type, the integer operand - -- is first converted to a fixed-point type of the same subtype - -- as the other operand using Copy_V with default rounding and - -- overflow modes. The operation is then performed between two - -- fixed-point operands in the normal way. - -- - ------------------------------------------------------------------ - - - ------------------------------------ - -- A.1. Unary "-" negation operator - ------------------------------------ - - -- A.1.1. SFix := - UFix - function "-" (R: UFix) return SFix; - - -- A.1.2. SFix := - SFix - function "-" (R: SFix) return SFix; - - - -------------------------------------------- - -- A.2. Unary "abs" absolute-value operator - -------------------------------------------- - - -- A.2.1. SFix := abs SFix - function "abs" (R: SFix) return SFix; - - - ------------------------------------- - -- A.3. Binary "+" addition operator - ------------------------------------- - - -- A.3.1. UFix := UFix + UFix - function "+" (L: UFix; R: UFix) return UFix; - - -- A.3.2. UFix := UFix + unsigned - function "+" (L: UFix; R: unsigned) return UFix; - - -- A.3.3. UFix := unsigned + UFix - function "+" (L: unsigned; R: UFix) return UFix; - - -- A.3.4. UFix := UFix + natural - function "+" (L: UFix; R: natural) return UFix; - - -- A.3.5. UFix := natural + UFix - function "+" (L: natural; R: UFix) return UFix; - - -- A.3.6. SFix := SFix + SFix - function "+" (L: SFix; R: SFix) return SFix; - - -- A.3.7. SFix := SFix + UFix - function "+" (L: SFix; R: UFix) return SFix; - - -- A.3.8. SFix := UFix + SFix - function "+" (L: UFix; R: SFix) return SFix; - - -- A.3.9. SFix := SFix + signed - function "+" (L: SFix; R: signed) return SFix; - - -- A.3.10. SFix := signed + SFix - function "+" (L: signed; R: SFix) return SFix; - - -- A.3.11. SFix := SFix + integer - function "+" (L: SFix; R: integer) return SFix; - - -- A.3.12. SFix := integer + SFix - function "+" (L: integer; R: SFix) return SFix; - - - ---------------------------------------- - -- A.4. Binary "-" subtraction operator - ---------------------------------------- - -- - -- NOTE: There is a special problem with subtraction - -- operators that return a UFix result if that result - -- goes negative. Our arbitrary decision is that we - -- truncate most-significant bits in this case. If you - -- wish to avoid the risk of this arbitrarily-defined - -- truncation behaviour, change one or more of your - -- operands to SFix and get a SFix result using this - -- idiom: - -- SFix := UFix + (-UFix) - -- or copy one of the UFix operands into a SFix that's - -- one bit wider, before performing the operation. - -- - -- Subtractions returning a UFix result take unsigned - -- operands and do not exhibit bit growth. - -- Subtractions returning a SFix result take signed or - -- unsigned operands and exhibit one-bit growth like addition. - - -- A.4.1. UFix := UFix - UFix - function "-" (L: UFix; R: UFix) return UFix; - - -- A.4.2. UFix := UFix - unsigned - function "-" (L: UFix; R: unsigned) return UFix; - - -- A.4.3. UFix := unsigned - UFix - function "-" (L: unsigned; R: UFix) return UFix; - - -- A.4.4. UFix := UFix - natural - function "-" (L: UFix; R: natural) return UFix; - - -- A.4.5. UFix := natural - UFix - function "-" (L: natural; R: UFix) return UFix; - - -- A.4.6. SFix := SFix - SFix - function "-" (L: SFix; R: SFix) return SFix; - - -- A.4.7. SFix := SFix - UFix - function "-" (L: SFix; R: UFix) return SFix; - - -- A.4.8. SFix := UFix - SFix - function "-" (L: UFix; R: SFix) return SFix; - - -- A.4.9. SFix := SFix - signed - function "-" (L: SFix; R: signed) return SFix; - - -- A.4.10. SFix := signed - SFix - function "-" (L: signed; R: SFix) return SFix; - - -- A.4.11. SFix := SFix - integer - function "-" (L: SFix; R: integer) return SFix; - - -- A.4.12. SFix := integer - SFix - function "-" (L: integer; R: SFix) return SFix; - - - ------------------------------------------- - -- A.5. Binary "*" multiplication operator - ------------------------------------------- - - -- A.5.1. UFix := UFix * UFix - function "*" (L: UFix; R: UFix) return UFix; - - -- A.5.2. UFix := UFix * unsigned - function "*" (L: UFix; R: unsigned) return UFix; - - -- A.5.3. UFix := unsigned * UFix - function "*" (L: unsigned; R: UFix) return UFix; - - -- A.5.4. UFix := UFix * natural - function "*" (L: UFix; R: natural) return UFix; - - -- A.5.5. UFix := natural * UFix - function "*" (L: natural; R: UFix) return UFix; - - -- A.5.6. SFix := SFix * SFix - function "*" (L: SFix; R: SFix) return SFix; - - -- A.5.7. SFix := SFix * UFix - function "*" (L: SFix; R: UFix) return SFix; - - -- A.5.8. SFix := UFix * SFix - function "*" (L: UFix; R: SFix) return SFix; - - -- A.5.9. SFix := SFix * signed - function "*" (L: SFix; R: signed) return SFix; - - -- A.5.10. SFix := signed * SFix - function "*" (L: signed; R: SFix) return SFix; - - -- A.5.11. SFix := SFix * integer - function "*" (L: SFix; R: integer) return SFix; - - -- A.5.12. SFix := integer * SFix - function "*" (L: integer; R: SFix) return SFix; - - - ------------------------------------------------------------------ - -- R. Relational operators - arithmetic comparisons involving - -- UFix, SFix and other numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- Note that in all cases comparisons are exact; if one - -- operand has more fraction bits than the other, the less - -- precise operand will have its LSBs zero-extended, and - -- these zero bits will take part in comparison with whatever - -- LSBs exist in the more precise operand. - ------------------------------------------------------------------ - - ------------------------------------- - -- R.1. Binary "=" equality operator - ------------------------------------- - - -- R.1.1. UFix = UFix - function "=" (L: UFix; R: UFix) return boolean; - - -- R.1.2. UFix = unsigned - function "=" (L: UFix; R: unsigned) return boolean; - - -- R.1.3. unsigned = UFix - function "=" (L: unsigned; R: UFix) return boolean; - - -- R.1.4. UFix = integer - function "=" (L: UFix; R: integer) return boolean; - - -- R.1.5. integer = UFix - function "=" (L: integer; R: UFix) return boolean; - - -- R.1.6. SFix = SFix - function "=" (L: SFix; R: SFix) return boolean; - - -- R.1.7. SFix = UFix - function "=" (L: SFix; R: UFix) return boolean; - - -- R.1.8. UFix = SFix - function "=" (L: UFix; R: SFix) return boolean; - - -- R.1.9. SFix = signed - function "=" (L: SFix; R: signed) return boolean; - - -- R.1.10. signed = SFix - function "=" (L: signed; R: SFix) return boolean; - - -- R.1.11. SFix = integer - function "=" (L: SFix; R: integer) return boolean; - - -- R.1.12. integer = SFix - function "=" (L: integer; R: SFix) return boolean; - - - -------------------------------------- - -- R.2. Binary "<" less-than operator - -------------------------------------- - - -- R.2.1. UFix < UFix - function "<" (L: UFix; R: UFix) return boolean; - - -- R.2.2. UFix < unsigned - function "<" (L: UFix; R: unsigned) return boolean; - - -- R.2.3. unsigned < UFix - function "<" (L: unsigned; R: UFix) return boolean; - - -- R.2.4. UFix < integer - function "<" (L: UFix; R: integer) return boolean; - - -- R.2.5. integer < UFix - function "<" (L: integer; R: UFix) return boolean; - - -- R.2.6. SFix < SFix - function "<" (L: SFix; R: SFix) return boolean; - - -- R.2.7. SFix < UFix - function "<" (L: SFix; R: UFix) return boolean; - - -- R.2.8. UFix < SFix - function "<" (L: UFix; R: SFix) return boolean; - - -- R.2.9. SFix < signed - function "<" (L: SFix; R: signed) return boolean; - - -- R.2.10. signed < SFix - function "<" (L: signed; R: SFix) return boolean; - - -- R.2.11. SFix < integer - function "<" (L: SFix; R: integer) return boolean; - - -- R.2.12. integer < SFix - function "<" (L: integer; R: SFix) return boolean; - - - ---------------------------------------- - -- R.3. Binary "/=" inequality operator - ---------------------------------------- - - -- R.3.1. UFix /= UFix - function "/=" (L: UFix; R: UFix) return boolean; - - -- R.3.2. UFix /= unsigned - function "/=" (L: UFix; R: unsigned) return boolean; - - -- R.3.3. unsigned /= UFix - function "/=" (L: unsigned; R: UFix) return boolean; - - -- R.3.4. UFix /= integer - function "/=" (L: UFix; R: integer) return boolean; - - -- R.3.5. integer /= UFix - function "/=" (L: integer; R: UFix) return boolean; - - -- R.3.6. SFix /= SFix - function "/=" (L: SFix; R: SFix) return boolean; - - -- R.3.7. SFix /= UFix - function "/=" (L: SFix; R: UFix) return boolean; - - -- R.3.8. UFix /= SFix - function "/=" (L: UFix; R: SFix) return boolean; - - -- R.3.9. SFix /= signed - function "/=" (L: SFix; R: signed) return boolean; - - -- R.3.10. signed /= SFix - function "/=" (L: signed; R: SFix) return boolean; - - -- R.3.11. SFix /= integer - function "/=" (L: SFix; R: integer) return boolean; - - -- R.3.12. integer /= SFix - function "/=" (L: integer; R: SFix) return boolean; - - - ----------------------------------------- - -- R.4. Binary ">" greater-than operator - ----------------------------------------- - - -- R.4.1. UFix > UFix - function ">" (L: UFix; R: UFix) return boolean; - - -- R.4.2. UFix > unsigned - function ">" (L: UFix; R: unsigned) return boolean; - - -- R.4.3. unsigned > UFix - function ">" (L: unsigned; R: UFix) return boolean; - - -- R.4.4. UFix > integer - function ">" (L: UFix; R: integer) return boolean; - - -- R.4.5. integer > UFix - function ">" (L: integer; R: UFix) return boolean; - - -- R.4.6. SFix > SFix - function ">" (L: SFix; R: SFix) return boolean; - - -- R.4.7. SFix > UFix - function ">" (L: SFix; R: UFix) return boolean; - - -- R.4.8. UFix > SFix - function ">" (L: UFix; R: SFix) return boolean; - - -- R.4.9. SFix > signed - function ">" (L: SFix; R: signed) return boolean; - - -- R.4.10. signed > SFix - function ">" (L: signed; R: SFix) return boolean; - - -- R.4.11. SFix > integer - function ">" (L: SFix; R: integer) return boolean; - - -- R.4.12. integer > SFix - function ">" (L: integer; R: SFix) return boolean; - - - ---------------------------------------------- - -- R.5. Binary ">=" greater-or-equal operator - ---------------------------------------------- - - -- R.5.1. UFix >= UFix - function ">=" (L: UFix; R: UFix) return boolean; - - -- R.5.2. UFix >= unsigned - function ">=" (L: UFix; R: unsigned) return boolean; - - -- R.5.3. unsigned >= UFix - function ">=" (L: unsigned; R: UFix) return boolean; - - -- R.5.4. UFix >= integer - function ">=" (L: UFix; R: integer) return boolean; - - -- R.5.5. integer >= UFix - function ">=" (L: integer; R: UFix) return boolean; - - -- R.5.6. SFix >= SFix - function ">=" (L: SFix; R: SFix) return boolean; - - -- R.5.7. SFix >= UFix - function ">=" (L: SFix; R: UFix) return boolean; - - -- R.5.8. UFix >= SFix - function ">=" (L: UFix; R: SFix) return boolean; - - -- R.5.9. SFix >= signed - function ">=" (L: SFix; R: signed) return boolean; - - -- R.5.10. signed >= SFix - function ">=" (L: signed; R: SFix) return boolean; - - -- R.5.11. SFix >= integer - function ">=" (L: SFix; R: integer) return boolean; - - -- R.5.12. integer >= SFix - function ">=" (L: integer; R: SFix) return boolean; - - - ------------------------------------------- - -- R.6. Binary "<=" less-or-equal operator - ------------------------------------------- - - -- R.6.1. UFix <= UFix - function "<=" (L: UFix; R: UFix) return boolean; - - -- R.6.2. UFix <= unsigned - function "<=" (L: UFix; R: unsigned) return boolean; - - -- R.6.3. unsigned <= UFix - function "<=" (L: unsigned; R: UFix) return boolean; - - -- R.6.4. UFix <= integer - function "<=" (L: UFix; R: integer) return boolean; - - -- R.6.5. integer <= UFix - function "<=" (L: integer; R: UFix) return boolean; - - -- R.6.6. SFix <= SFix - function "<=" (L: SFix; R: SFix) return boolean; - - -- R.6.7. SFix <= UFix - function "<=" (L: SFix; R: UFix) return boolean; - - -- R.6.8. UFix <= SFix - function "<=" (L: UFix; R: SFix) return boolean; - - -- R.6.9. SFix <= signed - function "<=" (L: SFix; R: signed) return boolean; - - -- R.6.10. signed <= SFix - function "<=" (L: signed; R: SFix) return boolean; - - -- R.6.11. SFix <= integer - function "<=" (L: SFix; R: integer) return boolean; - - -- R.6.12. integer <= SFix - function "<=" (L: integer; R: SFix) return boolean; - - - ------------------------------------------------------------------ - -- C. Concatenation operators between fixed-point operands, and - -- between fixed-point operands and other reasonable types. - -- Unlike the implicitly defined "&" operator, they preserve - -- place value and return an appropriately aligned subtype. - -- Preservation of place value means that some concatenation - -- operations are illegal. In particular, operations - -- [SFix & SFix] and [UFix & SFix] are illegal, and - -- the place values of operands in [SFix & UFix] and - -- [UFix & UFix] must match up - the rightmost subscript of - -- the left operand must be one higher than the leftmost - -- subscript of the right operand. - -- Single bits of type std_ulogic may be concatenated with - -- fixed-point types where there is no risk of losing - -- sign-extension information. - -- Because of the way VHDL defines implicit concatenation, - -- it is impossible to detect all these errors at compile time. - -- Instead they are detected by assertion statements at run time. - -- Tool vendors may choose to implement compile-time checks - -- so that the run-time checking overhead can be avoided. - ------------------------------------------------------------------ - - -- C.1.1. UFix := UFix & UFix - function "&" (L: UFix; R: UFix) return UFix; - - -- No need to define "&"[UFix, SFix] explicitly, because - -- the types are incompatible and so there's no default - - -- C.1.2. UFix := UFix & std_ulogic - function "&" (L: UFix; R: std_ulogic) return UFix; - - -- C.1.3. UFix := std_ulogic & UFix - function "&" (L: std_ulogic; R: UFix) return UFix; - - - -- C.2.1. SFix := SFix & UFix - function "&" (L: SFix; R: UFix) return SFix; - - -- C.2.2. SFix := SFix & SFix -- ILLEGAL - function "&" (L: SFix; R: SFix) return SFix; - - -- C.2.3. SFix := SFix & std_ulogic - function "&" (L: SFix; R: std_ulogic) return SFix; - - -- C.2.4. SFix := std_ulogic & SFix - function "&" (L: std_ulogic; R: SFix) return SFix; - - -end; -- package fix_std; diff --git a/lib/fix_std/fix_stdb.vhd b/lib/fix_std/fix_stdb.vhd deleted file mode 100644 index 695cd11..0000000 --- a/lib/fix_std/fix_stdb.vhd +++ /dev/null @@ -1,1910 +0,0 @@ ---------------------------------------------------------------------- --- --- Package body fix_std --- Fixed point arithmetic based on numeric_std --- Compile using VHDL-93 (required to support 'ASCENDING --- array attribute). --- ---------------------------------------------------------------------- --- --- This document describes a VHDL package of definitions and subprograms --- intended to support the use of fixed-point arithmetic in test benches --- and synthesisable designs. This document and the package it describes --- are made freely available to the HDL design community without warranty --- of any kind. You are welcome to make use of this information for your --- own private study and in your own designs. If you make use of the --- package, you accept sole responsibility for its fitness for purpose --- and its suitability in your application. You are free to modify the --- package in any way, and to record your contribution to it, but this --- notice must appear in a prominent place in any modified or derived --- version of the package or its supporting documentation. --- --- The author wishes to thank his employer Doulos Ltd for making --- available the facilities used to develop, test and distribute this --- package. However, Doulos Ltd accepts no responsibility for the --- package's contents and cannot support it in any way. --- ---------------------------------------------------------------------- --- Revision information: --- --- Version 0.1 06-May-2003 --- Alpha version, for review --- No division operators are provided, pending detailed --- consultation on their functionality. --- Some subprogram implementations are unnecessarily inefficient. --- Version 0.2 11-Jun-2003 --- Fixes aiming to make the package portable across all synthesis tools: --- * Removed deferred constants, made them package constants --- * Removed all variable initialisations in procedures, made them --- procedural initialisations in the code --- * Fixed definition of extract functions to return just one bit --- if their results would otherwise be null ---------------------------------------------------------------------- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -package body fix_std is - - -------------------------------------------------------------------- - -- DEFERRED CONSTANTS - -------------------------------------------------------------------- - -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC - -- IMPLEMENTATIONS OR APPLICATIONS. - -------------------------------------------------------------------- - - -- Fixed-point offset, the bit number (subscript) used for - -- the bit in a UFix or SFix vector having binary weight 2^0 - -- (the units bit). - -- - -- constant FixP : Fix_Subscr := 100; - - -- Default values for overflow and rounding modes: - -- - -- constant Fix_Default_Rounding : Fix_Rounding_Mode := clip_LS; - -- constant Fix_Default_Overflow : Fix_Overflow_Mode := clip_MS; - - -------------------------------------------------------------------- - -- END OF DEFERRED CONSTANTS - -------------------------------------------------------------------- - - -------------------------------------------------------------------- - -- IMPLEMENTATION CONSTANTS - -------------------------------------------------------------------- - -- THESE CONSTANTS MAY BE ADJUSTED TO SUIT THE NEEDS OF SPECIFIC - -- IMPLEMENTATIONS OR APPLICATIONS. - -------------------------------------------------------------------- - - -- Severity levels for various errors - - -- Concatenation errors - bad sign extension, discontiguous range etc - -- These are only warnings - they just give the wrong answer. - -- - constant concat_severity : severity_level := WARNING; - - -- Subtype direction errors - the present implementation can't - -- handle fixed-point objects with ascending ranges. These messages - -- are intended to give early warning of problems that would - -- definitely cause other fatal errors at elaboration or run time. - -- - constant direction_severity : severity_level := FAILURE; - - -- Assertion error message constants - - constant bad_direction_msg : string := - " has ascending range"; - - constant concat_range_msg : string := - "Concatenation bounds should have contiguous ranges"; - - constant concat_sxt_msg : string := - "Concatenation corrupts sign of result"; - - constant concat_signLS_msg : string := - "RHS of concatenation should be unsigned"; - - constant compare_meta_msg : string := - "Metavalue detected in FIX_STD comparison, returning FALSE"; - - -------------------------------------------------------------------- - -- END OF IMPLEMENTATION CONSTANTS - -------------------------------------------------------------------- - - -------------------------------------------------------------------- - -- DO NOT MODIFY ANY CODE BELOW THIS POINT. - -------------------------------------------------------------------- - - -- Assumed bit width of INTEGER type in VHDL - -- - constant INT_WIDTH : positive := 32; - - -- Single-bit zero values - subtype Izero_UFixT is UFix(FixP downto FixP); - subtype Izero_SFixT is SFix(FixP downto FixP); - subtype Fzero_UFixT is UFix(FixP-1 downto FixP-1); - constant Izero_UFix: Izero_UFixT := "0"; - constant Izero_SFix: Izero_SFixT := "0"; - constant Fzero_UFix: Fzero_UFixT := "0"; - - -------------------------------------------------------------------- - -- LOCAL PRIVATE SUBPROGRAMS - -------------------------------------------------------------------- - - -- Min, Max: Find minimum and maximum of two integers. - -- Useful for determining appropriate range for operation results. - -- - function Max(L, R: Fix_Subscr) return Fix_Subscr is - begin - if L>R then - return L; - else - return R; - end if; - end; - -- - function Min(L, R: Fix_Subscr) return Fix_Subscr is - begin - if L FixP then - return Span(U); - else - return U(U'LEFT downto FixP); - end if; - end; - - -- E.2. Return the fractional part of a UFix value - function Frac(U: UFix) return UFix is - begin - if U'LEFT < FixP-1 then - return Span(U); - elsif U'RIGHT >= FixP then - return Fzero_UFix; - else - return U(FixP-1 downto U'RIGHT); - end if; - end; - - -- E.3. Return the integral part of a SFix value - function Int(S: SFix) return SFix is - begin - if S'LENGTH = 0 then - return Izero_SFix; - elsif S'LEFT <= FixP then - return SFix'(FixP => S(S'LEFT)); - elsif S'RIGHT > FixP then - return Span(S); - else - return S(S'LEFT downto FixP); - end if; - end; - - -- E.4. Return the fractional part of a SFix value - function Frac(S: SFix) return UFix is - variable P: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP)); - begin - if S'LEFT < FixP then - for I in FixP-1 downto S'LEFT+1 loop - P(I) := S(S'LEFT); - end loop; - P(S'RANGE) := S; - return UFix(S(FixP-1 downto S'RIGHT)); - elsif S'RIGHT >= FixP then - return Fzero_UFix; - else - return UFix(S(FixP-1 downto S'RIGHT)); - end if; - end; - - -- E.5. Widen a SFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(S: SFix) return SFix is - variable F: SFix(Max(S'LEFT, FixP) downto Min(S'RIGHT, FixP)); - begin - F(S'RANGE) := S; - for I in F'LEFT downto S'LEFT+1 loop - F(I) := S(S'LEFT); - end loop; - for I in S'RIGHT-1 downto F'RIGHT loop - F(I) := '0'; - end loop; - return F; - end; - - -- E.6. Widen a UFix value if necessary so that - -- its range adjoins or spans the binary point - function Span(U: UFix) return UFix is - variable F: UFix(Max(U'LEFT, FixP-1) downto Min(U'RIGHT, FixP)); - begin - F(U'RANGE) := U; - for I in F'LEFT downto U'LEFT+1 loop - F(I) := '0'; - end loop; - for I in U'RIGHT-1 downto F'RIGHT loop - F(I) := '0'; - end loop; - return F; - end; - - --------------------------- - -- T. Conversion functions - --------------------------- - - -- T.1 to T.8: Unsigned conversions - - -- T.1. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.2. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_UFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.3. Conversion from integer to UFix. Provide number of - -- integer bits and number of fraction bits. Note that - -- negative input is tolerated! - -- - function to_UFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.4. Conversion from unsigned to UFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting UFix. - -- - function to_UFix( - N : unsigned; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return UFix is - variable F: UFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.5. Conversion from unsigned to UFix. Automatically set the - -- range of the resulting UFix to match the unsigned value, - -- as an integral UFix value with no fraction bits. - -- - function to_UFix( N : unsigned ) return UFix is - variable F: UFix(FixP+N'LENGTH-1 downto FixP); - begin - F := UFix(N); - return F; - end; - - -- T.6. Conversion from UFix to unsigned. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_unsigned( - N : UFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned is - variable F_UFix: UFix(N'LEFT downto FixP); - variable F: unsigned(F_UFix'LENGTH-1 downto 0); - begin - Copy_V(F_UFix, N, rounding=>rounding); - F := unsigned(F_UFix); - return F; - end; - - -- T.7. Conversion from UFix to unsigned. Caller specifies - -- required number of bits in unsigned result. - -- - function to_unsigned( - N : UFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return unsigned is - variable F_UFix: UFix(FixP+bits-1 downto FixP); - variable F: unsigned(F_UFix'LENGTH-1 downto 0); - begin - Copy_V(F_UFix, N, overflow, rounding); - F := unsigned(F_UFix); - return F; - end; - - -- T.8. Conversion from UFix to integer. Up to 31 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer is - variable F_UFix: UFix(Min(FixP+INT_WIDTH-2, N'LEFT) downto FixP); - begin - Copy_V(F_UFix, N, overflow, rounding); - return to_integer(unsigned(F_UFix)); - end; - - -- T.9 to T.16: Signed conversions - - -- T.9. Resizing an existing UFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : UFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.10. Resizing an existing SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : SFix; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.11. Conversion from integer to SFix. Provide number of - -- integer bits and number of fraction bits. - -- - function to_SFix( - N : integer; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.12. Conversion from signed to SFix. Provide subscripts of - -- MS and (optionally) LS bit of the resulting SFix. - -- - function to_SFix( - N : signed; - MSB_index : Fix_Subscr; - LSB_index : Fix_Subscr := FixP; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return SFix is - variable F: SFix(MSB_index downto LSB_index); - begin - Copy_V(F, N, overflow, rounding); - return F; - end; - - -- T.13. Conversion from signed to SFix. Automatically set the - -- range of the resulting SFix to match the signed value, - -- as an integral SFix value with no fraction bits. - -- - function to_SFix( N : signed ) return SFix is - variable F: SFix(FixP+N'LENGTH-1 downto FixP); - begin - F := SFix(N); - return F; - end; - - -- T.14. Conversion from SFix to signed. All integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_signed( - N : SFix; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed is - variable F_SFix: SFix(N'LEFT downto FixP); - variable F: signed(F_SFix'LENGTH-1 downto 0); - begin - Copy_V(F_SFix, N, rounding=>rounding); - F := signed(F_SFix); - return F; - end; - - -- T.15. Conversion from SFix to signed. Caller specifies - -- required number of bits in signed result. - -- - function to_signed( - N : SFix; - bits : positive; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return signed is - variable F_SFix: UFix(FixP+bits-1 downto FixP); - variable F: signed(F_SFix'LENGTH-1 downto 0); - begin - Copy_V(F_SFix, N, overflow, rounding); - F := signed(F_SFix); - return F; - end; - - -- T.16. Conversion from SFix to integer. Up to 32 integer bits are - -- preserved (including adding LS scale bits if necessary). - -- - function to_integer( - N : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) return integer is - variable F_SFix: SFix(Min(FixP+INT_WIDTH-1, N'LEFT) downto FixP); - begin - Copy_V(F_SFix, N, overflow, rounding); - return to_integer(signed(F_SFix)); - end; - - -- T.17. Conversion from UFix to SFix. This simply adds - -- an extra more significant bit, set to zero. - -- - function to_SFix(U: UFix) return SFix is - variable F: SFix(U'LEFT+1 downto U'RIGHT); - begin - F := SFix('0' & U); - return F; - end; - - - ---------------------------------- - -- V. Copy-to-variable procedures - ---------------------------------- - - -- Range-aware copying of an expression into a variable. The - -- ranges of destination variable and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- V.1 to V.5: Copy an expression into a UFix variable - - -- V.1. Copy UFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - subtype target_T is UFix(target'RANGE); - variable W: UFix(Max(target'LEFT, source'LEFT+1) downto - Min(target'RIGHT, source'RIGHT)); - constant HighZero: UFix(W'LEFT downto target'LEFT+1) := (others => '0'); - begin - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - W := (others => '0'); - W(source'RANGE) := source; - if target'RIGHT > source'RIGHT then - case rounding is - when clip_LS | towards_zero => - null; - when to_nearest => - W(W'LEFT downto target'RIGHT-1) := UFix( - unsigned(W(W'LEFT downto target'RIGHT-1)) + 1 - ); - end case; - end if; - target := W(target'RANGE); - if HighZero'LENGTH > 0 then - if unsigned(W(HighZero'RANGE)) /= unsigned(HighZero) then - case overflow is - when clip_MS => - null; - when saturate => - target := target_T'(others => '1'); - end case; - end if; - end if; - end; - - -- V.2. Copy SFix to UFix - -- - procedure Copy_V( - target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable W: SFix(Max(Source'LEFT, target'LEFT) downto target'RIGHT); - constant target_zero: UFix(target'RANGE) := (others => '0'); - begin - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - W := (others => '0'); - -- Rounding & sign-extend - Copy_V(W, source, clip_MS, rounding); - -- Saturation? - if W < 0 and overflow = saturate then - target := target_zero; - else - Copy_V(target, UFix(W), overflow, clip_LS); - end if; - end; - - -- V.3. Copy UNSIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant U: UFix(FixP+source'LENGTH-1 downto FixP) := UFix(source); - begin - Copy_V(target, U, overflow, rounding); - end; - - -- V.4. Copy SIGNED to UFix - -- - procedure Copy_V( - target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.5. Copy integer to UFix - -- - procedure Copy_V( - target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant N: signed(FixP+INT_WIDTH-1 downto FixP) - := to_signed(source, INT_WIDTH); - begin - -- Cop-out, this is very inefficient, but will do for now. - Copy_V(target, N, overflow, rounding); - end; - - -- V.6 to V.10: Copy an expression into a SFix variable - - -- V.6. Copy UFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH downto FixP) := to_SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.7. Copy SFix to SFix - -- - procedure Copy_V( - target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - subtype target_T is SFix(target'RANGE); - variable W: SFix(Max(target'LEFT, source'LEFT+1) downto - Min(target'RIGHT, source'RIGHT)); - variable HighSX: SFix(W'LEFT downto target'LEFT+1); - begin - for i in HighSX'RANGE loop - HighSX(i) := source(source'LEFT); - end loop; - assert not target'ASCENDING - report "target" & bad_direction_msg - severity direction_severity; - assert not source'ASCENDING - report "source" & bad_direction_msg - severity direction_severity; - -- Make W a copy of source, duly extended at both ends - W := (others => '0'); - W(source'RANGE) := source; - W(HighSX'RANGE) := HighSX; - -- Do any rounding required - if target'RIGHT > source'RIGHT then - case rounding is - when clip_LS => - null; - when towards_zero => - if - (to_UX01(W(W'LEFT)) = '1') -- it's negative? - and - (unsigned(W(target'RIGHT-1 downto W'RIGHT)) /= 0) -- round up? - then - W(W'LEFT downto target'RIGHT) := SFix( - signed(W(W'LEFT downto target'RIGHT)) + 1 - ); - end if; - when to_nearest => - W(W'LEFT downto target'RIGHT-1) := SFix( - signed(W(W'LEFT downto target'RIGHT-1)) + 1 - ); - end case; - end if; - -- Do any overflow required - target := W(target'RANGE); - if HighSX'LENGTH > 0 then - if signed(W(HighSX'RANGE)) /= signed(HighSX) then - case overflow is - when clip_MS => - null; - when saturate => - target := Target_T'(others => not W(W'LEFT)); - target(target'LEFT) := W(W'LEFT); - end case; - end if; - end if; - end; - - -- V.8. Copy UNSIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH downto FixP) := SFix('0' & source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.9. Copy SIGNED to SFix - -- - procedure Copy_V( - target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant S: SFix(FixP+source'LENGTH-1 downto FixP) := SFix(source); - begin - Copy_V(target, S, overflow, rounding); - end; - - -- V.10. Copy integer to SFix - -- - procedure Copy_V( - target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - constant N: signed(FixP+INT_WIDTH-1 downto FixP) - := to_signed(source, INT_WIDTH); - begin - -- Cop-out, this is very inefficient, but will do for now. - Copy_V(target, N, overflow, rounding); - end; - - - -------------------------------- - -- S. Copy-to-signal procedures - -------------------------------- - -- - -- Range-aware copying of an expression into a signal. The - -- ranges of destination signal and source expression are - -- used to determine correct rounding, overflow and scaling - -- behaviour. - - -- S.1 to S.5: Copy an expression into a UFix signal - -- - - -- S.1. Copy UFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.1. Copy SFix to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.3. Copy UNSIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.4. Copy SIGNED to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.5. Copy integer to UFix - -- - procedure Copy_S( - signal target : out UFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: UFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.6 to S.10: Copy an expression into a SFix signal - -- - - -- S.6. Copy UFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : UFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.7. Copy SFix to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : SFix; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.8. Copy UNSIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : unsigned; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.9. Copy SIGNED to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : signed; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - -- S.10. Copy integer to SFix - -- - procedure Copy_S( - signal target : out SFix; - source : integer; - overflow : Fix_Overflow_Mode := Fix_Default_Overflow; - rounding : Fix_Rounding_Mode := Fix_Default_Rounding - ) is - variable V: SFix(target'RANGE); - begin - Copy_V(V, source, overflow, rounding); - target <= V; - end; - - - ------------------------------------------------------------------ - -- A. Arithmetic operations involving UFix, SFix and other - -- numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- - -- IMPORTANT NOTE: - -- Arithmetic operators return a result that is wide enough - -- and precise enough so that no information is lost. THIS IS - -- SIGNIFICANTLY DIFFERENT FROM THE BEHAVIOUR OF numeric_std. - -- In the detailed description that follow, "scaling" means - -- the numerical value (weight) of the least significant bit - -- in a fixed-point value. - -- - -- ADDITION returns a result whose least significant bit - -- is the same as the least significant bit in either operand, - -- and whose most significant bit is one position higher than - -- the most significant bit in either operand. Addition of - -- two operands having the same bounds therefore results in - -- a growth of one bit at the most significant end. Addition - -- of an integer to a UFix or SFix is accomplished by first - -- converting the integer to the same subtype as the other - -- operand, thereby giving rise to one-bit growth; default - -- truncation and rounding modes are used for the conversion. - -- - -- SUBTRACTION where one or both operands are signed behaves - -- in the same way as addition. Subtraction where both operands - -- are unsigned returns a result whose most significant bit - -- position is the same as the most significant bit in either - -- operand, and whose least significant bit is the same as the - -- least significant bit in either operand. - -- - -- MULTIPLICATION returns a result whose width is the sum of - -- the widths of its two operands, and whose scaling is the - -- product of its two operands' scalings. - -- - -- UNARY NEGATION always gives a result having one more - -- significant bit than the operand. - -- - -- ABSOLUTE VALUE always gives a result having exactly the - -- same subtype as its operand. - -- - -- In binary operations where one operand is a fixed-point type - -- and the other is an integer numeric type, the integer operand - -- is first converted to a fixed-point type of the same subtype - -- as the other operand using Copy_V with default rounding and - -- overflow modes. The operation is then performed between two - -- fixed-point operands in the normal way. - -- - ------------------------------------------------------------------ - - - ------------------------------------ - -- A.1. Unary "-" negation operator - ------------------------------------ - - -- A.1.1. SFix := - UFix - function "-" (R: UFix) return SFix is - variable F: SFix(R'LEFT+1 downto R'RIGHT); - begin - F := SFix(-(signed('0' & R))); - return F; - end; - - -- A.1.2. SFix := - SFix - function "-" (R: SFix) return SFix is - variable F: SFix(R'LEFT+1 downto R'RIGHT); - begin - F := SFix(-(signed(R(R'LEFT) & R))); - return F; - end; - - - -------------------------------------------- - -- A.2. Unary "abs" absolute-value operator - -------------------------------------------- - - -- A.2.1. SFix := abs SFix - function "abs" (R: SFix) return SFix is - variable F: SFix(R'RANGE); - begin - F := R; - if to_X01(R(R'LEFT)) = '1' then - F := SFix(-(signed(R))); - end if; - return F; - end; - - - ------------------------------------- - -- A.3. Binary "+" addition operator - ------------------------------------- - - -- A.3.1. UFix := UFix + UFix - function "+" (L: UFix; R: UFix) return UFix is - variable F: UFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right)); - variable LU, RU: unsigned(F'RANGE); - begin - LU := (others => '0'); - RU := (others => '0'); - LU(L'RANGE) := unsigned(L); - RU(R'RANGE) := unsigned(R); - F := UFix(LU + RU); - return F; - end; - - -- A.3.2. UFix := UFix + unsigned - function "+" (L: UFix; R: unsigned) return UFix is - begin - return L + to_UFix(R); - end; - - -- A.3.3. UFix := unsigned + UFix - function "+" (L: unsigned; R: UFix) return UFix is - begin - return R+L; - end; - - -- A.3.4. UFix := UFix + natural - function "+" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L + R_fp; - end; - - -- A.3.5. UFix := natural + UFix - function "+" (L: natural; R: UFix) return UFix is - begin - return R+L; - end; - - -- A.3.6. SFix := SFix + SFix - function "+" (L: SFix; R: SFix) return SFix is - variable F: SFix(Max(L'LEFT, R'LEFT)+1 downto Min(L'Right, R'Right)); - variable LS, RS: signed(F'RANGE); - begin - LS := (others => '0'); - RS := (others => '0'); - LS(L'RANGE) := signed(L); - RS(R'RANGE) := signed(R); - for i in LS'LEFT downto L'LEFT+1 loop LS(i) := L(L'LEFT); end loop; - for i in RS'LEFT downto R'LEFT+1 loop RS(i) := R(R'LEFT); end loop; - F := SFix(LS + RS); - return F; - end; - - -- A.3.7. SFix := SFix + UFix - function "+" (L: SFix; R: UFix) return SFix is - begin - return L + SFix('0' & R); - end; - - -- A.3.8. SFix := UFix + SFix - function "+" (L: UFix; R: SFix) return SFix is - begin - return SFix('0' & L) + R; - end; - - -- A.3.9. SFix := SFix + signed - function "+" (L: SFix; R: signed) return SFix is - begin - return L + to_SFix(R); - end; - - -- A.3.10. SFix := signed + SFix - function "+" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) + R; - end; - - -- A.3.11. SFix := SFix + integer - function "+" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L + R_fp; - end; - - -- A.3.12. SFix := integer + SFix - function "+" (L: integer; R: SFix) return SFix is - begin - return R + L; - end; - - - ---------------------------------------- - -- A.4. Binary "-" subtraction operator - ---------------------------------------- - -- - -- NOTE: There is a special problem with subtraction - -- operators that return a UFix result if that result - -- goes negative. Our arbitrary decision is that we - -- truncate most-significant bits in this case. If you - -- wish to avoid the risk of this arbitrarily-defined - -- truncation behaviour, change one or more of your - -- operands to SFix and get a SFix result using this - -- idiom: - -- SFix := UFix + (-UFix) - -- or copy one of the UFix operands into a SFix that's - -- one bit wider, before performing the operation. - -- - -- Subtractions returning a UFix result take unsigned - -- operands and do not exhibit bit growth. - -- Subtractions returning a SFix result take signed or - -- unsigned operands and exhibit one-bit growth like addition. - - -- A.4.1. UFix := UFix - UFix - function "-" (L: UFix; R: UFix) return UFix is - variable F, LW, RW: UFix(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := L; - RW(R'RANGE) := R; - F := UFix(unsigned(LW) - unsigned(RW)); - return F; - end; - - -- A.4.2. UFix := UFix - unsigned - function "-" (L: UFix; R: unsigned) return UFix is - begin - return L - to_UFix(R); - end; - - -- A.4.3. UFix := unsigned - UFix - function "-" (L: unsigned; R: UFix) return UFix is - begin - return to_UFix(L) - R; - end; - - -- A.4.4. UFix := UFix - integer - function "-" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L - R_fp; - end; - - -- A.4.5. UFix := natural - UFix - function "-" (L: natural; R: UFix) return UFix is - variable L_fp: UFix(R'RANGE); - begin - Copy_V(L_fp, L); - return L_fp - R; - end; - - -- A.4.6. SFix := SFix - SFix - function "-" (L: SFix; R: SFix) return SFix is - begin - return L + (-R); - end; - - -- A.4.7. SFix := SFix - UFix - function "-" (L: SFix; R: UFix) return SFix is - begin - return L + (-R); - end; - - -- A.4.8. SFix := UFix - SFix - function "-" (L: UFix; R: SFix) return SFix is - begin - return To_SFix(L) - R; - end; - - -- A.4.9. SFix := SFix - signed - function "-" (L: SFix; R: signed) return SFix is - begin - return L - to_SFix(R); - end; - - -- A.4.10. SFix := signed - SFix - function "-" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) - R; - end; - - -- A.4.11. SFix := SFix - integer - function "-" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L - R_fp; - end; - - -- A.4.12. SFix := integer - SFix - function "-" (L: integer; R: SFix) return SFix is - variable L_fp: SFix(R'RANGE); - begin - Copy_V(L_fp, L); - return L_fp - R; - end; - - - ------------------------------------------- - -- A.5. Binary "*" multiplication operator - ------------------------------------------- - - -- A.5.1. UFix := UFix * UFix - function "*" (L: UFix; R: UFix) return UFix is - variable F: UFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - begin - F := UFix(unsigned(L) * unsigned(R)); - return F; - end; - - -- A.5.2. UFix := UFix * unsigned - function "*" (L: UFix; R: unsigned) return UFix is - begin - return L * to_UFix(R); - end; - - -- A.5.3. UFix := unsigned * UFix - function "*" (L: unsigned; R: UFix) return UFix is - begin - return to_UFix(L) * R; - end; - - -- A.5.4. UFix := UFix * natural - function "*" (L: UFix; R: natural) return UFix is - variable R_fp: UFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L * R_fp; - end; - - -- A.5.5. UFix := natural * UFix - function "*" (L: natural; R: UFix) return UFix is - begin - return R * L; - end; - - -- A.5.6. SFix := SFix * SFix - function "*" (L: SFix; R: SFix) return SFix is - variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - begin - F := SFix(signed(L) * signed(R)); - return F; - end; - - -- A.5.7. SFix := SFix * UFix - function "*" (L: SFix; R: UFix) return SFix is - constant RS: SFix := SFix('0' & R); - variable F: SFix(L'LEFT+R'LEFT+1-FixP downto L'RIGHT+R'RIGHT-FixP); - variable FW: SFix(F'LEFT+1 downto F'RIGHT); - begin - FW := SFix(signed(L) * signed(RS)); - Copy_V(F, FW); -- never overflows - return F; - end; - - -- A.5.8. SFix := UFix * SFix - function "*" (L: UFix; R: SFix) return SFix is - begin - return R * L; - end; - - -- A.5.9. SFix := SFix * signed - function "*" (L: SFix; R: signed) return SFix is - begin - return L * to_SFix(R); - end; - - -- A.5.10. SFix := signed * SFix - function "*" (L: signed; R: SFix) return SFix is - begin - return to_SFix(L) * R; - end; - - -- A.5.11. SFix := SFix * integer - function "*" (L: SFix; R: integer) return SFix is - variable R_fp: SFix(L'RANGE); - begin - Copy_V(R_fp, R); - return L * R_fp; - end; - - -- A.5.12. SFix := integer * SFix - function "*" (L: integer; R: SFix) return SFix is - begin - return R * L; - end; - - - ------------------------------------------------------------------ - -- R. Relational operators - arithmetic comparisons involving - -- UFix, SFix and other numeric types. - -- The operators are overloaded for most of the sensible - -- combinations of SFix, UFix, UNSIGNED, SIGNED and INTEGER. - -- Note that in all cases comparisons are exact; if one - -- operand has more fraction bits than the other, the less - -- precise operand will have its LSBs zero-extended, and - -- these zero bits will take part in comparison with whatever - -- LSBs exist in the more precise operand. - -- - -- Our implementation is based on only two operators, "=" and "<". - -- All other operators are derived from these two, either by - -- logical inversion of the result or by swapping operands. - ------------------------------------------------------------------ - - ------------------------------------- - -- R.1. Binary "=" equality operator - ------------------------------------- - - -- R.1.1. UFix = UFix - function "=" (L: UFix; R: UFix) return boolean is - variable LW, RW: UFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := L; - RW(R'RANGE) := R; - return unsigned(LW) = unsigned(RW); - end; - - -- R.1.2. UFix = unsigned - function "=" (L: UFix; R: unsigned) return boolean is - begin - return L = to_UFix(R); - end; - - -- R.1.3. unsigned = UFix - function "=" (L: unsigned; R: UFix) return boolean is - begin - return to_UFix(L) = R; - end; - - -- R.1.4. UFix = integer - function "=" (L: UFix; R: integer) return boolean is - variable RS: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(RS, R, clip_MS, clip_LS); - return To_SFix(L) = RS; - end; - - -- R.1.5. integer = UFix - function "=" (L: integer; R: UFix) return boolean is - begin - return R = L; - end; - - -- R.1.6. SFix = SFix - function "=" (L: SFix; R: SFix) return boolean is - variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto Min(L'RIGHT, R'RIGHT)); - begin - -- clip modes are OK because we aren't losing any bits - Copy_V(LW, L, clip_MS, clip_LS); - Copy_V(RW, R, clip_MS, clip_LS); - return signed(LW) = signed(RW); - end; - - -- R.1.7. SFix = UFix - function "=" (L: SFix; R: UFix) return boolean is - begin - return L = To_SFix(R); - end; - - -- R.1.8. UFix = SFix - function "=" (L: UFix; R: SFix) return boolean is - begin - return R = L; - end; - - -- R.1.9. SFix = signed - function "=" (L: SFix; R: signed) return boolean is - begin - return L = to_SFix(R); - end; - - -- R.1.10. signed = SFix - function "=" (L: signed; R: SFix) return boolean is - begin - return to_SFix(L) = R; - end; - - -- R.1.11. SFix = integer - function "=" (L: SFix; R: integer) return boolean is - variable RS: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(RS, R, clip_MS, clip_LS); - return L = RS; - end; - - -- R.1.12. integer = SFix - function "=" (L: integer; R: SFix) return boolean is - begin - return R = L; - end; - - - -------------------------------------- - -- R.2. Binary "<" less-than operator - -------------------------------------- - - -- R.2.1. UFix < UFix - function "<" (L: UFix; R: UFix) return boolean is - variable LW, RW: unsigned(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - LW := (others => '0'); - RW := (others => '0'); - LW(L'RANGE) := unsigned(L); - RW(R'RANGE) := unsigned(R); - return unsigned(LW) < unsigned(RW); - end; - - -- R.2.2. UFix < unsigned - function "<" (L: UFix; R: unsigned) return boolean is - begin - return L < To_UFix(R); - end; - - -- R.2.3. unsigned < UFix - function "<" (L: unsigned; R: UFix) return boolean is - begin - return To_UFix(L) < R; - end; - - -- R.2.4. UFix < integer - function "<" (L: UFix; R: integer) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, R, clip_MS, clip_LS); - return L < S; - end; - - -- R.2.5. integer < UFix - function "<" (L: integer; R: UFix) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, L, clip_MS, clip_LS); - return S < R; - end; - - -- R.2.6. SFix < SFix - function "<" (L: SFix; R: SFix) return boolean is - variable LW, RW: SFix(Max(L'LEFT, R'LEFT) downto - Min(L'RIGHT, R'RIGHT)); - begin - Copy_V(LW, L, clip_MS, clip_LS); - Copy_V(RW, R, clip_MS, clip_LS); - return signed(LW) < signed(RW); - end; - - -- R.2.7. SFix < UFix - function "<" (L: SFix; R: UFix) return boolean is - begin - return L < To_SFix(R); - end; - - -- R.2.8. UFix < SFix - function "<" (L: UFix; R: SFix) return boolean is - begin - return To_SFix(L) < R; - end; - - -- R.2.9. SFix < signed - function "<" (L: SFix; R: signed) return boolean is - begin - return L < To_SFix(R); - end; - - -- R.2.10. signed < SFix - function "<" (L: signed; R: SFix) return boolean is - begin - return To_SFix(L) < R; - end; - - -- R.2.11. SFix < integer - function "<" (L: SFix; R: integer) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, R, clip_MS, clip_LS); - return L < S; - end; - - -- R.2.12. integer < SFix - function "<" (L: integer; R: SFix) return boolean is - variable S: SFix(FixP+INT_WIDTH-1 downto FixP); - begin - Copy_V(S, L, clip_MS, clip_LS); - return S < R; - end; - - - ---------------------------------------- - -- R.3. Binary "/=" inequality operator - ---------------------------------------- - - -- R.3.1. UFix /= UFix - function "/=" (L: UFix; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.2. UFix /= unsigned - function "/=" (L: UFix; R: unsigned) return boolean is - begin - return not (L = R); - end; - - -- R.3.3. unsigned /= UFix - function "/=" (L: unsigned; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.4. UFix /= integer - function "/=" (L: UFix; R: integer) return boolean is - begin - return not (L = R); - end; - - -- R.3.5. integer /= UFix - function "/=" (L: integer; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.6. SFix /= SFix - function "/=" (L: SFix; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.7. SFix /= UFix - function "/=" (L: SFix; R: UFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.8. UFix /= SFix - function "/=" (L: UFix; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.9. SFix /= signed - function "/=" (L: SFix; R: signed) return boolean is - begin - return not (L = R); - end; - - -- R.3.10. signed /= SFix - function "/=" (L: signed; R: SFix) return boolean is - begin - return not (L = R); - end; - - -- R.3.11. SFix /= integer - function "/=" (L: SFix; R: integer) return boolean is - begin - return not (L = R); - end; - - -- R.3.12. integer /= SFix - function "/=" (L: integer; R: SFix) return boolean is - begin - return not (L = R); - end; - - - ----------------------------------------- - -- R.4. Binary ">" greater-than operator - ----------------------------------------- - - -- R.4.1. UFix > UFix - function ">" (L: UFix; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.2. UFix > unsigned - function ">" (L: UFix; R: unsigned) return boolean is - begin - return R < L; - end; - - -- R.4.3. unsigned > UFix - function ">" (L: unsigned; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.4. UFix > integer - function ">" (L: UFix; R: integer) return boolean is - begin - return R < L; - end; - - -- R.4.5. integer > UFix - function ">" (L: integer; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.6. SFix > SFix - function ">" (L: SFix; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.7. SFix > UFix - function ">" (L: SFix; R: UFix) return boolean is - begin - return R < L; - end; - - -- R.4.8. UFix > SFix - function ">" (L: UFix; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.9. SFix > signed - function ">" (L: SFix; R: signed) return boolean is - begin - return R < L; - end; - - -- R.4.10. signed > SFix - function ">" (L: signed; R: SFix) return boolean is - begin - return R < L; - end; - - -- R.4.11. SFix > integer - function ">" (L: SFix; R: integer) return boolean is - begin - return R < L; - end; - - -- R.4.12. integer > SFix - function ">" (L: integer; R: SFix) return boolean is - begin - return R < L; - end; - - - ---------------------------------------------- - -- R.5. Binary ">=" greater-or-equal operator - ---------------------------------------------- - - -- R.5.1. UFix >= UFix - function ">=" (L: UFix; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.2. UFix >= unsigned - function ">=" (L: UFix; R: unsigned) return boolean is - begin - return not (L < R); - end; - - -- R.5.3. unsigned >= UFix - function ">=" (L: unsigned; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.4. UFix >= integer - function ">=" (L: UFix; R: integer) return boolean is - begin - return not (L < R); - end; - - -- R.5.5. integer >= UFix - function ">=" (L: integer; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.6. SFix >= SFix - function ">=" (L: SFix; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.7. SFix >= UFix - function ">=" (L: SFix; R: UFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.8. UFix >= SFix - function ">=" (L: UFix; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.9. SFix >= signed - function ">=" (L: SFix; R: signed) return boolean is - begin - return not (L < R); - end; - - -- R.5.10. signed >= SFix - function ">=" (L: signed; R: SFix) return boolean is - begin - return not (L < R); - end; - - -- R.5.11. SFix >= integer - function ">=" (L: SFix; R: integer) return boolean is - begin - return not (L < R); - end; - - -- R.5.12. integer >= SFix - function ">=" (L: integer; R: SFix) return boolean is - begin - return not (L < R); - end; - - - ------------------------------------------- - -- R.6. Binary "<=" less-or-equal operator - ------------------------------------------- - - -- R.6.1. UFix <= UFix - function "<=" (L: UFix; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.2. UFix <= unsigned - function "<=" (L: UFix; R: unsigned) return boolean is - begin - return not (R < L); - end; - - -- R.6.3. unsigned <= UFix - function "<=" (L: unsigned; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.4. UFix <= integer - function "<=" (L: UFix; R: integer) return boolean is - begin - return not (R < L); - end; - - -- R.6.5. integer <= UFix - function "<=" (L: integer; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.6. SFix <= SFix - function "<=" (L: SFix; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.7. SFix <= UFix - function "<=" (L: SFix; R: UFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.8. UFix <= SFix - function "<=" (L: UFix; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.9. SFix <= signed - function "<=" (L: SFix; R: signed) return boolean is - begin - return not (R < L); - end; - - -- R.6.10. signed <= SFix - function "<=" (L: signed; R: SFix) return boolean is - begin - return not (R < L); - end; - - -- R.6.11. SFix <= integer - function "<=" (L: SFix; R: integer) return boolean is - begin - return not (R < L); - end; - - -- R.6.12. integer <= SFix - function "<=" (L: integer; R: SFix) return boolean is - begin - return not (R < L); - end; - - ------------------------------------------------------------------ - -- C. Concatenation operators between fixed-point operands, and - -- between fixed-point operands and other reasonable types. - -- Unlike the implicitly defined "&" operator, they preserve - -- place value and return an appropriately aligned subtype. - -- Preservation of place value means that some concatenation - -- operations are illegal. In particular, operations - -- [SFix & SFix] and [UFix & SFix] are illegal, and - -- the place values of operands in [SFix & UFix] and - -- [UFix & UFix] must match up - the rightmost subscript of - -- the left operand must be one higher than the leftmost - -- subscript of the right operand. - -- Single bits of type std_ulogic may be concatenated with - -- fixed-point types where there is no risk of losing - -- sign-extension information. - -- Because of the way VHDL defines implicit concatenation, - -- it is impossible to detect all these errors at compile time. - -- Instead they are detected by assertion statements at run time. - -- Tool vendors may choose to implement compile-time checks - -- so that the run-time checking overhead can be avoided. - ------------------------------------------------------------------ - - -- C.1.1. UFix := UFix & UFix - function "&" (L: UFix; R: UFix) return UFix is - begin - return UFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.1.2. UFix := UFix & std_ulogic - function "&" (L: UFix; R: std_ulogic) return UFix is - begin - return UFix(concat(std_logic_vector(L), R)); - end; - - -- C.1.3. UFix := std_ulogic & UFix - function "&" (L: std_ulogic; R: UFix) return UFix is - begin - return UFix(concat(L, std_logic_vector(R))); - end; - - - -- C.2.1. SFix := SFix & UFix - function "&" (L: SFix; R: UFix) return SFix is - begin - return SFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.2.2. SFix := SFix & SFix -- ILLEGAL - function "&" (L: SFix; R: SFix) return SFix is - begin - report concat_signLS_msg - severity concat_severity; - return SFix(concat(std_logic_vector(L), std_logic_vector(R))); - end; - - -- C.2.3. SFix := SFix & std_ulogic - function "&" (L: SFix; R: std_ulogic) return SFix is - begin - return SFix(concat(std_logic_vector(L), R)); - end; - - -- C.2.4. SFix := std_ulogic & SFix - function "&" (L: std_ulogic; R: SFix) return SFix is - begin - assert std_match(L, R(R'LEFT)) - report concat_sxt_msg - severity concat_severity; - return SFix(concat(L, std_logic_vector(R))); - end; - - -end; -- package body fix_std; diff --git a/lib/fixed/fixed_pkg_c.vhd b/lib/fixed/fixed_pkg_c.vhd deleted file mode 100644 index 68acdd1..0000000 --- a/lib/fixed/fixed_pkg_c.vhd +++ /dev/null @@ -1,7846 +0,0 @@ ------------------------------------------------------------------------------- --- "fixed_pkg" package contains functions for fixed point math. --- Please see the documentation for the fixed point package. --- This package should be compiled into "ieee_proposed" and used as follows: --- use ieee.std_logic_1164.all; --- use ieee.numeric_std.all; --- use ieee_proposed.fixed_pkg.all; --- Last Modified: $Date: 2008-08-23 08:20:29 $ --- RCS ID: $Id: fixed_pkg_c.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ --- --- Created for VHDL-200X par, David Bishop (dbishop@vhdl.org) ------------------------------------------------------------------------------- -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; --- synthesis translate_off -use std.textio.all; --- synthesis translate_on - -package fixed_pkg is - --%%% Uncomment the Generics --- new work.fixed_generic_pkg --- generic map ( --- fixed_round_style => true; -- fixed_round --- fixed_overflow_style => true; -- fixed_saturate --- fixed_guard_bits => 3; -- number of guard bits --- no_warning => false -- show warnings --- ); - --%%% REMOVE THE REST OF THIS FILE. - constant fixed_round_style : BOOLEAN := false; -- round - constant fixed_overflow_style : BOOLEAN := false; -- saturate - constant fixed_guard_bits : NATURAL := 3; -- number of guard bits - constant no_warning : BOOLEAN := false; -- issue warnings - -- Author David Bishop (dbishop@vhdl.org) - -- These 5 constants are used as defaults. - -- There is a mechanism to override them in every function - constant fixed_round : BOOLEAN := true; -- Turn on rounding routine - constant fixed_truncate : BOOLEAN := false; -- Trun off rounding routine - constant fixed_saturate : BOOLEAN := true; -- Saturate large numbers - constant fixed_wrap : BOOLEAN := false; -- Wrap large numbers - constant fixedsynth_or_real : BOOLEAN := true; -- differed constant - -- base Unsigned fixed point type, downto direction assumed - type ufixed is array (INTEGER range <>) of STD_LOGIC; - -- base Signed fixed point type, downto direction assumed - type sfixed is array (INTEGER range <>) of STD_LOGIC; - ----------------------------------------------------------------------------- - -- Fixed point type is defined as follows: - -- 0000000000 - -- 4321012345 - -- 4 0 -5 - -- The decimal point is assumed between the "0" and "-1" index - -- Thus "0011010000" = 6.5 and would be written as 00110.10000 - -- All types are assumed to be in the "downto" direction. - - --=========================================================================== - -- Arithmetic Operators: - --=========================================================================== - -- Modify the sign of the number, 2's complement - function "abs" (arg : sfixed) return sfixed; - function "-" (arg : sfixed)return sfixed; - - -- Convert a signed fixed to an unsigned fixed - function "abs" (arg : sfixed) return ufixed; - - -- Addition - -- ufixed(a downto b) + ufixed(c downto d) - -- = ufixed(max(a,c)+1 downto min(b,d)) - function "+" (l, r : ufixed) return ufixed; - - -- sfixed(a downto b) + sfixed(c downto d) - -- = sfixed(max(a,c)+1 downto min(b,d)) - function "+" (l, r : sfixed) return sfixed; - - -- Subtraction - -- ufixed(a downto b) - ufixed(c downto d) - -- = ufixed(max(a,c)+1 downto min(b,d)) - function "-" (l, r : ufixed) return ufixed; - - -- sfixed(a downto b) - sfixed(c downto d) - -- = sfixed(max(a,c)+1 downto min(b,d)) - function "-" (l, r : sfixed) return sfixed; - - -- Multiplication - -- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d) - function "*" (l, r : ufixed) return ufixed; - - -- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d) - function "*" (l, r : sfixed) return sfixed; - - -- Division - -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) - function "/" (l, r : ufixed) return ufixed; - - -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) - function "/" (l, r : sfixed) return sfixed; - - -- Remainder - -- ufixed (a downto b) rem ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b,d)) - function "rem" (l, r : ufixed) return ufixed; - - -- sfixed (a downto b) rem sfixed (c downto d) - -- = sfixed (min(a,c) downto min(b,d)) - function "rem" (l, r : sfixed) return sfixed; - - -- Modulo - -- ufixed (a downto b) mod ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b, d)) - function "mod" (l, r : ufixed) return ufixed; - - -- sfixed (a downto b) mod sfixed (c downto d) - -- = sfixed (c downto min(b, d)) - function "mod" (l, r : sfixed) return sfixed; - - ---------------------------------------------------------------------------- - -- Overload routines. In these routines the "real" or "natural" (integer) - -- are converted into a fixed point number and then the operation is - -- performed. It is assumed that the array will be large enough. - -- If the input is "real" then the real number is converted into a fixed of - -- the same size as the fixed point input. If the number is an "integer" - -- then it is converted into fixed with the range (l'high downto 0). - ---------------------------------------------------------------------------- - -- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b) - function "+" (l : ufixed; r : REAL) return ufixed; - - -- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d) - function "+" (l : REAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto min(0,b)) - function "+" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d)) - function "+" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b) - function "-" (l : ufixed; r : REAL) return ufixed; - - -- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d) - function "-" (l : REAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto min(0,b)) - function "-" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d)) - function "-" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b) - function "*" (l : ufixed; r : REAL) return ufixed; - - -- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d) - function "*" (l : REAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b) - function "*" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b) - function "*" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) - function "/" (l : ufixed; r : REAL) return ufixed; - - -- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1) - function "/" (l : REAL; r : ufixed) return ufixed; - - -- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1) - function "/" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1) - function "/" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b) - function "rem" (l : ufixed; r : REAL) return ufixed; - - -- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d) - function "rem" (l : REAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto min(b,0)) - function "rem" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto min(d,0)) - function "rem" (l : NATURAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b) - function "mod" (l : ufixed; r : REAL) return ufixed; - - -- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d) - function "mod" (l : REAL; r : ufixed) return ufixed; - - -- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto min(b,0)) - function "mod" (l : ufixed; r : NATURAL) return ufixed; - - -- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto min(d,0)) - function "mod" (l : NATURAL; r : ufixed) return ufixed; - - -- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b) - function "+" (l : sfixed; r : REAL) return sfixed; - - -- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d) - function "+" (l : REAL; r : sfixed) return sfixed; - - -- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto min(0,b)) - function "+" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto min(0,d)) - function "+" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b) - function "-" (l : sfixed; r : REAL) return sfixed; - - -- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d) - function "-" (l : REAL; r : sfixed) return sfixed; - - -- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto min(0,b)) - function "-" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto min(0,d)) - function "-" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b) - function "*" (l : sfixed; r : REAL) return sfixed; - - -- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d) - function "*" (l : REAL; r : sfixed) return sfixed; - - -- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b) - function "*" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d) - function "*" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a) - function "/" (l : sfixed; r : REAL) return sfixed; - - -- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c) - function "/" (l : REAL; r : sfixed) return sfixed; - - -- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a) - function "/" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c) - function "/" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b) - function "rem" (l : sfixed; r : REAL) return sfixed; - - -- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d) - function "rem" (l : REAL; r : sfixed) return sfixed; - - -- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto min(b,0)) - function "rem" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto min(d,0)) - function "rem" (l : INTEGER; r : sfixed) return sfixed; - - -- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b) - function "mod" (l : sfixed; r : REAL) return sfixed; - - -- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d) - function "mod" (l : REAL; r : sfixed) return sfixed; - - -- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto min(b,0)) - function "mod" (l : sfixed; r : INTEGER) return sfixed; - - -- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto min(d,0)) - function "mod" (l : INTEGER; r : sfixed) return sfixed; - - -- This version of divide gives the user more control - -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) - function divide ( - l, r : ufixed; - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return ufixed; - - -- This version of divide gives the user more control - -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) - function divide ( - l, r : sfixed; - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return sfixed; - - -- These functions return 1/X - -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1) - function reciprocal ( - arg : ufixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return ufixed; - - -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a) - function reciprocal ( - arg : sfixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return sfixed; - - -- REM function - -- ufixed (a downto b) rem ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b,d)) - function remainder ( - l, r : ufixed; - constant round_style : BOOLEAN := fixed_round_style) - return ufixed; - - -- sfixed (a downto b) rem sfixed (c downto d) - -- = sfixed (min(a,c) downto min(b,d)) - function remainder ( - l, r : sfixed; - constant round_style : BOOLEAN := fixed_round_style) - return sfixed; - - -- mod function - -- ufixed (a downto b) mod ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b, d)) - function modulo ( - l, r : ufixed; - constant round_style : BOOLEAN := fixed_round_style) - return ufixed; - - -- sfixed (a downto b) mod sfixed (c downto d) - -- = sfixed (c downto min(b, d)) - function modulo ( - l, r : sfixed; - constant overflow_style : BOOLEAN := fixed_overflow_style; - constant round_style : BOOLEAN := fixed_round_style) - return sfixed; - - -- Procedure for those who need an "accumulator" function. - -- add_carry (ufixed(a downto b), ufixed (c downto d)) - -- = ufixed (max(a,c) downto min(b,d)) - procedure add_carry ( - L, R : in ufixed; - c_in : in STD_ULOGIC; - result : out ufixed; - c_out : out STD_ULOGIC); - - -- add_carry (sfixed(a downto b), sfixed (c downto d)) - -- = sfixed (max(a,c) downto min(b,d)) - procedure add_carry ( - L, R : in sfixed; - c_in : in STD_ULOGIC; - result : out sfixed; - c_out : out STD_ULOGIC); - - -- Scales the result by a power of 2. Width of input = width of output with - -- the decimal point moved. - function scalb (y : ufixed; N : integer) return ufixed; - function scalb (y : ufixed; N : SIGNED) return ufixed; - function scalb (y : sfixed; N : integer) return sfixed; - function scalb (y : sfixed; N : SIGNED) return sfixed; - - function Is_Negative (arg : sfixed) return BOOLEAN; - --=========================================================================== - -- Comparison Operators - --=========================================================================== - function ">" (l, r : ufixed) return BOOLEAN; - function ">" (l, r : sfixed) return BOOLEAN; - function "<" (l, r : ufixed) return BOOLEAN; - function "<" (l, r : sfixed) return BOOLEAN; - function "<=" (l, r : ufixed) return BOOLEAN; - function "<=" (l, r : sfixed) return BOOLEAN; - function ">=" (l, r : ufixed) return BOOLEAN; - function ">=" (l, r : sfixed) return BOOLEAN; - function "=" (l, r : ufixed) return BOOLEAN; - function "=" (l, r : sfixed) return BOOLEAN; - function "/=" (l, r : ufixed) return BOOLEAN; - function "/=" (l, r : sfixed) return BOOLEAN; - --%%% Uncomment the following (new syntax) --- function "?=" (L, R : ufixed) return BOOLEAN; --- function "?=" (L, R : sfixed) return BOOLEAN; --- --%%% remove the following (old syntax) - function \?=\ (L, R : ufixed) return STD_ULOGIC; - function \?=\ (L, R : sfixed) return STD_ULOGIC; - -- These need to be overloaded for sfixed and ufixed - function \?/=\ (L, R : ufixed) return STD_ULOGIC; - function \?>\ (L, R : ufixed) return STD_ULOGIC; - function \?>=\ (L, R : ufixed) return STD_ULOGIC; - function \?<\ (L, R : ufixed) return STD_ULOGIC; - function \?<=\ (L, R : ufixed) return STD_ULOGIC; - function \?/=\ (L, R : sfixed) return STD_ULOGIC; - function \?>\ (L, R : sfixed) return STD_ULOGIC; - function \?>=\ (L, R : sfixed) return STD_ULOGIC; - function \?<\ (L, R : sfixed) return STD_ULOGIC; - function \?<=\ (L, R : sfixed) return STD_ULOGIC; - -- %%% Replace with the following (new syntax) --- function "?=" (L, R : ufixed) return STD_ULOGIC; --- function "?/=" (L, R : ufixed) return STD_ULOGIC; --- function "?>" (L, R : ufixed) return STD_ULOGIC; --- function "?>=" (L, R : ufixed) return STD_ULOGIC; --- function "?<" (L, R : ufixed) return STD_ULOGIC; --- function "?<=" (L, R : ufixed) return STD_ULOGIC; --- function "?=" (L, R : sfixed) return STD_ULOGIC; --- function "?/=" (L, R : sfixed) return STD_ULOGIC; --- function "?>" (L, R : sfixed) return STD_ULOGIC; --- function "?>=" (L, R : sfixed) return STD_ULOGIC; --- function "?<" (L, R : sfixed) return STD_ULOGIC; --- function "?<=" (L, R : sfixed) return STD_ULOGIC; - - function std_match (L, R : ufixed) return BOOLEAN; - function std_match (L, R : sfixed) return BOOLEAN; - - -- Overloads the default "maximum" and "minimum" function - function maximum (l, r : ufixed) return ufixed; - function minimum (l, r : ufixed) return ufixed; - function maximum (l, r : sfixed) return sfixed; - function minimum (l, r : sfixed) return sfixed; - - ---------------------------------------------------------------------------- - -- In these compare functions a natural is converted into a - -- fixed point number of the bounds "max(l'high,0) downto 0" - ---------------------------------------------------------------------------- - function "=" (l : ufixed; r : NATURAL) return BOOLEAN; - function "/=" (l : ufixed; r : NATURAL) return BOOLEAN; - function ">=" (l : ufixed; r : NATURAL) return BOOLEAN; - function "<=" (l : ufixed; r : NATURAL) return BOOLEAN; - function ">" (l : ufixed; r : NATURAL) return BOOLEAN; - function "<" (l : ufixed; r : NATURAL) return BOOLEAN; - - function "=" (l : NATURAL; r : ufixed) return BOOLEAN; - function "/=" (l : NATURAL; r : ufixed) return BOOLEAN; - function ">=" (l : NATURAL; r : ufixed) return BOOLEAN; - function "<=" (l : NATURAL; r : ufixed) return BOOLEAN; - function ">" (l : NATURAL; r : ufixed) return BOOLEAN; - function "<" (l : NATURAL; r : ufixed) return BOOLEAN; - - ---------------------------------------------------------------------------- - -- In these compare functions a real is converted into a - -- fixed point number of the bounds "l'high+1 downto l'low" - ---------------------------------------------------------------------------- - function "=" (l : ufixed; r : REAL) return BOOLEAN; - function "/=" (l : ufixed; r : REAL) return BOOLEAN; - function ">=" (l : ufixed; r : REAL) return BOOLEAN; - function "<=" (l : ufixed; r : REAL) return BOOLEAN; - function ">" (l : ufixed; r : REAL) return BOOLEAN; - function "<" (l : ufixed; r : REAL) return BOOLEAN; - - function "=" (l : REAL; r : ufixed) return BOOLEAN; - function "/=" (l : REAL; r : ufixed) return BOOLEAN; - function ">=" (l : REAL; r : ufixed) return BOOLEAN; - function "<=" (l : REAL; r : ufixed) return BOOLEAN; - function ">" (l : REAL; r : ufixed) return BOOLEAN; - function "<" (l : REAL; r : ufixed) return BOOLEAN; - - ---------------------------------------------------------------------------- - -- In these compare functions an integer is converted into a - -- fixed point number of the bounds "max(l'high,1) downto 0" - ---------------------------------------------------------------------------- - function "=" (l : sfixed; r : INTEGER) return BOOLEAN; - function "/=" (l : sfixed; r : INTEGER) return BOOLEAN; - function ">=" (l : sfixed; r : INTEGER) return BOOLEAN; - function "<=" (l : sfixed; r : INTEGER) return BOOLEAN; - function ">" (l : sfixed; r : INTEGER) return BOOLEAN; - function "<" (l : sfixed; r : INTEGER) return BOOLEAN; - - function "=" (l : INTEGER; r : sfixed) return BOOLEAN; - function "/=" (l : INTEGER; r : sfixed) return BOOLEAN; - function ">=" (l : INTEGER; r : sfixed) return BOOLEAN; - function "<=" (l : INTEGER; r : sfixed) return BOOLEAN; - function ">" (l : INTEGER; r : sfixed) return BOOLEAN; - function "<" (l : INTEGER; r : sfixed) return BOOLEAN; - - ---------------------------------------------------------------------------- - -- In these compare functions a real is converted into a - -- fixed point number of the bounds "l'high+1 downto l'low" - ---------------------------------------------------------------------------- - function "=" (l : sfixed; r : REAL) return BOOLEAN; - function "/=" (l : sfixed; r : REAL) return BOOLEAN; - function ">=" (l : sfixed; r : REAL) return BOOLEAN; - function "<=" (l : sfixed; r : REAL) return BOOLEAN; - function ">" (l : sfixed; r : REAL) return BOOLEAN; - function "<" (l : sfixed; r : REAL) return BOOLEAN; - - function "=" (l : REAL; r : sfixed) return BOOLEAN; - function "/=" (l : REAL; r : sfixed) return BOOLEAN; - function ">=" (l : REAL; r : sfixed) return BOOLEAN; - function "<=" (l : REAL; r : sfixed) return BOOLEAN; - function ">" (l : REAL; r : sfixed) return BOOLEAN; - function "<" (l : REAL; r : sfixed) return BOOLEAN; - - --=========================================================================== - -- Shift and Rotate Functions. - -- Note that sra and sla are not the same as the BIT_VECTOR version - --=========================================================================== - function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed; - function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed; - function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed; - function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed; - function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed; - function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed; - - ---------------------------------------------------------------------------- - -- logical functions - ---------------------------------------------------------------------------- - function "not" (L : ufixed) return ufixed; - function "and" (L, R : ufixed) return ufixed; - function "or" (L, R : ufixed) return ufixed; - function "nand" (L, R : ufixed) return ufixed; - function "nor" (L, R : ufixed) return ufixed; - function "xor" (L, R : ufixed) return ufixed; - function "xnor" (L, R : ufixed) return ufixed; - function "not" (L : sfixed) return sfixed; - function "and" (L, R : sfixed) return sfixed; - function "or" (L, R : sfixed) return sfixed; - function "nand" (L, R : sfixed) return sfixed; - function "nor" (L, R : sfixed) return sfixed; - function "xor" (L, R : sfixed) return sfixed; - function "xnor" (L, R : sfixed) return sfixed; - - -- Vector and std_ulogic functions, same as functions in numeric_std - function "and" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "and" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "or" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "or" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed; - function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed; - function "and" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "and" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "or" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "or" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed; - function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed; - function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed; - - -- Reduction operators, same as numeric_std functions - -- %%% remove 12 functions (old syntax) - function and_reduce(arg : ufixed) return STD_ULOGIC; - function nand_reduce(arg : ufixed) return STD_ULOGIC; - function or_reduce(arg : ufixed) return STD_ULOGIC; - function nor_reduce(arg : ufixed) return STD_ULOGIC; - function xor_reduce(arg : ufixed) return STD_ULOGIC; - function xnor_reduce(arg : ufixed) return STD_ULOGIC; - function and_reduce(arg : sfixed) return STD_ULOGIC; - function nand_reduce(arg : sfixed) return STD_ULOGIC; - function or_reduce(arg : sfixed) return STD_ULOGIC; - function nor_reduce(arg : sfixed) return STD_ULOGIC; - function xor_reduce(arg : sfixed) return STD_ULOGIC; - function xnor_reduce(arg : sfixed) return STD_ULOGIC; - -- %%% Uncomment the following 12 functions (new syntax) - -- function "and" ( arg : ufixed ) RETURN std_ulogic; - -- function "nand" ( arg : ufixed ) RETURN std_ulogic; - -- function "or" ( arg : ufixed ) RETURN std_ulogic; - -- function "nor" ( arg : ufixed ) RETURN std_ulogic; - -- function "xor" ( arg : ufixed ) RETURN std_ulogic; - -- function "xnor" ( arg : ufixed ) RETURN std_ulogic; - -- function "and" ( arg : sfixed ) RETURN std_ulogic; - -- function "nand" ( arg : sfixed ) RETURN std_ulogic; - -- function "or" ( arg : sfixed ) RETURN std_ulogic; - -- function "nor" ( arg : sfixed ) RETURN std_ulogic; - -- function "xor" ( arg : sfixed ) RETURN std_ulogic; - -- function "xnor" ( arg : sfixed ) RETURN std_ulogic; - - -- returns arg'low-1 if not found - function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER; - function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER; - - -- returns arg'high+1 if not found - function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER; - function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER; - - --=========================================================================== - -- RESIZE Functions - --=========================================================================== - -- resizes the number (larger or smaller) - -- The returned result will be ufixed (left_index downto right_index) - -- If "round_style" is true, then the result will be rounded. If the MSB - -- of the remainder is a "1" AND the LSB of the unround result is a '1' or - -- the lower bits of the remainder include a '1' then the result will be - -- increased by the smallest representable number for that type. - -- The default is "true" for round_style. - -- "overflow_style" can be "true" (saturate mode) or "false" (wrap mode). - -- In saturate mode, if the number overflows then the largest possible - -- representable number is returned. If wrap mode, then the upper bits - -- of the number are truncated. - function resize ( - arg : ufixed; -- input - constant left_index : INTEGER; -- integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed; - - -- "size_res" functions create the size of the output from the length - -- of the "size_res" input. The actual value of "size_res" is not used. - function resize ( - arg : ufixed; -- input - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed; - - -- Note that in "wrap" mode the sign bit is not replicated. Thus the - -- resize of a negative number can have a positive result in wrap mode. - function resize ( - arg : sfixed; -- input - constant left_index : INTEGER; -- integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - function resize ( - arg : sfixed; -- input - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - --=========================================================================== - -- Conversion Functions - --=========================================================================== - -- integer (natural) to unsigned fixed point. - -- arguments are the upper and lower bounds of the number, thus - -- ufixed (7 downto -3) <= to_ufixed (int, 7, -3); - function to_ufixed ( - arg : NATURAL; -- integer - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding - return ufixed; - - function to_ufixed ( - arg : NATURAL; -- integer - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding - return ufixed; - - -- real to unsigned fixed point - function to_ufixed ( - arg : REAL; -- real - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return ufixed; - - function to_ufixed ( - arg : REAL; -- real - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return ufixed; - - -- unsigned to unsigned fixed point - function to_ufixed ( - arg : UNSIGNED; -- unsigned - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return ufixed; - - function to_ufixed ( - arg : UNSIGNED; -- unsigned - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return ufixed; - - -- Performs a casting. ufixed (arg'range) is returned - function to_ufixed ( - arg : UNSIGNED) -- unsigned - return ufixed; - - -- unsigned fixed point to unsigned - function to_unsigned ( - arg : ufixed; -- fixed point input - constant size : NATURAL; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return UNSIGNED; - - -- unsigned fixed point to unsigned - function to_unsigned ( - arg : ufixed; -- fixed point input - size_res : UNSIGNED; -- used for length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return UNSIGNED; - - -- unsigned fixed point to real - function to_real ( - arg : ufixed) -- fixed point input - return REAL; - - -- unsigned fixed point to integer - function to_integer ( - arg : ufixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return NATURAL; - - -- Integer to sfixed - function to_sfixed ( - arg : INTEGER; -- integer - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - function to_sfixed ( - arg : INTEGER; -- integer - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - -- Real to sfixed - function to_sfixed ( - arg : REAL; -- real - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return sfixed; - - function to_sfixed ( - arg : REAL; -- real - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return sfixed; - - -- signed to sfixed - function to_sfixed ( - arg : SIGNED; -- signed - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - function to_sfixed ( - arg : SIGNED; -- signed - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return sfixed; - - -- signed to sfixed (output assumed to be size of signed input) - function to_sfixed ( - arg : SIGNED) -- signed - return sfixed; - - -- unsigned fixed point to signed fixed point (adds a "0" sign bit) - function add_sign ( - arg : ufixed) -- unsigned fixed point - return sfixed; - - -- signed fixed point to signed - function to_signed ( - arg : sfixed; -- fixed point input - constant size : NATURAL; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return SIGNED; - - -- signed fixed point to signed - function to_signed ( - arg : sfixed; -- fixed point input - size_res : SIGNED; -- used for length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return SIGNED; - - -- signed fixed point to real - function to_real ( - arg : sfixed) -- fixed point input - return REAL; - - -- signed fixed point to integer - function to_integer ( - arg : sfixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return INTEGER; - - -- Because of the farily complicated sizing rules in the fixed point - -- packages these functions are provided to compute the result ranges - -- Example: - -- signal uf1 : ufixed (3 downto -3); - -- signal uf2 : ufixed (4 downto -2); - -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto - -- ufixed_low (3, -3, '*', 4, -2)); - -- uf1multuf2 <= uf1 * uf2; - -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod) - function ufixed_high (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER; - function ufixed_low (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER; - function sfixed_high (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER; - function sfixed_low (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER; - -- Same as above, but using the "size_res" input only for their ranges: - -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto - -- ufixed_low (uf1, '*', uf2)); - -- uf1multuf2 <= uf1 * uf2; - function ufixed_high (size_res : ufixed; - operation : CHARACTER := 'X'; - size_res2 : ufixed) - return INTEGER; - function ufixed_low (size_res : ufixed; - operation : CHARACTER := 'X'; - size_res2 : ufixed) - return INTEGER; - function sfixed_high (size_res : sfixed; - operation : CHARACTER := 'X'; - size_res2 : sfixed) - return INTEGER; - function sfixed_low (size_res : sfixed; - operation : CHARACTER := 'X'; - size_res2 : sfixed) - return INTEGER; - - -- purpose: returns a saturated number - function saturate ( - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - -- purpose: returns a saturated number - function saturate ( - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - function saturate ( - size_res : ufixed) -- only the size of this is used - return ufixed; - - function saturate ( - size_res : sfixed) -- only the size of this is used - return sfixed; - - --=========================================================================== - -- Translation Functions - --=========================================================================== - -- Maps meta-logical values - function to_01 ( - s : ufixed; -- fixed point input - constant XMAP : STD_LOGIC := '0') -- Map x to - return ufixed; - - -- maps meta-logical values - function to_01 ( - s : sfixed; -- fixed point input - constant XMAP : STD_LOGIC := '0') -- Map x to - return sfixed; - - function Is_X (arg : ufixed) return BOOLEAN; - function Is_X (arg : sfixed) return BOOLEAN; - function to_X01 (arg : ufixed) return ufixed; - function to_X01 (arg : sfixed) return sfixed; - function to_X01Z (arg : ufixed) return ufixed; - function to_X01Z (arg : sfixed) return sfixed; - function to_UX01 (arg : ufixed) return ufixed; - function to_UX01 (arg : sfixed) return sfixed; - - -- straight vector conversion routines, needed for synthesis. - -- These functions are here so that a std_logic_vector can be - -- converted to and from sfixed and ufixed. Note that you can - -- not cast these vectors because of their negative index. - function to_slv ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR; --- alias to_StdLogicVector is to_slv [ufixed return STD_LOGIC_VECTOR]; --- alias to_Std_Logic_Vector is to_slv [ufixed return STD_LOGIC_VECTOR]; - - function to_slv ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR; --- alias to_StdLogicVector is to_slv [sfixed return STD_LOGIC_VECTOR]; --- alias to_Std_Logic_Vector is to_slv [sfixed return STD_LOGIC_VECTOR]; - - function to_sulv ( - arg : ufixed) -- fp vector - return STD_ULOGIC_VECTOR; --- alias to_StdULogicVector is to_sulv [ufixed return STD_ULOGIC_VECTOR]; --- alias to_Std_ULogic_Vector is to_sulv [ufixed return STD_ULOGIC_VECTOR]; - - function to_sulv ( - arg : sfixed) -- fp vector - return STD_ULOGIC_VECTOR; --- alias to_StdULogicVector is to_sulv [sfixed return STD_ULOGIC_VECTOR]; --- alias to_Std_ULogic_Vector is to_sulv [sfixed return STD_ULOGIC_VECTOR]; - - function to_ufixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - function to_ufixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - size_res : ufixed) -- for size only - return ufixed; - - function to_sfixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - function to_sfixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - size_res : sfixed) -- for size only - return sfixed; - - function to_ufixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - function to_ufixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - size_res : ufixed) -- for size only - return ufixed; - - function to_sfixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - function to_sfixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - size_res : sfixed) -- for size only - return sfixed; - - -- As a concession to those who use a graphical DSP environment, - -- these functions take parameters in those tools format and create - -- fixed point numbers. These functions are designed to convert from - -- a std_logic_vector to the VHDL fixed point format using the conventions - -- of these packages. In a pure VHDL environment you should use the - -- "to_ufixed" and "to_sfixed" routines. - -- Unsigned fixed point - function to_UFix ( - arg : STD_LOGIC_VECTOR; - width : NATURAL; -- width of vector - fraction : NATURAL) -- width of fraction - return ufixed; - -- signed fixed point - function to_SFix ( - arg : STD_LOGIC_VECTOR; - width : NATURAL; -- width of vector - fraction : NATURAL) -- width of fraction - return sfixed; - -- finding the bounds of a number. These functions can be used like this: - -- signal xxx : ufixed (7 downto -3); - -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))" - -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3) - -- downto UFix_low(11, 3, "+", 11, 3)); - -- Where "11" is the width of xxx (xxx'length), - -- and 3 is the lower bound (abs (xxx'low)) - -- In a pure VHDL environment use "ufixed_high" and "ufixed_low" - function UFix_high (width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER; - function UFix_low (width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER; - -- Same as above but for signed fixed point. Note that the width - -- of a signed fixed point number ignores the sign bit, thus - -- width = sxxx'length-1 - function SFix_high (width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER; - function SFix_low (width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER; - --=========================================================================== - -- string and textio Functions - --=========================================================================== --- rtl_synthesis off --- synthesis translate_off - -- purpose: writes fixed point into a line - procedure WRITE ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - -- purpose: writes fixed point into a line - procedure WRITE ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - procedure READ(L : inout LINE; - VALUE : out ufixed); - - procedure READ(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN); - - procedure READ(L : inout LINE; - VALUE : out sfixed); - - procedure READ(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN); - - alias bwrite is WRITE [LINE, ufixed, SIDE, width]; - alias bwrite is WRITE [LINE, sfixed, SIDE, width]; - alias bread is READ [LINE, ufixed]; - alias bread is READ [LINE, ufixed, BOOLEAN]; - alias bread is READ [LINE, sfixed]; - alias bread is READ [LINE, sfixed, BOOLEAN]; - - -- octal read and write - procedure OWRITE ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - procedure OWRITE ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - procedure OREAD(L : inout LINE; - VALUE : out ufixed); - - procedure OREAD(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN); - - procedure OREAD(L : inout LINE; - VALUE : out sfixed); - - procedure OREAD(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN); - - -- hex read and write - procedure HWRITE ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - -- purpose: writes fixed point into a line - procedure HWRITE ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0); - - procedure HREAD(L : inout LINE; - VALUE : out ufixed); - - procedure HREAD(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN); - - procedure HREAD(L : inout LINE; - VALUE : out sfixed); - - procedure HREAD(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN); - - -- returns a string, useful for: - -- assert (x = y) report "error found " & to_string(x) severity error; - function to_string ( - value : ufixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - alias to_bstring is to_string [ufixed, SIDE, width return STRING]; - - function to_ostring ( - value : ufixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - function to_hstring ( - value : ufixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - function to_string ( - value : sfixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - alias to_bstring is to_string [sfixed, SIDE, width return STRING]; - - function to_ostring ( - value : sfixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - function to_hstring ( - value : sfixed; - justified : SIDE := right; - field : WIDTH := 0 - ) return STRING; - - -- From string functions allow you to convert a string into a fixed - -- point number. Example: - -- signal uf1 : ufixed (3 downto -3); - -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5 - -- The "." is optional in this syntax, however it exist and is - -- in the wrong location an error is produced. Overflow will - -- result in saturation. - function from_string ( - bstring : STRING; -- binary string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - alias from_bstring is from_string [STRING, INTEGER, INTEGER return ufixed]; - - -- Octal and hex conversions work as follows: - -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped) - -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped) - function from_ostring ( - ostring : STRING; -- Octal string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - function from_hstring ( - hstring : STRING; -- hex string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed; - - function from_string ( - bstring : STRING; -- binary string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - alias from_bstring is from_string [STRING, INTEGER, INTEGER return sfixed]; - - function from_ostring ( - ostring : STRING; -- Octal string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - function from_hstring ( - hstring : STRING; -- hex string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed; - - -- Same as above, "size_res" is used for it's range only. - function from_string ( - bstring : STRING; -- binary string - size_res : ufixed) - return ufixed; - alias from_bstring is from_string [STRING, ufixed return ufixed]; - - function from_ostring ( - ostring : STRING; -- Octal string - size_res : ufixed) - return ufixed; - - function from_hstring ( - hstring : STRING; -- hex string - size_res : ufixed) - return ufixed; - - function from_string ( - bstring : STRING; -- binary string - size_res : sfixed) - return sfixed; - alias from_bstring is from_string [STRING, sfixed return sfixed]; - - function from_ostring ( - ostring : STRING; -- Octal string - size_res : sfixed) - return sfixed; - - function from_hstring ( - hstring : STRING; -- hex string - size_res : sfixed) - return sfixed; - - -- Direct converstion functions. Example: - -- signal uf1 : ufixed (3 downto -3); - -- uf1 <= from_string ("0110.100"); -- 6.5 - -- In this case the "." is not optional, and the size of - -- the output must match exactly. - function from_string ( - bstring : STRING) -- binary string - return ufixed; - alias from_bstring is from_string [STRING return ufixed]; - - -- Direct octal and hex converstion functions. In this case - -- the string lengths must match. Example: - -- signal sf1 := sfixed (5 downto -3); - -- sf1 <= from_ostring ("71.4") -- -6.5 - function from_ostring ( - ostring : STRING) -- Octal string - return ufixed; - - function from_hstring ( - hstring : STRING) -- hex string - return ufixed; - - function from_string ( - bstring : STRING) -- binary string - return sfixed; - alias from_bstring is from_string [STRING return sfixed]; - - function from_ostring ( - ostring : STRING) -- Octal string - return sfixed; - - function from_hstring ( - hstring : STRING) -- hex string - return sfixed; - --- synthesis translate_on --- rtl_synthesis on - -- This type is here for the floating point package. - type round_type is (round_nearest, -- Default, nearest LSB '0' - round_inf, -- Round to positive - round_neginf, -- Round to negate - round_zero); -- Round towards zero - -- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD, - -- and FE_TOWARDZERO floating point rounding macros. - function to_StdLogicVector ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR; - function to_Std_Logic_Vector ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR; - function to_StdLogicVector ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR; - function to_Std_Logic_Vector ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR; -end package fixed_pkg; -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; -use ieee.math_real.all; -use std.textio.all; -use ieee.std_logic_textio.all; -- %%% for testing only -package body fixed_pkg is - -- Author David Bishop (dbishop@vhdl.org) - -- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton - -- null array constants - constant NAUF : ufixed (0 downto 1) := (others => '0'); - constant NASF : sfixed (0 downto 1) := (others => '0'); - constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0'); - - -- This differed constant will tell you if the package body is synthesizable - -- or implemented as real numbers, set to "true" if synthesizable. --- constant fixedsynth_or_real : BOOLEAN := true; - - --%%% Can be removed in vhdl-200x, will be implicit. - -- purpose: To find the largest of 2 numbers - function maximum (l, r : INTEGER) - return INTEGER is - begin -- function maximum - if L > R then return L; - else return R; - end if; - end function maximum; - - function minimum (l, r : INTEGER) - return INTEGER is - begin -- function minimum - if L > R then return R; - else return L; - end if; - end function minimum; - - -- %%% Remove the following function (duplicates of new numeric_std) - function "sra" (arg : SIGNED; count : INTEGER) - return SIGNED is - begin - if (COUNT >= 0) then - return SHIFT_RIGHT(arg, count); - else - return SHIFT_LEFT(arg, -count); - end if; - end function "sra"; - - -- %%% Replace or_reducex with "or", and_reducex with "and", and - -- %%% xor_reducex with "xor", then remove the following 3 functions - -- purpose: OR all of the bits in a vector together - -- This is a copy of the proposed "or_reduce" from 1076.3 - function or_reducex (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '0'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := or_reducex (BUS_int (BUS_int'left downto Half)); - Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper or Lower; - end if; - end if; - return Result; - end function or_reducex; - - -- purpose: AND all of the bits in a vector together - -- This is a copy of the proposed "and_reduce" from 1076.3 - function and_reducex (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '1'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := and_reducex (BUS_int (BUS_int'left downto Half)); - Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper and Lower; - end if; - end if; - return Result; - end function and_reducex; - - function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is - variable Upper, Lower : STD_ULOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range - begin - if (arg'length >= 1) then - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := xor_reducex (BUS_int (BUS_int'left downto Half)); - Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper xor Lower; - end if; - end if; - return Result; - end function xor_reducex; - - --%%% remove the following function and table - -- Match table, copied form new std_logic_1164 - type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC; - constant match_logic_table : stdlogic_table := ( - ----------------------------------------------------- - -- U X 0 1 Z W L H - | | - ----------------------------------------------------- - ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X | - ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 | - ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W | - ('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L | - ('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H | - ('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - | - ); - - constant no_match_logic_table : stdlogic_table := ( - ----------------------------------------------------- - -- U X 0 1 Z W L H - | | - ----------------------------------------------------- - ('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X | - ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 | - ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z | - ('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W | - ('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L | - ('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H | - ('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - | - ); - - ------------------------------------------------------------------- - -- ?= functions, Similar to "std_match", but returns "std_ulogic". - ------------------------------------------------------------------- - -- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS - function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is - begin - return match_logic_table (l, r); - end function \?=\; - -- %%% END FUNCTION "?="; - -- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is - function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is - begin - return no_match_logic_table (l, r); - end function \?/=\; - -- %%% END FUNCTION "?/="; - -- %%% end remove - - -- Special version of "minimum" to do some boundary checking without errors - function mins (l, r : INTEGER) - return INTEGER is - begin -- function mins - if (L = INTEGER'low or R = INTEGER'low) then - return 0; -- error condition - end if; - return minimum (L, R); - end function mins; - - -- Special version of "minimum" to do some boundary checking with errors - function mine (l, r : INTEGER) - return INTEGER is - begin -- function mine - if (L = INTEGER'low or R = INTEGER'low) then - report "FIXED_GENERIC_PKG: Unbounded number passed, was a literal used?" - severity error; - return 0; - end if; - return minimum (L, R); - end function mine; - - -- The following functions are used only internally. Every function - -- calls "cleanvec" either directly or indirectly. - -- purpose: Fixes "downto" problem and resolves meta states - function cleanvec ( - arg : sfixed) -- input - return sfixed is - constant left_index : INTEGER := maximum(arg'left, arg'right); - constant right_index : INTEGER := mins(arg'left, arg'right); - variable result : sfixed (arg'range); - begin -- function cleanvec - assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low)) - report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto""" - severity error; - return arg; - end function cleanvec; - - -- purpose: Fixes "downto" problem and resolves meta states - function cleanvec ( - arg : ufixed) -- input - return ufixed is - constant left_index : INTEGER := maximum(arg'left, arg'right); - constant right_index : INTEGER := mins(arg'left, arg'right); - variable result : ufixed (arg'range); - begin -- function cleanvec - assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low)) - report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto""" - severity error; - return arg; - end function cleanvec; - - -- Type cast a "unsigned" into a "ufixed", used internally - function to_fixed ( - arg : UNSIGNED; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); --- variable j : INTEGER := arg'high; -- index for arg - begin -- function to_fixed - result := ufixed(arg); --- floop : for i in result'range loop --- result(i) := arg(j); -- res(4) := arg (4 + 3) --- j := j - 1; --- end loop floop; - return result; - end function to_fixed; - - -- Type cast a "signed" into an "sfixed", used internally - function to_fixed ( - arg : SIGNED; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); --- variable j : INTEGER := arg'high; -- index for arg - begin -- function to_fixed - result := sfixed(arg); --- floop : for i in result'range loop --- result(i) := arg(j); -- res(4) := arg (4 + 3) --- j := j - 1; --- end loop floop; - return result; - end function to_fixed; - - -- Type cast a "ufixed" into an "unsigned", used internally - function to_uns ( - arg : ufixed) -- fp vector - return UNSIGNED is - subtype t is UNSIGNED(arg'high - arg'low downto 0); - variable slv : t; - begin -- function to_uns - slv := t(arg); --- floop : for i in slv'range loop --- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3) --- end loop floop; - return UNSIGNED(to_X01(std_logic_vector(slv))); - end function to_uns; - - -- Type cast an "sfixed" into a "signed", used internally - function to_s ( - arg : sfixed) -- fp vector - return SIGNED is - subtype t is SIGNED(arg'high - arg'low downto 0); - variable slv : t; - begin -- function to_s - slv := t(arg); --- floop : for i in slv'range loop --- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3) --- end loop floop; - return SIGNED(to_X01(std_logic_vector(slv))); - end function to_s; - - -- adds 1 to the LSB of the number - procedure round_up (arg : in ufixed; - result : out ufixed; - overflowx : out BOOLEAN) is - variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0) := - (others => '0'); - begin -- round_up - arguns (arguns'high-1 downto 0) := to_uns (arg); - resuns := arguns + 1; - result := to_fixed(resuns(arg'high-arg'low - downto 0), arg'high, arg'low); - overflowx := (resuns(resuns'high) = '1'); - end procedure round_up; - - -- adds 1 to the LSB of the number - procedure round_up (arg : in sfixed; - result : out sfixed; - overflowx : out BOOLEAN) is - variable args, ress : SIGNED (arg'high-arg'low+1 downto 0); - begin -- round_up - args (args'high-1 downto 0) := to_s (arg); - args(args'high) := arg(arg'high); -- sign extend - ress := args + 1; - result := to_fixed(ress (ress'high-1 - downto 0), arg'high, arg'low); - overflowx := ((arg(arg'high) /= ress(ress'high-1)) - and (or_reducex (STD_LOGIC_VECTOR(ress)) /= '0')); - end procedure round_up; - - -- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up - -- when the remainder is > 0.5. If the remainder IS 0.5 then if the - -- bottom bit is a "1" it is rounded, otherwise it remains the same. - function round_fixed (arg : ufixed; - remainder : ufixed; - overflow_style : BOOLEAN := fixed_overflow_style) - return ufixed is - variable rounds : BOOLEAN; - variable round_overflow : BOOLEAN; - variable result : ufixed (arg'range); - begin - rounds := false; - if (remainder'length > 1) then - if (remainder (remainder'high) = '1') then - rounds := (arg(arg'low) = '1') - or (or_reducex (to_slv(remainder(remainder'high-1 downto - remainder'low))) = '1'); - end if; - else - rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1'); - end if; - if rounds then - round_up(arg => arg, - result => result, - overflowx => round_overflow); - else - result := arg; - end if; - if (overflow_style = fixed_saturate) and round_overflow then - result := saturate (result'high, result'low); - end if; - return result; - end function round_fixed; - - -- Rounding case statement - function round_fixed (arg : sfixed; - remainder : sfixed; - overflow_style : BOOLEAN := fixed_overflow_style) - return sfixed is - variable rounds : BOOLEAN; - variable round_overflow : BOOLEAN; - variable result : sfixed (arg'range); - begin - rounds := false; - if (remainder'length > 1) then - if (remainder (remainder'high) = '1') then - rounds := (arg(arg'low) = '1') - or (or_reducex (to_slv(remainder(remainder'high-1 downto - remainder'low))) = '1'); - end if; - else - rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1'); - end if; - if rounds then - round_up(arg => arg, - result => result, - overflowx => round_overflow); - else - result := arg; - end if; - if round_overflow then - if (overflow_style = fixed_saturate) then - if arg(arg'high) = '0' then - result := saturate (result'high, result'low); - else - result := not saturate (result'high, result'low); - end if; --- else --- result(result'high) := arg(arg'high); -- fix sign bit in wrap - end if; - end if; - return result; - end function round_fixed; - ------------------------------------------------------------------------------ --- Visible functions ------------------------------------------------------------------------------ - - -- casting functions. These are needed for synthesis where typically - -- the only input and output type is a std_logic_vector. - function to_slv ( - arg : ufixed) -- fixed point vector - return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0); - variable slv : t; - begin - if arg'length < 1 then - return NSLV; - end if; - slv := t (arg); - return slv; - end function to_slv; - - function to_slv ( - arg : sfixed) -- fixed point vector - return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0); - variable slv : t; - begin - if arg'length < 1 then - return NSLV; - end if; - slv := t (arg); - return slv; - end function to_slv; - - function to_sulv ( - arg : ufixed) -- fixed point vector - return STD_ULOGIC_VECTOR is - begin - return to_stdulogicvector (to_slv(arg)); - end function to_sulv; - - function to_sulv ( - arg : sfixed) -- fixed point vector - return STD_ULOGIC_VECTOR is - begin - return to_stdulogicvector (to_slv(arg)); - end function to_sulv; - - function to_ufixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); - begin - if (arg'length < 1 or right_index > left_index) then - return NAUF; - end if; - if (arg'length /= result'length) then - report "FIXED_GENERIC_PKG.TO_UFIXED (STD_LOGIC_VECTOR) " - & "Vector lengths do not match. Input length is " - & INTEGER'image(arg'length) & " and output will be " - & INTEGER'image(result'length) & " wide." - severity error; - return NAUF; - else - result := to_fixed (arg => UNSIGNED(arg), - left_index => left_index, - right_index => right_index); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); - begin - if (arg'length < 1 or right_index > left_index) then - return NASF; - end if; - if (arg'length /= result'length) then - report "FIXED_GENERIC_PKG.TO_SFIXED (STD_LOGIC_VECTOR) " - & "Vector lengths do not match. Input length is " - & INTEGER'image(arg'length) & " and output will be " - & INTEGER'image(result'length) & " wide." - severity error; - return NASF; - else - result := to_fixed (arg => SIGNED(arg), - left_index => left_index, - right_index => right_index); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - begin - return to_ufixed (arg => to_stdlogicvector(arg), - left_index => left_index, - right_index => right_index); - end function to_ufixed; - - function to_sfixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - begin - return to_sfixed (arg => to_stdlogicvector(arg), - left_index => left_index, - right_index => right_index); - end function to_sfixed; - - -- Two's complement number, Grows the vector by 1 bit. - -- because "abs (1000.000) = 01000.000" or abs(-16) = 16. - function "abs" ( - arg : sfixed) -- fixed point input - return sfixed is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := mine(arg'low, arg'low); - variable ressns : SIGNED (arg'length downto 0); - variable result : sfixed (left_index+1 downto right_index); - begin - if (arg'length < 1 or result'length < 1) then - return NASF; - end if; - ressns (arg'length-1 downto 0) := to_s (cleanvec (arg)); - ressns (arg'length) := ressns (arg'length-1); -- expand sign bit - result := to_fixed (abs(ressns), left_index+1, right_index); - return result; - end function "abs"; - - -- also grows the vector by 1 bit. - function "-" ( - arg : sfixed) -- fixed point input - return sfixed is - constant left_index : INTEGER := arg'high+1; - constant right_index : INTEGER := mine(arg'low, arg'low); - variable ressns : SIGNED (arg'length downto 0); - variable result : sfixed (left_index downto right_index); - begin - if (arg'length < 1 or result'length < 1) then - return NASF; - end if; - ressns (arg'length-1 downto 0) := to_s (cleanvec(arg)); - ressns (arg'length) := ressns (arg'length-1); -- expand sign bit - result := to_fixed (-ressns, left_index, right_index); - return result; - end function "-"; - - function "abs" (arg : sfixed) return ufixed is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := mine(arg'low, arg'low); - variable xarg : sfixed(left_index+1 downto right_index); - variable result : ufixed(left_index downto right_index); - begin - if arg'length < 1 then - return NAUF; - end if; - xarg := abs(arg); - result := ufixed (xarg (left_index downto right_index)); - return result; - end function "abs"; - - -- Addition - function "+" ( - l, r : ufixed) -- ufixed(a downto b) + ufixed(c downto d) = - return ufixed is -- ufixed(max(a,c)+1 downto min(b,d)) - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable result : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (left_index-right_index - downto 0); - variable result_slv : UNSIGNED (left_index-right_index - downto 0); - begin - if (l'length < 1 or r'length < 1) then - return NAUF; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - result_slv := lslv + rslv; - result := to_fixed(result_slv, left_index, right_index); - return result; - end function "+"; - - function "+" ( - l, r : sfixed) -- sfixed(a downto b) + sfixed(c downto d) = - return sfixed is -- sfixed(max(a,c)+1 downto min(b,d)) - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable result : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (left_index-right_index downto 0); - variable result_slv : SIGNED (left_index-right_index downto 0); - begin - if (l'length < 1 or r'length < 1) then - return NASF; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - result_slv := lslv + rslv; - result := to_fixed(result_slv, left_index, right_index); - return result; - end function "+"; - - -- Subtraction - function "-" ( - l, r : ufixed) -- ufixed(a downto b) - ufixed(c downto d) = - return ufixed is -- ufixed(max(a,c)+1 downto min(b,d)) - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable result : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (left_index-right_index - downto 0); - variable result_slv : UNSIGNED (left_index-right_index - downto 0); - begin - if (l'length < 1 or r'length < 1) then - return NAUF; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - result_slv := lslv - rslv; - result := to_fixed(result_slv, left_index, right_index); - return result; - end function "-"; - - function "-" ( - l, r : sfixed) -- sfixed(a downto b) - sfixed(c downto d) = - return sfixed is -- sfixed(max(a,c)+1 downto min(b,d)) - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable result : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (left_index-right_index downto 0); - variable result_slv : SIGNED (left_index-right_index downto 0); - begin - if (l'length < 1 or r'length < 1) then - return NASF; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - result_slv := lslv - rslv; - result := to_fixed(result_slv, left_index, right_index); - return result; - end function "-"; - - function "*" ( - l, r : ufixed) -- ufixed(a downto b) * ufixed(c downto d) = - return ufixed is -- ufixed(a+c+1 downto b+d) - variable lslv : UNSIGNED (l'length-1 downto 0); - variable rslv : UNSIGNED (r'length-1 downto 0); - variable result_slv : UNSIGNED (r'length+l'length-1 downto 0); - variable result : ufixed (l'high + r'high+1 downto - mine(l'low, l'low) + mine(r'low, r'low)); - begin - if (l'length < 1 or r'length < 1 or - result'length /= result_slv'length) then - return NAUF; - end if; - lslv := to_uns (cleanvec(l)); - rslv := to_uns (cleanvec(r)); - result_slv := lslv * rslv; - result := to_fixed (result_slv, result'high, result'low); - return result; - end function "*"; - - function "*" ( - l, r : sfixed) -- sfixed(a downto b) * sfixed(c downto d) = - return sfixed is -- sfixed(a+c+1 downto b+d) - variable lslv : SIGNED (l'length-1 downto 0); - variable rslv : SIGNED (r'length-1 downto 0); - variable result_slv : SIGNED (r'length+l'length-1 downto 0); - variable result : sfixed (l'high + r'high+1 downto - mine(l'low, l'low) + mine(r'low, r'low)); - begin - if (l'length < 1 or r'length < 1 or - result'length /= result_slv'length) then - return NASF; - end if; - lslv := to_s (cleanvec(l)); - rslv := to_s (cleanvec(r)); - result_slv := lslv * rslv; - result := to_fixed (result_slv, result'high, result'low); - return result; - end function "*"; - - function "/" ( - l, r : ufixed) -- ufixed(a downto b) / ufixed(c downto d) = - return ufixed is -- ufixed(a-d downto b-c-1) - begin - return divide (l, r); - end function "/"; - - function "/" ( - l, r : sfixed) -- sfixed(a downto b) / sfixed(c downto d) = - return sfixed is -- sfixed(a-d+1 downto b-c) - begin - return divide (l, r); - end function "/"; - - -- This version of divide gives the user more control - -- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1) - function divide ( - l, r : ufixed; - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return ufixed is - variable result : ufixed (l'high - mine(r'low, r'low) - downto mine (l'low, l'low) - r'high -1); - variable dresult : ufixed (result'high downto result'low -guard_bits); - variable lresize : ufixed (l'high downto l'high - dresult'length+1); - variable lslv : UNSIGNED (lresize'length-1 downto 0); - variable rslv : UNSIGNED (r'length-1 downto 0); - variable result_slv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NAUF; - end if; - lresize := resize (l, lresize'high, lresize'low); - lslv := to_uns (cleanvec (lresize)); - rslv := to_uns (cleanvec (r)); - if (rslv = 0) then - report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error; - result := saturate (result'high, result'low); -- saturate - else - result_slv := lslv / rslv; - dresult := to_fixed (result_slv, dresult'high, dresult'low); - result := resize (arg => dresult, - left_index => result'high, - right_index => result'low, - round_style => round_style, - overflow_style => fixed_wrap); -- overflow impossible - end if; - return result; - end function divide; - - -- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c) - function divide ( - l, r : sfixed; - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return sfixed is - variable result : sfixed (l'high - mine(r'low, r'low)+1 - downto mine (l'low, l'low) - r'high); - variable dresult : sfixed (result'high downto result'low-guard_bits); - variable lresize : sfixed (l'high+1 downto l'high+1 -dresult'length+1); - variable lslv : SIGNED (lresize'length-1 downto 0); - variable rslv : SIGNED (r'length-1 downto 0); - variable result_slv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NASF; - end if; - lresize := resize (l, lresize'high, lresize'low); - lslv := to_s (cleanvec (lresize)); - rslv := to_s (cleanvec (r)); - if (rslv = 0) then - report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error; - result := saturate (result'high, result'low); - else - result_slv := lslv / rslv; - dresult := to_fixed (result_slv, dresult'high, dresult'low); - result := resize (arg => dresult, - left_index => result'high, - right_index => result'low, - round_style => round_style, - overflow_style => fixed_wrap); -- overflow impossible - end if; - return result; - end function divide; - - -- 1 / ufixed(a downto b) = ufixed(-b downto -a-1) - function reciprocal ( - arg : ufixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return ufixed is - constant one : ufixed (0 downto 0) := "1"; - begin - return divide(l => one, - r => arg, - round_style => round_style, - guard_bits => guard_bits); - end function reciprocal; - - -- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a) - function reciprocal ( - arg : sfixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style; - constant guard_bits : NATURAL := fixed_guard_bits) - return sfixed is - constant one : sfixed (1 downto 0) := "01"; -- extra bit. - variable resultx : sfixed (-mine(arg'low, arg'low)+2 downto -arg'high); - begin - if (arg'length < 1 or resultx'length < 1) then - return NASF; - else - resultx := divide(l => one, - r => arg, - round_style => round_style, - guard_bits => guard_bits); - return resultx (resultx'high-1 downto resultx'low); -- remove extra bit - end if; - end function reciprocal; - - -- ufixed (a downto b) rem ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b,d)) - function "rem" ( - l, r : ufixed) -- fixed point input - return ufixed is - begin - return remainder (l => l, - r => r, - round_style => fixed_round_style); - end function "rem"; - - -- remainder - -- sfixed (a downto b) rem sfixed (c downto d) - -- = sfixed (min(a,c) downto min(b,d)) - function "rem" ( - l, r : sfixed) -- fixed point input - return sfixed is - begin - return remainder (l => l, - r => r, - round_style => fixed_round_style); - end function "rem"; - - -- ufixed (a downto b) rem ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b,d)) - function remainder ( - l, r : ufixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style) - return ufixed is - variable result : ufixed (minimum(l'high, r'high) downto mine(l'low, r'low)); - variable dresult : ufixed (r'high downto r'low); - variable lresize : ufixed (maximum(l'high, r'low) downto mins(r'low, r'low)); - variable lslv : UNSIGNED (lresize'length-1 downto 0); - variable rslv : UNSIGNED (r'length-1 downto 0); - variable result_slv : UNSIGNED (rslv'range); - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NAUF; - end if; - lresize := resize (arg => l, - left_index => lresize'high, - right_index => lresize'low, - overflow_style => fixed_wrap, -- vector only grows - round_style => fixed_truncate); - lslv := to_uns (lresize); - rslv := to_uns (cleanvec(r)); - if (rslv = 0) then - report "FIXED_GENERIC_PKG.rem uFixed point Division by zero" severity error; - result := saturate (result'high, result'low); -- saturate - else - if (r'low <= l'high) then - result_slv := lslv rem rslv; - dresult := to_fixed (result_slv, dresult'high, dresult'low); - result := resize (arg => dresult, - left_index => result'high, - right_index => result'low, - overflow_style => fixed_wrap, - round_style => round_style); --- result(result'high downto r'low) := dresult(result'high downto r'low); - end if; - if l'low < r'low then - result(mins(r'low-1, l'high) downto l'low) := - cleanvec(l(mins(r'low-1, l'high) downto l'low)); - end if; - end if; - return result; - end function remainder; - - -- remainder - -- sfixed (a downto b) rem sfixed (c downto d) - -- = sfixed (min(a,c) downto min(b,d)) - function remainder ( - l, r : sfixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style) - return sfixed is - variable l_abs : ufixed (l'range); - variable r_abs : ufixed (r'range); - variable result : sfixed (minimum(r'high, l'high) downto mine(r'low, l'low)); - variable neg_result : sfixed (minimum(r'high, l'high)+1 downto mins(r'low, l'low)); - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NASF; - end if; - l_abs := abs(l); - r_abs := abs(r); - result := sfixed(remainder (l => l_abs, - r => r_abs, - round_style => round_style)); - neg_result := -result; - if l(l'high) = '1' then - result := neg_result(result'range); - end if; - return result; - end function remainder; - - -- modulo - -- ufixed (a downto b) mod ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b, d)) - function "mod" ( - l, r : ufixed) -- fixed point input - return ufixed is - begin - return modulo (l => l, - r => r, - round_style => fixed_round_style); - end function "mod"; - - -- sfixed (a downto b) mod sfixed (c downto d) - -- = sfixed (c downto min(b, d)) - function "mod" ( - l, r : sfixed) -- fixed point input - return sfixed is - begin - return modulo(l => l, - r => r, - round_style => fixed_round_style); - end function "mod"; - - -- modulo - -- ufixed (a downto b) mod ufixed (c downto d) - -- = ufixed (min(a,c) downto min(b, d)) - function modulo ( - l, r : ufixed; -- fixed point input - constant round_style : BOOLEAN := fixed_round_style) - return ufixed is - begin - return remainder(l => l, - r => r, - round_style => round_style); - end function modulo; - - -- sfixed (a downto b) mod sfixed (c downto d) - -- = sfixed (c downto min(b, d)) - function modulo ( - l, r : sfixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; - constant round_style : BOOLEAN := fixed_round_style) - return sfixed is - variable l_abs : ufixed (l'range); - variable r_abs : ufixed (r'range); - variable result : sfixed (r'high downto - mine(r'low, l'low)); - variable dresult : sfixed (minimum(r'high, l'high)+1 downto - mins(r'low, l'low)); - variable dresult_not_zero : BOOLEAN; - begin - if (l'length < 1 or r'length < 1 or - mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then - return NASF; - end if; - l_abs := abs(l); - r_abs := abs(r); - dresult := "0" & sfixed(remainder (l => l_abs, - r => r_abs, - round_style => round_style)); - if (to_s(dresult) = 0) then - dresult_not_zero := false; - else - dresult_not_zero := true; - end if; - if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0' - and dresult_not_zero then - result := resize (arg => r - dresult, - left_index => result'high, - right_index => result'low, - overflow_style => overflow_style, - round_style => round_style); - elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then - result := resize (arg => -dresult, - left_index => result'high, - right_index => result'low, - overflow_style => overflow_style, - round_style => round_style); - elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1' - and dresult_not_zero then - result := resize (arg => dresult + r, - left_index => result'high, - right_index => result'low, - overflow_style => overflow_style, - round_style => round_style); - else - result := resize (arg => dresult, - left_index => result'high, - right_index => result'low, - overflow_style => overflow_style, - round_style => round_style); - end if; - return result; - end function modulo; - - -- Procedure for those who need an "accumulator" function - procedure add_carry ( - L, R : in ufixed; - c_in : in STD_ULOGIC; - result : out ufixed; - c_out : out STD_ULOGIC) is - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (left_index-right_index - downto 0); - variable result_slv : UNSIGNED (left_index-right_index - downto 0); - variable cx : UNSIGNED (0 downto 0); -- Carry in - begin - if (l'length < 1 or r'length < 1) then - result := NAUF; - c_out := '0'; - else - cx (0) := c_in; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - result_slv := lslv + rslv + cx; - c_out := result_slv(left_index); - result := to_fixed(result_slv (left_index-right_index-1 downto 0), - left_index-1, right_index); - end if; - end procedure add_carry; - - procedure add_carry ( - L, R : in sfixed; - c_in : in STD_ULOGIC; - result : out sfixed; - c_out : out STD_ULOGIC) is - constant left_index : INTEGER := maximum(l'high, r'high)+1; - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (left_index-right_index - downto 0); - variable result_slv : SIGNED (left_index-right_index - downto 0); - variable cx : SIGNED (1 downto 0); -- Carry in - begin - if (l'length < 1 or r'length < 1) then - result := NASF; - c_out := '0'; - else - cx (1) := '0'; - cx (0) := c_in; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - result_slv := lslv + rslv + cx; - c_out := result_slv(left_index); - result := to_fixed(result_slv (left_index-right_index-1 downto 0), - left_index-1, right_index); - end if; - end procedure add_carry; - - -- Scales the result by a power of 2. Width of input = width of output with - -- the decimal point moved. - function scalb (y : ufixed; N : integer) return ufixed is - variable result : ufixed (y'high+N downto y'low+N); - begin - if y'length < 1 then - return NAUF; - else - result := y; - return result; - end if; - end function scalb; - - function scalb (y : ufixed; N : SIGNED) return ufixed is - begin - return scalb (y => y, - N => to_integer(N)); - end function scalb; - - function scalb (y : sfixed; N : integer) return sfixed is - variable result : sfixed (y'high+N downto y'low+N); - begin - if y'length < 1 then - return NASF; - else - result := y; - return result; - end if; - end function scalb; - - function scalb (y : sfixed; N : SIGNED) return sfixed is - begin - return scalb (y => y, - N => to_integer(N)); - end function scalb; - - function Is_Negative (arg : sfixed) return BOOLEAN is - begin - if to_X01(arg(arg'high)) = '1' then - return true; - else - return false; - end if; - end function Is_Negative; - - function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER is - begin - for_loop : for i in arg'low to arg'high loop - if arg(i) = y then - return i; - end if; - end loop; - return arg'high+1; -- return out of bounds 'high - end function find_lsb; - - function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER is - begin - for_loop : for i in arg'high downto arg'low loop - if arg(i) = y then - return i; - end if; - end loop; - return arg'low-1; -- return out of bounds 'low - end function find_msb; - - function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER is - begin - for_loop : for i in arg'low to arg'high loop - if arg(i) = y then - return i; - end if; - end loop; - return arg'high+1; -- return out of bounds 'high - end function find_lsb; - - function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER is - begin - for_loop : for i in arg'high downto arg'low loop - if arg(i) = y then - return i; - end if; - end loop; - return arg'low-1; -- return out of bounds 'low - end function find_msb; - - function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - argslv := argslv sll COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sll"; - - function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - argslv := argslv srl COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "srl"; - - function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - argslv := argslv rol COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "rol"; - - function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - argslv := argslv ror COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "ror"; - - function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - -- Arithmetic shift on an unsigned is a logical shift - argslv := argslv sll COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sla"; - - function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed is - variable argslv : UNSIGNED (arg'length-1 downto 0); - variable result : ufixed (arg'range); - begin - argslv := to_uns (arg); - -- Arithmetic shift on an unsigned is a logical shift - argslv := argslv srl COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sra"; - - function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - argslv := argslv sll COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sll"; - - function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - argslv := argslv srl COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "srl"; - - function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - argslv := argslv rol COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "rol"; - - function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - argslv := argslv ror COUNT; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "ror"; - - function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - if COUNT > 0 then - -- Arithmetic shift left on a 2's complement number is a logic shift - argslv := argslv sll COUNT; - else - argslv := argslv sra -COUNT; - end if; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sla"; - - function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed is - variable argslv : SIGNED (arg'length-1 downto 0); - variable result : sfixed (arg'range); - begin - argslv := to_s (arg); - if COUNT > 0 then - argslv := argslv sra COUNT; - else - -- Arithmetic shift left on a 2's complement number is a logic shift - argslv := argslv sll -COUNT; - end if; - result := to_fixed (argslv, result'high, result'low); - return result; - end function "sra"; - - -- Because some people want the older functions. - function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed is - begin - if (ARG'length < 1) then - return NAUF; - end if; - return ARG sla COUNT; - end function SHIFT_LEFT; - function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed is - begin - if (ARG'length < 1) then - return NAUF; - end if; - return ARG sra COUNT; - end function SHIFT_RIGHT; - function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed is - begin - if (ARG'length < 1) then - return NASF; - end if; - return ARG sla COUNT; - end function SHIFT_LEFT; - function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed is - begin - if (ARG'length < 1) then - return NASF; - end if; - return ARG sra COUNT; - end function SHIFT_RIGHT; - - ---------------------------------------------------------------------------- - -- logical functions - ---------------------------------------------------------------------------- - function "not" (L : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - RESULT := not to_slv(L); - return to_ufixed(RESULT, L'high, L'low); - end function "not"; - - function "and" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) and to_slv(R); - else - report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "and"; - - function "or" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) or to_slv(R); - else - report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "or"; - - function "nand" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) nand to_slv(R); - else - report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "nand"; - - function "nor" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) nor to_slv(R); - else - report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "nor"; - - function "xor" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) xor to_slv(R); - else - report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "xor"; - - function "xnor" (L, R : ufixed) return ufixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) xnor to_slv(R); - else - report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_ufixed(RESULT, L'high, L'low); - end function "xnor"; - - function "not" (L : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - RESULT := not to_slv(L); - return to_sfixed(RESULT, L'high, L'low); - end function "not"; - - function "and" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) and to_slv(R); - else - report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "and"; - - function "or" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) or to_slv(R); - else - report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "or"; - - function "nand" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) nand to_slv(R); - else - report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "nand"; - - function "nor" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) nor to_slv(R); - else - report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "nor"; - - function "xor" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) xor to_slv(R); - else - report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "xor"; - - function "xnor" (L, R : sfixed) return sfixed is - variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto - begin - if (L'high = R'high and L'low = R'low) then - RESULT := to_slv(L) xnor to_slv(R); - else - report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE" - severity warning; - RESULT := (others => 'U'); - end if; - return to_sfixed(RESULT, L'high, L'low); - end function "xnor"; - - -- Vector and std_ulogic functions, same as functions in numeric_std - function "and" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L and R(i); - end loop; - return result; - end function "and"; - - function "and" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) and R; - end loop; - return result; - end function "and"; - - function "or" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L or R(i); - end loop; - return result; - end function "or"; - - function "or" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) or R; - end loop; - return result; - end function "or"; - - function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L nand R(i); - end loop; - return result; - end function "nand"; - - function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) nand R; - end loop; - return result; - end function "nand"; - - function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L nor R(i); - end loop; - return result; - end function "nor"; - - function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) nor R; - end loop; - return result; - end function "nor"; - - function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L xor R(i); - end loop; - return result; - end function "xor"; - - function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) xor R; - end loop; - return result; - end function "xor"; - - function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed is - variable result : ufixed (R'range); - begin - for i in result'range loop - result(i) := L xnor R(i); - end loop; - return result; - end function "xnor"; - - function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed is - variable result : ufixed (L'range); - begin - for i in result'range loop - result(i) := L(i) xnor R; - end loop; - return result; - end function "xnor"; - - function "and" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L and R(i); - end loop; - return result; - end function "and"; - - function "and" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) and R; - end loop; - return result; - end function "and"; - - function "or" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L or R(i); - end loop; - return result; - end function "or"; - - function "or" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) or R; - end loop; - return result; - end function "or"; - - function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L nand R(i); - end loop; - return result; - end function "nand"; - - function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) nand R; - end loop; - return result; - end function "nand"; - - function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L nor R(i); - end loop; - return result; - end function "nor"; - - function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) nor R; - end loop; - return result; - end function "nor"; - - function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L xor R(i); - end loop; - return result; - end function "xor"; - - function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) xor R; - end loop; - return result; - end function "xor"; - - function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed is - variable result : sfixed (R'range); - begin - for i in result'range loop - result(i) := L xnor R(i); - end loop; - return result; - end function "xnor"; - - function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed is - variable result : sfixed (L'range); - begin - for i in result'range loop - result(i) := L(i) xnor R; - end loop; - return result; - end function "xnor"; - - -- Reduction operators, same as numeric_std functions - -- %%% remove 12 functions (old syntax) - function and_reduce(arg : ufixed) return STD_ULOGIC is - begin - return and_reducex (to_slv(arg)); - end function and_reduce; - - function nand_reduce(arg : ufixed) return STD_ULOGIC is - begin - return not and_reducex (to_slv(arg)); - end function nand_reduce; - - function or_reduce(arg : ufixed) return STD_ULOGIC is - begin - return or_reducex (to_slv(arg)); - end function or_reduce; - - function nor_reduce(arg : ufixed) return STD_ULOGIC is - begin - return not or_reducex (to_slv(arg)); - end function nor_reduce; - - function xor_reduce(arg : ufixed) return STD_ULOGIC is - begin - return xor_reducex (to_slv(arg)); - end function xor_reduce; - - function xnor_reduce(arg : ufixed) return STD_ULOGIC is - begin - return not xor_reducex (to_slv(arg)); - end function xnor_reduce; - - function and_reduce(arg : sfixed) return STD_ULOGIC is - begin - return and_reducex (to_slv(arg)); - end function and_reduce; - - function nand_reduce(arg : sfixed) return STD_ULOGIC is - begin - return not and_reducex (to_slv(arg)); - end function nand_reduce; - - function or_reduce(arg : sfixed) return STD_ULOGIC is - begin - return or_reducex (to_slv(arg)); - end function or_reduce; - - function nor_reduce(arg : sfixed) return STD_ULOGIC is - begin - return not or_reducex (to_slv(arg)); - end function nor_reduce; - - function xor_reduce(arg : sfixed) return STD_ULOGIC is - begin - return xor_reducex (to_slv(arg)); - end function xor_reduce; - - function xnor_reduce(arg : sfixed) return STD_ULOGIC is - begin - return not xor_reducex (to_slv(arg)); - end function xnor_reduce; - -- %%% Uncomment the following 12 functions (new syntax) - -- function "and" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return and to_slv(arg); - -- end function "and"; - -- function "nand" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return nand to_slv(arg); - -- end function "nand";; - -- function "or" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return or to_slv(arg); - -- end function "or"; - -- function "nor" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return nor to_slv(arg); - -- end function "nor"; - -- function "xor" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return xor to_slv(arg); - -- end function "xor"; - -- function "xnor" ( arg : ufixed ) RETURN std_ulogic is - -- begin - -- return xnor to_slv(arg); - -- end function "xnor"; - -- function "and" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return and to_slv(arg); - -- end function "and";; - -- function "nand" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return nand to_slv(arg); - -- end function "nand";; - -- function "or" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return or to_slv(arg); - -- end function "or"; - -- function "nor" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return nor to_slv(arg); - -- end function "nor"; - -- function "xor" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return xor to_slv(arg); - -- end function "xor"; - -- function "xnor" ( arg : sfixed ) RETURN std_ulogic is - -- begin - -- return xnor to_slv(arg); - -- end function "xnor"; - - -- %%% Replace with the following (new syntax) --- function "?=" (L, R : ufixed) return STD_ULOGIC is - function \?=\ (L, R : ufixed) return STD_ULOGIC is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable result, result1 : STD_ULOGIC; -- result - begin -- ?= - if ((L'LENGTH < 1) or (R'LENGTH < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?="": null detected, returning X" - severity warning; - return 'X'; - else - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - result := '1'; - for i in lresize'reverse_range loop - result1 := \?=\(lresize(i), rresize(i)); - if result1 = 'U' then - return 'U'; - elsif result1 = 'X' or result = 'X' then - result := 'X'; - else - result := result and result1; - end if; - end loop; - return result; - end if; - end function \?=\; --- end function "?="; - --- function "?/=" (L, R : ufixed) return STD_ULOGIC is - function \?/=\ (L, R : ufixed) return STD_ULOGIC is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable result, result1 : STD_ULOGIC; -- result - begin -- ?/= - if ((L'LENGTH < 1) or (R'LENGTH < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?/="": null detected, returning X" - severity warning; - return 'X'; - else - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - result := '0'; - for i in lresize'reverse_range loop - result1 := \?/=\ (lresize(i), rresize(i)); - if result1 = 'U' then - return 'U'; - elsif result1 = 'X' or result = 'X' then - result := 'X'; - else - result := result or result1; - end if; - end loop; - return result; - end if; - end function \?/=\; --- end function "?/="; - --- function "?>" (L, R : ufixed) return STD_ULOGIC is - function \?>\ (L, R : ufixed) return STD_ULOGIC is - begin -- ?> - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?>"": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l > r then - return '1'; - else - return '0'; - end if; - end if; - end function \?>\; --- end function "?>"; - --- function "?>=" (L, R : ufixed) return STD_ULOGIC is - function \?>=\ (L, R : ufixed) return STD_ULOGIC is - begin -- ?>= - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?>="": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l >= r then - return '1'; - else - return '0'; - end if; - end if; - end function \?>=\; --- end function "?>="; - --- function "?<" (L, R : ufixed) return STD_ULOGIC is - function \?<\ (L, R : ufixed) return STD_ULOGIC is - begin -- ?< - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?<"": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l < r then - return '1'; - else - return '0'; - end if; - end if; - end function \?<\; --- end function "?<"; - --- function "?<=" (L, R : ufixed) return STD_ULOGIC is - function \?<=\ (L, R : ufixed) return STD_ULOGIC is - begin -- ?<= - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?<="": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l <= r then - return '1'; - else - return '0'; - end if; - end if; - end function \?<=\; --- end function "?<="; - - -- function "?=" (L, R : sfixed) return STD_ULOGIC is - function \?=\ (L, R : sfixed) return STD_ULOGIC is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable result, result1 : STD_ULOGIC; -- result - begin -- ?= - if ((L'LENGTH < 1) or (R'LENGTH < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?="": null detected, returning X" - severity warning; - return 'X'; - else - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - result := '1'; - for i in lresize'reverse_range loop - result1 := \?=\ (lresize(i), rresize(i)); - if result1 = 'U' then - return 'U'; - elsif result1 = 'X' or result = 'X' then - result := 'X'; - else - result := result and result1; - end if; - end loop; - return result; - end if; - end function \?=\; --- end function "?="; - --- function "?/=" (L, R : sfixed) return STD_ULOGIC is - function \?/=\ (L, R : sfixed) return STD_ULOGIC is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable result, result1 : STD_ULOGIC; -- result - begin -- ?/= - if ((L'LENGTH < 1) or (R'LENGTH < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?/="": null detected, returning X" - severity warning; - return 'X'; - else - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - result := '0'; - for i in lresize'reverse_range loop - result1 := \?/=\ (lresize(i), rresize(i)); - if result1 = 'U' then - return 'U'; - elsif result1 = 'X' or result = 'X' then - result := 'X'; - else - result := result or result1; - end if; - end loop; - return result; - end if; - end function \?/=\; --- end function "?/="; - --- function "?>" (L, R : sfixed) return STD_ULOGIC is - function \?>\ (L, R : sfixed) return STD_ULOGIC is - begin -- ?> - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?>"": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l > r then - return '1'; - else - return '0'; - end if; - end if; - end function \?>\; --- end function "?>"; - --- function "?>=" (L, R : sfixed) return STD_ULOGIC is - function \?>=\ (L, R : sfixed) return STD_ULOGIC is - begin -- ?>= - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?>="": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l >= r then - return '1'; - else - return '0'; - end if; - end if; - end function \?>=\; --- end function "?>="; - --- function "?<" (L, R : sfixed) return STD_ULOGIC is - function \?<\ (L, R : sfixed) return STD_ULOGIC is - begin -- ?< - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?<"": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l < r then - return '1'; - else - return '0'; - end if; - end if; - end function \?<\; --- end function "?<"; - --- function "?<=" (L, R : sfixed) return STD_ULOGIC is - function \?<=\ (L, R : sfixed) return STD_ULOGIC is - begin -- ?<= - if ((l'length < 1) or (r'length < 1)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""?<="": null detected, returning X" - severity warning; - return 'X'; - elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then - report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string" - severity error; - return 'X'; - else - if is_x(l) or is_x(r) then - return 'X'; - elsif l <= r then - return '1'; - else - return '0'; - end if; - end if; - end function \?<=\; --- end function "?<="; - - -- %%% end replace - -- Match function, similar to "std_match" from numeric_std - function std_match (L, R : ufixed) return BOOLEAN is - begin - if (L'high = R'high and L'low = R'low) then - return std_match(to_slv(L), to_slv(R)); - else - report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" - severity warning; - return false; - end if; - end function std_match; - - function std_match (L, R : sfixed) return BOOLEAN is - begin - if (L'high = R'high and L'low = R'low) then - return std_match(to_slv(L), to_slv(R)); - else - report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE" - severity warning; - return false; - end if; - end function std_match; - --%%% end remove - - -- compare functions - function "=" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv = rslv; - end function "="; - - function "=" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv = rslv; - end function "="; - - function "/=" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE" - severity warning; - return true; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE" - severity warning; - return true; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv /= rslv; - end function "/="; - - function "/=" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE" - severity warning; - return true; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE" - severity warning; - return true; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv /= rslv; - end function "/="; - - function ">" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv > rslv; - end function ">"; - - function ">" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv > rslv; - end function ">"; - - function "<" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv < rslv; - end function "<"; - - function "<" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv < rslv; - end function "<"; - - function ">=" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv >= rslv; - end function ">="; - - function ">=" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv >= rslv; - end function ">="; - - function "<=" ( - l, r : ufixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : ufixed (left_index downto right_index); - variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_uns (lresize); - rslv := to_uns (rresize); - return lslv <= rslv; - end function "<="; - - function "<=" ( - l, r : sfixed) -- fixed point input - return BOOLEAN is - constant left_index : INTEGER := maximum(l'high, r'high); - constant right_index : INTEGER := mins(l'low, r'low); - variable lresize, rresize : sfixed (left_index downto right_index); - variable lslv, rslv : SIGNED (lresize'length-1 downto 0); - begin - if (l'length < 1 or r'length < 1) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE" - severity warning; - return false; - elsif (Is_X(l) or Is_X(r)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE" - severity warning; - return false; - end if; - lresize := resize (l, left_index, right_index); - rresize := resize (r, left_index, right_index); - lslv := to_s (lresize); - rslv := to_s (rresize); - return lslv <= rslv; - end function "<="; - - -- overloads of the default maximum and minimum functions - function maximum (l, r : ufixed) return ufixed is - begin - if l > r then return l; - else return r; - end if; - end function maximum; - - function maximum (l, r : sfixed) return sfixed is - begin - if l > r then return l; - else return r; - end if; - end function maximum; - - function minimum (l, r : ufixed) return ufixed is - begin - if l > r then return r; - else return l; - end if; - end function minimum; - - function minimum (l, r : sfixed) return sfixed is - begin - if l > r then return r; - else return l; - end if; - end function minimum; - - function to_ufixed ( - arg : NATURAL; -- integer - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return ufixed is - variable argx : INTEGER; - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : ufixed (left_index downto fw) := (others => '0'); - variable sresult : UNSIGNED (left_index downto 0); -- integer portion - variable bound : NATURAL; -- find the numerical bounds - begin - if (left_index < fw) then - return NAUF; - end if; - if left_index >= 0 then - if (left_index < 30) then - bound := 2**(left_index+1); - else - bound := INTEGER'high; - end if; - end if; - if (arg /= 0) then - if arg >= bound or left_index < 0 then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_UFIXED(NATURAL): vector truncated" - severity warning; - if (overflow_style = fixed_wrap) then -- wrap - if bound = 0 then - argx := 0; - else - argx := arg mod bound; - end if; - else -- saturate - return saturate (result'high, result'low); - end if; - else - argx := arg; - end if; - else - return result; -- return zero - end if; - sresult := to_unsigned (argx, sresult'high+1); - result := resize (arg => ufixed (sresult), - left_index => left_index, - right_index => right_index, - round_style => round_style, - overflow_style => overflow_style); - return result; - end function to_ufixed; - - function to_sfixed ( - arg : INTEGER; -- integer - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return sfixed is - variable argx : INTEGER; - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : sfixed (left_index downto fw) := (others => '0'); - variable sresult : SIGNED (left_index+1 downto 0); -- integer portion - variable bound : NATURAL := 0; - begin - if (left_index < fw) then -- null range - return NASF; - end if; - if left_index >= 0 then - if (left_index < 30) then - bound := 2**(left_index); - else - bound := INTEGER'high; - end if; - end if; - if (arg /= 0) then - if (arg >= bound or arg < -bound or left_index < 0) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_SFIXED(INTEGER): vector truncated" - severity warning; - if overflow_style = fixed_wrap then -- wrap - if bound = 0 then -- negative integer_range trap - argx := 0; - else -- shift off the top bits - argx := arg rem (bound*2); - end if; - else -- saturate - if arg < 0 then - result := not saturate (result'high, result'low); -- underflow - else - result := saturate (result'high, result'low); -- overflow - end if; - return result; - end if; - else - argx := arg; - end if; - else - return result; -- return zero - end if; - sresult := to_signed (argx, sresult'length); - result := resize (arg => sfixed (sresult), - left_index => left_index, - right_index => right_index, - round_style => round_style, - overflow_style => overflow_style); - return result; - end function to_sfixed; - - function to_ufixed ( - arg : REAL; -- real - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return ufixed is - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : ufixed (left_index downto fw) := (others => '0'); - variable Xresult : ufixed (left_index downto fw-guard_bits) := (others => '0'); - variable presult : REAL; - variable overflow_needed : BOOLEAN; - begin - -- If negative or null range, return. - if (left_index < fw) then - return NAUF; - end if; - if (arg < 0.0) then - report "FIXED_GENERIC_PKG.TO_UFIXED: Negative argument passed " - & REAL'image(arg) severity error; - return result; - end if; - presult := arg; - if presult >= (2.0**(left_index+1)) then - assert NO_WARNING report "FIXED_GENERIC_PKG.TO_UFIXED(REAL): vector truncated" - severity warning; - overflow_needed := (overflow_style = fixed_saturate); - if overflow_style = fixed_wrap then - presult := presult mod (2.0**(left_index+1)); -- wrap - else - return saturate (result'high, result'low); - end if; - end if; - for i in Xresult'range loop - if presult >= 2.0**i then - Xresult(i) := '1'; - presult := presult - 2.0**i; - else - Xresult(i) := '0'; - end if; - end loop; - if guard_bits > 0 and round_style = fixed_round then - result := round_fixed (arg => Xresult (left_index - downto right_index), - remainder => Xresult (right_index-1 downto - right_index-guard_bits), - overflow_style => overflow_style); - else - result := Xresult (result'range); - end if; - return result; - end function to_ufixed; - - function to_sfixed ( - arg : REAL; -- real - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return sfixed is - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : sfixed (left_index downto fw) := (others => '0'); - variable Xresult : sfixed (left_index+1 downto fw-guard_bits) := (others => '0'); - variable presult : REAL; - begin - if (left_index < fw) then -- null range - return NASF; - end if; - if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then - assert NO_WARNING report "FIXED_GENERIC_PKG.TO_SFIXED(REAL): vector truncated" - severity warning; - if overflow_style = fixed_saturate then - if arg < 0.0 then -- saturate - result := not saturate (result'high, result'low); -- underflow - else - result := saturate (result'high, result'low); -- overflow - end if; - return result; - else - presult := abs(arg) mod (2.0**(left_index+1)); -- wrap - end if; - else - presult := abs(arg); - end if; - for i in Xresult'range loop - if presult >= 2.0**i then - Xresult(i) := '1'; - presult := presult - 2.0**i; - else - Xresult(i) := '0'; - end if; - end loop; - if arg < 0.0 then - Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low); - end if; - if guard_bits > 0 and round_style then - result := round_fixed (arg => Xresult (left_index - downto right_index), - remainder => Xresult (right_index-1 downto - right_index-guard_bits), - overflow_style => overflow_style); - else - result := Xresult (result'range); - end if; - return result; - end function to_sfixed; - - function to_ufixed ( - arg : UNSIGNED; -- unsigned - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return ufixed is - constant ARG_LEFT : INTEGER := ARG'length-1; - alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : ufixed (left_index downto fw); - begin - if arg'length < 1 or (left_index < fw) then - return NAUF; - end if; - result := resize (arg => ufixed (XARG), - left_index => left_index, - right_index => right_index, - round_style => round_style, - overflow_style => overflow_style); - return result; - end function to_ufixed; - - -- casted version - function to_ufixed ( - arg : UNSIGNED) -- unsigned - return ufixed is - constant ARG_LEFT : INTEGER := ARG'length-1; - alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG; - begin - if arg'length < 1 then - return NAUF; - end if; - return ufixed(xarg); - end function to_ufixed; - - function to_sfixed ( - arg : SIGNED; -- signed - constant left_index : INTEGER; -- size of integer portion - constant right_index : INTEGER := 0; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return sfixed is - constant ARG_LEFT : INTEGER := ARG'length-1; - alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; - constant fw : INTEGER := mine (right_index, right_index); -- catch literals - variable result : sfixed (left_index downto fw); - begin - if arg'length < 1 or (left_index < fw) then - return NASF; - end if; - result := resize (arg => sfixed (XARG), - left_index => left_index, - right_index => right_index, - round_style => round_style, - overflow_style => overflow_style); - return result; - end function to_sfixed; - - -- casted version - function to_sfixed ( - arg : SIGNED) -- signed - return sfixed is - constant ARG_LEFT : INTEGER := ARG'length-1; - alias XARG : SIGNED(ARG_LEFT downto 0) is ARG; - begin - if arg'length < 1 then - return NASF; - end if; - return sfixed(xarg); - end function to_sfixed; - - function add_sign (arg : ufixed) return sfixed is - variable result : sfixed (arg'high+1 downto arg'low); - begin - if arg'length < 1 then - return NASF; - end if; - result (arg'high downto arg'low) := sfixed(cleanvec(arg)); - result (arg'high+1) := '0'; - return result; - end function add_sign; - - -- Because of the farily complicated sizing rules in the fixed point - -- packages these functions are provided to compute the result ranges - -- Example: - -- signal uf1 : ufixed (3 downto -3); - -- signal uf2 : ufixed (4 downto -2); - -- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto - -- ufixed_low (3, -3, '*', 4, -2)); - -- uf1multuf2 <= uf1 * uf2; - -- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod), - -- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed) - function ufixed_high (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER is - begin - case operation is - when '+'| '-' => return maximum (left_index, left_index2) + 1; - when '*' => return left_index + left_index2 + 1; - when '/' => return left_index - right_index2; - when '1' => return -right_index; -- reciprocal - when 'R'|'r' => return mins (left_index, left_index2); -- "rem" - when 'M'|'m' => return mins (left_index, left_index2); -- "mod" - when others => return left_index; -- For abs and default - end case; - end function ufixed_high; - - function ufixed_low (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER is - begin - case operation is - when '+'| '-' => return mins (right_index, right_index2); - when '*' => return right_index + right_index2; - when '/' => return right_index - left_index2 - 1; - when '1' => return -left_index - 1; -- reciprocal - when 'R'|'r' => return mins (right_index, right_index2); -- "rem" - when 'M'|'m' => return mins (right_index, right_index2); -- "mod" - when others => return right_index; -- for abs and default - end case; - end function ufixed_low; - - function sfixed_high (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER is - begin - case operation is - when '+'| '-' => return maximum (left_index, left_index2) + 1; - when '*' => return left_index + left_index2 + 1; - when '/' => return left_index - right_index2 + 1; - when '1' => return -right_index + 1; -- reciprocal - when 'R'|'r' => return mins (left_index, left_index2); -- "rem" - when 'M'|'m' => return left_index2; -- "mod" - when 'A'|'a' => return left_index + 1; -- "abs" - when 'N'|'n' => return left_index + 1; -- -sfixed - when others => return left_index; - end case; - end function sfixed_high; - - function sfixed_low (left_index, right_index : INTEGER; - operation : CHARACTER := 'X'; - left_index2, right_index2 : INTEGER := 0) - return INTEGER is - begin - case operation is - when '+'| '-' => return mins (right_index, right_index2); - when '*' => return right_index + right_index2; - when '/' => return right_index - left_index2; - when '1' => return -left_index; -- reciprocal - when 'R'|'r' => return mins (right_index, right_index2); -- "rem" - when 'M'|'m' => return mins (right_index, right_index2); -- "mod" - when others => return right_index; -- default for abs, neg and default - end case; - end function sfixed_low; - -- Same as above, but using the "size_res" input only for their ranges: - -- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto - -- ufixed_low (uf1, '*', uf2)); - -- uf1multuf2 <= uf1 * uf2; - function ufixed_high (size_res : ufixed; - operation : CHARACTER := 'X'; - size_res2 : ufixed) - return INTEGER is - begin - return ufixed_high (left_index => size_res'high, - right_index => size_res'low, - operation => operation, - left_index2 => size_res2'high, - right_index2 => size_res2'low); - end function ufixed_high; - function ufixed_low (size_res : ufixed; - operation : CHARACTER := 'X'; - size_res2 : ufixed) - return INTEGER is - begin - return ufixed_low (left_index => size_res'high, - right_index => size_res'low, - operation => operation, - left_index2 => size_res2'high, - right_index2 => size_res2'low); - end function ufixed_low; - function sfixed_high (size_res : sfixed; - operation : CHARACTER := 'X'; - size_res2 : sfixed) - return INTEGER is - begin - return sfixed_high (left_index => size_res'high, - right_index => size_res'low, - operation => operation, - left_index2 => size_res2'high, - right_index2 => size_res2'low); - end function sfixed_high; - function sfixed_low (size_res : sfixed; - operation : CHARACTER := 'X'; - size_res2 : sfixed) - return INTEGER is - begin - return sfixed_low (left_index => size_res'high, - right_index => size_res'low, - operation => operation, - left_index2 => size_res2'high, - right_index2 => size_res2'low); - end function sfixed_low; - - -- purpose: returns a saturated number - function saturate ( - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - constant sat : ufixed (left_index downto right_index) := (others => '1'); - begin - return sat; - end function saturate; - - -- purpose: returns a saturated number - function saturate ( - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable sat : sfixed (left_index downto right_index) := (others => '1'); - begin - -- saturate positive, to saturate negative, just do "not saturate()" - sat (left_index) := '0'; - return sat; - end function saturate; - - function saturate ( - size_res : ufixed) -- only the size of this is used - return ufixed is - begin - return saturate (size_res'high, size_res'low); - end function saturate; - - function saturate ( - size_res : sfixed) -- only the size of this is used - return sfixed is - begin - return saturate (size_res'high, size_res'low); - end function saturate; - - -- As a concession to those who use a graphical DSP environment, - -- these functions take parameters in those tools format and create - -- fixed point numbers. These functions are designed to convert from - -- a std_logic_vector to the VHDL fixed point format using the conventions - -- of these packages. In a pure VHDL environment you should use the - -- "to_ufixed" and "to_sfixed" routines. - -- Unsigned fixed point - function to_UFix ( - arg : STD_LOGIC_VECTOR; - width : NATURAL; -- width of vector - fraction : NATURAL) -- width of fraction - return ufixed is - variable result : ufixed (width-fraction-1 downto -fraction); - begin - if (arg'length /= result'length) then - report "FIXED_GENERIC_PKG.TO_UFIX (STD_LOGIC_VECTOR) " - & "Vector lengths do not match. Input length is " - & INTEGER'image(arg'length) & " and output will be " - & INTEGER'image(result'length) & " wide." - severity error; - return NAUF; - else - result := to_ufixed (arg, result'high, result'low); - return result; - end if; - end function to_UFix; - - -- signed fixed point - function to_SFix ( - arg : STD_LOGIC_VECTOR; - width : NATURAL; -- width of vector - fraction : NATURAL) -- width of fraction - return sfixed is - variable result : sfixed (width-fraction-1 downto -fraction); - begin - if (arg'length /= result'length) then - report "FIXED_GENERIC_PKG.TO_SFIX (STD_LOGIC_VECTOR) " - & "Vector lengths do not match. Input length is " - & INTEGER'image(arg'length) & " and output will be " - & INTEGER'image(result'length) & " wide." - severity error; - return NASF; - else - result := to_sfixed (arg, result'high, result'low); - return result; - end if; - end function to_SFix; - - -- finding the bounds of a number. These functions can be used like this: - -- signal xxx : ufixed (7 downto -3); - -- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))" - -- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3) - -- downto UFix_low(11, 3, "+", 11, 3)); - -- Where "11" is the width of xxx (xxx'length), - -- and 3 is the lower bound (abs (xxx'low)) - -- In a pure VHDL environment use "ufixed_high" and "ufixed_low" - function ufix_high ( - width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER is - begin - return ufixed_high (left_index => width - 1 - fraction, - right_index => -fraction, - operation => operation, - left_index2 => width2 - 1 - fraction2, - right_index2 => -fraction2); - end function ufix_high; - function ufix_low ( - width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER is - begin - return ufixed_low (left_index => width - 1 - fraction, - right_index => -fraction, - operation => operation, - left_index2 => width2 - 1 - fraction2, - right_index2 => -fraction2); - end function ufix_low; - function sfix_high ( - width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER is - begin - return sfixed_high (left_index => width - fraction, - right_index => -fraction, - operation => operation, - left_index2 => width2 - fraction2, - right_index2 => -fraction2); - end function sfix_high; - function sfix_low ( - width, fraction : NATURAL; - operation : CHARACTER := 'X'; - width2, fraction2 : NATURAL := 0) - return INTEGER is - begin - return sfixed_low (left_index => width - fraction, - right_index => -fraction, - operation => operation, - left_index2 => width2 - fraction2, - right_index2 => -fraction2); - end function sfix_low; - - function to_unsigned ( - arg : ufixed; -- ufixed point input - constant size : NATURAL; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return UNSIGNED is - begin - return to_uns(resize (arg => arg, - left_index => size-1, - right_index => 0, - round_style => round_style, - overflow_style => overflow_style)); - end function to_unsigned; - - function to_unsigned ( - arg : ufixed; -- ufixed point input - size_res : UNSIGNED; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return UNSIGNED is - begin - return to_unsigned (arg => arg, - size => size_res'length, - round_style => round_style, - overflow_style => overflow_style); - end function to_unsigned; - - function to_signed ( - arg : sfixed; -- ufixed point input - constant size : NATURAL; -- length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return SIGNED is - begin - return to_s(resize (arg => arg, - left_index => size-1, - right_index => 0, - round_style => round_style, - overflow_style => overflow_style)); - end function to_signed; - - function to_signed ( - arg : sfixed; -- ufixed point input - size_res : SIGNED; -- used for length of output - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return SIGNED is - begin - return to_signed (arg => arg, - size => size_res'length, - round_style => round_style, - overflow_style => overflow_style); - end function to_signed; - - function to_real ( - arg : ufixed) -- ufixed point input - return REAL is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := arg'low; - variable result : REAL; -- result - variable arg_int : ufixed (left_index downto right_index); - begin - if (arg'length < 1) then - return 0.0; - end if; - arg_int := cleanvec(arg); - if (Is_X(arg_int)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0" - severity warning; - return 0.0; - end if; - result := 0.0; - for i in arg_int'range loop - if (arg_int(i) = '1') then - result := result + (2.0**i); - end if; - end loop; - return result; - end function to_real; - - function to_real ( - arg : sfixed) -- ufixed point input - return REAL is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := arg'low; - variable result : REAL; -- result - variable arg_int : sfixed (left_index downto right_index); - -- unsigned version of argument - variable arg_uns : ufixed (left_index downto right_index); - -- absolute of argument - begin - if (arg'length < 1) then - return 0.0; - end if; - arg_int := cleanvec(arg); - if (Is_X(arg_int)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0" - severity warning; - return 0.0; - end if; - arg_uns := abs(arg_int); - result := to_real (arg_uns); - if (arg_int(arg_int'high) = '1') then - result := -result; - end if; - return result; - end function to_real; - - function to_integer ( - arg : ufixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return NATURAL is - constant left_index : INTEGER := arg'high; - variable arg_uns : UNSIGNED (minimum(31, left_index+1) downto 0) - := (others => '0'); - begin - if (arg'length < 1) then - return 0; - end if; - if (Is_X (arg)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0" - severity warning; - return 0; - end if; - if (left_index < -1) then - return 0; - end if; - arg_uns := to_uns(resize (arg => arg, - left_index => arg_uns'high, - right_index => 0, - round_style => round_style, - overflow_style => overflow_style)); - return to_integer (arg_uns); - end function to_integer; - - function to_integer ( - arg : sfixed; -- fixed point input - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- rounding by default - return INTEGER is - constant left_index : INTEGER := arg'high; - constant right_index : INTEGER := arg'low; - variable arg_s : SIGNED (minimum(31, left_index+1) downto 0); - begin - if (arg'length < 1) then - return 0; - end if; - if (Is_X (arg)) then - assert NO_WARNING - report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0" - severity warning; - return 0; - end if; - if (left_index < -1) then - return 0; - end if; - arg_s := to_s(resize (arg => arg, - left_index => arg_s'high, - right_index => 0, - round_style => round_style, - overflow_style => overflow_style)); - return to_integer (arg_s); - end function to_integer; - - function to_01 ( - s : ufixed; -- ufixed point input - constant XMAP : STD_LOGIC := '0') -- Map x to - return ufixed is - variable result : ufixed (s'range); -- result - begin - for i in s'range loop - case s(i) is - when '0' | 'L' => result(i) := '0'; - when '1' | 'H' => result(i) := '1'; - when others => result(i) := XMAP; - end case; - end loop; - return result; - end function to_01; - - function to_01 ( - s : sfixed; -- ufixed point input - constant XMAP : STD_LOGIC := '0') -- Map x to - return sfixed is - variable result : sfixed (s'range); - begin - for i in s'range loop - case s(i) is - when '0' | 'L' => result(i) := '0'; - when '1' | 'H' => result(i) := '1'; - when others => result(i) := XMAP; - end case; - end loop; - return result; - end function to_01; - - function Is_X ( - arg : ufixed) - return BOOLEAN is - variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv - begin - argslv := to_slv(arg); - return Is_X(argslv); - end function Is_X; - - function Is_X ( - arg : sfixed) - return BOOLEAN is - variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv - begin - argslv := to_slv(arg); - return Is_X(argslv); - end function Is_X; - - function To_X01 ( - arg : ufixed) - return ufixed is - begin - return to_ufixed (To_X01(to_slv(arg)), arg'high, arg'low); - end function To_X01; - - function to_X01 ( - arg : sfixed) - return sfixed is - begin - return to_sfixed (To_X01(to_slv(arg)), arg'high, arg'low); - end function To_X01; - - function To_X01Z ( - arg : ufixed) - return ufixed is - begin - return to_ufixed (To_X01Z(to_slv(arg)), arg'high, arg'low); - end function To_X01Z; - - function to_X01Z ( - arg : sfixed) - return sfixed is - begin - return to_sfixed (To_X01Z(to_slv(arg)), arg'high, arg'low); - end function To_X01Z; - - function To_UX01 ( - arg : ufixed) - return ufixed is - begin - return to_ufixed (To_UX01(to_slv(arg)), arg'high, arg'low); - end function To_UX01; - - function to_UX01 ( - arg : sfixed) - return sfixed is - begin - return to_sfixed (To_UX01(to_slv(arg)), arg'high, arg'low); - end function To_UX01; - - - function resize ( - arg : ufixed; -- input - constant left_index : INTEGER; -- integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed is - constant arghigh : INTEGER := maximum (arg'high, arg'low); - constant arglow : INTEGER := mine (arg'high, arg'low); - variable invec : ufixed (arghigh downto arglow); - variable result : ufixed(left_index downto right_index) := - (others => '0'); - variable needs_rounding : BOOLEAN := false; - begin -- resize - if (arg'length < 1) or (result'length < 1) then - return NAUF; - elsif (invec'length < 1) then - return result; -- string literal value - else - invec := cleanvec(arg); - if (right_index > arghigh) then -- return top zeros - needs_rounding := (round_style = fixed_round) and - (right_index = arghigh+1); - elsif (left_index < arglow) then -- return overflow - if (overflow_style = fixed_saturate) and - (or_reducex(to_slv(invec)) = '1') then - result := saturate (result'high, result'low); -- saturate - end if; - elsif (arghigh > left_index) then - -- wrap or saturate? - if (overflow_style and - or_reducex(to_slv(invec(arghigh downto left_index+1))) = '1') - then - result := saturate (result'high, result'low); -- saturate - else - if (arglow >= right_index) then - result (left_index downto arglow) := - invec(left_index downto arglow); - else - result (left_index downto right_index) := - invec (left_index downto right_index); - needs_rounding := (round_style = fixed_round); -- round - end if; - end if; - else -- arghigh <= integer width - if (arglow >= right_index) then - result (arghigh downto arglow) := invec; - else - result (arghigh downto right_index) := - invec (arghigh downto right_index); - needs_rounding := (round_style = fixed_round); -- round - end if; - end if; - -- Round result - if needs_rounding then - result := round_fixed (arg => result, - remainder => invec (right_index-1 - downto arglow), - overflow_style => overflow_style); - end if; - return result; - end if; - end function resize; - - function resize ( - arg : sfixed; -- input - constant left_index : INTEGER; -- integer portion - constant right_index : INTEGER; -- size of fraction - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return sfixed is - constant arghigh : INTEGER := maximum (arg'high, arg'low); - constant arglow : INTEGER := mine (arg'high, arg'low); - variable invec : sfixed (arghigh downto arglow); - variable result : sfixed(left_index downto right_index) := - (others => '0'); - variable reduced : STD_ULOGIC; - variable needs_rounding : BOOLEAN := false; -- rounding - begin -- resize - if (arg'length < 1) or (result'length < 1) then - return NASF; - elsif (invec'length < 1) then - return result; -- string literal value - else - invec := cleanvec(arg); - if (right_index > arghigh) then -- return top zeros - if (arg'low /= INTEGER'low) then -- check for a literal - result := (others => arg(arghigh)); -- sign extend - end if; - needs_rounding := (round_style = fixed_round) and - (right_index = arghigh+1); - elsif (left_index < arglow) then -- return overflow - if (overflow_style) then - reduced := or_reducex(to_slv(invec)); - if (reduced = '1') then - if (invec(arghigh) = '0') then - -- saturate POSITIVE - result := saturate (result'high, result'low); - else - -- saturate negative - result := not saturate (result'high, result'low); - end if; - -- else return 0 (input was 0) - end if; - -- else return 0 (wrap) - end if; - elsif (arghigh > left_index) then - if (invec(arghigh) = '0') then - reduced := or_reducex(to_slv(invec(arghigh-1 downto - left_index))); - if overflow_style and reduced = '1' then - -- saturate positive - result := saturate (result'high, result'low); - else - if (right_index > arglow) then - result := invec (left_index downto right_index); - needs_rounding := (round_style = fixed_round); - else - result (left_index downto arglow) := - invec (left_index downto arglow); - end if; - end if; - else - reduced := and_reducex(to_slv(invec(arghigh-1 downto - left_index))); - if overflow_style and reduced = '0' then - result := not saturate (result'high, result'low); - else - if (right_index > arglow) then - result := invec (left_index downto right_index); - needs_rounding := (round_style = fixed_round); - else - result (left_index downto arglow) := - invec (left_index downto arglow); - end if; - end if; - end if; - else -- arghigh <= integer width - if (arglow >= right_index) then - result (arghigh downto arglow) := invec; - else - result (arghigh downto right_index) := - invec (arghigh downto right_index); - needs_rounding := (round_style = fixed_round); -- round - end if; - if (left_index > arghigh) then -- sign extend - result(left_index downto arghigh+1) := (others => invec(arghigh)); - end if; - end if; - -- Round result - if (needs_rounding) then - result := round_fixed (arg => result, - remainder => invec (right_index-1 - downto arglow), - overflow_style => overflow_style); - end if; - return result; - end if; - end function resize; - - -- size_res functions - -- These functions compute the size from a passed variable named "size_res" - -- The only part of this variable used it it's size, it is never passed - -- to a lower level routine. - function to_ufixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - size_res : ufixed) -- for size only - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : STD_LOGIC_VECTOR; -- shifted vector - size_res : sfixed) -- for size only - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - size_res : ufixed) -- for size only - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => to_stdlogicvector(arg), - left_index => size_res'high, - right_index => size_res'low); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : STD_ULOGIC_VECTOR; -- shifted vector - size_res : sfixed) -- for size only - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => to_stdlogicvector(arg), - left_index => size_res'high, - right_index => size_res'low); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : NATURAL; -- integer - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : INTEGER; -- integer - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : REAL; -- real - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - guard_bits => guard_bits, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : REAL; -- real - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default - constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - guard_bits => guard_bits, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_sfixed; - - function to_ufixed ( - arg : UNSIGNED; -- unsigned - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_ufixed; - - function to_sfixed ( - arg : SIGNED; -- signed - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default - constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function to_sfixed; - - function resize ( - arg : ufixed; -- input - size_res : ufixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return ufixed is - variable result : ufixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := resize (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function resize; - - function resize ( - arg : sfixed; -- input - size_res : sfixed; -- for size only - constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow - constant round_style : BOOLEAN := fixed_round_style) -- rounding - return sfixed is - variable result : sfixed (size_res'left downto size_res'right); - begin - if (result'length < 1) then - return result; - else - result := resize (arg => arg, - left_index => size_res'high, - right_index => size_res'low, - round_style => round_style, - overflow_style => overflow_style); - return result; - end if; - end function resize; - - -- Overloaded functions - function "+" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l + - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "+"; - - function "+" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - + r); - end function "+"; - - function "+" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l + - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "+"; - - function "+" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - + r); - end function "+"; - - -- Overloaded functions - function "-" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l - - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "-"; - - function "-" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - - r); - end function "-"; - - function "-" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l - - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "-"; - - function "-" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - - r); - end function "-"; - - -- Overloaded functions - function "*" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l * - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "*"; - - function "*" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - * r); - end function "*"; - - function "*" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l * - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "*"; - - function "*" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - * r); - end function "*"; - - -- Overloaded functions - function "/" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l / - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "/"; - - function "/" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - / r); - end function "/"; - - function "/" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l / - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "/"; - - function "/" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - / r); - end function "/"; - - -- Overloaded functions - function "rem" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l rem - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "rem"; - - function "rem" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - rem r); - end function "rem"; - - function "rem" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l rem - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "rem"; - - function "rem" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - rem r); - end function "rem"; - - function "mod" ( - l : ufixed; -- fixed point input - r : REAL) - return ufixed is - begin - return (l mod - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "mod"; - - function "mod" ( - l : REAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - mod r); - end function "mod"; - - function "mod" ( - l : sfixed; -- fixed point input - r : REAL) - return sfixed is - begin - return (l mod - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "mod"; - - function "mod" ( - l : REAL; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - mod r); - end function "mod"; - - -- Overloaded functions for integers - function "+" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l + to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); -- rounding not needed - end function "+"; - - function "+" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - + r); - end function "+"; - - function "+" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l + to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "+"; - - function "+" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - + r); - end function "+"; - - -- Overloaded functions - function "-" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "-"; - - function "-" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - - r); - end function "-"; - - function "-" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "-"; - - function "-" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - - r); - end function "-"; - - -- Overloaded functions - function "*" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l * to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "*"; - - function "*" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - * r); - end function "*"; - - function "*" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l * to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "*"; - - function "*" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - * r); - end function "*"; - - -- Overloaded functions - function "/" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l / to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "/"; - - function "/" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - / r); - end function "/"; - - function "/" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l / to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "/"; - - function "/" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - / r); - end function "/"; - - -- Overloaded functions - function "rem" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l rem to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "rem"; - - function "rem" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - rem r); - end function "rem"; - - function "rem" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l rem to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "rem"; - - function "rem" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - rem r); - end function "rem"; - - function "mod" ( - l : ufixed; -- fixed point input - r : NATURAL) - return ufixed is - begin - return (l mod to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "mod"; - - function "mod" ( - l : NATURAL; - r : ufixed) -- fixed point input - return ufixed is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - mod r); - end function "mod"; - - function "mod" ( - l : sfixed; -- fixed point input - r : INTEGER) - return sfixed is - begin - return (l mod to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "mod"; - - function "mod" ( - l : INTEGER; - r : sfixed) -- fixed point input - return sfixed is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - mod r); - end function "mod"; - - -- overloaded compare functions - function "=" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l = to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "="; - - function "/=" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l /= to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "/="; - - function ">=" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l >= to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function ">="; - - function "<=" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l <= to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "<="; - - function ">" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l > to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function ">"; - - function "<" ( - l : ufixed; - r : NATURAL) -- fixed point input - return BOOLEAN is - begin - return (l < to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "<"; - - function "=" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - = r); - end function "="; - - function "/=" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - /= r); - end function "/="; - - function ">=" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - >= r); - end function ">="; - - function "<=" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - <= r); - end function "<="; - - function ">" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - > r); - end function ">"; - - function "<" ( - l : NATURAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - < r); - end function "<"; - - function "=" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l = - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "="; - - function "/=" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l /= - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "/="; - - function ">=" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l >= - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function ">="; - - function "<=" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l <= - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "<="; - - function ">" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l > - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function ">"; - - function "<" ( - l : ufixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l < - to_ufixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "<"; - - function "=" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - = r); - end function "="; - - function "/=" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - /= r); - end function "/="; - - function ">=" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - >= r); - end function ">="; - - function "<=" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - <= r); - end function "<="; - - function ">" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - > r); - end function ">"; - - function "<" ( - l : REAL; - r : ufixed) -- fixed point input - return BOOLEAN is - begin - return (to_ufixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - < r); - end function "<"; - - function "=" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l = to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "="; - - function "/=" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l /= to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "/="; - - function ">=" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l >= to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function ">="; - - function "<=" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l <= to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "<="; - - function ">" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l > to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function ">"; - - function "<" ( - l : sfixed; - r : INTEGER) -- fixed point input - return BOOLEAN is - begin - return (l < to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style)); - end function "<"; - - function "=" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - = r); - end function "="; - - function "/=" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - /= r); - end function "/="; - - function ">=" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - >= r); - end function ">="; - - function "<=" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - <= r); - end function "<="; - - function ">" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - > r); - end function ">"; - - function "<" ( - l : INTEGER; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style) - < r); - end function "<"; - - function "=" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l = - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "="; - - function "/=" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l /= - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "/="; - - function ">=" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l >= - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function ">="; - - function "<=" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l <= - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "<="; - - function ">" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l > - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function ">"; - - function "<" ( - l : sfixed; - r : REAL) -- fixed point input - return BOOLEAN is - begin - return (l < - to_sfixed (arg => r, - left_index => l'high, - right_index => l'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits)); - end function "<"; - - function "=" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - = r); - end function "="; - - function "/=" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - /= r); - end function "/="; - - function ">=" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - >= r); - end function ">="; - - function "<=" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - <= r); - end function "<="; - - function ">" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - > r); - end function ">"; - - function "<" ( - l : REAL; - r : sfixed) -- fixed point input - return BOOLEAN is - begin - return (to_sfixed (arg => l, - left_index => r'high, - right_index => r'low, - overflow_style => fixed_overflow_style, - round_style => fixed_round_style, - guard_bits => fixed_guard_bits) - < r); - end function "<"; - - -- rtl_synthesis off - -- synthesis translate_off - -- copied from std_logic_textio - type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error); - type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER; - type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC; - type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus; - - constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-"; - constant char_to_MVL9 : MVL9_indexed_by_char := - ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', - 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U'); - constant char_to_MVL9plus : MVL9plus_indexed_by_char := - ('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z', - 'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error); - constant NBSP : CHARACTER := CHARACTER'val(160); -- space character - constant NUS : STRING(2 to 1) := (others => ' '); - - -- purpose: writes fixed point into a line - procedure write ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - variable s : STRING(1 to value'length +1) := (others => ' '); - variable sindx : INTEGER; - begin -- function write Example: 0011.1100 - sindx := 1; - for i in value'high downto value'low loop - if i = -1 then - s(sindx) := '.'; - sindx := sindx +1; - end if; - s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); - sindx := sindx +1; - end loop; - write(l, s, justified, field); - end procedure write; - - -- purpose: writes fixed point into a line - procedure write ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - variable s : STRING(1 to value'length +1); - variable sindx : INTEGER; - begin -- function write Example: 0011.1100 - sindx := 1; - for i in value'high downto value'low loop - if i = -1 then - s(sindx) := '.'; - sindx := sindx +1; - end if; - s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); - sindx := sindx +1; - end loop; - write(l, s, justified, field); - end procedure write; - - procedure READ(L : inout LINE; - VALUE : out ufixed) is - -- Possible data: 00000.0000000 - -- 000000000000 - variable c : CHARACTER; - variable s : STRING(1 to value'length-1); - variable readOk : BOOLEAN; - variable i : INTEGER; -- index variable - begin -- READ - VALUE (VALUE'range) := (others => 'U'); - loop -- skip white space - read(l, c, readOk); - exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - i := value'high; - readloop : loop - if readOk = false then -- Bail out if there was a bad read - report "FIXED_GENERIC_PKG.READ(ufixed) " - & "Error: end of string encountered" - severity error; - return; - elsif c = ' ' or c = NBSP or c = HT then -- reading done. - assert i = value'low - report "FIXED_GENERIC_PKG.READ(ufixed) " - & "Warning: Value truncated " severity warning; - return; - elsif c = '.' then -- separator, ignore - assert (i = -1) - report "FIXED_GENERIC_PKG.READ(ufixed) " - & "Warning: Decimal point does not match number format " - severity warning; - elsif (char_to_MVL9plus(c) = error) then - report "FIXED_GENERIC_PKG.READ(ufixed) " - & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." - severity error; - return; - else - value (i) := char_to_MVL9(c); - i := i - 1; - if i < value'low then - return; - end if; - end if; - read(l, c, readOk); - end loop readloop; - end procedure READ; - - procedure READ(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN) is - -- Possible data: 00000.0000000 - -- 000000000000 - variable c : CHARACTER; - variable i : INTEGER; -- index variable - variable readOk : BOOLEAN; - begin -- READ - VALUE (VALUE'range) := (others => 'U'); - loop -- skip white space - read(l, c, readOk); - exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - i := value'high; - good := true; - readloop : loop - if readOk = false then -- Bail out if there was a bad read - good := false; - return; - elsif c = ' ' or c = NBSP or c = HT then -- reading done - good := false; - return; - elsif c = '.' then -- separator, ignore - good := (i = -1); - elsif (char_to_MVL9plus(c) = error) then - good := false; - return; - else - value (i) := char_to_MVL9(c); - i := i - 1; - if i < value'low then - return; - end if; - end if; - read(l, c, readOk); - end loop readloop; - end procedure READ; - - procedure READ(L : inout LINE; - VALUE : out sfixed) is - -- Possible data: 00000.0000000 - -- 000000000000 - variable c : CHARACTER; - variable readOk : BOOLEAN; - variable i : INTEGER; -- index variable - begin -- READ - VALUE (VALUE'range) := (others => 'U'); - loop -- skip white space - read(l, c, readOk); - exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - i := value'high; - readloop : loop - if readOk = false then -- Bail out if there was a bad read - report "FIXED_GENERIC_PKG.READ(sfixed) " - & "Error end of string encountered" - severity error; - return; - elsif c = ' ' or c = NBSP or c = HT then -- reading done. - assert i = value'low - report "FIXED_GENERIC_PKG.READ(sfixed) " - & "Warning: Value truncated " severity warning; - return; - elsif c = '.' then -- separator, ignore - assert (i = -1) - report "FIXED_GENERIC_PKG.READ(sfixed) " - & "Warning: Decimal point does not match number format " - severity warning; - elsif (char_to_MVL9plus(c) = error) then - report "FIXED_GENERIC_PKG.READ(sfixed) " - & "Error: Character '" & c & "' read, expected STD_ULOGIC literal." - severity error; - return; - else - value (i) := char_to_MVL9(c); - i := i - 1; - if i < value'low then - return; - end if; - end if; - read(l, c, readOk); - end loop readloop; - end procedure READ; - - procedure READ(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN) is - -- Possible data: 00000.0000000 - -- 000000000000 - variable c : CHARACTER; - variable i : INTEGER; -- index variable - variable readOk : BOOLEAN; - begin -- READ - VALUE (VALUE'range) := (others => 'U'); - loop -- skip white space - read(l, c, readOk); - exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - i := value'high; - good := true; - readloop : loop - if readOk = false then -- Bail out if there was a bad read - good := false; - return; - elsif c = ' ' or c = NBSP or c = HT then -- reading done - good := false; - return; - elsif c = '.' then -- separator, ignore - good := (i = -1); - elsif (char_to_MVL9plus(c) = error) then - good := false; - return; - else - value (i) := char_to_MVL9(c); - i := i - 1; - if i < value'low then - return; - end if; - end if; - read(l, c, readOk); - end loop readloop; - end procedure READ; - - -- octal read and write - procedure owrite ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - begin -- Example 03.30 - write (L => L, - VALUE => to_ostring (VALUE), - JUSTIFIED => JUSTIFIED, - FIELD => FIELD); - end procedure owrite; - - procedure owrite ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - begin -- Example 03.30 - write (L => L, - VALUE => to_ostring (VALUE), - JUSTIFIED => JUSTIFIED, - FIELD => FIELD); - end procedure owrite; - - procedure Char2TriBits (C : CHARACTER; - RESULT : out STD_LOGIC_VECTOR(2 downto 0); - GOOD : out BOOLEAN; - ISSUE_ERROR : in BOOLEAN) is - begin - case c is - when '0' => result := o"0"; good := true; - when '1' => result := o"1"; good := true; - when '2' => result := o"2"; good := true; - when '3' => result := o"3"; good := true; - when '4' => result := o"4"; good := true; - when '5' => result := o"5"; good := true; - when '6' => result := o"6"; good := true; - when '7' => result := o"7"; good := true; - when 'Z' => result := "ZZZ"; good := true; - when 'X' => result := "XXX"; good := true; - when others => - assert not ISSUE_ERROR - report - "FIXED_GENERIC_PKG.OREAD Error: Read a '" & c & - "', expected an Octal character (0-7)." - severity error; - result := "UUU"; - good := false; - end case; - end procedure Char2TriBits; - - -- Note that for Octal and Hex read, you can not start with a ".", - -- the read is for numbers formatted "A.BC". These routines go to - -- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3). - procedure OREAD(L : inout LINE; - VALUE : out ufixed) is - constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; - constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : ufixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - report "FIXED_GENERIC_PKG.OREAD(ufixed): " - & "Error end of string encountered" - severity error; - return; - else - Char2triBits(c, nybble, igood, true); - i := hbv-lbv - 3; -- Top - 3 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood = false then - report "FIXED_GENERIC_PKG.OREAD(ufixed): " - & "Error end of string encountered" - severity error; - elsif (c = '.') then - if (i + 1 /= -lbv) then - igood := false; - report "FIXED_GENERIC_PKG.OREAD(ufixed): " - & "encountered ""."" at wrong index" - severity error; - end if; - else - Char2TriBits(c, nybble, igood, true); - slv (i downto i-2) := nybble; - i := i - 3; - end if; - end loop; - if igood then -- We did not get another error - assert (i = -1) and -- We read everything, and high bits 0 - (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') - report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated." - severity error; - if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then - assert NO_WARNING - report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated" - severity warning; - end if; - end if; - valuex := to_ufixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure OREAD; - - procedure OREAD(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN) is - constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; - constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : ufixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - return; - else - Char2triBits(c, nybble, igood, false); - i := hbv-lbv - 3; -- Top - 3 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood then - if (c = '.') then - igood := igood and (i + 1 = -lbv); - else - Char2TriBits(c, nybble, igood, false); - slv (i downto i-2) := nybble; - i := i - 3; - end if; - end if; - end loop; - good := igood and -- We did not get another error - (i = -1) and -- We read everything, and high bits 0 - (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0'); - valuex := to_ufixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure OREAD; - - procedure OREAD(L : inout LINE; - VALUE : out sfixed) is - constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; - constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : sfixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - report "FIXED_GENERIC_PKG.OREAD(sfixed): " - & "Error end of string encountered" - severity error; - return; - else - Char2triBits(c, nybble, igood, true); - i := hbv-lbv - 3; -- Top - 3 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood = false then - report "FIXED_GENERIC_PKG.OREAD(sfixed): " - & "Error end of string encountered" - severity error; - elsif (c = '.') then - if (i + 1 /= -lbv) then - igood := false; - report "FIXED_GENERIC_PKG.OREAD(sfixed): " - & "encountered ""."" at wrong index" - severity error; - end if; - else - Char2TriBits(c, nybble, igood, true); - slv (i downto i-2) := nybble; - i := i - 3; - end if; - end loop; - if igood then -- We did not get another error - assert (i = -1) and -- We read everything - ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits - or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or - (slv(VALUE'high-lbv) = '1' and - and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1')) - report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated." - severity error; - if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then - assert NO_WARNING - report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated" - severity warning; - end if; - end if; - valuex := to_sfixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure OREAD; - - procedure OREAD(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN) is - constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1; - constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : sfixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - return; - else - Char2triBits(c, nybble, igood, false); - i := hbv-lbv - 3; -- Top - 3 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood then - if (c = '.') then - igood := igood and (i + 1 = -lbv); - else - Char2TriBits(c, nybble, igood, false); - slv (i downto i-2) := nybble; - i := i - 3; - end if; - end if; - end loop; - good := igood -- We did not get another error - and (i = -1) -- We read everything - and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits - or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or - (slv(VALUE'high-lbv) = '1' and - and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1')); - valuex := to_sfixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure OREAD; - - -- hex read and write - procedure hwrite ( - L : inout LINE; -- input line - VALUE : in ufixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - begin -- Example 03.30 - write (L => L, - VALUE => to_hstring (VALUE), - JUSTIFIED => JUSTIFIED, - FIELD => FIELD); - end procedure hwrite; - - -- purpose: writes fixed point into a line - procedure hwrite ( - L : inout LINE; -- input line - VALUE : in sfixed; -- fixed point input - JUSTIFIED : in SIDE := right; - FIELD : in WIDTH := 0) is - begin -- Example 03.30 - write (L => L, - VALUE => to_hstring (VALUE), - JUSTIFIED => JUSTIFIED, - FIELD => FIELD); - end procedure hwrite; - - -- Hex Read and Write procedures for STD_ULOGIC_VECTOR. - -- Modified from the original to be more forgiving. - - procedure Char2QuadBits (C : CHARACTER; - RESULT : out STD_LOGIC_VECTOR(3 downto 0); - GOOD : out BOOLEAN; - ISSUE_ERROR : in BOOLEAN) is - begin - case c is - when '0' => result := x"0"; good := true; - when '1' => result := x"1"; good := true; - when '2' => result := x"2"; good := true; - when '3' => result := x"3"; good := true; - when '4' => result := x"4"; good := true; - when '5' => result := x"5"; good := true; - when '6' => result := x"6"; good := true; - when '7' => result := x"7"; good := true; - when '8' => result := x"8"; good := true; - when '9' => result := x"9"; good := true; - when 'A' | 'a' => result := x"A"; good := true; - when 'B' | 'b' => result := x"B"; good := true; - when 'C' | 'c' => result := x"C"; good := true; - when 'D' | 'd' => result := x"D"; good := true; - when 'E' | 'e' => result := x"E"; good := true; - when 'F' | 'f' => result := x"F"; good := true; - when 'Z' => result := "ZZZZ"; good := true; - when 'X' => result := "XXXX"; good := true; - when others => - assert not ISSUE_ERROR - report - "FIXED_GENERIC_PKG.HREAD Error: Read a '" & c & - "', expected a Hex character (0-F)." - severity error; - result := "UUUU"; - good := false; - end case; - end procedure Char2QuadBits; - - procedure HREAD(L : inout LINE; - VALUE : out ufixed) is - constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; - constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : ufixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - report "FIXED_GENERIC_PKG.HREAD(ufixed): " - & "Error end of string encountered" - severity error; - return; - else - Char2QuadBits(c, nybble, igood, true); - i := hbv-lbv - 4; -- Top - 4 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood = false then - report "FIXED_GENERIC_PKG.HREAD(ufixed): " - & "Error end of string encountered" - severity error; - elsif (c = '.') then - if (i + 1 /= -lbv) then - igood := false; - report "FIXED_GENERIC_PKG.HREAD(ufixed): " - & "encountered ""."" at wrong index" - severity error; - end if; - else - Char2QuadBits(c, nybble, igood, true); - slv (i downto i-3) := nybble; - i := i - 4; - end if; - end loop; - if igood then -- We did not get another error - assert (i = -1) and -- We read everything, and high bits 0 - (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') - report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated." - severity error; - if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then - assert NO_WARNING - report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated" - severity warning; - end if; - end if; - valuex := to_ufixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure HREAD; - - procedure HREAD(L : inout LINE; - VALUE : out ufixed; - GOOD : out BOOLEAN) is - constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; - constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : ufixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - return; - else - Char2QuadBits(c, nybble, igood, false); - i := hbv-lbv - 4; -- Top - 4 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood then - if (c = '.') then - igood := igood and (i + 1 = -lbv); - else - Char2QuadBits(c, nybble, igood, false); - slv (i downto i-3) := nybble; - i := i - 4; - end if; - end if; - end loop; - good := igood and -- We did not get another error - (i = -1) and -- We read everything, and high bits 0 - (or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0'); - valuex := to_ufixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure HREAD; - - procedure HREAD(L : inout LINE; - VALUE : out sfixed) is - constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; - constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : sfixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - report "FIXED_GENERIC_PKG.HREAD(sfixed): " - & "Error end of string encountered" - severity error; - return; - else - Char2QuadBits(c, nybble, igood, true); - i := hbv-lbv - 4; -- Top - 4 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood = false then - report "FIXED_GENERIC_PKG.HREAD(sfixed): " - & "Error end of string encountered" - severity error; - elsif (c = '.') then - if (i + 1 /= -lbv) then - igood := false; - report "FIXED_GENERIC_PKG.HREAD(sfixed): " - & "encountered ""."" at wrong index" - severity error; - end if; - else - Char2QuadBits(c, nybble, igood, true); - slv (i downto i-3) := nybble; - i := i - 4; - end if; - end loop; - if igood then -- We did not get another error - assert (i = -1) -- We read everything - and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits - or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or - (slv(VALUE'high-lbv) = '1' and - and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1')) - report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated." - severity error; - if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then - assert NO_WARNING - report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated" - severity warning; - end if; - end if; - valuex := to_sfixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure HREAD; - - procedure HREAD(L : inout LINE; - VALUE : out sfixed; - GOOD : out BOOLEAN) is - constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1; - constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4; - variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits - variable c : CHARACTER; -- to read the "." - variable valuex : sfixed (hbv downto lbv); - variable igood : BOOLEAN; - variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits - variable i : INTEGER; - begin - VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U" - loop -- skip white space - read(L, c, igood); - exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT)); - end loop; - if igood = false then - return; - else - Char2QuadBits(c, nybble, igood, false); - i := hbv-lbv - 4; -- Top - 4 - slv (hbv-lbv downto i+1) := nybble; - end if; - while (i /= -1) and igood and L.all'length /= 0 loop - read (L, c, igood); - if igood then - if (c = '.') then - igood := igood and (i + 1 = -lbv); - else - Char2QuadBits(c, nybble, igood, false); - slv (i downto i-3) := nybble; - i := i - 4; - end if; - end if; - end loop; - good := igood and -- We did not get another error - (i = -1) and -- We read everything - ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits - or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or - (slv(VALUE'high-lbv) = '1' and - and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1')); - valuex := to_sfixed (slv, hbv, lbv); - VALUE := valuex (VALUE'range); - end procedure HREAD; - - ----------------------------------------------------------------------------- - -- %%% Remove the following 3 functions. They are a duplicate needed for - -- testing - ----------------------------------------------------------------------------- - -- purpose: Justify a string to the right - function justify ( - value : STRING; - justified : SIDE := right; - field : width := 0) - return STRING is - constant VAL_LEN : INTEGER := value'length; - variable result : STRING (1 to field) := (others => ' '); - begin -- function justify - -- return value if field is too small - if VAL_LEN >= field then - return value; - end if; - if justified = left then - result(1 to VAL_LEN) := value; - elsif justified = right then - result(field - VAL_LEN + 1 to field) := value; - end if; - return result; - end function justify; - - function to_ostring ( - value : STD_LOGIC_VECTOR; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant ne : INTEGER := (value'length+2)/3; - variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1); - variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1); - variable result : STRING(1 to ne); - variable tri : STD_LOGIC_VECTOR(0 to 2); - begin - if value'length < 1 then - return NUS; - else - if value (value'left) = 'Z' then - pad := (others => 'Z'); - else - pad := (others => '0'); - end if; - ivalue := pad & value; - for i in 0 to ne-1 loop - tri := To_X01Z(ivalue(3*i to 3*i+2)); - case tri is - when o"0" => result(i+1) := '0'; - when o"1" => result(i+1) := '1'; - when o"2" => result(i+1) := '2'; - when o"3" => result(i+1) := '3'; - when o"4" => result(i+1) := '4'; - when o"5" => result(i+1) := '5'; - when o"6" => result(i+1) := '6'; - when o"7" => result(i+1) := '7'; - when "ZZZ" => result(i+1) := 'Z'; - when others => result(i+1) := 'X'; - end case; - end loop; - return justify(result, justified, field); - end if; - end function to_ostring; - ------------------------------------------------------------------- - function to_hstring ( - value : STD_LOGIC_VECTOR; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant ne : INTEGER := (value'length+3)/4; - variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1); - variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1); - variable result : STRING(1 to ne); - variable quad : STD_LOGIC_VECTOR(0 to 3); - begin - if value'length < 1 then - return NUS; - else - if value (value'left) = 'Z' then - pad := (others => 'Z'); - else - pad := (others => '0'); - end if; - ivalue := pad & value; - for i in 0 to ne-1 loop - quad := To_X01Z(ivalue(4*i to 4*i+3)); - case quad is - when x"0" => result(i+1) := '0'; - when x"1" => result(i+1) := '1'; - when x"2" => result(i+1) := '2'; - when x"3" => result(i+1) := '3'; - when x"4" => result(i+1) := '4'; - when x"5" => result(i+1) := '5'; - when x"6" => result(i+1) := '6'; - when x"7" => result(i+1) := '7'; - when x"8" => result(i+1) := '8'; - when x"9" => result(i+1) := '9'; - when x"A" => result(i+1) := 'A'; - when x"B" => result(i+1) := 'B'; - when x"C" => result(i+1) := 'C'; - when x"D" => result(i+1) := 'D'; - when x"E" => result(i+1) := 'E'; - when x"F" => result(i+1) := 'F'; - when "ZZZZ" => result(i+1) := 'Z'; - when others => result(i+1) := 'X'; - end case; - end loop; - return justify(result, justified, field); - end if; - end function to_hstring; - -- %%% End remove here - - function to_string ( - value : ufixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - variable s : STRING(1 to value'length +1) := (others => ' '); - variable sindx : INTEGER; - begin - if value'length < 1 then - return NUS; - else - if value'high < 0 then - return to_string (resize (value, 0, value'low), justified, field); - elsif value'low > 0 then - return to_string (resize (value, value'high, -1), justified, field); - else - sindx := 1; - for i in value'high downto value'low loop - if i = -1 then - s(sindx) := '.'; - sindx := sindx +1; - end if; - s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); - sindx := sindx +1; - end loop; - return justify(s, justified, field); - end if; - end if; - end function to_string; - - function to_string ( - value : sfixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - variable s : STRING(1 to value'length +1) := (others => ' '); - variable sindx : INTEGER; - begin - if value'length < 1 then - return NUS; - else - if value'high < 0 then - return to_string (resize (value, 0, value'low), justified, field); - elsif value'low > 0 then - return to_string (resize (value, value'high, -1), justified, field); - else - sindx := 1; - for i in value'high downto value'low loop - if i = -1 then - s(sindx) := '.'; - sindx := sindx +1; - end if; - s(sindx) := MVL9_to_char(STD_ULOGIC(value(i))); - sindx := sindx +1; - end loop; - return justify(s, justified, field); - end if; - end if; - end function to_string; - - function to_ostring ( - value : ufixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant lne : INTEGER := (-VALUE'low+2)/3; - constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) := - (others => '0'); - variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); - begin - if value'length < 1 then - return NUS; - else - if value'high < 0 then - return to_ostring (resize (value, 2, value'low), justified, field); - elsif value'low > 0 then - return to_ostring (resize (value, value'high, -3), justified, field); - else - slv := to_slv (value); - return justify(to_ostring(slv(slv'high downto slv'high-VALUE'high)) - & "." - & to_ostring(slv(slv'high-VALUE'high-1 downto 0)&lpad), - justified, field); - end if; - end if; - end function to_ostring; - - function to_hstring ( - value : ufixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant lne : INTEGER := (-VALUE'low+3)/4; - constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) := - (others => '0'); - variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); - begin - if value'length < 1 then - return NUS; - else - if value'high < 0 then - return to_hstring (resize (value, 3, value'low), justified, field); - elsif value'low > 0 then - return to_hstring (resize (value, value'high, -4), justified, field); - else - slv := to_slv (value); - return justify(to_hstring(slv(slv'high downto slv'high-VALUE'high)) - & "." - & to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad), - justified, field); - end if; - end if; - end function to_hstring; - - function to_ostring ( - value : sfixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant ne : INTEGER := ((value'high+1)+2)/3; - variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1); - constant lne : INTEGER := (-VALUE'low+2)/3; - constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) := - (others => '0'); - variable slv : STD_LOGIC_VECTOR (VALUE'high - VALUE'low downto 0); - begin - if value'length < 1 then - return NUS; - else - pad := (others => value(value'high)); - if value'high < 0 then - return to_ostring (resize (value, 2, value'low), justified, field); - elsif value'low > 0 then - return to_ostring (resize (value, value'high, -3), justified, field); - else - slv := to_slv (value); - return justify(to_ostring(pad - & slv(slv'high downto slv'high-VALUE'high)) - & "." - & to_ostring(slv(slv'high-VALUE'high-1 downto 0) - & lpad), - justified, field); - end if; - end if; - end function to_ostring; - - function to_hstring ( - value : sfixed; - justified : SIDE := right; - field : width := 0 - ) return STRING is - constant ne : INTEGER := ((value'high+1)+3)/4; - variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1); - constant lne : INTEGER := (-VALUE'low+3)/4; - constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) := - (others => '0'); - variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0); - begin - if value'length < 1 then - return NUS; - else - pad := (others => value(value'high)); - if value'high < 0 then - return to_hstring (resize (value, 3, value'low), justified, field); - elsif value'low > 0 then - return to_hstring (resize (value, value'high, -4), justified, field); - else - slv := to_slv (value); - return justify(to_hstring(pad&slv(slv'high downto slv'high-VALUE'high)) - & "." - & to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad), - justified, field); - end if; - end if; - end function to_hstring; - - -- From string functions allow you to convert a string into a fixed - -- point number. Example: - -- signal uf1 : ufixed (3 downto -3); - -- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5 - -- The "." is optional in this syntax, however it exist and is - -- in the wrong location an error is produced. Overflow will - -- result in saturation. - function from_string ( - bstring : STRING; -- binary string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(bstring); - read (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - return result; - end function from_string; - - -- Octal and hex conversions work as follows: - -- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped) - -- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped) - function from_ostring ( - ostring : STRING; -- Octal string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(ostring); - oread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - return result; - end function from_ostring; - - function from_hstring ( - hstring : STRING; -- hex string - constant left_index : INTEGER; - constant right_index : INTEGER) - return ufixed is - variable result : ufixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(hstring); - hread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - return result; - end function from_hstring; - - function from_string ( - bstring : STRING; -- binary string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(bstring); - read (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - return result; - end function from_string; - - function from_ostring ( - ostring : STRING; -- Octal string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(ostring); - oread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - return result; - end function from_ostring; - - function from_hstring ( - hstring : STRING; -- hex string - constant left_index : INTEGER; - constant right_index : INTEGER) - return sfixed is - variable result : sfixed (left_index downto right_index); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(hstring); - hread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - return result; - end function from_hstring; - - -- Same as above, "size_res" is used for it's range only. - function from_string ( - bstring : STRING; -- binary string - size_res : ufixed) - return ufixed is - variable result : ufixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(bstring); - read (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - return result; - end function from_string; - - function from_ostring ( - ostring : STRING; -- Octal string - size_res : ufixed) - return ufixed is - variable result : ufixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(ostring); - oread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - return result; - end function from_ostring; - - function from_hstring ( - hstring : STRING; -- hex string - size_res : ufixed) - return ufixed is - variable result : ufixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(hstring); - hread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - return result; - end function from_hstring; - - function from_string ( - bstring : STRING; -- binary string - size_res : sfixed) - return sfixed is - variable result : sfixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(bstring); - read (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - return result; - end function from_string; - - function from_ostring ( - ostring : STRING; -- Octal string - size_res : sfixed) - return sfixed is - variable result : sfixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(ostring); - oread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - return result; - end function from_ostring; - - function from_hstring ( - hstring : STRING; -- hex string - size_res : sfixed) - return sfixed is - variable result : sfixed (size_res'high downto size_res'low); - variable L : LINE; - variable good : BOOLEAN; - begin - L := new STRING'(hstring); - hread (L, result, good); - deallocate (L); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - return result; - end function from_hstring; - - -- purpose: find a dot in a string, return -1 if no dot (internal function) - function finddot ( - arg : STRING) - return INTEGER is - alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto - begin - for i in xarg'reverse_range loop - if (xarg(i) = '.') then - return i-1; - end if; - end loop; - return -1; - end function finddot; - - -- Direct converstion functions. Example: - -- signal uf1 : ufixed (3 downto -3); - -- uf1 <= from_string ("0110.100"); -- 6.5 - -- In this case the "." is not optional, and the size of - -- the output must match exactly. - function from_string ( - bstring : STRING) -- binary string - return ufixed is - variable result : ufixed (bstring'length-2 downto 0); - variable result_nodot : ufixed (bstring'length-1 downto 0); - variable bstring_nodot : STRING (1 to bstring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(bstring); - if (dot = -1) then - L := new STRING'(bstring); - read (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - deallocate (L); - return result_nodot; - else - j := 1; - for i in 1 to bstring'high loop - if (bstring(i) /= '.') then - bstring_nodot(j) := bstring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(bstring_nodot); - read (L, result, good); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - deallocate (L); - return to_ufixed(to_slv(result), bstring'length-dot-2, -dot); - end if; - end function from_string; - - -- Direct octal and hex converstion functions. In this case - -- the string lengths must match. Example: - -- signal sf1 := sfixed (5 downto -3); - -- sf1 <= from_ostring ("71.4") -- -6.5 - function from_ostring ( - ostring : STRING) -- Octal string - return ufixed is - variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0); - variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0); - variable ostring_nodot : STRING (1 to ostring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(ostring); - if (dot = -1) then - L := new STRING'(ostring); - oread (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - deallocate (L); - return to_ufixed(UNSIGNED(result_nodot)); - else - j := 1; - for i in 1 to ostring'high loop - if (ostring(i) /= '.') then - ostring_nodot(j) := ostring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(ostring_nodot); - oread (L, result, good); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - deallocate (L); - return to_ufixed(result, (ostring'length-1-dot)*3-1, -dot*3); - end if; - end function from_ostring; - - function from_hstring ( - hstring : STRING) -- hex string - return ufixed is - variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0); - variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0); - variable hstring_nodot : STRING (1 to hstring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(hstring); - if (dot = -1) then - L := new STRING'(hstring); - hread (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - deallocate (L); - return to_ufixed(UNSIGNED(result_nodot)); - else - j := 1; - for i in 1 to hstring'high loop - if (hstring(i) /= '.') then - hstring_nodot(j) := hstring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(hstring_nodot); - hread (L, result, good); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - deallocate (L); - return to_ufixed(result, (hstring'length-1-dot)*4-1, -dot*4); - end if; - end function from_hstring; - - function from_string ( - bstring : STRING) -- binary string - return sfixed is - variable result : sfixed (bstring'length-2 downto 0); - variable result_nodot : sfixed (bstring'length-1 downto 0); - variable bstring_nodot : STRING (1 to bstring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(bstring); - if (dot = -1) then - L := new STRING'(bstring); - read (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - deallocate (L); - return result_nodot; - else - j := 1; - for i in 1 to bstring'high loop - if (bstring(i) /= '.') then - bstring_nodot(j) := bstring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(bstring_nodot); - read (L, result, good); - assert (good) - report "fixed_generic_pkg.from_string: Bad string "& bstring severity error; - deallocate (L); - return to_sfixed(to_slv(result), bstring'length-dot-2, -dot); - end if; - end function from_string; - - function from_ostring ( - ostring : STRING) -- Octal string - return sfixed is - variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0); - variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0); - variable ostring_nodot : STRING (1 to ostring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(ostring); - if (dot = -1) then - L := new STRING'(ostring); - oread (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - deallocate (L); - return to_sfixed(SIGNED(result_nodot)); - else - j := 1; - for i in 1 to ostring'high loop - if (ostring(i) /= '.') then - ostring_nodot(j) := ostring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(ostring_nodot); - oread (L, result, good); - assert (good) - report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error; - deallocate (L); - return to_sfixed(result, (ostring'length-1-dot)*3-1, -dot*3); - end if; - end function from_ostring; - - function from_hstring ( - hstring : STRING) -- hex string - return sfixed is - variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0); - variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0); - variable hstring_nodot : STRING (1 to hstring'length-1); - variable L : LINE; - variable good : BOOLEAN; - variable dot, i, j : INTEGER; - begin - dot := finddot(hstring); - if (dot = -1) then - L := new STRING'(hstring); - hread (L, result_nodot, good); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - deallocate (L); - return sfixed(SIGNED(result_nodot)); - else - j := 1; - for i in 1 to hstring'high loop - if (hstring(i) /= '.') then - hstring_nodot(j) := hstring(i); -- get rid of the dot. - j := j + 1; - end if; - end loop; - L := new STRING'(hstring_nodot); - hread (L, result, good); - assert (good) - report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error; - deallocate (L); - return to_sfixed(result, (hstring'length-1-dot)*4-1, -dot*4); - end if; - end function from_hstring; - --- synthesis translate_on --- rtl_synthesis on - function to_StdLogicVector ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR is - begin - return to_slv (arg); - end function to_StdLogicVector; - function to_Std_Logic_Vector ( - arg : ufixed) -- fp vector - return STD_LOGIC_VECTOR is - begin - return to_slv (arg); - end function to_Std_Logic_Vector; - function to_StdLogicVector ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR is - begin - return to_slv (arg); - end function to_StdLogicVector; - function to_Std_Logic_Vector ( - arg : sfixed) -- fp vector - return STD_LOGIC_VECTOR is - begin - return to_slv (arg); - end function to_Std_Logic_Vector; - function to_StdULogicVector ( - arg : ufixed) -- fp vector - return STD_ULOGIC_VECTOR is - begin - return to_sulv (arg); - end function to_StdULogicVector; - function to_Std_ULogic_Vector ( - arg : ufixed) -- fp vector - return STD_ULOGIC_VECTOR is - begin - return to_sulv (arg); - end function to_Std_ULogic_Vector; - function to_StdULogicVector ( - arg : sfixed) -- fp vector - return STD_ULOGIC_VECTOR is - begin - return to_sulv (arg); - end function to_StdULogicVector; - function to_Std_ULogic_Vector ( - arg : sfixed) -- fp vector - return STD_ULOGIC_VECTOR is - begin - return to_sulv (arg); - end function to_Std_ULogic_Vector; -end package body fixed_pkg; diff --git a/lib/fixed_ja/fixed_ja.vhd b/lib/fixed_ja/fixed_ja.vhd deleted file mode 100644 index bcd2700..0000000 --- a/lib/fixed_ja/fixed_ja.vhd +++ /dev/null @@ -1,322 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; - -package fixed_ja is - - - type ufixed_t is array (integer range <>) of STD_LOGIC; - type sfixed_t is array (integer range <>) of STD_LOGIC; - type ufixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - type sfixed_array_t is array (natural range <>, integer range <>) of STD_LOGIC; - - type round_mode_t is (none, round_to_zero, round_pos_infinity, round_neg_infinity, round_half_up, round_half_down, round_nearest, round_convergent); - type saturate_mode_t is (none, saturate); - - -- Declare functions and procedure - - constant ASSERT_NO_WARN : boolean := false; - constant default_round_mode : round_mode_t := none; - constant default_saturate_mode : saturate_mode_t := none; - - -- null array constants - constant NAUF : ufixed_t (0 downto 1) := (others => '0'); - constant NASF : sfixed_t (0 downto 1) := (others => '0'); - constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0'); - - -- Constructor helpers - -- Use: variable v8u2 : ufixed_t(ufixed(8,2)'range); - function uproto (nbits : integer; nbits_int : integer) return ufixed_t; - - -- Use: variable v8s2 : sfixed_t(sfixed(8,2)'range); - function sproto (nbits : integer; nbits_int : integer) return sfixed_t; - - function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t; - function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t; - - -- Conversion Functions - function to_ufixed(src : ufixed_t) return ufixed_t; - function to_sfixed(src : sfixed_t) return sfixed_t; - function to_ufixed(src : sfixed_t) return ufixed_t; - function to_sfixed(src : ufixed_t) return sfixed_t; - - function to_ufixed - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_ufixed - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_sfixed - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - function to_sfixed - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - -- fixed <= integer - function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t; - - -- fixed <= integer - function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t; - - -- ufixed <= unsigned - function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : unsigned; proto : ufixed_t) return ufixed_t; - - -- sfixed <= signed - function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : signed; proto : sfixed_t) return sfixed_t; - - -- fixed <= slv - function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t; - function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t; - function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t; - function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t; - - -- ufixed <= real - function to_ufixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - function to_ufixed - ( - src : real; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t; - - -- sfixed <= real - function to_sfixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - function to_sfixed - ( - src : real; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t; - - -- Slicing functions for unconstrained array types - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t; - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t; - - -- ufixed <= string - function to_ufixed (src : string) return ufixed_t; - - -- sfixed <= string - function to_sfixed (src : string) return sfixed_t; - - -- real <= ufixed - function to_real(src : ufixed_t) return real; - - -- real <= sfixed - function to_real(src : sfixed_t) return real; - - -- slv <= ufixed - function to_slv(src : ufixed_t) return std_logic_vector; - - -- slv <= sfixed - function to_slv(src : sfixed_t) return std_logic_vector; - - -- UNSIGNED <= ufixed - function to_unsigned (src : ufixed_t) return UNSIGNED; - - -- SIGNED <= sfixed - function to_signed (src : sfixed_t) return SIGNED; - - -- integer <= ufixed - function to_integer (src : ufixed_t) return integer; - - -- integer <= sfixed - function to_integer (src : sfixed_t) return integer; - - function to_string(src : ufixed_t) return string; - function to_string(src : sfixed_t) return string; - function to_string(src : std_logic_vector) return string; - - ------------------------------------------------------------- - -- Arithmetic shift left - ------------------------------------------------------------- - function "sla" (src : ufixed_t; count : integer) return ufixed_t; - function "sla" (src : sfixed_t; count : integer) return sfixed_t; - - ------------------------------------------------------------- - -- Arithmetic shift right - ------------------------------------------------------------- - function "sra" (src : ufixed_t; count : integer) return ufixed_t; - function "sra" (src : sfixed_t; count : integer) return sfixed_t; - - ------------------------------------------------------------- - -- Multiplication - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Sum - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : integer) return ufixed_t; - function "+" (a : sfixed_t; b : integer) return sfixed_t; - function "+" (a : ufixed_t; b : unsigned) return ufixed_t; - function "+" (a : sfixed_t; b : signed) return sfixed_t; - function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t; - function "+" (a : ufixed_t; b : std_logic) return ufixed_t; - function "+" (a : sfixed_t; b : std_logic) return sfixed_t; - - - ------------------------------------------------------------- - -- Difference - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : integer) return ufixed_t; - function "-" (a : sfixed_t; b : integer) return sfixed_t; - function "-" (a : ufixed_t; b : unsigned) return ufixed_t; - function "-" (a : sfixed_t; b : signed) return sfixed_t; - function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t; - function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t; - function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t; - function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t; - function "-" (a : ufixed_t; b : std_logic) return ufixed_t; - function "-" (a : sfixed_t; b : std_logic) return sfixed_t; - - ------------------------------------------------------------- - -- Equality - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : ufixed_t) return boolean; - function "=" (a : sfixed_t; b : sfixed_t) return boolean; - function "=" (a : ufixed_t; b : sfixed_t) return boolean; - function "=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Inequality - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : ufixed_t) return boolean; - function "/=" (a : sfixed_t; b : sfixed_t) return boolean; - function "/=" (a : ufixed_t; b : sfixed_t) return boolean; - function "/=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Less than - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : ufixed_t) return boolean; - function "<" (a : sfixed_t; b : sfixed_t) return boolean; - function "<" (a : ufixed_t; b : sfixed_t) return boolean; - function "<" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Greater than - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : ufixed_t) return boolean; - function ">" (a : sfixed_t; b : sfixed_t) return boolean; - function ">" (a : ufixed_t; b : sfixed_t) return boolean; - function ">" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Less or equal than - ------------------------------------------------------------- - function "<=" (a : ufixed_t; b : ufixed_t) return boolean; - function "<=" (a : sfixed_t; b : sfixed_t) return boolean; - function "<=" (a : ufixed_t; b : sfixed_t) return boolean; - function "<=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Greater or equal than - ------------------------------------------------------------- - function ">=" (a : ufixed_t; b : ufixed_t) return boolean; - function ">=" (a : sfixed_t; b : sfixed_t) return boolean; - function ">=" (a : ufixed_t; b : sfixed_t) return boolean; - function ">=" (a : sfixed_t; b : ufixed_t) return boolean; - - ------------------------------------------------------------- - -- Unary Arithmetic Operators - ------------------------------------------------------------- - function "abs" (src : sfixed_t) return sfixed_t; - function "-" (src : ufixed_t) return sfixed_t; - function "-" (src : sfixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Misc. Operators - ------------------------------------------------------------- - function ipart (src : ufixed_t) return ufixed_t; - function fpart (src : ufixed_t) return ufixed_t; - function ipart (src : sfixed_t) return sfixed_t; - function fpart (src : sfixed_t) return sfixed_t; - - ------------------------------------------------------------- - -- Print function - ------------------------------------------------------------- - procedure print_info(src : in ufixed_t; prefix : in string); - procedure print_info(src : in sfixed_t; prefix : in string); - procedure print_info(src : in string; prefix : in string); - - ------------------------------------------------------------- - -- Helpers - ------------------------------------------------------------- - function cmsb(src : ufixed_t) return integer; - function clsb(src : ufixed_t) return integer; - - function MIN (X, Y: INTEGER) return INTEGER; - function MAX (X, Y: INTEGER) return INTEGER; - - function "MOD" (X, Y: in REAL ) return REAL; - function ipart(src : real) return real; - function fpart(src : real) return real; - - function and_red(arg : ufixed_t) return STD_ULOGIC; - function nand_red(arg : ufixed_t) return STD_ULOGIC; - function or_red(arg : ufixed_t) return STD_ULOGIC; - function nor_red(arg : ufixed_t) return STD_ULOGIC; - function xor_red(arg : ufixed_t) return STD_ULOGIC; - function xnor_red(arg : ufixed_t) return STD_ULOGIC; - function and_red(arg : sfixed_t) return STD_ULOGIC; - function nand_red(arg : sfixed_t) return STD_ULOGIC; - function or_red(arg : sfixed_t) return STD_ULOGIC; - function nor_red(arg : sfixed_t) return STD_ULOGIC; - function xor_red(arg : sfixed_t) return STD_ULOGIC; - function xnor_red(arg : sfixed_t) return STD_ULOGIC; - - -------------------------------------------------------------- - -end; -- package fixed_ja; - diff --git a/lib/fixed_ja/fixed_ja_body.vhd b/lib/fixed_ja/fixed_ja_body.vhd deleted file mode 100644 index a85b626..0000000 --- a/lib/fixed_ja/fixed_ja_body.vhd +++ /dev/null @@ -1,1921 +0,0 @@ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use ieee.math_real.all; -use std.textio.all; - -package body fixed_ja is - - ------------------------------------------------------------- - -- Local Procedures - ------------------------------------------------------------- - -- adds 1 to the LSB of the number - procedure round_up - ( - src : in ufixed_t; - result : out ufixed_t; - overflowx : out BOOLEAN ) is - - variable srcuns, resuns : UNSIGNED (src'high-src'low+1 downto 0) := (others => '0'); - begin -- round_up - srcuns (srcuns'high-1 downto 0) := to_unsigned (src); - resuns := srcuns + 1; - - result := to_ufixed(resuns(src'high-src'low downto 0), src); - overflowx := (resuns(resuns'high) = '1'); - - end procedure round_up; - - ------------------------------------------------------------- - -- adds 1 to the LSB of the number - procedure round_up - ( - src : in sfixed_t; - result : out sfixed_t; - overflowx : out BOOLEAN ) is - - variable srcs, ress : SIGNED (src'high-src'low+1 downto 0); - begin -- round_up - srcs (srcs'high-1 downto 0) := to_signed (src); - srcs(srcs'high) := src(src'high); -- sign extend - ress := srcs + 1; - - result := to_sfixed(ress (ress'high-1 downto 0), src); - overflowx := ((src(src'high) /= ress(ress'high-1)) and (or_red (sfixed_t(ress)) /= '0')); - - end procedure round_up; - - ------------------------------------------------------------- - -- Local functions - ------------------------------------------------------------- - -- round_fixed() --- function round_fixed --- ( --- src : ufixed_t; --- remainder : ufixed_t; --- rnd_mode : round_mode_t := default_round_mode --- ) return ufixed_t is --- variable res : ufixed_t(src'range); --- begin --- return res; --- --- end round_fixed; - - ------------------------------------------------------------- --- function round_fixed --- ( --- src : sfixed_t; --- remainder : sfixed_t; --- rnd_mode : round_mode_t := default_round_mode --- ) return sfixed_t is --- variable res : signed(src'length-1 downto 0); --- begin --- return src; --- --- end round_fixed; - - ------------------------------------------------------------- - function reshape - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - variable RemainLow : ufixed_t (proto'low-1 downto src'low) := (others => '0'); - variable RemainHigh : ufixed_t (src'high downto proto'high+1) := (others => '0'); - variable dst, tmp : ufixed_t (proto'high downto proto'low) := (others => '0'); - variable ovf, isTruncLo, isTruncHi : boolean := false; - begin - - if proto'high < -1 then - assert false report "U: reshape: Bad dual point (Upper bound < (-1))" severity error; - end if; - - -- Check for high and low truncation - isTruncLo := (src'low < dst'low); - isTruncHi := (src'high > dst'high); - - -- Reshape - dst := (others => '0'); - dst(min(src'high, dst'high) downto max(src'low, dst'low)) := src(min(src'high, dst'high) downto max(src'low, dst'low)); - tmp := dst; - - -- Get low remainder - if isTruncLo then - RemainLow := src(RemainLow'range); - end if; - - -- Get high remainder - if isTruncHi then - RemainHigh := src(RemainHigh'range); - end if; - - ovf := false; - - -- Rounding - if isTruncLo then - - case rnd_mode is - - -- Round to positive infinity (round ceiling) - when round_pos_infinity => - if or_red(RemainLow) = '1' then - round_up(tmp, dst, ovf); - end if; - - -- Round Half-up - -- Round nearest - when round_half_up | round_nearest => - if (RemainLow(RemainLow'high) = '1') then - round_up(tmp, dst, ovf); - end if; - - -- Round convergent - when round_convergent => - if RemainLow(RemainLow'high) = '1' then - if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then - round_up(tmp, dst, ovf); - elsif tmp(dst'low) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round to zero - when round_to_zero | none => null; - - when others => - assert false report "Reshape(U): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error; - - end case; - end if; - - -- Saturating - if sat_mode = saturate then - - -- Check overflow - if isTruncHi then - ovf := ovf or or_red(RemainHigh) = '1'; - end if; - - -- Saturate - if ovf then - dst := (others => '1'); - end if; - - end if; - - return dst; - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - begin - return reshape(src, uproto(nbits, nbits_int), rnd_mode, sat_mode); - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - variable RemainLow : sfixed_t (proto'low-1 downto src'low) := (others => '0'); - variable RemainHigh : sfixed_t (src'high-1 downto proto'high) := (others => '0'); - variable dst, tmp : sfixed_t (proto'high downto proto'low) := (others => '0'); - variable ovf, isTruncLo, isTruncHi : boolean := false; - variable sign : std_logic; - begin - - if proto'high < 0 then - assert false report "Reshape(S): Bad dual point (Upper bound < (0))" severity error; - end if; - - -- Check for high and low truncation - isTruncLo := (src'low < dst'low); - isTruncHi := (src'high > dst'high); - - -- Reshape - sign := src(src'high); - dst := (others => '0'); - dst(dst'high downto max(src'low, dst'low)) := (dst'high downto min(src'high, dst'high) => sign) & src(min(src'high, dst'high)-1 downto max(src'low, dst'low)); - tmp := dst; - - -- Get low remainder - if isTruncLo then - RemainLow := src(RemainLow'range); - end if; - - -- Get high remainder - if isTruncHi then - RemainHigh := src(RemainHigh'range); - end if; - - ovf := false; - - -- Rounding - if isTruncLo then - - case rnd_mode is - - -- Round to positive infinity (round ceiling) - when round_pos_infinity => - round_up(tmp, dst, ovf); - if ovf then - dst(dst'high) := '0'; - end if; - - -- Round Half-up - when round_half_up => - if RemainLow(RemainLow'high) = '1' then - round_up(tmp, dst, ovf); - end if; - - -- Round nearest - when round_nearest => - if RemainLow(RemainLow'high) = '1' then - if RemainLow'length = 1 then - if sign = '0' then - round_up(tmp, dst, ovf); - end if; - elsif sign = '0' or (sign and or_red(RemainLow(RemainLow'high-1 downto RemainLow'low))) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round convergent - when round_convergent => - if RemainLow(RemainLow'high) = '1' then - if or_red(RemainLow(RemainLow'high-1 downto RemainLow'low)) = '1' then - round_up(tmp, dst, ovf); - elsif tmp(dst'low) = '1' then - round_up(tmp, dst, ovf); - end if; - end if; - - -- Round to zero - when round_to_zero => - if (or_red(RemainLow) = '1' and sign = '1') then - round_up(tmp, dst, ovf); - end if; - - -- No Round - when none => - -- Same as RoundToZero but overflow detection is omitted - dst := tmp + (or_red(RemainLow) and sign); - - when others => - assert false report "Reshape(S): Rounding mode (" & round_mode_t'image(rnd_mode) & ") not implemented!" severity error; - - end case; - - -- Check negative zero - if dst(dst'high) = '1' then - if or_red(dst(dst'high-1 downto dst'low)) = '0' then - dst(dst'high) := '0'; - -- assert false report "Reshape(S): -0 detected" severity note; - end if; - end if; - end if; - - -- Saturating - if sat_mode = saturate then - - -- Check overflow - if isTruncHi then - ovf := ovf or - (sign = '1' and src(dst'high) = '0' and or_red(tmp(dst'high-1 downto dst'low)) = '1') or - (sign = '1' and src(dst'high) = '1' and or_red(tmp(dst'high-1 downto dst'low)) = '0') or - (sign = '0' and or_red(RemainHigh) = '1'); - end if; - - -- Saturate - if ovf then - if (sign = '1') then - dst := '1' & (dst'high-1 downto dst'low+1 => '0') & '1'; - else - dst := '0' & (dst'high-1 downto dst'low => '1'); - end if; - end if; - - end if; - - return dst; - - end reshape; - - ------------------------------------------------------------- - function reshape - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - begin - return reshape(src, sproto(nbits, nbits_int), rnd_mode, sat_mode); - - end reshape; - - ------------------------------------------------------------- - -- Constuctor helpers - ------------------------------------------------------------- - function uproto (nbits : integer; nbits_int : integer) return ufixed_t is - constant result : ufixed_t (nbits_int-1 downto nbits_int-nbits) := (others => '0'); - begin - return result(nbits_int-1 downto nbits_int-nbits); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_int : integer) return sfixed_t is - constant result : sfixed_t (nbits_int downto nbits_int-nbits+1) := (others => '0'); - begin - return result(nbits_int downto nbits_int-nbits+1); - end sproto; - - ------------------------------------------------------------- - function uproto (a : ufixed_t; op : character; b : ufixed_t) return ufixed_t is - constant result : ufixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0'); - variable hi, lo : integer := 0; - - begin - - case op is - when '+' => - hi := max(a'high, b'high); - if a'high = b'high then - hi := hi + 1; - end if; - lo := min(a'low, b'low); - - when '-' => - hi := max(a'high, b'high); - lo := min(a'low, b'low); - - when '*' => - hi := a'high + b'high + 1; - if (a'high < 0 or b'high < 0) then - if (hi > -1) then - hi := hi-1; - end if; - end if; - lo := hi - a'length - b'length + 1; - - when others => null; - - end case; - - return result(hi downto lo); - end uproto; - - ------------------------------------------------------------- - function sproto (a : sfixed_t; op : character; b : sfixed_t) return sfixed_t is - constant result : sfixed_t(a'high + b'high + 4 downto a'low + b'low - 4) := (others => '0'); - variable hi, lo : integer := 0; - - begin - - case op is - when '+' => - hi := max(a'high, b'high); - if a'high = b'high then - hi := hi + 1; - end if; - lo := min(a'low, b'low); - - when '-' => - hi := max(a'high, b'high); - lo := min(a'low, b'low); - - when '*' => - hi := a'high + b'high; - if (a'high = 0 or b'high = 0) then - if (hi > 0) then - hi := hi-1; - end if; - end if; - lo := hi - a'length - b'length + 1; - - when others => null; - - end case; - - return result(hi downto lo); - end sproto; - - ------------------------------------------------------------- - -- Type conversions - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed(src : ufixed_t) return ufixed_t is - begin - return to_ufixed(src, src); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= sfixed - function to_ufixed(src : sfixed_t) return ufixed_t is - variable dst : ufixed_t(src'range) := (others => '0'); - begin - dst := ufixed_t(abs(src)); - return dst(src'high-1 downto src'low); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed(src : sfixed_t) return sfixed_t is - begin - return src; - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= ufixed - function to_sfixed(src : ufixed_t) return sfixed_t is - variable dst : sfixed_t(src'high+1 downto src'low) := (others => '0'); - begin - dst(src'range) := sfixed_t(src); - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed - ( - src : ufixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return reshape(src, nbits, nbits_int, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= ufixed - function to_ufixed - ( - src : ufixed_t; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return reshape(src, proto, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed - ( - src : sfixed_t; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return reshape(src, nbits, nbits_int, rnd_mode, sat_mode); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= sfixed - function to_sfixed - ( - src : sfixed_t; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return reshape(src, proto, rnd_mode, sat_mode); - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= integer - function to_ufixed (src : integer; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end to_ufixed; - - function to_ufixed (src : integer; proto : ufixed_t) return ufixed_t is - begin - return to_ufixed(to_unsigned(src, proto'length), proto); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= unsigned - function to_ufixed (src : unsigned; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end to_ufixed; - - ------------------------------------------------------------- - -- ufixed <= unsigned - function to_ufixed(src : unsigned; proto : ufixed_t) return ufixed_t is - variable dst : ufixed_t(proto'high downto proto'low) := (others => '0'); - begin - - dst(dst'low + min(dst'length, src'length)-1 downto dst'low) := ufixed_t(src(min(dst'length, src'length)-1 downto 0)); - - return dst; - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= integer - function to_sfixed (src : integer; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - - function to_sfixed (src : integer; proto : sfixed_t) return sfixed_t is - begin - - return to_sfixed(to_signed(src, proto'length), proto); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= signed - function to_sfixed (src : signed; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - - ------------------------------------------------------------- - -- sfixed <= signed - function to_sfixed(src : signed; proto : sfixed_t) return sfixed_t is - variable dst : sfixed_t(proto'high downto proto'low) := (others => '0'); - begin - - dst(dst'low + min(dst'length, src'length)-2 downto dst'low) := sfixed_t(src(min(dst'length, src'length)-2 downto 0)); - dst(dst'high) := src(src'high); - - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - function to_ufixed (src : STD_LOGIC_VECTOR; proto : ufixed_t) return ufixed_t is - variable result : ufixed_t (proto'left downto proto'right); - begin - if (result'length < 1) then - return result; - else - result := to_ufixed (unsigned(src), proto); - return result; - end if; - - end function to_ufixed; - - ------------------------------------------------------------- - function to_ufixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return ufixed_t is - begin - return to_ufixed(src, uproto(nbits, nbits_int)); - - end function to_ufixed; - - ------------------------------------------------------------- - function to_sfixed (src : STD_LOGIC_VECTOR; proto : sfixed_t) return sfixed_t is - variable result : sfixed_t (proto'left downto proto'right); - begin - if (result'length < 1) then - return result; - else - result := to_sfixed (signed(src), proto); - return result; - end if; - - end function to_sfixed; - - ------------------------------------------------------------- - function to_sfixed (src : STD_LOGIC_VECTOR; nbits : integer; nbits_int : integer) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int)); - - end to_sfixed; - ------------------------------------------------------------- - - -- ufixed <= real - function to_ufixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - - constant nbits_ext : integer := nbits + 1; - constant fix_hi : integer := nbits_int - 1; - constant fix_lo : integer := nbits_int - nbits_ext; - - variable dst : ufixed_t (fix_hi downto fix_lo) := (others => '0'); - variable i : integer := 0; - variable remain : real := 0.0; - - begin - - if (nbits_int < 0) then - assert false report "to_ufixed: Bad dual point (N integer bits < 0)" severity error; - end if; - - if ((2.0**nbits_int - 1.0) < ipart(abs(src))) then --- assert ASSERT_NO_WARN report "to_ufixed: Overflow (" & REAL'image(src) & ") " severity warning; --- print_info(dst, "dst: "); - end if; - - remain := abs(src); - for i in dst'range loop - if remain >= 2.0**i then - dst(i) := '1'; - remain := remain - 2.0**i; - else - dst(i) := '0'; - end if; - end loop; - - return to_ufixed(dst, nbits, nbits_int, rnd_mode, sat_mode); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= real - function to_sfixed - ( - src : real; - proto : sfixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - - variable utmp : ufixed_t(proto'high-1 downto proto'low) := (others => '0'); - variable dst : sfixed_t(proto'high downto proto'low) := (others => '0'); - - begin - utmp := to_ufixed(src, utmp, rnd_mode, sat_mode); - if (src < 0.0) then - dst := -to_sfixed(utmp); - else - dst := to_sfixed(utmp); - end if; - - return dst; - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= real - function to_ufixed - ( - src : real; - proto : ufixed_t; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return ufixed_t is - begin - return to_ufixed(src, proto'length, proto'high+1, rnd_mode, sat_mode); - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= real - function to_sfixed - ( - src : real; - nbits : integer; - nbits_int : integer; - rnd_mode : round_mode_t := default_round_mode; - sat_mode : saturate_mode_t := default_saturate_mode - ) return sfixed_t is - begin - return to_sfixed(src, sproto(nbits, nbits_int), rnd_mode, sat_mode); - end to_sfixed; - - ------------------------------------------------------------------------------- - -- ufixed <= ufixed_array(i) - function to_ufixed(src : ufixed_array_t; index : integer) return ufixed_t is - variable dst : ufixed_t(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_ufixed; - - ------------------------------------------------------------------------------- - -- sfixed <= sfixed_array(i) - function to_sfixed(src : sfixed_array_t; index : integer) return sfixed_t is - variable dst : sfixed_t(src'range(2)); - begin - for j in src'range(2) loop - dst(j) := src(index, j); - end loop; - - return dst; - - end to_sfixed; - - ------------------------------------------------------------- - -- ufixed <= string - function to_ufixed (src : string) return ufixed_t is - - variable i, j, nbits, nbits_int, nbits_frac : integer := 0; - variable dst : unsigned(src'length downto 0) := (others => '0'); - variable dp_found : boolean := false; - begin - - for i in src'reverse_range loop - case src(i) is - when '.' => - if dp_found then - assert false report "More than one DP not found." severity error; - else - dp_found := true; - nbits_frac := j; - end if; - - when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1; - when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1; - when others => - assert false report "Illegal character in binary string." severity error; - - end case; - - end loop ; - if not dp_found then - assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning; - end if; - - nbits_int := nbits - nbits_frac; - - return to_ufixed(dst(nbits-1 downto 0), nbits, nbits_int); - - end to_ufixed; - - ------------------------------------------------------------- - -- sfixed <= string - function to_sfixed (src : string) return sfixed_t is - - variable i, j, nbits, nbits_int, nbits_frac : integer := 0; - variable dst : signed(src'length downto 0) := (others => '0'); - variable dp_found : boolean := false; - variable is_neg : boolean := false; - begin - - is_neg := src(src'left) = '-'; - - for i in src'reverse_range loop - case src(i) is - when '-' => null; - when '+' => null; - - when '.' => - if dp_found then - assert false report "More than one DP not found." severity error; - else - dp_found := true; - nbits_frac := j; - end if; - - when '0' => dst(nbits) := '0'; nbits := nbits + 1; j := j + 1; - when '1' => dst(nbits) := '1'; nbits := nbits + 1; j := j + 1; - when others => - assert false report "Illegal character in binary string." severity error; - end case; - end loop ; - nbits := nbits + 1; - - if not dp_found then - assert ASSERT_NO_WARN report "DP not found. Using left alignment." severity warning; - end if; - - nbits_int := nbits - nbits_frac-1; - - if is_neg then - dst(nbits-1 downto 0) := -dst(nbits-1 downto 0); - end if; - - return to_sfixed(dst(nbits-1 downto 0), nbits, nbits_int); - - end to_sfixed; - - ------------------------------------------------------------- - function to_unsigned (src : ufixed_t) return UNSIGNED is - subtype t is UNSIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return UNSIGNED(to_X01(std_logic_vector(slv))); - - end function to_unsigned; - - ------------------------------------------------------------- - function to_signed (src : sfixed_t) return SIGNED is - subtype t is SIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return SIGNED(to_X01(std_logic_vector(slv))); - - end function to_signed; - - ------------------------------------------------------------- - -- integer <= ufixed - function to_integer (src : ufixed_t) return integer is - begin - return to_integer(to_unsigned(src)); - end to_integer; - - ------------------------------------------------------------- - -- integer <= sfixed - function to_integer (src : sfixed_t) return integer is - begin - return to_integer(to_signed(src)); - end to_integer; - - ------------------------------------------------------------- - -- to_real - function to_real(src : ufixed_t) return real is - variable dst : real := 0.0; - begin - for i in src'range loop - if (src(i) = '1') then - dst := dst + real(2.0**i); - end if; - end loop; - return dst; - - end to_real; - - ------------------------------------------------------------- - function to_real(src : sfixed_t) return real is - variable dst : real := 0.0; - begin - dst := to_real(to_ufixed(src)); - - if (src(src'high) = '1') then - dst := -dst; - end if; - - return dst; - - end to_real; - - ------------------------------------------------------------- - -- to_slv - function to_slv (src : ufixed_t) return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0); - variable slv : t; - begin - if src'length < 1 then - return NSLV; - end if; - slv := t (src); - return slv; - - end function to_slv; - - ------------------------------------------------------------- - -- to_slv - function to_slv (src : sfixed_t) return STD_LOGIC_VECTOR is - subtype t is STD_LOGIC_VECTOR (src'high - src'low downto 0); - variable slv : t; - begin - if src'length < 1 then - return NSLV; - end if; - slv := t (src); - return slv; - - end function to_slv; - - ------------------------------------------------------------- - function to_string(src : ufixed_t) return string is - variable str : string(src'length+1 downto 1) := (others => '0'); - variable i, j : integer := 0; - - begin - j := src'length+1; - for i in src'high downto 0 loop - if (src(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - str(j) := '.'; - j := j - 1; - - for i in -1 downto src'low loop - if (src(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - return str; - - end to_string; - - ------------------------------------------------------------- - function to_string(src : sfixed_t) return string is - variable str : string(src'length+1 downto 1) := (others => '0'); - variable i, j, start : integer := 0; - variable strlen : integer := 0; - variable src_abs : sfixed_t(src'range) := (others => '0'); - - begin - if (src'high < 0) then - assert false report "Illegal signed fix point number" severity error; - end if; - - start := src'high; - strlen := src'length; - - j := src'length+1; - if (src(start) = '1') then - str(j) := '-'; - j := j - 1; - start := start - 1; - strlen := strlen + 1; - end if; - - src_abs := abs(src); - - for i in start downto 0 loop - if (src_abs(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - str(j) := '.'; - j := j - 1; - - for i in -1 downto src'low loop - if (src_abs(i) = '1') then - str(j) := '1'; - end if; - j := j - 1; - end loop; - - return str(strlen downto 1); - - end to_string; - - ------------------------------------------------------------- - function to_string(src : std_logic_vector) return string is - variable str : string(src'length downto 1) := (others => '0'); - variable i : integer := 0; - - begin - for i in src'range loop - if (src(i) = '1') then - str(i+1) := '1'; - end if; - end loop; - - return str; - - end to_string; - - ------------------------------------------------------------- - -- Binary Operators - ------------------------------------------------------------- - function "sla" (src : ufixed_t; count : integer) return ufixed_t is - variable result : ufixed_t (src'high downto src'low) := (others => '0'); - - begin - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sra -count; - elsif (count < src'length) then - result(src'high downto src'low) := src(src'high-count downto src'low) & (count-1 downto 0 => '0'); - end if; - return result; - - end "sla"; - - ------------------------------------------------------------- - function "sla" (src : sfixed_t; count : integer) return sfixed_t is - variable result : sfixed_t (src'high downto src'low) := (others => '0'); - variable sign : std_logic := '0'; - - begin - sign := src(src'high); - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sra -count; - elsif (count < src'length-1) then - result(src'high downto src'low) := sign & src(src'high-count-1 downto src'low) & (count-1 downto 0 => '0'); - end if; - return result; - - end "sla"; - - ------------------------------------------------------------- - function "sra" (src : ufixed_t; count : integer) return ufixed_t is - variable result : ufixed_t (src'high downto src'low) := (others => '0'); - - begin - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sla -count; - elsif (count < src'length) then - result(src'high downto src'low) := (count-1 downto 0 => '0') & src(src'high downto src'low + count); - end if; - return result; - - end "sra"; - - ------------------------------------------------------------- - function "sra" (src : sfixed_t; count : integer) return sfixed_t is - variable result : sfixed_t (src'high downto src'low) := (others => '0'); - variable res_slv, src_slv : signed (src'length-1 downto 0) := (others => '0'); - variable sign, do_sub : std_logic := '0'; - - begin - src_slv := to_signed(src); - sign := src(src'high); - do_sub := src(src'high) and src(src'low); - if (count = 0) then - result := src; - elsif (count < 0) then - result := src sla -count; - elsif (count < src'length-1) then - res_slv := (count downto 0 => sign) & src_slv(src'length-2 downto count); - if (do_sub = '1') then - result(src'high downto src'low) := to_sfixed(res_slv+1, result); - else - result(src'high downto src'low) := to_sfixed(res_slv, result); - end if; - end if; - return result; - - end "sra"; - - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'*',b)'high downto uproto(a,'*',b)'low); - - begin - if (a'high < 0 and b'high >= 0) or (a'high >= 0 and b'high < 0) then - result := to_ufixed(to_unsigned(a) * to_unsigned(b), result) sla 1; - else - result := to_ufixed(to_unsigned(a) * to_unsigned(b), result); - end if; - return result; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'*',b)'high downto sproto(a,'*',b)'low); - - begin - if (a'high = 0 and b'high > 0) or (a'high > 0 and b'high = 0) then - result := to_sfixed(signed(a) * signed(b), result) sla 2; - else - result := to_sfixed(signed(a) * signed(b), result) sla 1; - end if; - return result; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : ufixed_t; b : sfixed_t) return sfixed_t is - - begin - return to_sfixed(a) * b; - - end "*"; - - ------------------------------------------------------------- - function "*" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return b * a; - - end "*"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'+',b)'high downto uproto(a,'+',b)'low); - - begin - result := ufixed_t(unsigned(reshape(a, result)) + unsigned(reshape(b, result))); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'+',b)'high downto sproto(a,'+',b)'low); - - begin - result := to_sfixed(signed(reshape(a,result)) + signed(reshape(b,result)), result); --- result := to_sfixed(signed(a) + signed(b), result); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : sfixed_t) return sfixed_t is - - begin - return to_sfixed(a) + b; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return b + a; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : unsigned) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) + b); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : signed) return sfixed_t is - - begin - - return sfixed_t(signed(a) + b); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : integer) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) + to_unsigned(b, a'length)); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : integer) return sfixed_t is - - begin - - return sfixed_t(signed(a) + to_signed(b, a'length)); - - end "+"; - - ------------------------------------------------------------- - function "+" (a : ufixed_t; b : std_logic) return ufixed_t is - variable result : ufixed_t (a'high downto a'low); - variable buns : unsigned(a'length-1 downto 0); - - begin - buns := (a'length-1 downto 1 => '0') & b; - result := ufixed_t(to_unsigned(a) + buns); - return result; - - end "+"; - - ------------------------------------------------------------- - function "+" (a : sfixed_t; b : std_logic) return sfixed_t is - variable result : sfixed_t (a'high downto a'low); - variable bs : signed(a'length-1 downto 0); - - begin - bs := (a'length-1 downto 1 => '0') & b; - result := sfixed_t(to_signed(a) + bs); - return result; - - end "+"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : ufixed_t) return ufixed_t is - variable result : ufixed_t (uproto(a,'-',b)'high downto uproto(a,'-',b)'low); - begin - result := to_ufixed(to_sfixed(a) - to_sfixed(b)); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : sfixed_t) return sfixed_t is - variable result : sfixed_t (sproto(a,'-',b)'high downto sproto(a,'-',b)'low); - - begin - result := to_sfixed(signed(reshape(a,result)) - signed(reshape(b,result)), result); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : sfixed_t) return sfixed_t is - begin - return to_sfixed(a) - b; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : ufixed_t) return sfixed_t is - - begin - return a - to_sfixed(b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : unsigned) return ufixed_t is - - begin - return ufixed_t(unsigned(a) - b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : signed) return sfixed_t is - - begin - return sfixed_t(signed(a) - b); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : integer) return ufixed_t is - - begin - - return ufixed_t(unsigned(a) - to_unsigned(b, a'length)); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : integer) return sfixed_t is - - begin - - return sfixed_t(signed(a) - to_signed(b, a'length)); - - end "-"; - - ------------------------------------------------------------- - function "-" (a : ufixed_t; b : std_logic) return ufixed_t is - variable result : ufixed_t (a'high downto a'low); - variable buns : unsigned(a'length-1 downto 0); - - begin - buns := (a'length-1 downto 1 => '0') & b; - result := ufixed_t(unsigned(a) - buns); - return result; - - end "-"; - - ------------------------------------------------------------- - function "-" (a : sfixed_t; b : std_logic) return sfixed_t is - variable result : sfixed_t (a'high downto a'low); - variable bs : signed(a'length-1 downto 0); - - begin - bs := (a'length-1 downto 1 => '0') & b; - result := sfixed_t(signed(a) - bs); - return result; - - end "-"; - - ------------------------------------------------------------- - -- Unary Operators - ------------------------------------------------------------- - function "abs" (src : sfixed_t) return sfixed_t is - begin - return to_sfixed(abs(signed(src)), src); - - end "abs"; - - ------------------------------------------------------------- - function "-" (src : ufixed_t) return sfixed_t is - begin - return -to_sfixed(src); - - end "-"; - - ------------------------------------------------------------- - function "-" (src : sfixed_t) return sfixed_t is - begin - return to_sfixed(-signed(src), src); - - end "-"; - - ------------------------------------------------------------- - -- Binary Equality - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) = to_unsigned(tb); - - end "="; - - ------------------------------------------------------------- - function "=" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) = to_signed(tb); - - end "="; - - ------------------------------------------------------------- - function "=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) = b; - end "="; - - ------------------------------------------------------------- - function "=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return b = a; - end "="; - - ------------------------------------------------------------- - -- Binary Inequality - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a = b); - - end "/="; - - ------------------------------------------------------------- - function "/=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a = b); - - end "/="; - - ------------------------------------------------------------- - function "/=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a = b); - end "/="; - - ------------------------------------------------------------- - function "/=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a = b); - end "/="; - - ------------------------------------------------------------- - -- Binary less than - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) < to_unsigned(tb); - - end "<"; - - ------------------------------------------------------------- - function "<" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) < to_signed(tb); - - end "<"; - - ------------------------------------------------------------- - function "<" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) < b; - - end "<"; - - ------------------------------------------------------------- - function "<" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return a < to_sfixed(b); - - end "<"; - - ------------------------------------------------------------- - -- Binary greater than - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : ufixed_t) return boolean is - variable ta, tb: ufixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_ufixed(a, ta); - tb := to_ufixed(b, tb); - return to_unsigned(ta) > to_unsigned(tb); - - end ">"; - - ------------------------------------------------------------- - function ">" (a : sfixed_t; b : sfixed_t) return boolean is - variable ta, tb: sfixed_t(max(a'high, b'high) downto min(a'low, b'low)); - begin - ta := (others => '0'); - tb := (others => '0'); - ta := to_sfixed(a, ta); - tb := to_sfixed(b, tb); - return to_signed(ta) > to_signed(tb); - - end ">"; - - ------------------------------------------------------------- - function ">" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return to_sfixed(a) > b; - end ">"; - - ------------------------------------------------------------- - function ">" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return a > to_sfixed(b); - end ">"; - - ------------------------------------------------------------- - -- Binary less equal than - ------------------------------------------------------------- - function "<=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a > b); - end "<="; - - function "<=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a > b); - end "<="; - - ------------------------------------------------------------- - -- Binary greater or equal than - ------------------------------------------------------------- - function ">=" (a : ufixed_t; b : ufixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : sfixed_t; b : sfixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : ufixed_t; b : sfixed_t) return boolean is - begin - return not (a < b); - end ">="; - - function ">=" (a : sfixed_t; b : ufixed_t) return boolean is - begin - return not (a < b); - end ">="; - - ------------------------------------------------------------- - -- Misc. Operators - ------------------------------------------------------------- - function ipart (src : ufixed_t) return ufixed_t is - begin - return src(src'high downto 0); - end ipart; - - function fpart (src : ufixed_t) return ufixed_t is - begin - return src(-1 downto src'low); - end fpart; - - function ipart (src : sfixed_t) return sfixed_t is - begin - return src(src'high-1 downto 0); - end ipart; - - function fpart (src : sfixed_t) return sfixed_t is - begin - return src(-1 downto src'low); - end fpart; - - ------------------------------------------------------------- - -- Print functions - ------------------------------------------------------------- - procedure print_info(src : in ufixed_t; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'value = B");write (L, to_string(src)); - writeline (output, L); - - write (L, prefix & "'value = ");write (L, to_real(src)); - writeline (output, L); - - -- write (L, prefix & "'cmsb = ");write (L, cmsb(src)); - -- writeline (output, L); - - -- write (L, prefix & "'clsb = ");write (L, clsb(src)); - -- writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - procedure print_info(src : in sfixed_t; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'value = B");write (L, to_string(src)); - writeline (output, L); - - write (L, prefix & "'value = ");write (L, to_real(src)); - writeline (output, L); - - -- write (L, prefix & "'cmsb = ");write (L, cmsb(src)); - -- writeline (output, L); - - -- write (L, prefix & "'clsb = ");write (L, clsb(src)); - -- writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - procedure print_info(src : in string; prefix : in string) is - variable L : line; - - begin - write (L, prefix & "'length = ");write (L, src'length); - writeline (output, L); - - write (L, prefix & "'high(left) = "); - write (L, src'high); - write (L, '('); - write (L, src'left); - write (L, ')'); - writeline (output, L); - - write (L, prefix & "'low(right) = "); - write (L, src'low); - write (L, '('); - write (L, src'right); - write (L, ')'); - writeline (output, L); - - writeline (output, L); - - end print_info; - - ------------------------------------------------------------- - -- Helpers - ------------------------------------------------------------- - -- Count significant bits for integer part - function cmsb(src : ufixed_t) return integer is - variable j, i : integer := src'high; - begin - for i in src'range loop - if src(i) = '1' then - exit; - end if; - j := j - 1; - end loop; - - -- LRM nachlesen: hier is i=src'high re-initialisert - - return j; - - end cmsb; - - ------------------------------------------------------------- - -- Count significant bits for fractional part - function clsb(src : ufixed_t) return integer is - variable j, i : integer := src'low; - begin - for i in src'reverse_range loop - if src(i) = '1' then - exit; - end if; - j := j + 1; - end loop; - - -- LRM nachlesen: hier is i=src'low re-initialisert - - return j; - - end clsb; - - ------------------------------------------------------------- - function MIN (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y < X then - res := Y; - end if; - - return res; - - end MIN; - - ------------------------------------------------------------- - function MAX (X, Y: INTEGER) return INTEGER is - variable res : integer := X; - begin - if Y > X then - res := Y; - end if; - - return res; - - end MAX; - - ------------------------------------------------------------- - function "MOD" (X, Y: in REAL ) return REAL is - -- Description: - -- See function declaration in IEEE Std 1076.2-1996 - -- Notes: - -- a) Returns 0.0 on error - - variable XNEGATIVE : BOOLEAN := X < 0.0; - variable YNEGATIVE : BOOLEAN := Y < 0.0; - variable VALUE : REAL; - begin - -- Check validity of input arguments - if (Y = 0.0) then - assert FALSE - report "MOD(X, 0.0) is undefined" - severity ERROR; - return 0.0; - end if; - - -- Compute value - if ( XNEGATIVE ) then - if ( YNEGATIVE ) then - VALUE := X + (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X + (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - end if; - else - if ( YNEGATIVE ) then - VALUE := X - (CEIL(ABS(X)/ABS(Y)))*ABS(Y); - else - VALUE := X - (FLOOR(ABS(X)/ABS(Y)))*ABS(Y); - end if; - end if; - - return VALUE; - - end "MOD"; - - ------------------------------------------------------------- - -- misc. conversion - function ipart(src : real) return real is - begin - return floor(src); - - end ipart; - - ------------------------------------------------------------- - function fpart(src : real) return real is - begin - return src - floor(src); - - end fpart; - - ------------------------------------------------------------- - function or_red (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '0'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := or_red (BUS_int (BUS_int'left downto Half)); - Lower := or_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper or Lower; - end if; - end if; - return Result; - - end function or_red; - - ------------------------------------------------------------- - function and_red (arg : STD_LOGIC_VECTOR) - return STD_LOGIC is - variable Upper, Lower : STD_LOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_LOGIC; - begin - if (arg'length < 1) then -- In the case of a NULL range - Result := '1'; - else - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := and_red (BUS_int (BUS_int'left downto Half)); - Lower := and_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper and Lower; - end if; - end if; - return Result; - - end function and_red; - - ------------------------------------------------------------- - function xor_red (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is - variable Upper, Lower : STD_ULOGIC; - variable Half : INTEGER; - variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0); - variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range - begin - if (arg'length >= 1) then - BUS_int := to_ux01 (arg); - if (BUS_int'length = 1) then - Result := BUS_int (BUS_int'left); - elsif (BUS_int'length = 2) then - Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left); - else - Half := (BUS_int'length + 1) / 2 + BUS_int'right; - Upper := xor_red (BUS_int (BUS_int'left downto Half)); - Lower := xor_red (BUS_int (Half - 1 downto BUS_int'right)); - Result := Upper xor Lower; - end if; - end if; - return Result; - - end function xor_red; - - ------------------------------------------------------------- - -- Reduction operators, same as numeric_std functions - function and_red(arg : ufixed_t) return STD_ULOGIC is - begin - return and_red (to_slv(arg)); - end function and_red; - - function nand_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not and_red (to_slv(arg)); - end function nand_red; - - function or_red(arg : ufixed_t) return STD_ULOGIC is - begin - return or_red (to_slv(arg)); - end function or_red; - - function nor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not or_red (to_slv(arg)); - end function nor_red; - - function xor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return xor_red (to_slv(arg)); - end function xor_red; - - function xnor_red(arg : ufixed_t) return STD_ULOGIC is - begin - return not xor_red (to_slv(arg)); - end function xnor_red; - - function and_red(arg : sfixed_t) return STD_ULOGIC is - begin - return and_red (to_slv(arg)); - end function and_red; - - function nand_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not and_red (to_slv(arg)); - end function nand_red; - - function or_red(arg : sfixed_t) return STD_ULOGIC is - begin - return or_red (to_slv(arg)); - end function or_red; - - function nor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not or_red (to_slv(arg)); - end function nor_red; - - function xor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return xor_red (to_slv(arg)); - end function xor_red; - - function xnor_red(arg : sfixed_t) return STD_ULOGIC is - begin - return not xor_red (to_slv(arg)); - end function xnor_red; - - ------------------------------------------------------------- - -end; -- package body fixed_ja; diff --git a/lib/jasm/cg.inc.jsm b/lib/jasm/cg.inc.jsm deleted file mode 100644 index 01c36c4..0000000 --- a/lib/jasm/cg.inc.jsm +++ /dev/null @@ -1,72 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xio-address equates for -; reg_cg_char_addr: equ 0xXX ; RW -; reg_cg_line_addr: equ 0xXX ; RW -; reg_cg_data: equ 0xXX ; RW -; reg_cg_ctrl: equ 0xXX ; WO - -; needs delay.inc.jsm - -; ------------------------------------------------- -cg_clr_line: push R0 - mov R0, 2 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -cg_clr_screen: push R0 - mov R0, 1 - xout (reg_cg_ctrl), R0 - pop R0 - ret - -; ------------------------------------------------- -; R0 : char address -; R1 : line address -cg_set_addr: call cg_wait_rdy - xout (reg_cg_line_addr), R1 - xout (reg_cg_char_addr), R0 - ret - -; ------------------------------------------------- -; R0 : character -cg_putchar: call cg_wait_rdy - xout (reg_cg_data), R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts: push R0 -cg_p_lp: movx R0, (R1) - inc R1 - tst R0 - jz ex_cgp - call cg_putchar - jmp cg_p_lp -ex_cgp: pop R0 - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_clr_puts: call cg_clr_line - call cg_puts - ret - -; ------------------------------------------------- -; R1 : ptr to string -cg_puts_clr: call cg_puts - call cg_clr_line - ret - -; ------------------------------------------------- -cg_wait_rdy: push R0 -cg_wr_lp: xin R0, (reg_hwstat) - and R0, 0x02 - jz cg_wr_lp - pop R0 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/cregs.inc.jsm b/lib/jasm/cregs.inc.jsm deleted file mode 100644 index 06d39d9..0000000 --- a/lib/jasm/cregs.inc.jsm +++ /dev/null @@ -1,7 +0,0 @@ -; JCPU On-Chip register -cpu_revision: equ 0x00 ; RO -cpu_control: equ 0x01 ; R/W -cpu_status: equ 0x02 ; RO -cpu_int_ctrl: equ 0x03 ; RW -cpu_cmem_high: equ 0x04 ; RW -cpu_stack_high: equ 0x05 ; RW diff --git a/lib/jasm/delays.inc.jsm b/lib/jasm/delays.inc.jsm deleted file mode 100644 index 6f002ee..0000000 --- a/lib/jasm/delays.inc.jsm +++ /dev/null @@ -1,64 +0,0 @@ -; ------------------------------------------------- -; Delays -; ------------------------------------------------- -delay1s: push R15 - mov R15, 10 -loop1s: call delay100ms - dec R15 - jnz loop1s - pop R15 - ret - -delay100ms: push R15 - mov R15, 10 -loop100ms: call delay10ms - dec R15 - jnz loop100ms - pop R15 - ret - -delay10ms: push R15 - mov R15, 10 -loop10ms: call delay1ms - dec R15 - jnz loop10ms - pop R15 - ret - -delay1ms: push R15 - mov R15, 10 -loop1ms: call delay100us - dec R15 - jnz loop1ms - pop R15 - ret - -delay100us: push R15 - mov R15, 10 -loop100us: call delay10us - dec R15 - jnz loop100us - pop R15 - ret - -delay10us: push R15 - mov R15, 99 -loop10us: nop - nop - nop - dec R15 - jnz loop10us - pop R15 - ret - -delay1us: push R15 - mov R15, 9 -loop1us: nop - nop - nop - dec R15 - jnz loop1us - pop R15 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/lcd.inc.jsm b/lib/jasm/lcd.inc.jsm deleted file mode 100644 index d2883fa..0000000 --- a/lib/jasm/lcd.inc.jsm +++ /dev/null @@ -1,208 +0,0 @@ -; ------------------------------------------------- -; lcd.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - lcd_port (LCD-Base) - -; needs delay.inc.jsm - -; ------------------------------------------------- -lcd_cmd: equ 0x00 -lcd_rd: equ 0x20 -lcd_data: equ 0x40 -lcd_enable: equ 0x80 - -LCD_CMD_Z1: equ 0x80 -LCD_CMD_Z2: equ 0xC0 -LCD_CMD_CLEAR: equ 0x01 - -; ------------------------------------------------- -; Init LCD -; ------------------------------------------------- -LCD_init: mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - mov R2, 0x00 - mov R0, 0x03 - call _write_lcd - call delay10ms - - mov R2, 0x00 - mov R0, 0x02 - call _write_lcd - call delay1ms - - ; 1. Function set: 4-Bit mode, two display lines - mov R0, 0x28 - call LCD_writecmd - - ; 2. Display on, no cursor - mov R0, 0x0C - call LCD_writecmd - - ; 3. Cursor shift during write - mov R0, 0x06 - call LCD_writecmd - - ; 4. Display clear - mov R0, 0x01 - call LCD_writecmd - - ret - -; ------------------------------------------------- -; LCD_waitbsy -; ------------------------------------------------- -LCD_waitbsy: push R0 -bsy_loop: call LCD_readstat - and R0, 0x80 - jz ex_bsy - call delay1us - jmp bsy_loop -ex_bsy: pop R0 - ret - -; ------------------------------------------------- -; LCD_writecmd -; ------------------------------------------------- -; R0 = cmd -LCD_writeaddr: -LCD_writecmd: push R2 - mov R2, lcd_cmd - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_putsx -; ------------------------------------------------- -; R1 = address of null-terminated string in XMEM -LCD_putsx: push R0 -putsx_loop: movx R0, (R1) - inc R1 - tst R0 - jz putsx_ex - call LCD_writechar - jmp putsx_loop -putsx_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_putsc -; ------------------------------------------------- -; R1 = address of null-terminated string in CMEM -LCD_putsc: push R0 -putsc_loop: movc R0, (R1) - inc R1 - tst R0 - jz putsc_ex - call LCD_writechar - jmp putsc_loop -putsc_ex: pop R0 - ret - -; ------------------------------------------------- -; LCD_writechar -; ------------------------------------------------- -; R0 = char -LCD_writedata: -LCD_writechar: push R2 - mov R2, lcd_data - call LCD_write - pop R2 - ret - -; ------------------------------------------------- -; LCD_write -; ------------------------------------------------- -; R0 = input -; R2 = register -LCD_write: call LCD_waitbsy - push R0 - swap R0 - call _write_lcd - pop R0 - call _write_lcd - ret - -; ------------------------------------------------- -; LCD_readstat -; ------------------------------------------------- -; R0 = status -LCD_readstat: push R2 - mov R2, lcd_cmd - call LCD_read - pop R2 - ret - -; ------------------------------------------------- -; LCD_read -; ------------------------------------------------- -; R0 = output -; R2 = register -LCD_read: call _read_lcd - swap R0 - push R0 - call _read_lcd - pop R2 - or R0, R2 - ret - -; ------------------------------------------------- -; _write -; ------------------------------------------------- -; R0 = input -_write_lcd: push R1 - - and R0, 0x0F - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - - mov R1, R0 - or R1, R2 - xout (lcd_port), R1 - call delay1us - - or R1, lcd_rd - xout (lcd_port), R1 - - pop R1 - ret - -; ------------------------------------------------- -; _read -; ------------------------------------------------- -; R0 = output -_read_lcd: push R1 - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - mov R1, lcd_rd - or R1, R2 - or R1, lcd_enable - xout (lcd_port), R1 - call delay1us - xin R0, (lcd_port) - and R0, 0x0F - - mov R1, lcd_rd - or R1, R2 - xout (lcd_port), R1 - call delay1us - - pop R1 - ret - - \ No newline at end of file diff --git a/lib/jasm/mul8x8.inc.jsm b/lib/jasm/mul8x8.inc.jsm deleted file mode 100644 index 2f66e2a..0000000 --- a/lib/jasm/mul8x8.inc.jsm +++ /dev/null @@ -1,42 +0,0 @@ -; ------------------------------------------------- -; mul8x8.inc.jsm -; ------------------------------------------------- - -; ------------------------------------------------- -; Parameter: -; R0 : operand 1 -; R1 : operand 2 -; Return: -; R0 : product low -; R1 : product high -mul8x8: push R2 - push R3 - push R4 - - mov R4, R1 - mov R1, 0 - mov R2, 0 - mov R3, 0 - -loop1: cmp R4, 0x01 - jeq ende1 - - shr R4 - jnc next1 - - add R2, R0 - addc R3, R1 - -next1: shl R0 - rolc R1 - jmp loop1 - -ende1: add R0, R2 - addc R1, R3 - - pop R4 - pop R3 - pop R2 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/uart.inc.jsm b/lib/jasm/uart.inc.jsm deleted file mode 100644 index df557b1..0000000 --- a/lib/jasm/uart.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; uart.inc.jsm -; ------------------------------------------------- -; needs xmem-address definition for -; - uart_status (Status register) -; - uart_data (Data register) - -; ------------------------------------------------- -; sout -; ------------------------------------------------- -; R0 = input -sout: push R1 -sout1: xin R1, (uart_status) - and R1, 0x02 - jnz sout1 - xout (uart_data), R0 - pop R1 - ret - -; ------------------------------------------------- -; sin -; ------------------------------------------------- -; R0 = output -sin: push R1 -sin1: xin R1, (uart_status) - and R1, 0x10 - jz sin1 - xin R0, (uart_data) - pop R1 - ret - -; ------------------------------------------------- diff --git a/lib/jasm/utils.inc.jsm b/lib/jasm/utils.inc.jsm deleted file mode 100644 index f354d7c..0000000 --- a/lib/jasm/utils.inc.jsm +++ /dev/null @@ -1,32 +0,0 @@ -; ------------------------------------------------- -; utils.inc.jsm -; ------------------------------------------------- - - -; ------------------------------------------------- -; Parameter -; R0 : Bin value in lower nibble -; Return -; R0 : Hex character representing lower nibble -nibble2hex: and R0, 0x0F - cmp R0, 0x0A - jlt isNum1 - add R0, 0x07 -isNum1: add R0, 0x30 - ret - -; ------------------------------------------------- -; Parameter -; R0 : Bin value -; Return -; R0 : Hex character high -; R1 : Hex character low -bin2hex: push R0 - call nibble2hex - mov R1, R0 - pop R0 - swap R0 - call nibble2hex - ret - -; ------------------------------------------------- diff --git a/lib/misc/debounce.vhd b/lib/misc/debounce.vhd deleted file mode 100644 index 79317a5..0000000 --- a/lib/misc/debounce.vhd +++ /dev/null @@ -1,91 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 19:34:24 10/23/05 --- Design Name: --- Module Name: debounce - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity debounce is - Generic ( ncyc_latency : integer := 100); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end debounce; - -architecture Behavioral of debounce is - -type debounce_state_t is (init_st, wait_st, rel_st); -signal debounce_cs : debounce_state_t; -signal debounce_ns : debounce_state_t; -signal count : integer range 0 to ncyc_latency; -signal input_last : std_logic; - -begin - - debounce_clk: process(rst, clk, debounce_ns, debounce_cs, input) - begin - if (rst = '1') then - count <= 0; - output <= input; - input_last <= input; - else - if rising_edge(clk) then - debounce_cs <= debounce_ns; - if (debounce_cs = wait_st) then - if (count /= 0) then - count <= count - 1; - end if; - else - count <= ncyc_latency; - if (debounce_cs = rel_st) then - output <= input; - input_last <= input; - end if; - end if; - end if; - end if; - end process; - - debounce_in: process(rst, clk, input, input_last, debounce_cs, count) - begin - debounce_ns <= debounce_cs; - case debounce_cs is - when init_st => - if (input /= input_last) then - debounce_ns <= wait_st; - end if; - when wait_st => - if (count = 0) then - debounce_ns <= rel_st; - end if; - when others => - debounce_ns <= init_st; - end case; - end process; - -end Behavioral; diff --git a/lib/misc/debounce2.vhd b/lib/misc/debounce2.vhd deleted file mode 100644 index 206a61c..0000000 --- a/lib/misc/debounce2.vhd +++ /dev/null @@ -1,142 +0,0 @@ -------------------------------------------------- --- Signal Debouncer --- Jeff Bazinet --- February 14, 2002 ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/debounce2.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - - -library ieee; -use ieee.std_logic_1164.all; -library lpm; -use lpm.lpm_components.lpm_counter; - - -entity debounce is - generic(BUFFER_WIDTH: positive:= 30; - CLOCK_DIV: positive:= 15 - ); - port( clock: in std_logic; - reset: in std_logic; - signal_in: in std_logic; - signal_out: out std_logic - ); -end entity debounce; - - -architecture rtl of debounce is - - --------------------------------------------------------------- - -- SIGNAL DECLARATION - --------------------------------------------------------------- - - -- General - signal reset_n: std_logic; - - -- SLOW CLOCK GENERATION - signal clock_reg: std_logic_vector(CLOCK_DIV-1 downto 0); - signal clock_reg_high: std_logic_vector(CLOCK_DIV-1 downto 1); - signal clock_slow: std_logic; - signal clock_slow_wire: std_logic; - - -- DATA BUFFER FILL - signal counter_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0); - signal data_buffer_reg: std_logic_vector(BUFFER_WIDTH-1 downto 0); - - -- CHECK FOR DEBOUNCE STABILITY - signal stable: std_logic; - signal stable_old: std_logic; - signal stable_state_reg:std_logic_vector(BUFFER_WIDTH-1 downto 0); - - -- PUSH BUTTON ENABLE - signal button_pushed: std_logic; - - begin - - --------------------------------------------------------------- - -- SLOW CLOCK GENERATION - --------------------------------------------------------------- - - COUNTER_1: lpm_counter - generic map (lpm_width => CLOCK_DIV) - port map ( - clock => clock, - sclr => reset_n, - cout => clock_slow_wire - ); - - process (clock) is - begin - - clock_slow <= clock_slow_wire; - - end process; - - --------------------------------------------------------------- - -- DATA BUFFER FILL - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - data_buffer_reg <= (others => '1'); - elsif rising_edge(clock_slow) then - data_buffer_reg <= data_buffer_reg(BUFFER_WIDTH-2 downto 0) & signal_in; - end if; - - end process; - - --------------------------------------------------------------- - -- CHECK FOR DEBOUNCE STABILITY - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - stable <= '0'; - stable_old <= '0'; - stable_state_reg <= (others => '0'); - elsif rising_edge(clock) then - if (data_buffer_reg = stable_state_reg) then - stable <= '1'; - stable_state_reg <= (others => '0'); - else - stable <= '0'; - end if; - stable_old <= stable; - end if; - - end process; - - --------------------------------------------------------------- - -- PUSH BUTTON ENABLE - --------------------------------------------------------------- - - process (clock) is - begin - - if (reset = '0') then - -- Initialization - button_pushed <= '0'; - elsif rising_edge(clock) then - if (stable_old = '0' and stable = '1') then - button_pushed <= '1'; - else - button_pushed <= '0'; - end if; - end if; - - end process; - - --------------------------------------------------------------- - --------------------------------------------------------------- - - signal_out <= button_pushed; - reset_n <= not reset; - -end rtl; diff --git a/lib/misc/dpram_1w1r.vhd b/lib/misc/dpram_1w1r.vhd deleted file mode 100644 index dee0972..0000000 --- a/lib/misc/dpram_1w1r.vhd +++ /dev/null @@ -1,79 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram_1w1r is - Generic ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_1w1r; - -architecture Behavioral of dpram_1w1r is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - -begin - -process (clka) -begin -if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; -end if; -end process; - -process (clkb) -begin -if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/dpram_1w1r_dist.vhd b/lib/misc/dpram_1w1r_dist.vhd deleted file mode 100644 index e07555c..0000000 --- a/lib/misc/dpram_1w1r_dist.vhd +++ /dev/null @@ -1,84 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_1w1r_dist.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.NUMERIC_STD.ALL; - -entity dpram_1w1r_dist is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clka : in STD_LOGIC; - clkb : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_1w1r_dist; - -architecture Behavioral of dpram_1w1r_dist is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - signal RAM : RAMtype; - - attribute ram_style : string; - attribute ram_style of RAM: signal is "distributed"; - -begin - -process (clka) - begin - if clka'event and clka = '1' then - if en_a = '1' then - if we_a = '1' then - RAM(to_integer(addr_a)) <= din_a; - end if; - end if; - end if; -end process; - -process (clkb) - begin - if clkb'event and clkb = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - end if; - end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/dpram_2w2r.vhd b/lib/misc/dpram_2w2r.vhd deleted file mode 100644 index 33152f3..0000000 --- a/lib/misc/dpram_2w2r.vhd +++ /dev/null @@ -1,88 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -entity dpram_2w2r is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_2w2r; - -architecture Behavioral of dpram_2w2r is - - constant depth : integer := 2**addr_width; - type RAMtype is array (0 to depth-1) of unsigned (data_width-1 downto 0); - shared variable RAM : RAMtype; - -begin - -process (clk_a) -begin -if clk_a'event and clk_a = '1' then - if en_a = '1' then - dout_a <= RAM(to_integer(addr_a)); - if we_a = '1' then - RAM(to_integer(addr_a)) := din_a; - end if; - end if; -end if; -end process; - -process (clk_b) -begin -if clk_b'event and clk_b = '1' then - if en_b = '1' then - dout_b <= RAM(to_integer(addr_b)); - if we_b = '1' then - RAM(to_integer(addr_b)) := din_b; - end if; - end if; -end if; -end process; - - -end Behavioral; - diff --git a/lib/misc/dpram_2w2r_virtex4.vhd b/lib/misc/dpram_2w2r_virtex4.vhd deleted file mode 100644 index 6d8bc83..0000000 --- a/lib/misc/dpram_2w2r_virtex4.vhd +++ /dev/null @@ -1,211 +0,0 @@ -------------------------------------------------------------------------- --- Project: JCPU, a portable 8-bit RISC CPU written in VHDL --- This file: Dual-ported register file with asynchrous read - --- Copyright (C) 2007 J. Ahrensfeld - --- This library is free software; you can redistribute it and/or --- modify it under the terms of the GNU Lesser General Public --- License as published by the Free Software Foundation; either --- version 2.1 of the License, or (at your option) any later version. - --- This library is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --- Lesser General Public License for more details. - --- You should have received a copy of the GNU Lesser General Public --- License along with this library; if not, write to the Free Software --- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA - --- For questions and ideas, please contact the author at jens@jayfield.org - ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r_virtex4.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.numeric_std.ALL; - -library UNISIM; -use UNISIM.vcomponents.all; - -entity dpram_2w2r is - Generic - ( - addr_width : integer := 3; - data_width : integer := 8 - ); - Port - ( - clk_a : in STD_LOGIC; - clk_b : in STD_LOGIC; - en_a : in STD_LOGIC; - en_b : in STD_LOGIC; - we_a : in STD_LOGIC; - we_b : in STD_LOGIC; - addr_a : in unsigned (addr_width-1 downto 0); - addr_b : in unsigned (addr_width-1 downto 0); - din_a : in unsigned (data_width-1 downto 0); - din_b : in unsigned (data_width-1 downto 0); - dout_a : out unsigned (data_width-1 downto 0); - dout_b : out unsigned (data_width-1 downto 0) - ); -end dpram_2w2r; - -architecture Structure of dpram_2w2r is - - signal do_a : std_logic_vector(31 downto 0); - signal do_b : std_logic_vector(31 downto 0); - signal di_a : std_logic_vector(31 downto 0); - signal di_b : std_logic_vector(31 downto 0); - signal ad_a : std_logic_vector(14 downto 0); - signal ad_b : std_logic_vector(14 downto 0); - signal wr_a : std_logic_vector(3 downto 0); - signal wr_b : std_logic_vector(3 downto 0); - -begin - --- RAMB16: 16k+2k Parity Paramatizable block RAM --- Virtex-4 --- Xilinx HDL Libraries Guide, version 9.1i -RAMB16_inst : RAMB16 -generic map -( - DOA_REG => 0, -- Optional output registers on the A port (0 or 1) - DOB_REG => 0, -- Optional output registers on the B port (0 or 1) - INIT_A => X"000000000", -- Initial values on A output port - INIT_B => X"000000000", -- Initial values on B output port - INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE) - INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE) - RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded - RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded - READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36 - READ_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36 - SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY", - - -- "GENERATE_X_ONLY" or "NONE" - SRVAL_A => X"000000000", -- Port A output value upon SSR assertion - SRVAL_B => X"000000000", -- Port B output value upon SSR assertion - WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE - WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36 - WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36 - - -- The following INIT_xx declarations specify the initial contents of the RAM - INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000", - INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000", - - -- The next set of INITP_xx are for the parity bits - INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", - INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000" -) -port map -( - CASCADEOUTA => open, -- 1-bit cascade output - CASCADEOUTB => open, -- 1-bit cascade output - DOA => do_a, -- 32-bit A port Data Output - DOB => do_b, -- 32-bit B port Data Output - DOPA => open, -- 4-bit A port Parity Output - DOPB => open, -- 4-bit B port Parity Output - ADDRA => ad_a, -- 15-bit A Port Address Input - ADDRB => ad_b, -- 15-bit B Port Address Input - CASCADEINA => '0', -- 1-bit cascade A input - CASCADEINB => '0', -- 1-bit cascade B input - CLKA => clk_a, -- Port A Clock - CLKB => clk_b, -- Port B Clock - DIA => di_a, -- 32-bit A port Data Input - DIB => di_b, -- 32-bit B port Data Input - DIPA => "0000", -- 4-bit A port parity Input - DIPB => "0000", -- 4-bit B port parity Input - ENA => en_a, -- 1-bit A port Enable Input - ENB => en_b, -- 1-bit B port Enable Input - REGCEA => '0', -- 1-bit A port register enable input - REGCEB => '0', -- 1-bit B port register enable input - SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input - SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input - WEA => wr_a, -- 4-bit A port Write Enable Input - WEB => wr_b -- 4-bit B port Write Enable Input -); --- End of RAMB16_inst instantiation - - dout_a <= unsigned(do_a(7 downto 0)); - dout_b <= unsigned(do_b(7 downto 0)); - di_a <= X"000000" & std_logic_vector(din_a); - di_b <= X"000000" & std_logic_vector(din_b); - ad_a <= '0' & std_logic_vector(addr_a) & "000"; - ad_b <= '0' & std_logic_vector(addr_b) & "000"; - wr_a <= (3 downto 0 => we_a); - wr_b <= (3 downto 0 => we_b); - -end Structure; - diff --git a/lib/misc/lcd_port.vhd b/lib/misc/lcd_port.vhd deleted file mode 100644 index 11f97eb..0000000 --- a/lib/misc/lcd_port.vhd +++ /dev/null @@ -1,69 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - - ------------------------------------------------------------------ -entity lcd_port is - Port ( - rst : in std_logic; - clk : in std_logic; - we : in std_logic; - din : in unsigned(7 downto 0); - dout : out unsigned(7 downto 0); - lcd_d : inout unsigned(3 downto 0); - lcd_e : out std_logic; - lcd_rs : out std_logic; - lcd_rw : out std_logic - ); - end lcd_port; - -architecture Behavioral of lcd_port is - - constant clcd_e : integer := 7; - constant clcd_rs : integer := 6; - constant clcd_rw : integer := 5; - - type lcd_t is record - d : unsigned(3 downto 0); - e : std_logic; - rs : std_logic; - rw : std_logic; - end record; - - ------------------------------------------------------------------ - begin - - proc_lcd_port: - process(rst, clk) - variable vlcd : lcd_t; - begin - if (rst = '1') then - dout <= (others => '0'); - vlcd.d := (others => '0'); - vlcd.e := '0'; - vlcd.rw := '1'; - vlcd.rs := '0'; - elsif rising_edge(clk) then - dout <= unsigned("0000" & lcd_d); - if we = '1' then - vlcd.d := din(3 downto 0); - vlcd.e := din(clcd_e); - vlcd.rs := din(clcd_rs); - vlcd.rw := din(clcd_rw); - end if; - end if; - if vlcd.rw = '0' then - lcd_d <= unsigned(vlcd.d); - else - lcd_d <= (others => 'Z'); - end if; - lcd_e <= vlcd.e; - lcd_rs <= vlcd.rs; - lcd_rw <= vlcd.rw; - end process; - ------------------------------------------------------------------ - -end Behavioral; diff --git a/lib/misc/oneshot.vhd b/lib/misc/oneshot.vhd deleted file mode 100644 index 2f5d8bd..0000000 --- a/lib/misc/oneshot.vhd +++ /dev/null @@ -1,223 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:52:19 10/22/05 --- Design Name: --- Module Name: oneshot - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/oneshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ --- Component Template --- --- COMPONENT oneshot --- GENERIC (mode : integer); --- PORT( --- rst : IN std_logic; --- clk : IN std_logic; --- input : IN std_logic; --- output : OUT std_logic --- ); --- END COMPONENT; --- --- Instantation Template --- --- oneshot_int: oneshot --- GENERIC MAP ( --- mode => 1) --- PORT MAP( --- rst => , --- clk => , --- input => , --- output => --- ); --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity oneshot is - Generic ( mode : integer range 0 to 2 := 1); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end oneshot; - -architecture Behavioral of oneshot is - -type shot_state_t is (shot_pos_st, shot_neg_st, release_pos_st, release_neg_st); - -signal shot_cs : shot_state_t; -signal shot_ns : shot_state_t; - -begin - -mode_0: -if mode = 0 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when release_pos_st => - if (input = '0') then - shot_ns <= shot_neg_st; - end if; - when shot_neg_st => - shot_ns <= release_neg_st; - when release_neg_st => - if (input = '1') then - shot_ns <= release_pos_st; - end if; - when others => null; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - -mode_1: -if mode = 1 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when shot_pos_st => - shot_ns <= release_pos_st; - when release_pos_st => - if (input = '0') then - shot_ns <= release_neg_st; - end if; - when release_neg_st => - if (input = '1') then - shot_ns <= shot_pos_st; - end if; - when others => null; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - -mode_2: -if mode = 2 generate -begin - shot_clk: process(rst, clk, shot_ns, input) - begin - if (rst = '1') then - if (input = '1') then - shot_cs <= release_pos_st; - else - shot_cs <= release_neg_st; - end if; - else - if rising_edge(clk) then - shot_cs <= shot_ns; - end if; - end if; - end process; - - shot_in: process(rst, clk, input, shot_cs) - begin - shot_ns <= shot_cs; - case shot_cs is - when shot_pos_st => - shot_ns <= release_pos_st; - when release_pos_st => - if (input = '0') then - shot_ns <= shot_neg_st; - end if; - when shot_neg_st => - shot_ns <= release_neg_st; - when release_neg_st => - if (input = '1') then - shot_ns <= shot_pos_st; - end if; - end case; - end process; - - shot_out: process(shot_cs) - begin - output <= '0'; - case shot_cs is - when shot_pos_st => - output <= '1'; - when shot_neg_st => - output <= '1'; - when others => null; - end case; - end process; -end generate; - - - -end Behavioral; diff --git a/lib/misc/singleshot.vhd b/lib/misc/singleshot.vhd deleted file mode 100644 index 25f7013..0000000 --- a/lib/misc/singleshot.vhd +++ /dev/null @@ -1,155 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 21:52:19 10/22/05 --- Design Name: --- Module Name: singleshot - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/singleshot.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ --- Component Template --- --- COMPONENT singleshot --- GENERIC (mode : integer); --- PORT( --- rst : IN std_logic; --- clk : IN std_logic; --- input : IN std_logic; --- output : OUT std_logic --- ); --- END COMPONENT; --- --- Instantation Template --- --- singleshot_int: oneshot --- GENERIC MAP ( --- mode => 1) --- PORT MAP( --- rst => , --- clk => , --- input => , --- output => --- ); --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; - -entity singleshot is - Generic ( mode : integer range 0 to 2 := 1); - Port ( rst : in std_logic; - clk : in std_logic; - input : in std_logic; - output : out std_logic); -end singleshot; - -architecture Behavioral of singleshot is - -type s_t is (idle, shot_in, active, shot_out); -signal s, sn : s_t; - -begin - -process (rst, clk, sn) -begin - if rising_edge(clk) then - if rst = '1' then - s <= idle; - else - s <= sn; - end if; - end if; -end process; - -mode_1: -if mode = 1 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - output <= '1'; - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - sn <= idle; - when others => null; - end case; - end process; -end generate; - -mode_0: -if mode = 0 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - output <= '1'; - sn <= idle; - when others => null; - end case; - end process; -end generate; - -mode_2: -if mode = 2 generate -begin - process (input, s) - begin - output <= '0'; - sn <= s; - case s is - when idle => - if input = '1' then - sn <= shot_in; - end if; - when shot_in => - output <= '1'; - sn <= active; - when active => - if input = '0' then - sn <= shot_out; - end if; - when shot_out => - output <= '1'; - sn <= idle; - when others => null; - end case; - end process; -end generate; - -end Behavioral; diff --git a/lib/misc/tb_template.vhd b/lib/misc/tb_template.vhd deleted file mode 100644 index f96f294..0000000 --- a/lib/misc/tb_template.vhd +++ /dev/null @@ -1,63 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/tb_template.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.MATH_REAL.ALL; -USE IEEE.NUMERIC_STD.ALL; -USE STD.TEXTIO.ALL; - --- LIBRARY WORK; --- USE.YOURLIB.WHATELSE - -ENTITY tb_template IS -END tb_template; - -ARCHITECTURE behavior OF tb_template IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT your_comp - GENERIC - ( - ); - PORT - ( - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - --Inputs - signal clk : STD_LOGIC := '0'; - - --Outputs - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: your_comp - GENERIC MAP - ( - ) - PORT MAP - ( - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - - assert false report "Test finished" severity error; - wait; - - END PROCESS; - -END tb_template; diff --git a/lib/misc/utils_pkg.vhd b/lib/misc/utils_pkg.vhd deleted file mode 100644 index 2fcaec6..0000000 --- a/lib/misc/utils_pkg.vhd +++ /dev/null @@ -1,63 +0,0 @@ ------------------------------------------------------------------------ --- $Header: /tmp/cvsroot/VHDL/lib/misc/utils_pkg.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $ ------------------------------------------------------------------------ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.NUMERIC_STD.ALL; -use IEEE.MATH_REAL.ALL; - -package utils_pkg is - - -- Constants - - -- Functions - function NextPowerOfTwo(x : natural) return natural; - function NextExpBaseTwo(x : natural) return natural; - function GCD(a, b : natural) return natural; - function LCM(a, b : natural) return natural; - -end utils_pkg; - - -package body utils_pkg is - - function NextExpBaseTwo(x : natural) return natural is - begin - return natural(ceil(log2(real(x)))); - end NextExpBaseTwo; - - function NextPowerOfTwo(x : natural) return natural is - begin - - return 2**NextExpBaseTwo(x); - end NextPowerOfTwo; - - function GCD(a, b : natural) return natural is - variable aa : natural; - variable bb : natural; - begin - aa := a; - bb := b; - while bb /= 0 loop - if aa > bb then - aa := aa - bb; - else - bb := bb - aa; - end if; - end loop; - - return aa; - - end GCD; - - function LCM(a, b : natural) return natural is - begin - - return (a * b)/GCD(a, b); - - end LCM; - -end utils_pkg; - - diff --git a/lib/radio/mix/sim/tb_mix_cpx.fdo b/lib/radio/mix/sim/tb_mix_cpx.fdo deleted file mode 100644 index 14d9422..0000000 --- a/lib/radio/mix/sim/tb_mix_cpx.fdo +++ /dev/null @@ -1,13 +0,0 @@ -vlib work -vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/mix_pkg.vhd" -vcom -explicit -93 "../src/mix_cpx.vhd" -vcom -explicit -93 "../src/tb_mix_cpx.vhd" -vsim -t 1ps -lib work tb_mix_cpx -do {tb_mix_cpx.wdo} -view wave -view structure -view signals -run 500ns diff --git a/lib/radio/mix/sim/tb_mix_cpx.wdo b/lib/radio/mix/sim/tb_mix_cpx.wdo deleted file mode 100644 index c84c651..0000000 --- a/lib/radio/mix/sim/tb_mix_cpx.wdo +++ /dev/null @@ -1,42 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mix_cpx/clk -add wave -noupdate -format Logic /tb_mix_cpx/srst -add wave -noupdate -divider {Fixed In} -add wave -noupdate -format Logic /tb_mix_cpx/in_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_re_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/x_im_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_re_in -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/y_im_in -add wave -noupdate -divider {Fixed OUT} -add wave -noupdate -format Logic /tb_mix_cpx/out_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_re_out -add wave -noupdate -format Literal -radix decimal /tb_mix_cpx/z_im_out -add wave -noupdate -divider {Convenient real out} -add wave -noupdate -format Literal /tb_mix_cpx/x_re -add wave -noupdate -format Literal /tb_mix_cpx/x_im -add wave -noupdate -format Literal /tb_mix_cpx/y_re -add wave -noupdate -format Literal /tb_mix_cpx/y_im -add wave -noupdate -format Literal /tb_mix_cpx/z_re -add wave -noupdate -format Literal /tb_mix_cpx/z_im -add wave -noupdate -format Logic /tb_mix_cpx/fileout_enable -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_left -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_re_right -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_left -add wave -noupdate -format Literal /tb_mix_cpx/uut/p_im_right -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {90000 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {348406 ps} diff --git a/lib/radio/mix/sim/tb_mix_real.fdo b/lib/radio/mix/sim/tb_mix_real.fdo deleted file mode 100644 index cbf7dd0..0000000 --- a/lib/radio/mix/sim/tb_mix_real.fdo +++ /dev/null @@ -1,13 +0,0 @@ -vlib work -vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/mix_pkg.vhd" -vcom -explicit -93 "../src/mix_real.vhd" -vcom -explicit -93 "../src/tb_mix_real.vhd" -vsim -t 1ps -lib work tb_mix_real -do {tb_mix_real.wdo} -view wave -view structure -view signals -run 500ns diff --git a/lib/radio/mix/sim/tb_mix_real.wdo b/lib/radio/mix/sim/tb_mix_real.wdo deleted file mode 100644 index 6643ce3..0000000 --- a/lib/radio/mix/sim/tb_mix_real.wdo +++ /dev/null @@ -1,36 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_mix_real/clk -add wave -noupdate -format Logic /tb_mix_real/srst -add wave -noupdate -divider {Fixed In} -add wave -noupdate -format Logic /tb_mix_real/in_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_real/x_re_din -add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_re_din -add wave -noupdate -format Literal -radix decimal /tb_mix_real/y_im_din -add wave -noupdate -divider {Fixed OUT} -add wave -noupdate -format Logic /tb_mix_real/out_valid -add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_re_dout -add wave -noupdate -format Literal -radix decimal /tb_mix_real/z_im_dout -add wave -noupdate -divider {Convenient real out} -add wave -noupdate -format Literal /tb_mix_real/x_re -add wave -noupdate -format Literal /tb_mix_real/y_re -add wave -noupdate -format Literal /tb_mix_real/y_im -add wave -noupdate -format Literal /tb_mix_real/z_re -add wave -noupdate -format Literal /tb_mix_real/z_im -add wave -noupdate -format Logic /tb_mix_real/fileout_enable -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {120000 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {0 ps} {348406 ps} diff --git a/lib/radio/mix/sim/tb_undc_real.fdo b/lib/radio/mix/sim/tb_undc_real.fdo deleted file mode 100644 index f7d989f..0000000 --- a/lib/radio/mix/sim/tb_undc_real.fdo +++ /dev/null @@ -1,13 +0,0 @@ -vlib work -vcom -explicit -93 "../../../../lib/fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../../lib/PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/mix_pkg.vhd" -vcom -explicit -93 "../src/undc_real.vhd" -vcom -explicit -93 "../src/tb_undc_real.vhd" -vsim -t 1ps -lib work tb_undc_real -do {tb_undc_real.wdo} -view wave -view structure -view signals -run 500us diff --git a/lib/radio/mix/sim/tb_undc_real.wdo b/lib/radio/mix/sim/tb_undc_real.wdo deleted file mode 100644 index f965905..0000000 --- a/lib/radio/mix/sim/tb_undc_real.wdo +++ /dev/null @@ -1,38 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_undc_real/clk -add wave -noupdate -format Logic /tb_undc_real/srst -add wave -noupdate -format Logic /tb_undc_real/din_valid -add wave -noupdate -format Logic /tb_undc_real/kin_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/din -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/kin -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dout -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/dc_out -add wave -noupdate -format Logic /tb_undc_real/dout_valid -add wave -noupdate -format Literal /tb_undc_real/k -add wave -noupdate -format Literal /tb_undc_real/x -add wave -noupdate -format Literal /tb_undc_real/y -add wave -noupdate -format Literal /tb_undc_real/dc -add wave -noupdate -divider UUT -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/k -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/x -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y1 -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/y2 -add wave -noupdate -format Literal -radix hexadecimal /tb_undc_real/uut/dc -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {97905405 ps} 0} -configure wave -namecolwidth 150 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 100 -configure wave -griddelta 40 -configure wave -timeline 1 -update -WaveRestoreZoom {0 ps} {157500 ns} diff --git a/lib/radio/mix/src/mix_cpx.vhd b/lib/radio/mix/src/mix_cpx.vhd deleted file mode 100644 index f77a312..0000000 --- a/lib/radio/mix/src/mix_cpx.vhd +++ /dev/null @@ -1,166 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.mix_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity mix_cpx is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - nbits_scale_z : integer := 0; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_in : in sfixed; - x_im_in : in sfixed; - y_re_in : in sfixed; - y_im_in : in sfixed; - out_valid : out std_logic; - z_re_out : out sfixed; - z_im_out : out sfixed -); -end mix_cpx; - -architecture Behavioral of mix_cpx is -constant nbits_prod : integer := nbits_out + nbits_scale_z; -constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z; - -signal x_re, x_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal p_re_left, p_re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal p_im_left, p_im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg: process(srst, clk, in_valid, x_re_in, x_im_in, y_re_in, y_im_in) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x_re <= to_sfixed(0, x_re); - x_im <= to_sfixed(0, x_im); - y_re <= to_sfixed(0, y_re); - y_im <= to_sfixed(0, y_im); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - x_re <= x_re_in; - x_im <= x_im_in; - y_re <= y_re_in; - y_im <= y_im_in; - end if; - end if; - end if; - else - x_re <= x_re_in; - x_im <= x_im_in; - y_re <= y_re_in; - y_im <= y_im_in; - valid <= in_valid; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, x_re, x_im, y_re, y_im) - variable re_left, re_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low); - variable im_left, im_right : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_out, nbits_prod_frac)'low); - - begin - re_left := resize(x_re * y_re, re_left); - re_right := resize(x_im * y_im, re_right); - im_left := resize(x_re * y_im, im_left); - im_right := resize(x_im * y_re, im_right); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - p_re_left <= to_sfixed(0, p_re_left); - p_re_right <= to_sfixed(0, p_re_right); - p_im_left <= to_sfixed(0, p_im_left); - p_im_right <= to_sfixed(0, p_im_right); - p_valid <= '0'; - else - p_re_left <= re_left; - p_re_right <= re_right; - p_im_left <= im_left; - p_im_right <= im_right; - p_valid <= valid; - end if; - end if; - else - p_re_left <= re_left; - p_re_right <= re_right; - p_im_left <= im_left; - p_im_right <= im_right; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, p_re_left, p_re_right, p_im_left, p_im_right) - variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - sum_re := resize(scalb(p_re_left - p_re_right, nbits_scale_z), re, rounding, saturating); - sum_im := resize(scalb(p_im_left + p_im_right, nbits_scale_z), im, rounding, saturating); - if has_out_reg = true then - if rising_edge(clk) then - if srst = '1' then - z_re_out <= to_sfixed(0, re); - z_im_out <= to_sfixed(0, im); - out_valid <= '0'; - else - z_re_out <= sum_re; - z_im_out <= sum_im; - out_valid <= p_valid; - end if; - end if; - else - z_re_out <= re; - z_im_out <= im; - out_valid <= p_valid; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/mix/src/mix_pkg.vhd b/lib/radio/mix/src/mix_pkg.vhd deleted file mode 100644 index 9e6dcbf..0000000 --- a/lib/radio/mix/src/mix_pkg.vhd +++ /dev/null @@ -1,62 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use work.fixed_pkg.all; - -package mix_pkg is - - ------------------------------------------------------------- - -- Constructor helpers - -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range); - function uproto (nbits : integer; nbits_frac : integer) return ufixed; - - -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range); - function sproto (nbits : integer; nbits_frac : integer) return sfixed; - - function to_unsigned (src : ufixed) return UNSIGNED; - function to_signed (src : sfixed) return SIGNED; - -------------------------------------------------------------------------------- -end; -- package mix_cpx_pkg; - -package body mix_pkg is - - ------------------------------------------------------------- - -- Constuctor helpers - function uproto (nbits : integer; nbits_frac : integer) return ufixed is - constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0'); - begin - return result(nbits-nbits_frac-1 downto -nbits_frac); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_frac : integer) return sfixed is - constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0'); - begin - return result(nbits-nbits_frac downto -nbits_frac+1); - end sproto; - - ------------------------------------------------------------- - function to_unsigned (src : ufixed) return UNSIGNED is - subtype t is UNSIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return UNSIGNED(to_X01(std_logic_vector(slv))); - - end function to_unsigned; - - ------------------------------------------------------------- - function to_signed (src : sfixed) return SIGNED is - subtype t is SIGNED(src'high - src'low downto 0); - variable slv : t; - begin - slv := t(src); - return SIGNED(to_X01(std_logic_vector(slv))); - - end function to_signed; - - -------------------------------------------------------------------------------- -end; -- package mix_pkg; diff --git a/lib/radio/mix/src/mix_real.vhd b/lib/radio/mix/src/mix_real.vhd deleted file mode 100644 index 3dfe3cc..0000000 --- a/lib/radio/mix/src/mix_real.vhd +++ /dev/null @@ -1,155 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.mix_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity mix_real is -Generic -( - nbits_in : integer := 12; - nbits_in_frac : integer := 12; - nbits_out : integer := 12; - nbits_out_frac : integer := 12; - nbits_scale_z : integer := 0; - has_in_reg : boolean := false; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_din : in sfixed; - y_re_din : in sfixed; - y_im_din : in sfixed; - out_valid : out std_logic; - z_re_dout : out sfixed; - z_im_dout : out sfixed -); -end mix_real; - -architecture Behavioral of mix_real is - -constant nbits_prod : integer := nbits_out + nbits_scale_z; -constant nbits_prod_frac : integer := nbits_out_frac + nbits_scale_z; - -signal x_re : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal y_re, y_im : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); -signal p_re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal p_im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); -signal valid, p_valid : std_logic; ------------------------------------------------------------- -begin - - ------------------------------------------------------------- - proc_in_reg: process(srst, clk, in_valid, x_re_din, y_re_din, y_im_din) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x_re <= to_sfixed(0, x_re); - y_re <= to_sfixed(0, y_re); - y_im <= to_sfixed(0, y_im); - valid <= '0'; - else - valid <= in_valid; - if in_valid = '1' then - x_re <= x_re_din; - y_re <= y_re_din; - y_im <= y_im_din; - end if; - end if; - end if; - else - x_re <= x_re_din; - y_re <= y_re_din; - y_im <= y_im_din; - valid <= in_valid; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(srst, clk, valid, x_re, y_re, y_im) - variable re_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); - variable im_left : sfixed(sproto(nbits_prod, nbits_prod_frac)'high downto sproto(nbits_prod, nbits_prod_frac)'low); - - begin - re_left := resize(x_re * y_re, re_left); - im_left := resize(x_re * y_im, im_left); - if has_pipe_reg = true then - if rising_edge(clk) then - if srst = '1' then - p_re_left <= to_sfixed(0, p_re_left); - p_im_left <= to_sfixed(0, p_im_left); - p_valid <= '0'; - else - p_re_left <= re_left; - p_im_left <= im_left; - p_valid <= valid; - end if; - end if; - else - p_re_left <= re_left; - p_im_left <= im_left; - p_valid <= valid; - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(srst, clk, p_valid, p_re_left, p_im_left) - variable re, im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_re : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - variable sum_im : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - begin - sum_re := resize(scalb(p_re_left, nbits_scale_z), re, rounding, saturating); - sum_im := resize(scalb(p_im_left, nbits_scale_z), im, rounding, saturating); - if has_out_reg = true then - if rising_edge(clk) then - if srst = '1' then - z_re_dout <= to_sfixed(0, re); - z_im_dout <= to_sfixed(0, im); - out_valid <= '0'; - else - z_re_dout <= sum_re; - z_im_dout <= sum_im; - out_valid <= p_valid; - end if; - end if; - else - z_re_dout <= re; - z_im_dout <= im; - out_valid <= p_valid; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/mix/src/tb_mix_cpx.vhd b/lib/radio/mix/src/tb_mix_cpx.vhd deleted file mode 100644 index 7882185..0000000 --- a/lib/radio/mix/src/tb_mix_cpx.vhd +++ /dev/null @@ -1,208 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.mix_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_mix_cpx IS - Generic ( - nbits_in : integer := 24; - nbits_in_frac : integer := 24; - nbits_out : integer := 24; - nbits_out_frac : integer := 24; - nbits_scale_z : integer := 0; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_mix_cpx; - -ARCHITECTURE behavior OF tb_mix_cpx IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix_cpx - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - nbits_scale_z : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_in : in sfixed; - x_im_in : in sfixed; - y_re_in : in sfixed; - y_im_in : in sfixed; - out_valid : out std_logic; - z_re_out : out sfixed; - z_im_out : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL x_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_re_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_im_in : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL z_re_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL z_im_out : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL out_valid : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - SIGNAL x_re : real := 0.0; - SIGNAL x_im : real := 0.0; - SIGNAL y_re : real := 0.0; - SIGNAL y_im : real := 0.0; - SIGNAL z_re : real := 0.0; - SIGNAL z_im : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: mix_cpx - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_scale_z => nbits_scale_z, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_re_in => x_re_in, - x_im_in => x_im_in, - y_re_in => y_re_in, - y_im_in => y_im_in, - out_valid => out_valid, - z_re_out => z_re_out, - z_im_out => z_im_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.5, x_re_in); - x_im_in <= to_sfixed(0.5, x_im_in); - y_re_in <= to_sfixed(0.5, y_re_in); - y_im_in <= to_sfixed(0.5, y_im_in); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(-0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.125, x_re_in); - x_im_in <= to_sfixed(-0.25, x_im_in); - y_re_in <= to_sfixed(0.25, y_re_in); - y_im_in <= to_sfixed(0.125, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.3, x_re_in); - x_im_in <= to_sfixed(0.0, x_im_in); - y_re_in <= to_sfixed(-0.5, y_re_in); - y_im_in <= to_sfixed(0.5, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_in <= to_sfixed(0.0, x_re_in); - x_im_in <= to_sfixed(-0.7071, x_im_in); - y_re_in <= to_sfixed(0.0, y_re_in); - y_im_in <= to_sfixed(-0.7071, y_im_in); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - x_re <= to_real(x_re_in); - x_im <= to_real(x_im_in); - y_re <= to_real(y_re_in); - y_im <= to_real(y_im_in); - z_re <= to_real(z_re_out); - z_im <= to_real(z_im_out); - -END; diff --git a/lib/radio/mix/src/tb_mix_real.vhd b/lib/radio/mix/src/tb_mix_real.vhd deleted file mode 100644 index a9e458e..0000000 --- a/lib/radio/mix/src/tb_mix_real.vhd +++ /dev/null @@ -1,197 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.mix_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_mix_real IS - Generic ( - nbits_in : integer := 24; - nbits_in_frac : integer := 24; - nbits_out : integer := 24; - nbits_out_frac : integer := 24; - nbits_scale_z : integer := 0; - has_in_reg : boolean := true; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_mix_real; - -ARCHITECTURE behavior OF tb_mix_real IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT mix_real - GENERIC - ( - nbits_in : integer; - nbits_in_frac : integer; - nbits_out : integer; - nbits_out_frac : integer; - nbits_scale_z : integer; - has_in_reg : boolean; - has_pipe_reg : boolean; - has_out_reg : boolean; - rounding : boolean; - saturating : boolean - ); - PORT - ( - srst : in std_logic; - clk : in std_logic; - in_valid : in std_logic; - x_re_din : in sfixed; - y_re_din : in sfixed; - y_im_din : in sfixed; - out_valid : out std_logic; - z_re_dout : out sfixed; - z_im_dout : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL in_valid : std_logic := '0'; - SIGNAL x_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_re_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - SIGNAL y_im_din : sfixed(sproto(nbits_in, nbits_in_frac)'high downto sproto(nbits_in, nbits_in_frac)'low); - - --Outputs - SIGNAL z_re_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL z_im_dout : sfixed(sproto(nbits_out, nbits_out_frac)'high downto sproto(nbits_out, nbits_out_frac)'low); - SIGNAL out_valid : std_logic; - - SIGNAL fileout_enable : std_logic := '0'; - SIGNAL x_re : real := 0.0; - SIGNAL y_re : real := 0.0; - SIGNAL y_im : real := 0.0; - SIGNAL z_re : real := 0.0; - SIGNAL z_im : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: mix_real - GENERIC MAP - ( - nbits_in => nbits_in, - nbits_in_frac => nbits_in_frac, - nbits_out => nbits_out, - nbits_out_frac => nbits_out_frac, - nbits_scale_z => nbits_scale_z, - has_in_reg => has_in_reg, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - in_valid => in_valid, - x_re_din => x_re_din, - y_re_din => y_re_din, - y_im_din => y_im_din, - out_valid => out_valid, - z_re_dout => z_re_dout, - z_im_dout => z_im_dout - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.5, x_re_din); - y_re_din <= to_sfixed(0.5, y_re_din); - y_im_din <= to_sfixed(0.5, y_im_din); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - wait until rising_edge(clk); - in_valid <= '0'; - wait for 5*PERIOD; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.125, x_re_din); - y_re_din <= to_sfixed(0.25, y_re_din); - y_im_din <= to_sfixed(0.125, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.3, x_re_din); - y_re_din <= to_sfixed(-0.5, y_re_din); - y_im_din <= to_sfixed(0.5, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - x_re_din <= to_sfixed(0.0, x_re_din); - y_re_din <= to_sfixed(0.0, y_re_din); - y_im_din <= to_sfixed(-0.7071, y_im_din); - in_valid <= '1'; - ------------------------------------------ - wait until rising_edge(clk); - in_valid <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - x_re <= to_real(x_re_din); - y_re <= to_real(y_re_din); - y_im <= to_real(y_im_din); - z_re <= to_real(z_re_dout); - z_im <= to_real(z_im_dout); - -END; diff --git a/lib/radio/mix/src/tb_undc_real.vhd b/lib/radio/mix/src/tb_undc_real.vhd deleted file mode 100644 index 3c7a52f..0000000 --- a/lib/radio/mix/src/tb_undc_real.vhd +++ /dev/null @@ -1,158 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_mix_cpx --- Module Name: tb_mix_cpx.vhd --- Project Name: mix_cpx --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.mix_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_undc_real IS - Generic ( - nbits_data : integer := 24; - nbits_data_frac : integer := 24; - nbits_k : integer := 24; - nbits_k_frac : integer := 24; - has_in_reg : boolean := true; - rounding : boolean := true; - saturating : boolean := true - ); -END tb_undc_real; - -ARCHITECTURE behavior OF tb_undc_real IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT undc_real - Generic - ( - nbits_data : integer; - nbits_data_frac : integer; - nbits_k : integer; - nbits_k_frac : integer; - has_in_reg : boolean; - rounding : boolean; - saturating : boolean - ); - Port - ( - srst : in std_logic; - clk : in std_logic; - din_valid : in std_logic; - din : in sfixed; - kin_valid : in std_logic; - kin : in sfixed; - dout_valid : out std_logic; - dout : out sfixed; - dc_out : out sfixed - ); - END COMPONENT; - - --Constants - constant PERIOD : time := 10 ns; - - - --Inputs - SIGNAL clk : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL din_valid : std_logic := '0'; - SIGNAL kin_valid : std_logic := '0'; - SIGNAL din : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL kin : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low); - - --Outputs - SIGNAL dout : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL dc_out : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); - SIGNAL dout_valid : std_logic; - - SIGNAL k : real := 0.0; - SIGNAL x : real := 0.0; - SIGNAL y : real := 0.0; - SIGNAL dc : real := 0.0; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: undc_real - GENERIC MAP - ( - nbits_data => nbits_data, - nbits_data_frac => nbits_data_frac, - nbits_k => nbits_k, - nbits_k_frac => nbits_k_frac, - has_in_reg => has_in_reg, - rounding => rounding, - saturating => saturating - ) - PORT MAP - ( - srst => srst, - clk => clk, - din_valid => din_valid, - din => din, - kin_valid => kin_valid, - kin => kin, - dout_valid => dout_valid, - dout => dout, - dc_out => dc_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - ------------------------------------------ - -- Load k - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - kin <= to_sfixed(0.0005, kin); - kin_valid <= '1'; - wait until rising_edge(clk); - kin_valid <= '1'; - ------------------------------------------ - -- Process - ------------------------------------------ - wait for 2*PERIOD; - wait until rising_edge(clk); - din <= to_sfixed(0.5, din); - din_valid <= '1'; - wait until rising_edge(clk); - din_valid <= '1'; - wait for 5*PERIOD; - - wait for 200*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - k <= to_real(kin); - x <= to_real(din); - y <= to_real(dout); - dc <= to_real(dc_out); - -END; diff --git a/lib/radio/mix/src/undc_real.vhd b/lib/radio/mix/src/undc_real.vhd deleted file mode 100644 index be6df6e..0000000 --- a/lib/radio/mix/src/undc_real.vhd +++ /dev/null @@ -1,139 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: mix_cpx - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.mix_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; -entity undc_real is -Generic -( - nbits_data : integer := 12; - nbits_data_frac : integer := 12; - nbits_k : integer := 12; - nbits_k_frac : integer := 12; - has_in_reg : boolean := false; - rounding : boolean := true; - saturating : boolean := true -); -Port -( - srst : in std_logic; - clk : in std_logic; - din_valid : in std_logic; - din : in sfixed; - kin_valid : in std_logic; - kin : in sfixed; - dout_valid : out std_logic; - dout : out sfixed; - dc_out : out sfixed -); -end undc_real; - -architecture Behavioral of undc_real is - -constant nbits_internal : integer := nbits_data + nbits_data; -constant nbits_internal_frac : integer := nbits_data_frac + nbits_data_frac; - -signal x : sfixed(sproto(nbits_data, nbits_data_frac)'high downto sproto(nbits_data, nbits_data_frac)'low); -signal k : sfixed(sproto(nbits_k, nbits_k_frac)'high downto sproto(nbits_k, nbits_k_frac)'low); -signal dc : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y1 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); -signal y2 : sfixed(sproto(nbits_internal, nbits_internal_frac)'high downto sproto(nbits_internal, nbits_internal_frac)'low); - -begin - -dout <= resize(y, sproto(nbits_data, nbits_data_frac), rounding, saturating); -dc_out <= resize(dc, sproto(nbits_data, nbits_data_frac), false, false); - ------------------------------------------------------------- - proc_din_reg: process(clk, din_valid, din) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - x <= to_sfixed(0, x); - else - if din_valid = '1' then - x <= din; - end if; - end if; - end if; - else - x <= din; - end if; - end process; - ------------------------------------------------------------- - proc_valid_reg: process(clk, din_valid) - begin - if has_in_reg = true then - if rising_edge(clk) then - if srst = '1' then - dout_valid <= '0'; - else - dout_valid <= din_valid; - end if; - end if; - else - dout_valid <= din_valid; - end if; - end process; - ------------------------------------------------------------- - proc_kin_reg: process(clk, kin_valid, kin) - begin - if rising_edge(clk) then - if srst = '1' then - k <= to_sfixed(0, k); - else - if kin_valid = '1' then - k <= kin; - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_y: process(clk, x, dc) - begin - y <= resize(x - dc, y, false, false); - if rising_edge(clk) then - if srst = '1' then - y1 <= to_sfixed(0, y1); - y2 <= to_sfixed(0, y2); - dc <= to_sfixed(0, dc); - else - y1 <= y; - y2 <= resize(y1 * k, y2, false, false); - dc <= resize(y2 + dc, dc, false, false); - end if; - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/sim/tb_nco.fdo b/lib/radio/nco/sim/tb_nco.fdo deleted file mode 100644 index ae31dbf..0000000 --- a/lib/radio/nco/sim/tb_nco.fdo +++ /dev/null @@ -1,15 +0,0 @@ -vlib work -vcom -explicit -93 "../../../fixed/fixed_pkg_c.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993.vhd" -vcom -explicit -93 "../../../PCK_FIO-2002.7/PCK_FIO_1993_BODY.vhd" -vcom -explicit -93 "../src/nco_pkg.vhd" -vcom -explicit -93 "../src/waverom_dual.vhd" -vcom -explicit -93 "../src/wavelut.vhd" -vcom -explicit -93 "../src/nco_dbg.vhd" -vcom -explicit -93 "../src/tb_nco.vhd" -vsim -t 1ps -lib work tb_nco -do {tb_nco.wdo} -view wave -view structure -view signals -run 250us diff --git a/lib/radio/nco/sim/tb_nco.wdo b/lib/radio/nco/sim/tb_nco.wdo deleted file mode 100644 index 0fd0917..0000000 --- a/lib/radio/nco/sim/tb_nco.wdo +++ /dev/null @@ -1,46 +0,0 @@ -onerror {resume} -quietly WaveActivateNextPane {} 0 -add wave -noupdate -format Logic /tb_nco/uut/srst -add wave -noupdate -format Logic /tb_nco/uut/clk -add wave -noupdate -format Logic /tb_nco/uut/pacc_clr -add wave -noupdate -format Logic /tb_nco/uut/pacc_inc -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in -add wave -noupdate -format Logic /tb_nco/uut/freq_load -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in -add wave -noupdate -format Logic /tb_nco/uut/phase_load -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_out -add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_i -add wave -noupdate -format Analog-Step -radix decimal -scale 7.629423635191479e-005 /tb_nco/uut/wave_out_q -add wave -noupdate -format Logic /tb_nco/uut/out_valid -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/debug_out -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/freq_in_r -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/phase_in_r -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_ud -add wave -noupdate -format Literal -radix hexadecimal /tb_nco/uut/lut_addr_d -add wave -noupdate -format Literal /tb_nco/uut/wave_i_d -add wave -noupdate -format Literal /tb_nco/uut/wave_q_d -add wave -noupdate -format Literal /tb_nco/uut/wave_i_ud -add wave -noupdate -format Literal /tb_nco/uut/wave_q_ud -add wave -noupdate -format Literal /tb_nco/uut/lfsr -add wave -noupdate -format Literal /tb_nco/uut/lfsr_out -add wave -noupdate -format Logic /tb_nco/uut/lut_addr_valid -add wave -noupdate -format Logic /tb_nco/uut/lfsr_valid -add wave -noupdate -format Logic /tb_nco/uut/wave_d_valid -add wave -noupdate -format Logic /tb_nco/uut/wave_ud_valid -TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {249141632 ps} 0} -configure wave -namecolwidth 193 -configure wave -valuecolwidth 100 -configure wave -justifyvalue left -configure wave -signalnamewidth 1 -configure wave -snapdistance 10 -configure wave -datasetprefix 0 -configure wave -rowmargin 4 -configure wave -childrowmargin 2 -configure wave -gridoffset 0 -configure wave -gridperiod 1 -configure wave -griddelta 40 -configure wave -timeline 0 -update -WaveRestoreZoom {249024188 ps} {250051359 ps} diff --git a/lib/radio/nco/sim/tb_nco_results.m b/lib/radio/nco/sim/tb_nco_results.m deleted file mode 100644 index 4147cea..0000000 --- a/lib/radio/nco/sim/tb_nco_results.m +++ /dev/null @@ -1,61 +0,0 @@ -% Read data -function tb_nco_results(nbins) -fa = 100.0; -f = TEXTREAD('freq.txt')*1E-6 - -I_ud = TEXTREAD('q_ud.txt')'; -I_d = TEXTREAD('q_d.txt')'; -LFSR = TEXTREAD('lfsr.txt'); - -N= length(I_ud); -N_fft = min(16384, N); -N_fft2 = N_fft/2; - -fft_y2 = 2/N_fft*abs(fft(I_ud(1:N_fft).*hann(N_fft)')); -fft_y3 = 2/N_fft*abs(fft(I_d(1:N_fft).*hann(N_fft)')); - -[i, v] = get_maxpur(fft_y2, fa, f); -max_spur_freq = (i*fa/N_fft); -max_spur_value = 20*log10(v); - -[i, v] = get_maxpur(fft_y3, fa, f); -max_ditherd_spur_freq = (i*fa/N_fft); -max_ditherd_spur_value = 20*log10(v); - -% Output -close all; - -subplot(2,1,1) -plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y2(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_spur_value*ones(1,N_fft2+1), 'r-', [max_spur_freq], [max_spur_value], 'ro'); grid; -spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_spur_value, max_spur_freq); -legend('With dithering', spur_legend); -legend('No dithering', spur_legend); -title('Table'); -ylabel('dB'); -xlabel('f/MHz'); -axis([0 fa/2 -120 0]); -subplot(2,1,2) -plot(fa/N_fft*(0:N_fft2),20*log10(1E-6+fft_y3(1:N_fft2+1)), '-', fa/N_fft*(0:N_fft2), max_ditherd_spur_value*ones(1,N_fft2+1), 'r-', [max_ditherd_spur_freq], [max_ditherd_spur_value], 'ro'); grid; -spur_legend = sprintf('Max. spur %.1fdB at %.1fMHz', max_ditherd_spur_value, max_ditherd_spur_freq); -legend('With dithering', spur_legend); -title('Table'); -ylabel('dB'); -xlabel('f/MHz'); -axis([0 fa/2 -120 0]); - -figure; -hist(LFSR, nbins) - -function [max_i, max_v] = get_maxpur(spec, fa, f) -max_v = 0; -max_i = 0; -for ii=1:fix(length(spec)/2+1), - fi = ii*fa/length(spec); - dfi = fi - f; - if abs(dfi) > 0.05*f - if spec(ii) > max_v - max_v = spec(ii); - max_i = ii; - end - end; -end; diff --git a/lib/radio/nco/src/nco.vhd b/lib/radio/nco/src/nco.vhd deleted file mode 100644 index 25b7f1d..0000000 --- a/lib/radio/nco/src/nco.vhd +++ /dev/null @@ -1,223 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - q_phase : phase_relation_t; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid, lfsr_valid, wave_d_valid : std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i_d; - wave_out_q <= wave_q_d; - out_valid <= wave_d_valid; - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither-1 downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - lfsr_valid <= '0'; - lfsr_out <= (others => '0'); - for i in lfsr'range loop - lfsr(i) <= to_unsigned(2**i, nbits_lfsr); - end loop; - else - lfsr_valid <= '0'; - if pacc_inc ='1' then - lfsr_valid <= '1'; - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; - -- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(clk, phase) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - phase_out <= phase; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - variable lfsr_sum : unsigned(nbits_phase-1 downto 0); - begin - if rising_edge(clk) then - lut_addr_valid <= '0'; - if srst = '1' then - lfsr_sum := (others => '0'); - elsif lfsr_valid = '1' then - lut_addr_valid <= '1'; - lfsr_sum := lfsr_out + phase; - end if; - end if; - lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end process; - ------------------------------------------------------------- - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_d, - wave_i_out => wave_i_d, - wave_q_out => wave_q_d, - valid_out => wave_d_valid - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco.vhd.bak b/lib/radio/nco/src/nco.vhd.bak deleted file mode 100644 index 657b97a..0000000 --- a/lib/radio/nco/src/nco.vhd.bak +++ /dev/null @@ -1,240 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 12; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal valid : std_logic_vector(3 downto 0); - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lsfr_sum : unsigned(nbits_phase-1 downto 0); - signal lut_addr : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i, wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid _ std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i; - wave_out_q <= wave_q; - ------------------------------------------------------------- - proc_ctrl: process(srst, clk, pacc_inc, pacc_clr) - begin - if rising_edge(clk) then - if srst = '1' then - valid <= (others => '0'); - else - valid <= valid(valid'left-1 downto valid'right) & (pacc_inc or pacc_clr); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - for i in lfsr'range loop - lfsr(i) <= to_unsigned(1234+2**i, nbits_lfsr); - end loop; - elsif pacc_inc ='1' then - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; --- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - begin - if rising_edge(clk) then - lsfr_sum <= lfsr_out + phase; - lut_addr <= lsfr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end if; - end process; - ------------------------------------------------------------- - proc_out_reg: process(clk, phase) - begin - if has_out_reg = true then - if rising_edge(clk) then - phase_out <= phase; - end if; - else - phase_out <= phase; - end if; - end process; - ------------------------------------------------------------- - proc_valid_reg: process(clk, valid) - begin - out_valid <= valid(valid'right+1); - if has_out_reg = true then - out_valid <= valid(valid'right+2); - if has_pipe_reg = true then - out_valid <= valid(valid'right+3); - end if; - elsif has_pipe_reg = true then - out_valid <= valid(valid'right+2); - end if; - end process; - ------------------------------------------------------------- - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - has_out_reg => has_out_reg - ) - PORT MAP - ( - clk => clk, - addr => lut_addr, - addr_valid => lut_addr_valid, - wave_i_out => wave_i, - wave_q_out => wave_q - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco_dbg.vhd b/lib/radio/nco/src/nco_dbg.vhd deleted file mode 100644 index c0038a9..0000000 --- a/lib/radio/nco/src/nco_dbg.vhd +++ /dev/null @@ -1,253 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity nco is -Generic -( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_pipe_reg : boolean := false; - has_out_reg : boolean := false -); -Port -( - srst : in std_logic; - clk : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic; - debug_out : out debug_out_t -); -end nco; - -architecture Behavioral of nco is - - COMPONENT wavelut - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_lut_depth : integer; - q_phase : phase_relation_t; - has_out_reg : boolean - ); - Port - ( - clk : in std_logic; - rst : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic - ); - END COMPONENT; - -------------------------------------------------------------------------------- - constant nbits_wave_frac : integer := nbits_wave; - -------------------------------------------------------------------------------- - constant lfsr_gen_poly : unsigned(nbits_lfsr-1 downto 0) := to_unsigned(lfsr_poly(nbits_lfsr), nbits_lfsr); -- 24 - - signal phase : unsigned(nbits_phase-1 downto 0); - signal freq_in_r : unsigned(nbits_phase-1 downto 0); - signal phase_in_r : unsigned(nbits_phase-1 downto 0); - signal lut_addr_ud : unsigned(nbits_lut_depth-1 downto 0); - signal lut_addr_d : unsigned(nbits_lut_depth-1 downto 0); - signal wave_i_d, wave_q_d : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - signal wave_i_ud, wave_q_ud : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - - type lfsr_t is array (0 to 1) of unsigned(nbits_lfsr-1 downto 0); - signal lfsr : lfsr_t; - signal lfsr_out : unsigned(nbits_dither-1 downto 0); - signal lut_addr_valid, lfsr_valid, wave_d_valid, wave_ud_valid : std_logic; - -------------------------------------------------------------------------------- -begin - - wave_out_i <= wave_i_d; - wave_out_q <= wave_q_d; - out_valid <= wave_d_valid; - - debug_out.lfsr <= (debug_out.lfsr'left downto (debug_out.lfsr'right+lfsr_out'left+1) => '0') & lfsr_out; - debug_out.i_d <= to_real(wave_i_d); - debug_out.q_d <= to_real(wave_q_d); - debug_out.i_ud <= to_real(wave_i_ud); - debug_out.q_ud <= to_real(wave_q_ud); - ------------------------------------------------------------- - proc_lfsr: process(srst, clk, lfsr, pacc_inc) - variable lo : unsigned(nbits_dither-1 downto 0); - begin - if rising_edge(clk) then - if srst = '1' then - lfsr_valid <= '0'; - lfsr_out <= (others => '0'); - for i in lfsr'range loop - lfsr(i) <= to_unsigned(2**i, nbits_lfsr); - end loop; - else - lfsr_valid <= '0'; - if pacc_inc ='1' then - lfsr_valid <= '1'; - lo := (others => '0'); - for i in lfsr'range loop - if lfsr(i)(lfsr(i)'left) = '1' then - lfsr(i) <= (lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left)) xor lfsr_gen_poly; - else - lfsr(i) <= lfsr(i)(lfsr(i)'left-1 downto 0) & lfsr(i)(lfsr(i)'left); - end if; - end loop; - for i in lfsr'range loop - lo := lo + lfsr(i)(nbits_dither-1 downto 0); - end loop; - -- lo := lfsr(0)(nbits_dither downto 0); - lfsr_out <= lo(nbits_dither-1 downto 0); - end if; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_phase_accu: process(srst, clk, pacc_clr, pacc_inc, freq_in_r, phase_in_r) - variable phase_accu : unsigned(nbits_phase-1 downto 0); - - begin - if rising_edge(clk) then - if srst = '1' then - phase_accu := (others => '0'); - else - phase <= phase_accu + phase_in_r; - if pacc_clr = '1' then - phase_accu := (others => '0'); - elsif pacc_inc = '1' then - phase_accu := phase_accu + freq_in_r; - end if; - end if; - end if; - phase_out <= phase; - end process; - ------------------------------------------------------------- - freq_in_reg: process(srst, clk, freq_load, freq_in) - begin - if rising_edge(clk) then - if srst = '1' then - freq_in_r <= (others => '0'); - elsif freq_load = '1' then - freq_in_r <= freq_in; - end if; - end if; - end process; - ------------------------------------------------------------- - phase_in_reg: process(srst, clk, phase_load, phase_in) - begin - if rising_edge(clk) then - if srst = '1' then - phase_in_r <= (others => '0'); - elsif phase_load = '1' then - phase_in_r <= phase_in; - end if; - end if; - end process; - ------------------------------------------------------------- - proc_pipe_reg: process(clk) - variable lfsr_sum : unsigned(nbits_phase-1 downto 0); - begin - if rising_edge(clk) then - lut_addr_valid <= '0'; - if srst = '1' then - lfsr_sum := (others => '0'); - elsif lfsr_valid = '1' then - lut_addr_valid <= '1'; - lfsr_sum := lfsr_out + phase; - end if; - end if; - lut_addr_d <= lfsr_sum(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - lut_addr_ud <= phase(nbits_phase-1 downto nbits_phase-nbits_lut_depth); - end process; - ------------------------------------------------------------- - inst_wavelut_ud: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_ud, - wave_i_out => wave_i_ud, - wave_q_out => wave_q_ud, - valid_out => wave_ud_valid - ); - - inst_wavelut_d: wavelut - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_lut_depth => nbits_lut_depth, - q_phase => q_phase, - has_out_reg => has_out_reg - ) - PORT MAP - ( - rst => srst, - clk => clk, - addr_valid => lut_addr_valid, - addr => lut_addr_d, - wave_i_out => wave_i_d, - wave_q_out => wave_q_d, - valid_out => wave_d_valid - ); - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/nco_pkg.vhd b/lib/radio/nco/src/nco_pkg.vhd deleted file mode 100644 index 0bb9cef..0000000 --- a/lib/radio/nco/src/nco_pkg.vhd +++ /dev/null @@ -1,117 +0,0 @@ - -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use ieee.numeric_std.all; -use IEEE.MATH_REAL.ALL; -use work.fixed_pkg.all; - -------------------------------------------------------------------------------- -package nco_pkg is - - constant tpd : time := 0 ns; - - -- Global set arithmetic rounding mode - constant pi : real := 3.141592653589793e+000; - constant sqrt2 : real := 1.414213562373095e+000; - constant sqrt2_inv : real := 7.071067811865475e-001; - - type real_array_t is array (natural range <>) of real; - type natural_array_t is array (natural range <>) of natural; - type phase_relation_t is (phase_90deg, phase_270deg); - - type debug_out_t is record - lfsr : unsigned(31 downto 0); - i_ud : real; - q_ud : real; - i_d : real; - q_d : real; - end record; - - constant lfsr_poly : natural_array_t(3 to 24) := - ( - 12, -- 3 - 24, -- 4 - 58, -- 5 - 114, -- 6 - 210, -- 7 - 500, -- 8 - 1000, -- 9 - 1824, -- 10 - 3712, -- 11 - 7184, -- 12 - 14592, -- 13 - 28674, -- 14 - 59392, -- 15 - 106512, -- 16 - 245760, -- 17 - 466944, -- 18 - 933888, -- 19 - 1654784, -- 20 - 3735552, -- 21 - 7342080, -- 22 - 14745600, -- 23 - 14811138 -- 24 - ); - - function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t; - function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t; - - ------------------------------------------------------------- - -- Constructor helpers - -- Use: variable v8u6 : ufixed_t(ufixed(8,6)'range); - function uproto (nbits : integer; nbits_frac : integer) return ufixed; - - -- Use: variable v8s6 : sfixed_t(sfixed(8,6)'range); - function sproto (nbits : integer; nbits_frac : integer) return sfixed; - -end; -- package nco_pkg; - -------------------------------------------------------------------------------- -package body nco_pkg is - - function sin_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is - variable tbl : real_array_t (0 to nsamples-1); - variable phi : real := phi_in; - variable dphi : real := 2.0*pi*omega; - - begin - for i in 0 to nsamples-1 loop - tbl(i) := sin(phi); - phi := phi + dphi; - end loop; - - return tbl; - end sin_tbl; - - ------------------------------------------------------------- - function cos_tbl(nsamples : integer; omega, phi_in : real) return real_array_t is - variable tbl : real_array_t (0 to nsamples-1); - variable phi : real := phi_in; - variable dphi : real := 2.0*pi*omega; - - begin - for i in 0 to nsamples-1 loop - tbl(i) := cos(phi); - phi := phi + dphi; - end loop; - - return tbl; - end cos_tbl; - - ------------------------------------------------------------- - -- Constuctor helpers - function uproto (nbits : integer; nbits_frac : integer) return ufixed is - constant result : ufixed (nbits-nbits_frac-1 downto -nbits_frac) := (others => '0'); - begin - return result(nbits-nbits_frac-1 downto -nbits_frac); - end uproto; - - ------------------------------------------------------------- - function sproto (nbits : integer; nbits_frac : integer) return sfixed is - constant result : sfixed (nbits-nbits_frac downto -nbits_frac+1) := (others => '0'); - begin - return result(nbits-nbits_frac downto -nbits_frac+1); - end sproto; - -------------------------------------------------------------------------------- -end; -- package nco_pkg; diff --git a/lib/radio/nco/src/tb_nco.vhd b/lib/radio/nco/src/tb_nco.vhd deleted file mode 100644 index f2d930a..0000000 --- a/lib/radio/nco/src/tb_nco.vhd +++ /dev/null @@ -1,299 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 17:16:42 13.05.2007 --- Design Name: tb_nco --- Module Name: tb_nco.vhd --- Project Name: nco --- Target Device: --- Tool versions: --- Description: --- --------------------------------------------------------------------------------- -LIBRARY ieee; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use std.textio.all; -- Imports the standard textio package. - -library work; -use work.fixed_pkg.all; -use work.nco_pkg.all; -use work.PCK_FIO.all; - -ENTITY tb_nco IS - Generic ( - nbits_wave : integer := 18; - nbits_phase : integer := 16; - nbits_lut_depth : integer := 12; - nbits_dither : integer := 4; - nbits_lfsr : integer := 12; - q_phase : phase_relation_t := phase_270deg; - has_pipe_reg : boolean := true; - has_out_reg : boolean := true - ); -END tb_nco; - -ARCHITECTURE behavior OF tb_nco IS - - -- Component Declaration for the Unit Under Test (UUT) - COMPONENT nco - GENERIC ( - nbits_wave : integer; - nbits_phase : integer; - nbits_lut_depth : integer; - nbits_dither : integer; - nbits_lfsr : integer; - q_phase : phase_relation_t; - has_pipe_reg : boolean; - has_out_reg : boolean - ); - PORT( - srst : in std_logic; - clk : in std_logic; --- ce : in std_logic; - pacc_clr : in std_logic; - pacc_inc : in std_logic; - freq_in : in unsigned(nbits_phase-1 downto 0); - freq_load : in std_logic; - phase_in : in unsigned(nbits_phase-1 downto 0); - phase_load : in std_logic; - phase_out : out unsigned(nbits_phase-1 downto 0); - wave_out_i : out sfixed; - wave_out_q : out sfixed; - out_valid : out std_logic; - debug_out : out debug_out_t - ); - END COMPONENT; - - --Constants - constant f : REAL := 4.1667E6; - constant df : REAL := 10.0E3; - constant fa : REAL := 100.0E6; - constant PERIOD : time := 10 ns; - constant nbits_wave_frac : integer := nbits_wave; - - SIGNAL freq_word : integer := integer(f/fa*2.0**nbits_phase); - SIGNAL dfreq_word : integer := integer(df/fa*2.0**nbits_phase); - - --Inputs - SIGNAL clk : std_logic := '0'; --- SIGNAL ce : std_logic := '0'; - SIGNAL srst : std_logic := '1'; - SIGNAL pacc_clr : std_logic := '0'; - SIGNAL pacc_inc : std_logic := '0'; - SIGNAL phase_load : std_logic := '0'; - SIGNAL freq_load : std_logic := '0'; - SIGNAL freq_in : unsigned(nbits_phase-1 downto 0); - SIGNAL phase_in : unsigned(nbits_phase-1 downto 0); - - --Outputs - SIGNAL wave_out_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - SIGNAL wave_out_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - SIGNAL out_valid : std_logic; - SIGNAL phase_out : unsigned(nbits_phase-1 downto 0); - SIGNAL debug_out : debug_out_t; - - SIGNAL fileout_enable : std_logic := '0'; - -BEGIN - - -- Instantiate the Unit Under Test (UUT) - uut: nco - GENERIC MAP ( - nbits_wave => nbits_wave, - nbits_phase => nbits_phase, - nbits_lut_depth => nbits_lut_depth, - nbits_dither => nbits_dither, - nbits_lfsr => nbits_lfsr, - q_phase => q_phase, - has_pipe_reg => has_pipe_reg, - has_out_reg => has_out_reg - ) - PORT MAP( - srst => srst, - clk => clk, --- ce => ce, - pacc_clr => pacc_clr, - pacc_inc => pacc_inc, - freq_in => freq_in, - freq_load => freq_load, - phase_in => phase_in, - phase_load => phase_load, - phase_out => phase_out, - wave_out_i => wave_out_i, - wave_out_q => wave_out_q, - out_valid => out_valid, - debug_out => debug_out - ); - - tb_clk : PROCESS - BEGIN - clk <= not clk; - wait for PERIOD/2; - END PROCESS; - - tb : PROCESS - file RESULT_FREQ: text open write_mode is "freq.txt"; - variable L: line; - - BEGIN - - -- Wait 100 ns for global reset to finish - wait for 4*PERIOD; - srst <= '0'; - - fprint(RESULT_FREQ, L,"%s\n", REAL'image(f)); - - wait for 2*PERIOD; --- ce <= '1'; - ------------------------------------------- - -- 1 - phase_in <= to_unsigned(0,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - freq_in <= to_unsigned(1411,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 2*PERIOD; - pacc_inc <= '1'; - - wait for 2*PERIOD; - wait until rising_edge(clk); - - wait for 40*PERIOD; - ------------------------------------------- - freq_in <= to_unsigned(643,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 40*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(800,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - wait for 20*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(45072,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - wait for 20*PERIOD; - ------------------------------------------- - phase_in <= to_unsigned(20593,nbits_phase); - wait until rising_edge(clk); - phase_load <= '1'; - wait until rising_edge(clk); - phase_load <= '0'; - - ------------------------------------------- - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 20*PERIOD; - fileout_enable <= '1'; - - wait for 20000*PERIOD; - fileout_enable <= '0'; - - ------------------------------------------- - -- Sweep - freq_word <= 100; - for i in 1 to 200 loop - wait for 20*PERIOD; - freq_word <= freq_word + dfreq_word; - - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - end loop; - - pacc_inc <= '0'; - wait for 20*PERIOD; - fileout_enable <= '0'; - wait until rising_edge(clk); - pacc_clr <= '1'; - wait until rising_edge(clk); - pacc_clr <= '0'; - wait for 20*PERIOD; - pacc_inc <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - pacc_clr <= '1'; - wait until rising_edge(clk); - pacc_clr <= '0'; - wait for 20*PERIOD; - pacc_inc <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - pacc_inc <= '1'; - wait until rising_edge(clk); - pacc_inc <= '0'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - freq_in <= to_unsigned(freq_word,nbits_phase); - wait until rising_edge(clk); - freq_load <= '1'; - wait until rising_edge(clk); - freq_load <= '0'; - - wait for 20*PERIOD; - pacc_inc <= '1'; - wait for 20*PERIOD; - wait until rising_edge(clk); - srst <= '1'; - wait until rising_edge(clk); - srst <= '0'; - wait for 20*PERIOD; - pacc_inc <= '0'; - - wait for 20*PERIOD; - - assert false report "Test finished" severity error; - wait; - END PROCESS; - - tb_fo : PROCESS(clk, fileout_enable, out_valid) - file RESULT_I: text open write_mode is "i_ud.txt"; - file RESULT_Q: text open write_mode is "q_ud.txt"; - file RESULT_ID: text open write_mode is "i_d.txt"; - file RESULT_QD: text open write_mode is "q_d.txt"; - file RESULT_LFSR: text open write_mode is "lfsr.txt"; - variable L: line; - - BEGIN - if rising_edge(clk) and fileout_enable = '1' and out_valid = '1' then - fprint(RESULT_I, L,"%s\n", REAL'image(debug_out.i_ud)); - fprint(RESULT_Q, L,"%s\n", REAL'image(debug_out.q_ud)); - fprint(RESULT_ID, L,"%s\n", REAL'image(debug_out.i_d)); - fprint(RESULT_QD, L,"%s\n", REAL'image(debug_out.q_d)); - fprint(RESULT_LFSR, L,"%s\n", INTEGER'image(to_integer(debug_out.lfsr))); - end if; - - END PROCESS; - - -END; diff --git a/lib/radio/nco/src/wavelut.vhd b/lib/radio/nco/src/wavelut.vhd deleted file mode 100644 index 4b0f02e..0000000 --- a/lib/radio/nco/src/wavelut.vhd +++ /dev/null @@ -1,239 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity wavelut is -Generic -( - nbits_wave : integer := 12; - nbits_wave_frac : integer := 12; - nbits_lut_depth : integer := 12; - q_phase : phase_relation_t := phase_90deg; - has_out_reg : boolean := false -); -Port -( - rst : in std_logic; - clk : in std_logic; - addr_valid : in std_logic; - addr : in unsigned(nbits_lut_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed; - valid_out : out std_logic -); -end wavelut; - -architecture Behavioral of wavelut is - - COMPONENT waverom_dual - Generic - ( - nbits_wave : integer; - nbits_wave_frac : integer; - nbits_rom_depth : integer - ); - Port - ( - clk : in std_logic; - addr_i : in unsigned(nbits_rom_depth-1 downto 0); - addr_q : in unsigned(nbits_rom_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed - ); - END COMPONENT; - -------------------------------------------------------------------------------- -constant nbits_rom_depth : integer := nbits_lut_depth-2; - -------------------------------------------------------------------------------- -signal wave_i : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); -signal wave_q : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); -signal inv_i : std_logic; -signal inv_q : std_logic; -signal addr_i : unsigned(nbits_rom_depth-1 downto 0); -signal addr_q : unsigned(nbits_rom_depth-1 downto 0); -signal zero_i : std_logic; -signal zero_q : std_logic; - -------------------------------------------------------------------------------- -begin - - inst_waverom_dual: waverom_dual - GENERIC MAP - ( - nbits_wave => nbits_wave, - nbits_wave_frac => nbits_wave_frac, - nbits_rom_depth => nbits_rom_depth - ) - PORT MAP - ( - clk => clk, - addr_i => addr_i, - addr_q => addr_q, - wave_i_out => wave_i, - wave_q_out => wave_q - ); - ------------------------------------------------------------- -proc_valid: process(clk) - variable v : unsigned(0 to 1); - begin - if rising_edge(clk) then - if rst = '1' then - v := (others => '0'); - valid_out <= '0'; - else - valid_out <= v(1); - v(1) := v(0); - v(0) := addr_valid; - end if; - end if; - end process; - ------------------------------------------------------------- -proc_tbl_addr_i: process(clk, addr) - variable index : unsigned(addr'left downto addr'right); - variable n2 : integer; - constant N_2 : integer := 2**(nbits_lut_depth-1); - constant N_4 : integer := 2**(nbits_lut_depth-2); - begin - n2 := to_integer(addr(addr'left-1 downto addr'right)); - if n2 > N_4 then - index := to_unsigned(N_2 - n2, index'length); - else - index := to_unsigned(n2, index'length); - end if; - - if rising_edge(clk) then - if rst = '1' then - addr_i <= (others => '0'); - zero_i <= '0'; - inv_i <= '0'; - elsif addr_valid = '1' then - addr_i <= index(addr'left-2 downto addr'right); - zero_i <= index(addr'left-1); - inv_i <= addr(addr'left) xor addr(addr'left-1); - end if; - end if; - - end process; - -------------------------------------------------------------------------------- -proc_tbl_addr_q: process(clk, addr) - variable index : unsigned(addr'left downto addr'right); - variable n2 : integer; - constant N_4 : integer := 2**(nbits_lut_depth-2); - - begin - n2 := to_integer(addr(addr'left-1 downto addr'right)); - if n2 > N_4 then - index := to_unsigned(n2 - N_4, index'length); - else - index := to_unsigned(N_4 - n2, index'length); - end if; - - if rising_edge(clk) then - if rst = '1' then - addr_q <= (others => '0'); - zero_q <= '0'; - inv_q <= '0'; - elsif addr_valid = '1' then - addr_q <= index(addr'left-2 downto addr'right); - zero_q <= index(addr'left-1); - if q_phase = phase_90deg then - inv_q <= addr(addr'left); - elsif q_phase = phase_270deg then - inv_q <= not addr(addr'left); - end if; - end if; - end if; - - end process; - ------------------------------------------------------------- -proc_out_i: process(clk, wave_i, inv_i, zero_i) - variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - variable z, inv : std_logic; - begin - - w := to_sfixed(0.0, w); - if z = '0' then - w := wave_i; - if inv = '1' then - w := resize(-wave_i, w, fixed_truncate, fixed_wrap); - end if; - end if; - - if has_out_reg = true then - if rising_edge(clk) then - wave_i_out <= w; - end if; - else - wave_i_out <= w; - end if; - - if rising_edge(clk) then - z := zero_i; - inv := inv_i; - end if; - - end process; - ------------------------------------------------------------- -proc_out_q: process(clk, wave_q, inv_q, zero_q) - variable w : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - variable z, inv : std_logic; - begin - - w := to_sfixed(0.0, w); - if z = '0' then - w := wave_q; - if inv = '1' then - w := resize(-wave_q, w, fixed_truncate, fixed_wrap); - end if; - end if; - - if has_out_reg = true then - if rising_edge(clk) then - wave_q_out <= w; - end if; - else - wave_q_out <= w; - end if; - - if rising_edge(clk) then - z := zero_q; - inv := inv_q; - end if; - - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/radio/nco/src/waverom_dual.vhd b/lib/radio/nco/src/waverom_dual.vhd deleted file mode 100644 index 4824eb0..0000000 --- a/lib/radio/nco/src/waverom_dual.vhd +++ /dev/null @@ -1,86 +0,0 @@ --------------------------------------------------------------------------------- --- Company: --- Engineer: --- --- Create Date: 12:16:14 10/02/05 --- Design Name: --- Module Name: cordic_stage - Behavioral --- Project Name: --- Target Device: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- --------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.MATH_REAL.ALL; -USE ieee.numeric_std.ALL; -use work.fixed_pkg.all; -use work.nco_pkg.all; - ----- Uncomment the following library declaration if instantiating ----- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity waverom_dual is -Generic -( - nbits_wave : integer := 12; - nbits_wave_frac : integer := 12; - nbits_rom_depth : integer := 12 -); -Port -( - clk : in std_logic; - addr_i : in unsigned(nbits_rom_depth-1 downto 0); - addr_q : in unsigned(nbits_rom_depth-1 downto 0); - wave_i_out : out sfixed; - wave_q_out : out sfixed -); -end waverom_dual; - -architecture Behavioral of waverom_dual is - -------------------------------------------------------------------------------- -constant rom_depth : integer := 2**nbits_rom_depth; -type wave_mem_t is array (0 to rom_depth-1) of sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low); - -constant sfixed_proto : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low) := (others => '0'); - -------------------------------------------------------------------------------- -function to_wave_mem(wave_real : real_array_t; len : integer; proto : sfixed) return wave_mem_t is -variable res : wave_mem_t; -begin - for i in 0 to len-1 loop - res(i) := to_sfixed(wave_real(i), proto, fixed_round, fixed_saturate); - end loop; - - return res; -end to_wave_mem; - -------------------------------------------------------------------------------- --- Create ROM -constant real_wave_tbl : real_array_t(0 to rom_depth-1) := cos_tbl(rom_depth, 0.25/real(rom_depth), 0.0); -constant wave_tbl : wave_mem_t := to_wave_mem(real_wave_tbl, rom_depth, sfixed_proto); - -------------------------------------------------------------------------------- -begin - -------------------------------------------------------------------------------- -proc_wave: process(clk) - begin - if rising_edge(clk) then - wave_i_out <= wave_tbl(to_integer(addr_i)); - wave_q_out <= wave_tbl(to_integer(addr_q)); - end if; - end process; - ------------------------------------------------------------- -end Behavioral; diff --git a/lib/uart/bbfifo_16x8.vhd b/lib/uart/bbfifo_16x8.vhd deleted file mode 100644 index d6604a6..0000000 --- a/lib/uart/bbfifo_16x8.vhd +++ /dev/null @@ -1,281 +0,0 @@ --- 'Bucket Brigade' FIFO --- 16 deep --- 8-bit data --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 14th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for BBFIFO_16x8 --- -entity bbfifo_16x8 is - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end bbfifo_16x8; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for BBFIFO_16x8 --- -architecture low_level_definition of bbfifo_16x8 is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in BBFIFO_16x8 --- ------------------------------------------------------------------------------------- --- -signal pointer : std_logic_vector(3 downto 0); -signal next_count : std_logic_vector(3 downto 0); -signal half_count : std_logic_vector(3 downto 0); -signal count_carry : std_logic_vector(2 downto 0); - -signal pointer_zero : std_logic; -signal pointer_full : std_logic; -signal decode_data_present : std_logic; -signal data_present_int : std_logic; -signal valid_write : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of zero_lut : label is "0001"; -attribute INIT of full_lut : label is "8000"; -attribute INIT of dp_lut : label is "BFA0"; -attribute INIT of valid_lut : label is "C4"; --- ------------------------------------------------------------------------------------- --- --- Start of BBFIFO_16x8 circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- SRL16E data storage - - data_width_loop: for i in 0 to 7 generate - -- - attribute INIT : string; - attribute INIT of data_srl : label is "0000"; - -- - begin - - data_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_in(i), - CE => valid_write, - CLK => clk, - A0 => pointer(0), - A1 => pointer(1), - A2 => pointer(2), - A3 => pointer(3), - Q => data_out(i) ); - - end generate data_width_loop; - - -- 4-bit counter to act as data pointer - -- Counter is clock enabled by 'data_present' - -- Counter will be reset when 'reset' is active - -- Counter will increment when 'valid_write' is active - - count_width_loop: for i in 0 to 3 generate - -- - attribute INIT : string; - attribute INIT of count_lut : label is "6606"; - -- - begin - - register_bit: FDRE - port map ( D => next_count(i), - Q => pointer(i), - CE => data_present_int, - R => reset, - C => clk); - - count_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"6606") - --synthesis translate_on - port map( I0 => pointer(i), - I1 => read, - I2 => pointer_zero, - I3 => write, - O => half_count(i)); - - lsb_count: if i=0 generate - begin - - count_muxcy: MUXCY - port map( DI => pointer(i), - CI => valid_write, - S => half_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => half_count(i), - CI => valid_write, - O => next_count(i)); - - end generate lsb_count; - - mid_count: if i>0 and i<3 generate - begin - - count_muxcy: MUXCY - port map( DI => pointer(i), - CI => count_carry(i-1), - S => half_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => half_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate mid_count; - - upper_count: if i=3 generate - begin - - count_xor: XORCY - port map( LI => half_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate upper_count; - - end generate count_width_loop; - - - -- Detect when pointer is zero and maximum - - zero_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0001") - --synthesis translate_on - port map( I0 => pointer(0), - I1 => pointer(1), - I2 => pointer(2), - I3 => pointer(3), - O => pointer_zero ); - - - full_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"8000") - --synthesis translate_on - port map( I0 => pointer(0), - I1 => pointer(1), - I2 => pointer(2), - I3 => pointer(3), - O => pointer_full ); - - - -- Data Present status - - dp_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"BFA0") - --synthesis translate_on - port map( I0 => write, - I1 => read, - I2 => pointer_zero, - I3 => data_present_int, - O => decode_data_present ); - - dp_flop: FDR - port map ( D => decode_data_present, - Q => data_present_int, - R => reset, - C => clk); - - -- Valid write signal - - valid_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"C4") - --synthesis translate_on - port map( I0 => pointer_full, - I1 => write, - I2 => read, - O => valid_write ); - - - -- assign internal signals to outputs - - full <= pointer_full; - half_full <= pointer(3); - data_present <= data_present_int; - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE BBFIFO_16x8.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/kcuart_rx.vhd b/lib/uart/kcuart_rx.vhd deleted file mode 100644 index a7ac1a2..0000000 --- a/lib/uart/kcuart_rx.vhd +++ /dev/null @@ -1,352 +0,0 @@ --- Constant (K) Compact UART Receiver --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 16th October 2002 --- --- Start of design entry : 16th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for KCUART_RX --- -entity kcuart_rx is - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - data_strobe : out std_logic; - en_16_x_baud : in std_logic; - clk : in std_logic); - end kcuart_rx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for KCUART_RX --- -architecture low_level_definition of kcuart_rx is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in KCUART_RX --- ------------------------------------------------------------------------------------- --- -signal sync_serial : std_logic; -signal stop_bit : std_logic; -signal data_int : std_logic_vector(7 downto 0); -signal data_delay : std_logic_vector(7 downto 0); -signal start_delay : std_logic; -signal start_bit : std_logic; -signal edge_delay : std_logic; -signal start_edge : std_logic; -signal decode_valid_char : std_logic; -signal valid_char : std_logic; -signal decode_purge : std_logic; -signal purge : std_logic; -signal valid_srl_delay : std_logic_vector(8 downto 0); -signal valid_reg_delay : std_logic_vector(8 downto 0); -signal decode_data_strobe : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of start_srl : label is "0000"; -attribute INIT of edge_srl : label is "0000"; -attribute INIT of valid_lut : label is "0040"; -attribute INIT of purge_lut : label is "54"; -attribute INIT of strobe_lut : label is "8"; --- ------------------------------------------------------------------------------------- --- --- Start of KCUART_RX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- Synchronise input serial data to system clock - - sync_reg: FD - port map ( D => serial_in, - Q => sync_serial, - C => clk); - - stop_reg: FD - port map ( D => sync_serial, - Q => stop_bit, - C => clk); - - - -- Data delays to capture data at 16 time baud rate - -- Each SRL16E is followed by a flip-flop for best timing - - data_loop: for i in 0 to 7 generate - begin - - lsbs: if i<7 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_int(i+1), - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => data_delay(i) ); - - end generate lsbs; - - msb: if i=7 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => stop_bit, - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => data_delay(i) ); - - end generate msb; - - data_reg: FDE - port map ( D => data_delay(i), - Q => data_int(i), - CE => en_16_x_baud, - C => clk); - - end generate data_loop; - - -- Assign internal signals to outputs - - data_out <= data_int; - - -- Data delays to capture start bit at 16 time baud rate - - start_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => data_int(0), - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => start_delay ); - - start_reg: FDE - port map ( D => start_delay, - Q => start_bit, - CE => en_16_x_baud, - C => clk); - - - -- Data delays to capture start bit leading edge at 16 time baud rate - -- Delay ensures data is captured at mid-bit position - - edge_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => start_bit, - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '0', - A2 => '1', - A3 => '0', - Q => edge_delay ); - - edge_reg: FDE - port map ( D => edge_delay, - Q => start_edge, - CE => en_16_x_baud, - C => clk); - - -- Detect a valid character - - valid_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0040") - --synthesis translate_on - port map( I0 => purge, - I1 => stop_bit, - I2 => start_edge, - I3 => edge_delay, - O => decode_valid_char ); - - valid_reg: FDE - port map ( D => decode_valid_char, - Q => valid_char, - CE => en_16_x_baud, - C => clk); - - -- Purge of data status - - purge_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"54") - --synthesis translate_on - port map( I0 => valid_reg_delay(8), - I1 => valid_char, - I2 => purge, - O => decode_purge ); - - purge_reg: FDE - port map ( D => decode_purge, - Q => purge, - CE => en_16_x_baud, - C => clk); - - -- Delay of valid_char pulse of length equivalent to the time taken - -- to purge data shift register of all data which has been used. - -- Requires 9x16 + 8 delays which is achieved by packing of SRL16E with - -- up to 16 delays and utilising the dedicated flip flop in each stage. - - valid_loop: for i in 0 to 8 generate - begin - - lsb: if i=0 generate - -- - attribute INIT : string; - attribute INIT of delay15_srl : label is "0000"; - -- - begin - - delay15_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => valid_char, - CE => en_16_x_baud, - CLK => clk, - A0 => '0', - A1 => '1', - A2 => '1', - A3 => '1', - Q => valid_srl_delay(i) ); - - end generate lsb; - - msbs: if i>0 generate - -- - attribute INIT : string; - attribute INIT of delay16_srl : label is "0000"; - -- - begin - - delay16_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => valid_reg_delay(i-1), - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '1', - A2 => '1', - A3 => '1', - Q => valid_srl_delay(i) ); - - end generate msbs; - - data_reg: FDE - port map ( D => valid_srl_delay(i), - Q => valid_reg_delay(i), - CE => en_16_x_baud, - C => clk); - - end generate valid_loop; - - -- Form data strobe - - strobe_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => valid_char, - I1 => en_16_x_baud, - O => decode_data_strobe ); - - strobe_reg: FD - port map ( D => decode_data_strobe, - Q => data_strobe, - C => clk); - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE KCUART_RX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/kcuart_tx.vhd b/lib/uart/kcuart_tx.vhd deleted file mode 100644 index 556ac58..0000000 --- a/lib/uart/kcuart_tx.vhd +++ /dev/null @@ -1,394 +0,0 @@ --- Constant (K) Compact UART Transmitter --- --- Version : 1.10 --- Version Date : 3rd December 2003 --- Reason : '--translate' directives changed to '--synthesis translate' directives --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 2nd October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for KCUART_TX --- -entity kcuart_tx is - Port ( data_in : in std_logic_vector(7 downto 0); - send_character : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - Tx_complete : out std_logic; - clk : in std_logic); - end kcuart_tx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for KCUART_TX --- -architecture low_level_definition of kcuart_tx is --- ------------------------------------------------------------------------------------- --- ------------------------------------------------------------------------------------- --- --- Signals used in KCUART_TX --- ------------------------------------------------------------------------------------- --- -signal data_01 : std_logic; -signal data_23 : std_logic; -signal data_45 : std_logic; -signal data_67 : std_logic; -signal data_0123 : std_logic; -signal data_4567 : std_logic; -signal data_01234567 : std_logic; -signal bit_select : std_logic_vector(2 downto 0); -signal next_count : std_logic_vector(2 downto 0); -signal mask_count : std_logic_vector(2 downto 0); -signal mask_count_carry : std_logic_vector(2 downto 0); -signal count_carry : std_logic_vector(2 downto 0); -signal ready_to_start : std_logic; -signal decode_Tx_start : std_logic; -signal Tx_start : std_logic; -signal decode_Tx_run : std_logic; -signal Tx_run : std_logic; -signal decode_hot_state : std_logic; -signal hot_state : std_logic; -signal hot_delay : std_logic; -signal Tx_bit : std_logic; -signal decode_Tx_stop : std_logic; -signal Tx_stop : std_logic; -signal decode_Tx_complete : std_logic; --- --- ------------------------------------------------------------------------------------- --- --- Attributes to define LUT contents during implementation --- The information is repeated in the generic map for functional simulation-- --- ------------------------------------------------------------------------------------- --- -attribute INIT : string; -attribute INIT of mux1_lut : label is "E4FF"; -attribute INIT of mux2_lut : label is "E4FF"; -attribute INIT of mux3_lut : label is "E4FF"; -attribute INIT of mux4_lut : label is "E4FF"; -attribute INIT of ready_lut : label is "10"; -attribute INIT of start_lut : label is "0190"; -attribute INIT of run_lut : label is "1540"; -attribute INIT of hot_state_lut : label is "94"; -attribute INIT of delay14_srl : label is "0000"; -attribute INIT of stop_lut : label is "0180"; -attribute INIT of complete_lut : label is "8"; --- ------------------------------------------------------------------------------------- --- --- Start of KCUART_TX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- 8 to 1 multiplexer to convert parallel data to serial - - mux1_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(0), - I2 => data_in(1), - I3 => Tx_run, - O => data_01 ); - - mux2_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(2), - I2 => data_in(3), - I3 => Tx_run, - O => data_23 ); - - mux3_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(4), - I2 => data_in(5), - I3 => Tx_run, - O => data_45 ); - - mux4_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"E4FF") - --synthesis translate_on - port map( I0 => bit_select(0), - I1 => data_in(6), - I2 => data_in(7), - I3 => Tx_run, - O => data_67 ); - - mux5_muxf5: MUXF5 - port map( I1 => data_23, - I0 => data_01, - S => bit_select(1), - O => data_0123 ); - - mux6_muxf5: MUXF5 - port map( I1 => data_67, - I0 => data_45, - S => bit_select(1), - O => data_4567 ); - - mux7_muxf6: MUXF6 - port map( I1 => data_4567, - I0 => data_0123, - S => bit_select(2), - O => data_01234567 ); - - -- Register serial output and force start and stop bits - - pipeline_serial: FDRS - port map ( D => data_01234567, - Q => serial_out, - R => Tx_start, - S => Tx_stop, - C => clk); - - -- 3-bit counter - -- Counter is clock enabled by en_16_x_baud - -- Counter will be reset when 'Tx_start' is active - -- Counter will increment when Tx_bit is active - -- Tx_run must be active to count - -- count_carry(2) indicates when terminal count (7) is reached and Tx_bit=1 (ie overflow) - - count_width_loop: for i in 0 to 2 generate - -- - attribute INIT : string; - attribute INIT of count_lut : label is "8"; - -- - begin - - register_bit: FDRE - port map ( D => next_count(i), - Q => bit_select(i), - CE => en_16_x_baud, - R => Tx_start, - C => clk); - - count_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => bit_select(i), - I1 => Tx_run, - O => mask_count(i)); - - mask_and: MULT_AND - port map( I0 => bit_select(i), - I1 => Tx_run, - LO => mask_count_carry(i)); - - lsb_count: if i=0 generate - begin - - count_muxcy: MUXCY - port map( DI => mask_count_carry(i), - CI => Tx_bit, - S => mask_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => mask_count(i), - CI => Tx_bit, - O => next_count(i)); - - end generate lsb_count; - - upper_count: if i>0 generate - begin - - count_muxcy: MUXCY - port map( DI => mask_count_carry(i), - CI => count_carry(i-1), - S => mask_count(i), - O => count_carry(i)); - - count_xor: XORCY - port map( LI => mask_count(i), - CI => count_carry(i-1), - O => next_count(i)); - - end generate upper_count; - - end generate count_width_loop; - - -- Ready to start decode - - ready_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"10") - --synthesis translate_on - port map( I0 => Tx_run, - I1 => Tx_start, - I2 => send_character, - O => ready_to_start ); - - -- Start bit enable - - start_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0190") - --synthesis translate_on - port map( I0 => Tx_bit, - I1 => Tx_stop, - I2 => ready_to_start, - I3 => Tx_start, - O => decode_Tx_start ); - - Tx_start_reg: FDE - port map ( D => decode_Tx_start, - Q => Tx_start, - CE => en_16_x_baud, - C => clk); - - - -- Run bit enable - - run_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"1540") - --synthesis translate_on - port map( I0 => count_carry(2), - I1 => Tx_bit, - I2 => Tx_start, - I3 => Tx_run, - O => decode_Tx_run ); - - Tx_run_reg: FDE - port map ( D => decode_Tx_run, - Q => Tx_run, - CE => en_16_x_baud, - C => clk); - - -- Bit rate enable - - hot_state_lut: LUT3 - --synthesis translate_off - generic map (INIT => X"94") - --synthesis translate_on - port map( I0 => Tx_stop, - I1 => ready_to_start, - I2 => Tx_bit, - O => decode_hot_state ); - - hot_state_reg: FDE - port map ( D => decode_hot_state, - Q => hot_state, - CE => en_16_x_baud, - C => clk); - - delay14_srl: SRL16E - --synthesis translate_off - generic map (INIT => X"0000") - --synthesis translate_on - port map( D => hot_state, - CE => en_16_x_baud, - CLK => clk, - A0 => '1', - A1 => '0', - A2 => '1', - A3 => '1', - Q => hot_delay ); - - Tx_bit_reg: FDE - port map ( D => hot_delay, - Q => Tx_bit, - CE => en_16_x_baud, - C => clk); - - -- Stop bit enable - - stop_lut: LUT4 - --synthesis translate_off - generic map (INIT => X"0180") - --synthesis translate_on - port map( I0 => Tx_bit, - I1 => Tx_run, - I2 => count_carry(2), - I3 => Tx_stop, - O => decode_Tx_stop ); - - Tx_stop_reg: FDE - port map ( D => decode_Tx_stop, - Q => Tx_stop, - CE => en_16_x_baud, - C => clk); - - -- Tx_complete strobe - - complete_lut: LUT2 - --synthesis translate_off - generic map (INIT => X"8") - --synthesis translate_on - port map( I0 => count_carry(2), - I1 => en_16_x_baud, - O => decode_Tx_complete ); - - Tx_complete_reg: FD - port map ( D => decode_Tx_complete, - Q => Tx_complete, - C => clk); - - -end low_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE KCUART_TX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/uart_rx.vhd b/lib/uart/uart_rx.vhd deleted file mode 100644 index 69eb70e..0000000 --- a/lib/uart/uart_rx.vhd +++ /dev/null @@ -1,146 +0,0 @@ --- UART Receiver with integral 16 byte FIFO buffer --- --- 8 bit, no parity, 1 stop bit --- --- Version : 1.00 --- Version Date : 16th October 2002 --- --- Start of design entry : 16th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for UART_RX --- -entity uart_rx is - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - read_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - buffer_data_present : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic); - end uart_rx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for UART_RX --- -architecture macro_level_definition of uart_rx is --- ------------------------------------------------------------------------------------- --- --- Components used in UART_RX and defined in subsequent entities. --- ------------------------------------------------------------------------------------- --- --- Constant (K) Compact UART Receiver --- -component kcuart_rx - Port ( serial_in : in std_logic; - data_out : out std_logic_vector(7 downto 0); - data_strobe : out std_logic; - en_16_x_baud : in std_logic; - clk : in std_logic); - end component; --- --- 'Bucket Brigade' FIFO --- -component bbfifo_16x8 - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end component; --- ------------------------------------------------------------------------------------- --- --- Signals used in UART_RX --- ------------------------------------------------------------------------------------- --- -signal uart_data_out : std_logic_vector(7 downto 0); -signal fifo_write : std_logic; --- ------------------------------------------------------------------------------------- --- --- Start of UART_RX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- 8 to 1 multiplexer to convert parallel data to serial - - kcuart: kcuart_rx - port map ( serial_in => serial_in, - data_out => uart_data_out, - data_strobe => fifo_write, - en_16_x_baud => en_16_x_baud, - clk => clk ); - - - buf: bbfifo_16x8 - port map ( data_in => uart_data_out, - data_out => data_out, - reset => reset_buffer, - write => fifo_write, - read => read_buffer, - full => buffer_full, - half_full => buffer_half_full, - data_present => buffer_data_present, - clk => clk); - -end macro_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE UART_RX.VHD --- ------------------------------------------------------------------------------------- - - diff --git a/lib/uart/uart_tx.vhd b/lib/uart/uart_tx.vhd deleted file mode 100644 index 8c4e63d..0000000 --- a/lib/uart/uart_tx.vhd +++ /dev/null @@ -1,148 +0,0 @@ --- UART Transmitter with integral 16 byte FIFO buffer --- --- 8 bit, no parity, 1 stop bit --- --- Version : 1.00 --- Version Date : 14th October 2002 --- --- Start of design entry : 14th October 2002 --- --- Ken Chapman --- Xilinx Ltd --- Benchmark House --- 203 Brooklands Road --- Weybridge --- Surrey KT13 ORH --- United Kingdom --- --- chapman@xilinx.com --- ------------------------------------------------------------------------------------- --- --- NOTICE: --- --- Copyright Xilinx, Inc. 2002. This code may be contain portions patented by other --- third parties. By providing this core as one possible implementation of a standard, --- Xilinx is making no representation that the provided implementation of this standard --- is free from any claims of infringement by any third party. Xilinx expressly --- disclaims any warranty with respect to the adequacy of the implementation, including --- but not limited to any warranty or representation that the implementation is free --- from claims of any third party. Futhermore, Xilinx is providing this core as a --- courtesy to you and suggests that you contact all third parties to obtain the --- necessary rights to use this implementation. --- ------------------------------------------------------------------------------------- --- --- Library declarations --- --- The Unisim Library is used to define Xilinx primitives. It is also used during --- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd --- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; -library unisim; -use unisim.vcomponents.all; --- ------------------------------------------------------------------------------------- --- --- Main Entity for UART_TX --- -entity uart_tx is - Port ( data_in : in std_logic_vector(7 downto 0); - write_buffer : in std_logic; - reset_buffer : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - buffer_full : out std_logic; - buffer_half_full : out std_logic; - clk : in std_logic); - end uart_tx; --- ------------------------------------------------------------------------------------- --- --- Start of Main Architecture for UART_TX --- -architecture macro_level_definition of uart_tx is --- ------------------------------------------------------------------------------------- --- --- Components used in UART_TX and defined in subsequent entities. --- ------------------------------------------------------------------------------------- --- --- Constant (K) Compact UART Transmitter --- -component kcuart_tx - Port ( data_in : in std_logic_vector(7 downto 0); - send_character : in std_logic; - en_16_x_baud : in std_logic; - serial_out : out std_logic; - Tx_complete : out std_logic; - clk : in std_logic); - end component; --- --- 'Bucket Brigade' FIFO --- -component bbfifo_16x8 - Port ( data_in : in std_logic_vector(7 downto 0); - data_out : out std_logic_vector(7 downto 0); - reset : in std_logic; - write : in std_logic; - read : in std_logic; - full : out std_logic; - half_full : out std_logic; - data_present : out std_logic; - clk : in std_logic); - end component; --- ------------------------------------------------------------------------------------- --- --- Signals used in UART_TX --- ------------------------------------------------------------------------------------- --- -signal fifo_data_out : std_logic_vector(7 downto 0); -signal fifo_data_present : std_logic; -signal fifo_read : std_logic; --- ------------------------------------------------------------------------------------- --- --- Start of UART_TX circuit description --- ------------------------------------------------------------------------------------- --- -begin - - -- 8 to 1 multiplexer to convert parallel data to serial - - kcuart: kcuart_tx - port map ( data_in => fifo_data_out, - send_character => fifo_data_present, - en_16_x_baud => en_16_x_baud, - serial_out => serial_out, - Tx_complete => fifo_read, - clk => clk); - - - buf: bbfifo_16x8 - port map ( data_in => data_in, - data_out => fifo_data_out, - reset => reset_buffer, - write => write_buffer, - read => fifo_read, - full => buffer_full, - half_full => buffer_half_full, - data_present => fifo_data_present, - clk => clk); - -end macro_level_definition; - ------------------------------------------------------------------------------------- --- --- END OF FILE UART_TX.VHD --- ------------------------------------------------------------------------------------- - -