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- decimating is now working

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git-svn-id: http://moon:8086/svn/vhdl/trunk@223 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2009-01-11 12:57:26 +00:00
parent 748bd9e52a
commit dd42e17b18
2 changed files with 93 additions and 55 deletions
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lib/filter/src/fir_semi_parallel.vhd
+37 -34
View File
@@ -81,8 +81,8 @@ architecture Behavioral of fir_semi_parallel is
signal count_array : count_array_t; signal count_array : count_array_t;
signal count0 : count_t; signal count0 : count_t;
signal ce0 : std_logic;
signal ce_array : unsigned(nstages downto 0); signal ce_array : unsigned(nstages downto 0);
signal en_array : unsigned(nstages downto 0);
signal coef_addr : unsigned(coef_addr_nbits-1 downto 0); signal coef_addr : unsigned(coef_addr_nbits-1 downto 0);
SIGNAL x : stage_array_t; SIGNAL x : stage_array_t;
@@ -90,9 +90,10 @@ architecture Behavioral of fir_semi_parallel is
SIGNAL y : stage_array_t; SIGNAL y : stage_array_t;
SIGNAL accu : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac)); SIGNAL accu : sfixed(shi(nbits_stages, nbits_stages_frac) downto slo(nbits_stages, nbits_stages_frac));
signal en : std_logic; SIGNAL act : std_logic := '0';
SIGNAL start_r : std_logic := '0';
signal accu_load : std_logic; signal accu_load : std_logic;
signal accu_ld_pipe : unsigned(nstages+input_latency+coef_latency+pipe_latency downto 0); signal accu_ld_pipe : unsigned(nstages+input_latency+coef_latency+pipe_latency-2 downto 0);
signal din_r : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); signal din_r : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
signal coef_we : unsigned(nstages-1 downto 0); signal coef_we : unsigned(nstages-1 downto 0);
@@ -111,6 +112,7 @@ begin
y(0) <= to_sfixed(0.0, y(0)); y(0) <= to_sfixed(0.0, y(0));
accu_load <= accu_ld_pipe(accu_ld_pipe'left); accu_load <= accu_ld_pipe(accu_ld_pipe'left);
start_r <= act and ce_array(ce_array'left) and not ce_array(ce_array'left-1);
din_register: din_register:
process(clk) process(clk)
@@ -128,8 +130,8 @@ accu_load_pipe:
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
accu_ld_pipe <= (others => '0'); accu_ld_pipe <= (others => '0');
elsif en = '1' then else
accu_ld_pipe <= accu_ld_pipe(accu_ld_pipe'left-1 downto 0) & ce0; accu_ld_pipe <= accu_ld_pipe(accu_ld_pipe'left-1 downto 0) & start_r;
end if; end if;
end if; end if;
end process; end process;
@@ -151,41 +153,43 @@ coef_we_gen:
end if; end if;
end process; end process;
counter: rdy_logic:
process(clk) process(clk)
variable cnt : count_t;
begin begin
if rising_edge(clk) then if rising_edge(clk) then
ce0 <= '0';
count0 <= cnt;
if rst = '1' then if rst = '1' then
rdy <= '1'; rdy <= '1';
en <= '0'; act <= '0';
cnt := count_t'high; elsif start = '1' then
elsif cnt /= count_t'high then rdy <= '0';
cnt := cnt + 1; act <= '1';
if cnt = count_t'high-1 then elsif count0 = count_t'high-2 then
rdy <= '1'; rdy <= '1';
end if; act <= '0';
else
en <= '0';
if din_vld = '1' then
en <= '1';
cnt := 0;
ce0 <= '1';
rdy <= '0';
end if;
end if; end if;
end if; end if;
end process; end process;
cnt_pipe: counter:
process(clk) process(clk)
variable cnt : count_t;
variable enable : std_logic;
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if en = '1' then if rst = '1' then
count_array <= count_array(count_array'left-1 downto 0) & count0; cnt := count_t'high;
elsif cnt /= count_t'high then
cnt := cnt + 1;
else
enable := '0';
if start_r = '1' then
enable := '1';
cnt := 0;
end if;
end if; end if;
count0 <= cnt;
count_array <= count_array(count_array'left-1 downto 0) & cnt;
en_array <= en_array(en_array'left-1 downto 0) & enable;
end if; end if;
end process; end process;
@@ -195,8 +199,8 @@ ce_pipe:
if rising_edge(clk) then if rising_edge(clk) then
if rst = '1' then if rst = '1' then
ce_array <= (others => '0'); ce_array <= (others => '0');
elsif en = '1' then else
ce_array <= ce_array(ce_array'left-1 downto 0) & ce0; ce_array <= ce_array(ce_array'left-1 downto 0) & din_vld;
end if; end if;
end if; end if;
end process; end process;
@@ -218,7 +222,7 @@ gen_coef_ram:
clka => clk, clka => clk,
clkb => clk, clkb => clk,
en_a => '1', en_a => '1',
en_b => en, en_b => en_array(i),
we_a => coef_we(i), we_a => coef_we(i),
addr_a => addr_a, addr_a => addr_a,
addr_b => addr_b, addr_b => addr_b,
@@ -247,7 +251,7 @@ gen_stages:
PORT MAP PORT MAP
( (
clk => clk, clk => clk,
ce => en, ce => en_array(i),
x_in => x(i+1), x_in => x(i+1),
y_in => y(i), y_in => y(i),
h_in => h_in, h_in => h_in,
@@ -272,7 +276,6 @@ gen_delays:
( (
rst => rst, rst => rst,
clk => clk, clk => clk,
ce => en,
shift_en => ce_array(i), shift_en => ce_array(i),
delay => count_array(i), delay => count_array(i),
din => x(i), din => x(i),
@@ -284,10 +287,10 @@ acumulator:
process(clk) process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
dout_vld <= accu_load;
if rst = '1' then if rst = '1' then
dout_vld <= '0'; dout_vld <= '0';
elsif en = '1' then elsif en_array(en_array'left) = '1' then
dout_vld <= accu_load;
if accu_load = '1' then if accu_load = '1' then
dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac)); dout <= resize(accu, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac));
accu <= y(nstages); accu <= y(nstages);
lib/filter/src/tb_fir_semi_parallel.vhd
+56 -21
View File
@@ -31,8 +31,8 @@ use work.PCK_FIO.all;
ENTITY tb_fir_semi_parallel IS ENTITY tb_fir_semi_parallel IS
Generic Generic
( (
ntaps_per_stage : integer := 16; ntaps_per_stage : integer := 32;
nstages : integer := 4; nstages : integer := 2;
nbits_in : integer := 32; nbits_in : integer := 32;
nbits_in_frac : integer := 30; nbits_in_frac : integer := 30;
nbits_stages : integer := 32; nbits_stages : integer := 32;
@@ -48,6 +48,7 @@ ARCHITECTURE behavior OF tb_fir_semi_parallel IS
--Constants --Constants
constant PERIOD : time := 10 ns; constant PERIOD : time := 10 ns;
constant nsamples : integer := 32; constant nsamples : integer := 32;
constant M : integer := 2;
--Inputs --Inputs
SIGNAL clk : std_logic := '0'; SIGNAL clk : std_logic := '0';
@@ -104,10 +105,10 @@ ARCHITECTURE behavior OF tb_fir_semi_parallel IS
0.0, 0.0,
0.0, 0.0,
0.0, 0.0,
1.0,
0.0,
0.0, 0.0,
0.0, 0.0,
0.9999,
-0.0000,
0.0, 0.0,
0.0, 0.0,
0.0, 0.0,
@@ -176,7 +177,8 @@ BEGIN
tb : PROCESS tb : PROCESS
file fi : file_t open read_mode is "wav_in.dat"; file fi : file_t open read_mode is "wav_in.dat";
variable si : sample_t; variable si : sample_t;
variable remain : integer;
variable j : integer;
BEGIN BEGIN
-- Wait 100 ns for global reset to finish -- Wait 100 ns for global reset to finish
@@ -193,43 +195,76 @@ BEGIN
h_we <= '1'; h_we <= '1';
end loop; end loop;
wait until rising_edge(clk); wait until rising_edge(clk);
h_addr <= 0; -- h_addr <= 0;
h_in <= to_sfixed(0.25, h_in); -- h_in <= to_sfixed(0.25, h_in);
h_we <= '1'; -- h_we <= '1';
wait until rising_edge(clk); -- wait until rising_edge(clk);
h_we <= '0'; h_we <= '0';
-- Write zeros -- Write zeros
for i in 0 to ntaps_per_stage*nstages-1 loop remain := ntaps_per_stage*nstages;
j := 0;
while remain /= 0 loop
wait until rising_edge(clk) and rdy = '1'; wait until rising_edge(clk) and rdy = '1';
d_in <= to_sfixed(0.0, d_in); for i in 0 to M-1 loop
din_vld <= '1'; d_in <= to_sfixed(0.0, d_in);
din_vld <= '1';
j := j + 1;
remain := remain - 1;
wait until rising_edge(clk);
end loop;
din_vld <= '0';
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
start <= '1'; start <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
din_vld <= '0';
start <= '0'; start <= '0';
end loop; end loop;
------------------------------------------ ------------------------------------------
-- Write data -- Write data
for i in 0 to nsamples-1 loop remain := nsamples;
j := 0;
while remain /= 0 loop
wait until rising_edge(clk) and rdy = '1'; wait until rising_edge(clk) and rdy = '1';
d_in <= to_sfixed(x_input(i), d_in); for i in 0 to M-1 loop
din_vld <= '1'; d_in <= to_sfixed(x_input(j), d_in);
din_vld <= '1';
j := j + 1;
remain := remain - 1;
wait until rising_edge(clk);
end loop;
din_vld <= '0';
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
start <= '1'; start <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
din_vld <= '0';
start <= '0'; start <= '0';
end loop; end loop;
-- Write zeros -- Write zeros
for i in 0 to 99 loop remain := 100;
j := 0;
while remain /= 0 loop
wait until rising_edge(clk) and rdy = '1'; wait until rising_edge(clk) and rdy = '1';
d_in <= to_sfixed(0.0, d_in); for i in 0 to M-1 loop
din_vld <= '1'; d_in <= to_sfixed(0.0, d_in);
din_vld <= '1';
j := j + 1;
remain := remain - 1;
wait until rising_edge(clk);
end loop;
din_vld <= '0';
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
-- wait until rising_edge(clk);
start <= '1'; start <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
din_vld <= '0';
start <= '0'; start <= '0';
end loop; end loop;