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- Ratio and gain are set at synthesis time (simpler)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@176 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-12-30 18:56:12 +00:00
parent 7c7fc19162
commit dc63b8df76
5 changed files with 48 additions and 120 deletions
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lib/radio/ddc/src/ddc.vhd
+12 -32
View File
@@ -33,10 +33,8 @@ ENTITY ddc IS
lo_nbits_phase : integer := 20; lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20; lo_nbits_freq : integer := 20;
cic_nstages : integer := 3; cic_nstages : integer := 3;
cic_max_ratio : integer := 4096; cic_ratio : integer := 64;
cic_max_diff_delay : integer := 2; cic_scale_nbits : integer := 18
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32
); );
PORT PORT
( (
@@ -46,9 +44,6 @@ ENTITY ddc IS
lo_nco_en : in std_logic; lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0); lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed; din_i : in sfixed;
din_q : in sfixed; din_q : in sfixed;
dout_i : out sfixed; dout_i : out sfixed;
@@ -92,10 +87,8 @@ ARCHITECTURE behavior OF ddc IS
GENERIC GENERIC
( (
nstages : integer; nstages : integer;
ratio_max : integer; ratio : integer;
scale_nbits_min : integer; scale_nbits : integer;
scale_nbits_max : integer;
max_diff_delay : integer;
in_width : integer; in_width : integer;
in_width_frac : integer; in_width_frac : integer;
out_width : integer; out_width : integer;
@@ -106,9 +99,6 @@ ARCHITECTURE behavior OF ddc IS
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
vld_in : in std_logic; vld_in : in std_logic;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed; din : in sfixed;
dout : out sfixed; dout : out sfixed;
vld_out : out std_logic vld_out : out std_logic
@@ -122,8 +112,8 @@ ARCHITECTURE behavior OF ddc IS
constant cic_nbits_in : integer := lo_nbits_out; constant cic_nbits_in : integer := lo_nbits_out;
constant cic_nbits_in_frac : integer := lo_nbits_out_frac; constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
constant cic_nbits_out : integer := nbits_out; constant cic_nbits_out : integer := nbits_out+1;
constant cic_nbits_out_frac : integer := nbits_out_frac; constant cic_nbits_out_frac : integer := nbits_out_frac+1;
SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac)); SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
@@ -137,8 +127,8 @@ ARCHITECTURE behavior OF ddc IS
BEGIN BEGIN
dout_vld <= dec_dout_vld_i and dec_dout_vld_q; dout_vld <= dec_dout_vld_i and dec_dout_vld_q;
dout_i <= dec_dout_i; dout_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_q <= dec_dout_q; dout_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-- Instantiate the Unit Under Test (UUT) -- Instantiate the Unit Under Test (UUT)
inst_mixer: mix inst_mixer: mix
@@ -171,10 +161,8 @@ BEGIN
GENERIC MAP GENERIC MAP
( (
nstages => cic_nstages, nstages => cic_nstages,
ratio_max => cic_max_ratio, ratio => cic_ratio,
scale_nbits_min => cic_scale_nbits_min, scale_nbits => cic_scale_nbits,
scale_nbits_max => cic_scale_nbits_max,
max_diff_delay => cic_max_diff_delay,
in_width => cic_nbits_in, in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac, in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out, out_width => cic_nbits_out,
@@ -185,9 +173,6 @@ BEGIN
clk => clk, clk => clk,
rst => rst, rst => rst,
vld_in => mix_dout_vld, vld_in => mix_dout_vld,
ratio => cic_ratio,
diff_delay => cic_diff_delay,
shift_in => cic_shift_in,
din => mix_dout_i, din => mix_dout_i,
dout => dec_dout_i, dout => dec_dout_i,
vld_out => dec_dout_vld_i vld_out => dec_dout_vld_i
@@ -197,10 +182,8 @@ BEGIN
GENERIC MAP GENERIC MAP
( (
nstages => cic_nstages, nstages => cic_nstages,
ratio_max => cic_max_ratio, ratio => cic_ratio,
scale_nbits_min => cic_scale_nbits_min, scale_nbits => cic_scale_nbits,
scale_nbits_max => cic_scale_nbits_max,
max_diff_delay => cic_max_diff_delay,
in_width => cic_nbits_in, in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac, in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out, out_width => cic_nbits_out,
@@ -211,9 +194,6 @@ BEGIN
clk => clk, clk => clk,
rst => rst, rst => rst,
vld_in => mix_dout_vld, vld_in => mix_dout_vld,
ratio => cic_ratio,
diff_delay => cic_diff_delay,
shift_in => cic_shift_in,
din => mix_dout_q, din => mix_dout_q,
dout => dec_dout_q, dout => dec_dout_q,
vld_out => dec_dout_vld_q vld_out => dec_dout_vld_q
lib/radio/ddc/src/syn_ddc.vhd
+8 -23
View File
@@ -29,15 +29,13 @@ use work.cordic_pkg.all;
( (
nbits_in : integer := 18; nbits_in : integer := 18;
nbits_in_frac : integer := 16; nbits_in_frac : integer := 16;
nbits_out : integer := 18; nbits_out : integer := 24;
nbits_out_frac : integer := 16; nbits_out_frac : integer := 22;
lo_nbits_phase : integer := 20; lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20; lo_nbits_freq : integer := 20;
cic_nstages : integer := 3; cic_nstages : integer := 3;
cic_max_ratio : integer := 1024; cic_ratio : integer := 64;
cic_max_diff_delay : integer := 2; cic_scale_nbits : integer := 18
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32
); );
PORT PORT
( (
@@ -47,9 +45,6 @@ use work.cordic_pkg.all;
lo_nco_en : in std_logic; lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0); lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in signed(nbits_in-1 downto 0); din_i : in signed(nbits_in-1 downto 0);
din_q : in signed(nbits_in-1 downto 0); din_q : in signed(nbits_in-1 downto 0);
dout_i : out signed(nbits_out-1 downto 0); dout_i : out signed(nbits_out-1 downto 0);
@@ -72,10 +67,8 @@ ARCHITECTURE behavior OF syn_ddc IS
lo_nbits_phase : integer; lo_nbits_phase : integer;
lo_nbits_freq : integer; lo_nbits_freq : integer;
cic_nstages : integer; cic_nstages : integer;
cic_max_ratio : integer; cic_ratio : integer;
cic_max_diff_delay : integer; cic_scale_nbits : integer
cic_scale_nbits_min : integer;
cic_scale_nbits_max : integer
); );
PORT PORT
( (
@@ -85,9 +78,6 @@ ARCHITECTURE behavior OF syn_ddc IS
lo_nco_en : in std_logic; lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0); lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed; din_i : in sfixed;
din_q : in sfixed; din_q : in sfixed;
dout_i : out sfixed; dout_i : out sfixed;
@@ -116,10 +106,8 @@ BEGIN
lo_nbits_phase => lo_nbits_phase, lo_nbits_phase => lo_nbits_phase,
lo_nbits_freq => lo_nbits_freq, lo_nbits_freq => lo_nbits_freq,
cic_nstages => cic_nstages, cic_nstages => cic_nstages,
cic_max_ratio => cic_max_ratio, cic_ratio => cic_ratio,
cic_max_diff_delay => cic_max_diff_delay, cic_scale_nbits => cic_scale_nbits
cic_scale_nbits_min => cic_scale_nbits_min,
cic_scale_nbits_max => cic_scale_nbits_max
) )
PORT MAP PORT MAP
( (
@@ -129,9 +117,6 @@ BEGIN
lo_nco_en => lo_nco_en, lo_nco_en => lo_nco_en,
lo_freq_in => lo_freq_in, lo_freq_in => lo_freq_in,
lo_phase_in => lo_phase_in, lo_phase_in => lo_phase_in,
cic_ratio => cic_ratio,
cic_diff_delay => cic_diff_delay,
cic_shift_in => cic_shift_in,
din_i => ddc_din_i, din_i => ddc_din_i,
din_q => ddc_din_q, din_q => ddc_din_q,
dout_i => ddc_dout_i, dout_i => ddc_dout_i,
lib/radio/ddc/src/tb_ddc.vhd
+10 -25
View File
@@ -31,15 +31,13 @@ ENTITY tb_ddc IS
( (
nbits_in : integer := 16; nbits_in : integer := 16;
nbits_in_frac : integer := 14; nbits_in_frac : integer := 14;
nbits_out : integer := 18; nbits_out : integer := 24;
nbits_out_frac : integer := 16; nbits_out_frac : integer := 22;
lo_nbits_phase : integer := 20; lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20; lo_nbits_freq : integer := 20;
cic_nstages : integer := 3; cic_nstages : integer := 3;
cic_max_ratio : integer := 4096; cic_ratio : integer := 50;
cic_max_diff_delay : integer := 1; cic_scale_nbits : integer := 16;
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32;
rfgen_nbits_phase : integer := 20; rfgen_nbits_phase : integer := 20;
rfgen_nbits_freq : integer := 20 rfgen_nbits_freq : integer := 20
); );
@@ -58,10 +56,8 @@ ARCHITECTURE behavior OF tb_ddc IS
lo_nbits_phase : integer; lo_nbits_phase : integer;
lo_nbits_freq : integer; lo_nbits_freq : integer;
cic_nstages : integer; cic_nstages : integer;
cic_max_ratio : integer; cic_ratio : integer;
cic_max_diff_delay : integer; cic_scale_nbits : integer
cic_scale_nbits_min : integer;
cic_scale_nbits_max : integer
); );
PORT PORT
( (
@@ -71,9 +67,6 @@ ARCHITECTURE behavior OF tb_ddc IS
lo_nco_en : in std_logic; lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0); lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0); lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed; din_i : in sfixed;
din_q : in sfixed; din_q : in sfixed;
dout_i : out sfixed; dout_i : out sfixed;
@@ -131,9 +124,6 @@ ARCHITECTURE behavior OF tb_ddc IS
SIGNAL ddc_nco_en : std_logic := '0'; SIGNAL ddc_nco_en : std_logic := '0';
SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0'); SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0'); SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
SIGNAL ddc_diff_delay : natural := 1;
SIGNAL ddc_ratio : natural := 64;
SIGNAL ddc_shift_in : natural := 18-cic_scale_nbits_min;
--Outputs --Outputs
SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac)); SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
@@ -188,10 +178,8 @@ BEGIN
lo_nbits_phase => lo_nbits_phase, lo_nbits_phase => lo_nbits_phase,
lo_nbits_freq => lo_nbits_freq, lo_nbits_freq => lo_nbits_freq,
cic_nstages => cic_nstages, cic_nstages => cic_nstages,
cic_max_ratio => cic_max_ratio, cic_ratio => cic_ratio,
cic_max_diff_delay => cic_max_diff_delay, cic_scale_nbits => cic_scale_nbits
cic_scale_nbits_min => cic_scale_nbits_min,
cic_scale_nbits_max => cic_scale_nbits_max
) )
PORT MAP PORT MAP
( (
@@ -201,9 +189,6 @@ BEGIN
lo_nco_en => ddc_nco_en, lo_nco_en => ddc_nco_en,
lo_freq_in => ddc_freq_in, lo_freq_in => ddc_freq_in,
lo_phase_in => ddc_phase_in, lo_phase_in => ddc_phase_in,
cic_ratio => ddc_ratio,
cic_diff_delay => ddc_diff_delay,
cic_shift_in => ddc_shift_in,
din_i => ddc_din_i, din_i => ddc_din_i,
din_q => ddc_din_q, din_q => ddc_din_q,
dout_i => ddc_dout_i, dout_i => ddc_dout_i,
@@ -310,7 +295,7 @@ BEGIN
rfgen_q_out_f <= to_real(rfgen_dout_q); rfgen_q_out_f <= to_real(rfgen_dout_q);
tb : PROCESS tb : PROCESS
file RESULT_FREQ: text open write_mode is "freq.txt"; file RESULT_FREQ: text open write_mode is "ratio.txt";
variable L: line; variable L: line;
BEGIN BEGIN
@@ -319,7 +304,7 @@ BEGIN
wait for 4*PERIOD; wait for 4*PERIOD;
rst <= '0'; rst <= '0';
fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo)); fprint(RESULT_FREQ, L,"%s\n", natural'image(cic_ratio));
wait for 2*PERIOD; wait for 2*PERIOD;
------------------------------------------- -------------------------------------------
lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
+12 -19
View File
@@ -28,10 +28,9 @@ ENTITY cic_decim_pipe IS
Generic Generic
( (
nstages : integer := 3; nstages : integer := 3;
max_diff_delay : integer := 2; diff_delay : integer := 1;
ratio_max : integer := 64; ratio : integer := 64;
scale_nbits_min : integer := 9; scale_nbits : integer := 9;
scale_nbits_max : integer := 24;
in_width : integer := 32; in_width : integer := 32;
in_width_frac : integer := 20; in_width_frac : integer := 20;
out_width : integer := 32; out_width : integer := 32;
@@ -42,9 +41,6 @@ ENTITY cic_decim_pipe IS
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
vld_in : in std_logic; vld_in : in std_logic;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed; din : in sfixed;
dout : out sfixed; dout : out sfixed;
vld_out : out std_logic vld_out : out std_logic
@@ -89,14 +85,13 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
); );
END COMPONENT; END COMPONENT;
constant min_gain_bits : natural := scale_nbits_min; constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio)**real(nstages)));
constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio_max)**real(nstages)));
constant integ_nbits : natural := in_width + max_gain_bits; constant integ_nbits : natural := in_width + max_gain_bits;
constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac); constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac);
constant comb_nbits : natural := out_width + 1; constant comb_nbits : natural := out_width+1;
constant comb_nbits_frac : natural := out_width_frac + 1; constant comb_nbits_frac : natural := out_width_frac+1;
subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac)); subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
type word_i_pipe_t is array (0 to nstages) of word_i_t; type word_i_pipe_t is array (0 to nstages) of word_i_t;
@@ -112,12 +107,11 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
signal vld_c_pipe : unsigned (0 to nstages); signal vld_c_pipe : unsigned (0 to nstages);
signal vld_c : std_logic; signal vld_c : std_logic;
signal resample_cnt : natural range 1 to ratio_max; signal resample_cnt : natural range 1 to ratio;
signal resample_vld : std_logic; signal resample_vld : std_logic;
BEGIN BEGIN
assert false report "min_gain_bits = " & natural'image(min_gain_bits) & "." severity note;
assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note; assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note;
assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note; assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note;
assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note; assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note;
@@ -132,9 +126,8 @@ input_scale:
begin begin
if rising_edge(clk) then if rising_edge(clk) then
x := resize(din, x); x := resize(din, x);
xs := x sra min_gain_bits; xs := x sra scale_nbits;
xsi := xs sra shift_in; word_i_pipe(0) <= xs;
word_i_pipe(0) <= xsi;
vld_i_pipe(0) <= vld_in; vld_i_pipe(0) <= vld_in;
end if; end if;
end process; end process;
@@ -159,7 +152,7 @@ input_scale:
); );
end generate; end generate;
word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0)); word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0), fixed_wrap, fixed_truncate);
vld_c_pipe(0) <= resample_vld; vld_c_pipe(0) <= resample_vld;
vld_c <= vld_c_pipe(nstages); vld_c <= vld_c_pipe(nstages);
@@ -171,7 +164,7 @@ input_scale:
inst_cic_c_pipe: cic_c_pipe inst_cic_c_pipe: cic_c_pipe
GENERIC MAP GENERIC MAP
( (
max_diff_delay => max_diff_delay, max_diff_delay => diff_delay,
max_width => comb_nbits, max_width => comb_nbits,
max_width_frac => comb_nbits_frac max_width_frac => comb_nbits_frac
) )
lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
+6 -21
View File
@@ -29,10 +29,8 @@ ENTITY tb_cic_decim_pipe IS
Generic Generic
( (
nstages : integer := 3; nstages : integer := 3;
ratio_max : integer := 1024; ratio : integer := 64;
scale_nbits_min : integer := 9; scale_nbits : integer := 18;
scale_nbits_max : integer := 32;
max_diff_delay : integer := 2;
in_width : integer := 18; in_width : integer := 18;
in_width_frac : integer := 16; in_width_frac : integer := 16;
out_width : integer := 18; out_width : integer := 18;
@@ -47,10 +45,8 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
GENERIC GENERIC
( (
nstages : integer; nstages : integer;
ratio_max : integer; ratio : integer;
scale_nbits_min : integer; scale_nbits : integer;
scale_nbits_max : integer;
max_diff_delay : integer;
in_width : integer; in_width : integer;
in_width_frac : integer; in_width_frac : integer;
out_width : integer; out_width : integer;
@@ -61,9 +57,6 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
vld_in : in std_logic; vld_in : in std_logic;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed; din : in sfixed;
dout : out sfixed; dout : out sfixed;
vld_out : out std_logic vld_out : out std_logic
@@ -79,9 +72,6 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
SIGNAL srst : std_logic := '1'; SIGNAL srst : std_logic := '1';
SIGNAL vld_in : std_logic := '0'; SIGNAL vld_in : std_logic := '0';
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac)); SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
SIGNAL diff_delay : natural := 1;
SIGNAL ratio : natural := 64;
SIGNAL shift_in : natural := 18-scale_nbits_min;
--Outputs --Outputs
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac)); SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
@@ -101,10 +91,8 @@ BEGIN
GENERIC MAP GENERIC MAP
( (
nstages => nstages, nstages => nstages,
ratio_max => ratio_max, ratio => ratio,
scale_nbits_min => scale_nbits_min, scale_nbits => scale_nbits,
scale_nbits_max => scale_nbits_max,
max_diff_delay => max_diff_delay,
in_width => in_width, in_width => in_width,
in_width_frac => in_width_frac, in_width_frac => in_width_frac,
out_width => out_width, out_width => out_width,
@@ -115,9 +103,6 @@ BEGIN
clk => clk, clk => clk,
rst => srst, rst => srst,
vld_in => vld_in, vld_in => vld_in,
ratio => ratio,
diff_delay => diff_delay,
shift_in => shift_in,
din => din, din => din,
dout => dout, dout => dout,
vld_out => vld_out vld_out => vld_out