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- Ratio and gain are set at synthesis time (simpler)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@176 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-12-30 18:56:12 +00:00
parent 7c7fc19162
commit dc63b8df76
5 changed files with 48 additions and 120 deletions
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lib/radio/decimator/CIC/src/cic_decim_pipe.vhd
+12 -19
View File
@@ -28,10 +28,9 @@ ENTITY cic_decim_pipe IS
Generic
(
nstages : integer := 3;
max_diff_delay : integer := 2;
ratio_max : integer := 64;
scale_nbits_min : integer := 9;
scale_nbits_max : integer := 24;
diff_delay : integer := 1;
ratio : integer := 64;
scale_nbits : integer := 9;
in_width : integer := 32;
in_width_frac : integer := 20;
out_width : integer := 32;
@@ -42,9 +41,6 @@ ENTITY cic_decim_pipe IS
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
@@ -89,14 +85,13 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
);
END COMPONENT;
constant min_gain_bits : natural := scale_nbits_min;
constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio_max)**real(nstages)));
constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio)**real(nstages)));
constant integ_nbits : natural := in_width + max_gain_bits;
constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac);
constant comb_nbits : natural := out_width + 1;
constant comb_nbits_frac : natural := out_width_frac + 1;
constant comb_nbits : natural := out_width+1;
constant comb_nbits_frac : natural := out_width_frac+1;
subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
type word_i_pipe_t is array (0 to nstages) of word_i_t;
@@ -112,12 +107,11 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
signal vld_c_pipe : unsigned (0 to nstages);
signal vld_c : std_logic;
signal resample_cnt : natural range 1 to ratio_max;
signal resample_cnt : natural range 1 to ratio;
signal resample_vld : std_logic;
BEGIN
assert false report "min_gain_bits = " & natural'image(min_gain_bits) & "." severity note;
assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note;
assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note;
assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note;
@@ -132,9 +126,8 @@ input_scale:
begin
if rising_edge(clk) then
x := resize(din, x);
xs := x sra min_gain_bits;
xsi := xs sra shift_in;
word_i_pipe(0) <= xsi;
xs := x sra scale_nbits;
word_i_pipe(0) <= xs;
vld_i_pipe(0) <= vld_in;
end if;
end process;
@@ -159,7 +152,7 @@ input_scale:
);
end generate;
word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0));
word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0), fixed_wrap, fixed_truncate);
vld_c_pipe(0) <= resample_vld;
vld_c <= vld_c_pipe(nstages);
@@ -171,7 +164,7 @@ input_scale:
inst_cic_c_pipe: cic_c_pipe
GENERIC MAP
(
max_diff_delay => max_diff_delay,
max_diff_delay => diff_delay,
max_width => comb_nbits,
max_width_frac => comb_nbits_frac
)
lib/radio/decimator/CIC/src/tb_cic_decim_pipe.vhd
+6 -21
View File
@@ -29,10 +29,8 @@ ENTITY tb_cic_decim_pipe IS
Generic
(
nstages : integer := 3;
ratio_max : integer := 1024;
scale_nbits_min : integer := 9;
scale_nbits_max : integer := 32;
max_diff_delay : integer := 2;
ratio : integer := 64;
scale_nbits : integer := 18;
in_width : integer := 18;
in_width_frac : integer := 16;
out_width : integer := 18;
@@ -47,10 +45,8 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
GENERIC
(
nstages : integer;
ratio_max : integer;
scale_nbits_min : integer;
scale_nbits_max : integer;
max_diff_delay : integer;
ratio : integer;
scale_nbits : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
@@ -61,9 +57,6 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
@@ -79,9 +72,6 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
SIGNAL srst : std_logic := '1';
SIGNAL vld_in : std_logic := '0';
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
SIGNAL diff_delay : natural := 1;
SIGNAL ratio : natural := 64;
SIGNAL shift_in : natural := 18-scale_nbits_min;
--Outputs
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
@@ -101,10 +91,8 @@ BEGIN
GENERIC MAP
(
nstages => nstages,
ratio_max => ratio_max,
scale_nbits_min => scale_nbits_min,
scale_nbits_max => scale_nbits_max,
max_diff_delay => max_diff_delay,
ratio => ratio,
scale_nbits => scale_nbits,
in_width => in_width,
in_width_frac => in_width_frac,
out_width => out_width,
@@ -115,9 +103,6 @@ BEGIN
clk => clk,
rst => srst,
vld_in => vld_in,
ratio => ratio,
diff_delay => diff_delay,
shift_in => shift_in,
din => din,
dout => dout,
vld_out => vld_out