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- Ratio and gain are set at synthesis time (simpler)

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git-svn-id: http://moon:8086/svn/vhdl/trunk@176 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
jens
2008-12-30 18:56:12 +00:00
parent 7c7fc19162
commit dc63b8df76
5 changed files with 48 additions and 120 deletions
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lib/radio/ddc/src/ddc.vhd
+12 -32
View File
@@ -33,10 +33,8 @@ ENTITY ddc IS
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
cic_nstages : integer := 3;
cic_max_ratio : integer := 4096;
cic_max_diff_delay : integer := 2;
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32
cic_ratio : integer := 64;
cic_scale_nbits : integer := 18
);
PORT
(
@@ -46,9 +44,6 @@ ENTITY ddc IS
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
@@ -92,10 +87,8 @@ ARCHITECTURE behavior OF ddc IS
GENERIC
(
nstages : integer;
ratio_max : integer;
scale_nbits_min : integer;
scale_nbits_max : integer;
max_diff_delay : integer;
ratio : integer;
scale_nbits : integer;
in_width : integer;
in_width_frac : integer;
out_width : integer;
@@ -106,9 +99,6 @@ ARCHITECTURE behavior OF ddc IS
clk : in std_logic;
rst : in std_logic;
vld_in : in std_logic;
ratio : in natural range 1 to ratio_max;
diff_delay : in natural range 1 to max_diff_delay;
shift_in : in natural range 0 to scale_nbits_max;
din : in sfixed;
dout : out sfixed;
vld_out : out std_logic
@@ -122,8 +112,8 @@ ARCHITECTURE behavior OF ddc IS
constant cic_nbits_in : integer := lo_nbits_out;
constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
constant cic_nbits_out : integer := nbits_out;
constant cic_nbits_out_frac : integer := nbits_out_frac;
constant cic_nbits_out : integer := nbits_out+1;
constant cic_nbits_out_frac : integer := nbits_out_frac+1;
SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
@@ -137,8 +127,8 @@ ARCHITECTURE behavior OF ddc IS
BEGIN
dout_vld <= dec_dout_vld_i and dec_dout_vld_q;
dout_i <= dec_dout_i;
dout_q <= dec_dout_q;
dout_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
dout_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
-- Instantiate the Unit Under Test (UUT)
inst_mixer: mix
@@ -171,10 +161,8 @@ BEGIN
GENERIC MAP
(
nstages => cic_nstages,
ratio_max => cic_max_ratio,
scale_nbits_min => cic_scale_nbits_min,
scale_nbits_max => cic_scale_nbits_max,
max_diff_delay => cic_max_diff_delay,
ratio => cic_ratio,
scale_nbits => cic_scale_nbits,
in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out,
@@ -185,9 +173,6 @@ BEGIN
clk => clk,
rst => rst,
vld_in => mix_dout_vld,
ratio => cic_ratio,
diff_delay => cic_diff_delay,
shift_in => cic_shift_in,
din => mix_dout_i,
dout => dec_dout_i,
vld_out => dec_dout_vld_i
@@ -197,10 +182,8 @@ BEGIN
GENERIC MAP
(
nstages => cic_nstages,
ratio_max => cic_max_ratio,
scale_nbits_min => cic_scale_nbits_min,
scale_nbits_max => cic_scale_nbits_max,
max_diff_delay => cic_max_diff_delay,
ratio => cic_ratio,
scale_nbits => cic_scale_nbits,
in_width => cic_nbits_in,
in_width_frac => cic_nbits_in_frac,
out_width => cic_nbits_out,
@@ -211,9 +194,6 @@ BEGIN
clk => clk,
rst => rst,
vld_in => mix_dout_vld,
ratio => cic_ratio,
diff_delay => cic_diff_delay,
shift_in => cic_shift_in,
din => mix_dout_q,
dout => dec_dout_q,
vld_out => dec_dout_vld_q
lib/radio/ddc/src/syn_ddc.vhd
+8 -23
View File
@@ -29,15 +29,13 @@ use work.cordic_pkg.all;
(
nbits_in : integer := 18;
nbits_in_frac : integer := 16;
nbits_out : integer := 18;
nbits_out_frac : integer := 16;
nbits_out : integer := 24;
nbits_out_frac : integer := 22;
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
cic_nstages : integer := 3;
cic_max_ratio : integer := 1024;
cic_max_diff_delay : integer := 2;
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32
cic_ratio : integer := 64;
cic_scale_nbits : integer := 18
);
PORT
(
@@ -47,9 +45,6 @@ use work.cordic_pkg.all;
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in signed(nbits_in-1 downto 0);
din_q : in signed(nbits_in-1 downto 0);
dout_i : out signed(nbits_out-1 downto 0);
@@ -72,10 +67,8 @@ ARCHITECTURE behavior OF syn_ddc IS
lo_nbits_phase : integer;
lo_nbits_freq : integer;
cic_nstages : integer;
cic_max_ratio : integer;
cic_max_diff_delay : integer;
cic_scale_nbits_min : integer;
cic_scale_nbits_max : integer
cic_ratio : integer;
cic_scale_nbits : integer
);
PORT
(
@@ -85,9 +78,6 @@ ARCHITECTURE behavior OF syn_ddc IS
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
@@ -116,10 +106,8 @@ BEGIN
lo_nbits_phase => lo_nbits_phase,
lo_nbits_freq => lo_nbits_freq,
cic_nstages => cic_nstages,
cic_max_ratio => cic_max_ratio,
cic_max_diff_delay => cic_max_diff_delay,
cic_scale_nbits_min => cic_scale_nbits_min,
cic_scale_nbits_max => cic_scale_nbits_max
cic_ratio => cic_ratio,
cic_scale_nbits => cic_scale_nbits
)
PORT MAP
(
@@ -129,9 +117,6 @@ BEGIN
lo_nco_en => lo_nco_en,
lo_freq_in => lo_freq_in,
lo_phase_in => lo_phase_in,
cic_ratio => cic_ratio,
cic_diff_delay => cic_diff_delay,
cic_shift_in => cic_shift_in,
din_i => ddc_din_i,
din_q => ddc_din_q,
dout_i => ddc_dout_i,
lib/radio/ddc/src/tb_ddc.vhd
+10 -25
View File
@@ -31,15 +31,13 @@ ENTITY tb_ddc IS
(
nbits_in : integer := 16;
nbits_in_frac : integer := 14;
nbits_out : integer := 18;
nbits_out_frac : integer := 16;
nbits_out : integer := 24;
nbits_out_frac : integer := 22;
lo_nbits_phase : integer := 20;
lo_nbits_freq : integer := 20;
cic_nstages : integer := 3;
cic_max_ratio : integer := 4096;
cic_max_diff_delay : integer := 1;
cic_scale_nbits_min : integer := 9;
cic_scale_nbits_max : integer := 32;
cic_ratio : integer := 50;
cic_scale_nbits : integer := 16;
rfgen_nbits_phase : integer := 20;
rfgen_nbits_freq : integer := 20
);
@@ -58,10 +56,8 @@ ARCHITECTURE behavior OF tb_ddc IS
lo_nbits_phase : integer;
lo_nbits_freq : integer;
cic_nstages : integer;
cic_max_ratio : integer;
cic_max_diff_delay : integer;
cic_scale_nbits_min : integer;
cic_scale_nbits_max : integer
cic_ratio : integer;
cic_scale_nbits : integer
);
PORT
(
@@ -71,9 +67,6 @@ ARCHITECTURE behavior OF tb_ddc IS
lo_nco_en : in std_logic;
lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
cic_ratio : in natural range 1 to cic_max_ratio;
cic_diff_delay : in natural range 1 to cic_max_diff_delay;
cic_shift_in : in natural range 0 to cic_scale_nbits_max;
din_i : in sfixed;
din_q : in sfixed;
dout_i : out sfixed;
@@ -131,9 +124,6 @@ ARCHITECTURE behavior OF tb_ddc IS
SIGNAL ddc_nco_en : std_logic := '0';
SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
SIGNAL ddc_diff_delay : natural := 1;
SIGNAL ddc_ratio : natural := 64;
SIGNAL ddc_shift_in : natural := 18-cic_scale_nbits_min;
--Outputs
SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
@@ -188,10 +178,8 @@ BEGIN
lo_nbits_phase => lo_nbits_phase,
lo_nbits_freq => lo_nbits_freq,
cic_nstages => cic_nstages,
cic_max_ratio => cic_max_ratio,
cic_max_diff_delay => cic_max_diff_delay,
cic_scale_nbits_min => cic_scale_nbits_min,
cic_scale_nbits_max => cic_scale_nbits_max
cic_ratio => cic_ratio,
cic_scale_nbits => cic_scale_nbits
)
PORT MAP
(
@@ -201,9 +189,6 @@ BEGIN
lo_nco_en => ddc_nco_en,
lo_freq_in => ddc_freq_in,
lo_phase_in => ddc_phase_in,
cic_ratio => ddc_ratio,
cic_diff_delay => ddc_diff_delay,
cic_shift_in => ddc_shift_in,
din_i => ddc_din_i,
din_q => ddc_din_q,
dout_i => ddc_dout_i,
@@ -310,7 +295,7 @@ BEGIN
rfgen_q_out_f <= to_real(rfgen_dout_q);
tb : PROCESS
file RESULT_FREQ: text open write_mode is "freq.txt";
file RESULT_FREQ: text open write_mode is "ratio.txt";
variable L: line;
BEGIN
@@ -319,7 +304,7 @@ BEGIN
wait for 4*PERIOD;
rst <= '0';
fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo));
fprint(RESULT_FREQ, L,"%s\n", natural'image(cic_ratio));
wait for 2*PERIOD;
-------------------------------------------