- Ratio and gain are set at synthesis time (simpler)
git-svn-id: http://moon:8086/svn/vhdl/trunk@176 cc03376c-175c-47c8-b038-4cd826a8556b
This commit is contained in:
+12
-32
@@ -33,10 +33,8 @@ ENTITY ddc IS
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lo_nbits_phase : integer := 20;
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lo_nbits_freq : integer := 20;
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cic_nstages : integer := 3;
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cic_max_ratio : integer := 4096;
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cic_max_diff_delay : integer := 2;
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cic_scale_nbits_min : integer := 9;
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cic_scale_nbits_max : integer := 32
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cic_ratio : integer := 64;
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cic_scale_nbits : integer := 18
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);
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PORT
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(
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@@ -46,9 +44,6 @@ ENTITY ddc IS
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lo_nco_en : in std_logic;
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lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
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lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
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cic_ratio : in natural range 1 to cic_max_ratio;
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cic_diff_delay : in natural range 1 to cic_max_diff_delay;
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cic_shift_in : in natural range 0 to cic_scale_nbits_max;
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din_i : in sfixed;
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din_q : in sfixed;
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dout_i : out sfixed;
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@@ -92,10 +87,8 @@ ARCHITECTURE behavior OF ddc IS
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GENERIC
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(
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nstages : integer;
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ratio_max : integer;
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scale_nbits_min : integer;
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scale_nbits_max : integer;
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max_diff_delay : integer;
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ratio : integer;
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scale_nbits : integer;
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in_width : integer;
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in_width_frac : integer;
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out_width : integer;
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@@ -106,9 +99,6 @@ ARCHITECTURE behavior OF ddc IS
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clk : in std_logic;
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rst : in std_logic;
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vld_in : in std_logic;
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ratio : in natural range 1 to ratio_max;
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diff_delay : in natural range 1 to max_diff_delay;
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shift_in : in natural range 0 to scale_nbits_max;
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din : in sfixed;
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dout : out sfixed;
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vld_out : out std_logic
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@@ -122,8 +112,8 @@ ARCHITECTURE behavior OF ddc IS
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constant cic_nbits_in : integer := lo_nbits_out;
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constant cic_nbits_in_frac : integer := lo_nbits_out_frac;
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constant cic_nbits_out : integer := nbits_out;
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constant cic_nbits_out_frac : integer := nbits_out_frac;
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constant cic_nbits_out : integer := nbits_out+1;
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constant cic_nbits_out_frac : integer := nbits_out_frac+1;
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SIGNAL mix_dout_i : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
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SIGNAL mix_dout_q : sfixed(shi(lo_nbits_out, lo_nbits_out_frac) downto slo(lo_nbits_out, lo_nbits_out_frac));
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@@ -137,8 +127,8 @@ ARCHITECTURE behavior OF ddc IS
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BEGIN
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dout_vld <= dec_dout_vld_i and dec_dout_vld_q;
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dout_i <= dec_dout_i;
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dout_q <= dec_dout_q;
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dout_i <= resize(dec_dout_i, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
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dout_q <= resize(dec_dout_q, shi(nbits_out, nbits_out_frac), slo(nbits_out, nbits_out_frac), fixed_wrap, fixed_round);
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-- Instantiate the Unit Under Test (UUT)
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inst_mixer: mix
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@@ -171,10 +161,8 @@ BEGIN
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GENERIC MAP
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(
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nstages => cic_nstages,
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ratio_max => cic_max_ratio,
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scale_nbits_min => cic_scale_nbits_min,
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scale_nbits_max => cic_scale_nbits_max,
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max_diff_delay => cic_max_diff_delay,
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ratio => cic_ratio,
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scale_nbits => cic_scale_nbits,
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in_width => cic_nbits_in,
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in_width_frac => cic_nbits_in_frac,
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out_width => cic_nbits_out,
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@@ -185,9 +173,6 @@ BEGIN
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clk => clk,
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rst => rst,
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vld_in => mix_dout_vld,
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ratio => cic_ratio,
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diff_delay => cic_diff_delay,
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shift_in => cic_shift_in,
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din => mix_dout_i,
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dout => dec_dout_i,
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vld_out => dec_dout_vld_i
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@@ -197,10 +182,8 @@ BEGIN
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GENERIC MAP
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(
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nstages => cic_nstages,
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ratio_max => cic_max_ratio,
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scale_nbits_min => cic_scale_nbits_min,
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scale_nbits_max => cic_scale_nbits_max,
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max_diff_delay => cic_max_diff_delay,
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ratio => cic_ratio,
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scale_nbits => cic_scale_nbits,
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in_width => cic_nbits_in,
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in_width_frac => cic_nbits_in_frac,
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out_width => cic_nbits_out,
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@@ -211,9 +194,6 @@ BEGIN
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clk => clk,
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rst => rst,
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vld_in => mix_dout_vld,
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ratio => cic_ratio,
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diff_delay => cic_diff_delay,
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shift_in => cic_shift_in,
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din => mix_dout_q,
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dout => dec_dout_q,
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vld_out => dec_dout_vld_q
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@@ -29,15 +29,13 @@ use work.cordic_pkg.all;
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(
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nbits_in : integer := 18;
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nbits_in_frac : integer := 16;
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nbits_out : integer := 18;
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nbits_out_frac : integer := 16;
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nbits_out : integer := 24;
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nbits_out_frac : integer := 22;
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lo_nbits_phase : integer := 20;
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lo_nbits_freq : integer := 20;
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cic_nstages : integer := 3;
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cic_max_ratio : integer := 1024;
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cic_max_diff_delay : integer := 2;
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cic_scale_nbits_min : integer := 9;
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cic_scale_nbits_max : integer := 32
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cic_ratio : integer := 64;
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cic_scale_nbits : integer := 18
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);
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PORT
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(
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@@ -47,9 +45,6 @@ use work.cordic_pkg.all;
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lo_nco_en : in std_logic;
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lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
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lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
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cic_ratio : in natural range 1 to cic_max_ratio;
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cic_diff_delay : in natural range 1 to cic_max_diff_delay;
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cic_shift_in : in natural range 0 to cic_scale_nbits_max;
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din_i : in signed(nbits_in-1 downto 0);
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din_q : in signed(nbits_in-1 downto 0);
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dout_i : out signed(nbits_out-1 downto 0);
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@@ -72,10 +67,8 @@ ARCHITECTURE behavior OF syn_ddc IS
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lo_nbits_phase : integer;
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lo_nbits_freq : integer;
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cic_nstages : integer;
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cic_max_ratio : integer;
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cic_max_diff_delay : integer;
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cic_scale_nbits_min : integer;
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cic_scale_nbits_max : integer
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cic_ratio : integer;
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cic_scale_nbits : integer
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);
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PORT
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(
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@@ -85,9 +78,6 @@ ARCHITECTURE behavior OF syn_ddc IS
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lo_nco_en : in std_logic;
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lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
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lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
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cic_ratio : in natural range 1 to cic_max_ratio;
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cic_diff_delay : in natural range 1 to cic_max_diff_delay;
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cic_shift_in : in natural range 0 to cic_scale_nbits_max;
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din_i : in sfixed;
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din_q : in sfixed;
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dout_i : out sfixed;
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@@ -116,10 +106,8 @@ BEGIN
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lo_nbits_phase => lo_nbits_phase,
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lo_nbits_freq => lo_nbits_freq,
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cic_nstages => cic_nstages,
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cic_max_ratio => cic_max_ratio,
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cic_max_diff_delay => cic_max_diff_delay,
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cic_scale_nbits_min => cic_scale_nbits_min,
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cic_scale_nbits_max => cic_scale_nbits_max
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cic_ratio => cic_ratio,
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cic_scale_nbits => cic_scale_nbits
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)
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PORT MAP
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(
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@@ -129,9 +117,6 @@ BEGIN
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lo_nco_en => lo_nco_en,
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lo_freq_in => lo_freq_in,
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lo_phase_in => lo_phase_in,
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cic_ratio => cic_ratio,
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cic_diff_delay => cic_diff_delay,
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cic_shift_in => cic_shift_in,
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din_i => ddc_din_i,
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din_q => ddc_din_q,
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dout_i => ddc_dout_i,
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@@ -31,15 +31,13 @@ ENTITY tb_ddc IS
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(
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nbits_in : integer := 16;
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nbits_in_frac : integer := 14;
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nbits_out : integer := 18;
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nbits_out_frac : integer := 16;
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nbits_out : integer := 24;
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nbits_out_frac : integer := 22;
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lo_nbits_phase : integer := 20;
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lo_nbits_freq : integer := 20;
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cic_nstages : integer := 3;
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cic_max_ratio : integer := 4096;
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cic_max_diff_delay : integer := 1;
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cic_scale_nbits_min : integer := 9;
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cic_scale_nbits_max : integer := 32;
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cic_ratio : integer := 50;
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cic_scale_nbits : integer := 16;
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rfgen_nbits_phase : integer := 20;
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rfgen_nbits_freq : integer := 20
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);
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@@ -58,10 +56,8 @@ ARCHITECTURE behavior OF tb_ddc IS
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lo_nbits_phase : integer;
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lo_nbits_freq : integer;
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cic_nstages : integer;
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cic_max_ratio : integer;
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cic_max_diff_delay : integer;
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cic_scale_nbits_min : integer;
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cic_scale_nbits_max : integer
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cic_ratio : integer;
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cic_scale_nbits : integer
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);
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PORT
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(
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@@ -71,9 +67,6 @@ ARCHITECTURE behavior OF tb_ddc IS
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lo_nco_en : in std_logic;
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lo_freq_in : in unsigned(lo_nbits_freq-1 downto 0);
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lo_phase_in : in unsigned(lo_nbits_phase-1 downto 0);
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cic_ratio : in natural range 1 to cic_max_ratio;
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cic_diff_delay : in natural range 1 to cic_max_diff_delay;
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cic_shift_in : in natural range 0 to cic_scale_nbits_max;
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din_i : in sfixed;
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din_q : in sfixed;
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dout_i : out sfixed;
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@@ -131,9 +124,6 @@ ARCHITECTURE behavior OF tb_ddc IS
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SIGNAL ddc_nco_en : std_logic := '0';
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SIGNAL ddc_freq_in : unsigned(lo_nbits_freq-1 downto 0) := (others => '0');
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SIGNAL ddc_phase_in : unsigned(lo_nbits_phase-1 downto 0) := (others => '0');
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SIGNAL ddc_diff_delay : natural := 1;
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SIGNAL ddc_ratio : natural := 64;
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SIGNAL ddc_shift_in : natural := 18-cic_scale_nbits_min;
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--Outputs
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SIGNAL ddc_din_i : sfixed(shi(nbits_in, nbits_in_frac) downto slo(nbits_in, nbits_in_frac));
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@@ -188,10 +178,8 @@ BEGIN
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lo_nbits_phase => lo_nbits_phase,
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lo_nbits_freq => lo_nbits_freq,
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cic_nstages => cic_nstages,
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cic_max_ratio => cic_max_ratio,
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cic_max_diff_delay => cic_max_diff_delay,
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cic_scale_nbits_min => cic_scale_nbits_min,
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cic_scale_nbits_max => cic_scale_nbits_max
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cic_ratio => cic_ratio,
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cic_scale_nbits => cic_scale_nbits
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)
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PORT MAP
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(
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@@ -201,9 +189,6 @@ BEGIN
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lo_nco_en => ddc_nco_en,
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lo_freq_in => ddc_freq_in,
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lo_phase_in => ddc_phase_in,
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cic_ratio => ddc_ratio,
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cic_diff_delay => ddc_diff_delay,
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cic_shift_in => ddc_shift_in,
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din_i => ddc_din_i,
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din_q => ddc_din_q,
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dout_i => ddc_dout_i,
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@@ -310,7 +295,7 @@ BEGIN
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rfgen_q_out_f <= to_real(rfgen_dout_q);
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tb : PROCESS
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file RESULT_FREQ: text open write_mode is "freq.txt";
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file RESULT_FREQ: text open write_mode is "ratio.txt";
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variable L: line;
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BEGIN
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@@ -319,7 +304,7 @@ BEGIN
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wait for 4*PERIOD;
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rst <= '0';
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fprint(RESULT_FREQ, L,"%s\n", REAL'image(flo));
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fprint(RESULT_FREQ, L,"%s\n", natural'image(cic_ratio));
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wait for 2*PERIOD;
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-------------------------------------------
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@@ -28,10 +28,9 @@ ENTITY cic_decim_pipe IS
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Generic
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(
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nstages : integer := 3;
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max_diff_delay : integer := 2;
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ratio_max : integer := 64;
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scale_nbits_min : integer := 9;
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scale_nbits_max : integer := 24;
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diff_delay : integer := 1;
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ratio : integer := 64;
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scale_nbits : integer := 9;
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in_width : integer := 32;
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in_width_frac : integer := 20;
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out_width : integer := 32;
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@@ -42,9 +41,6 @@ ENTITY cic_decim_pipe IS
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clk : in std_logic;
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rst : in std_logic;
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vld_in : in std_logic;
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ratio : in natural range 1 to ratio_max;
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diff_delay : in natural range 1 to max_diff_delay;
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shift_in : in natural range 0 to scale_nbits_max;
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din : in sfixed;
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dout : out sfixed;
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vld_out : out std_logic
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@@ -89,14 +85,13 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
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);
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END COMPONENT;
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constant min_gain_bits : natural := scale_nbits_min;
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constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio_max)**real(nstages)));
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constant max_gain_bits : natural := natural(NextExpBaseTwo(real(ratio)**real(nstages)));
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constant integ_nbits : natural := in_width + max_gain_bits;
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constant integ_nbits_frac : natural := integ_nbits - (in_width - in_width_frac);
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constant comb_nbits : natural := out_width + 1;
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constant comb_nbits_frac : natural := out_width_frac + 1;
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constant comb_nbits : natural := out_width+1;
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constant comb_nbits_frac : natural := out_width_frac+1;
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subtype word_i_t is sfixed(shi(integ_nbits, integ_nbits_frac) downto slo(integ_nbits, integ_nbits_frac));
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type word_i_pipe_t is array (0 to nstages) of word_i_t;
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@@ -112,12 +107,11 @@ ARCHITECTURE behavior OF cic_decim_pipe IS
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signal vld_c_pipe : unsigned (0 to nstages);
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signal vld_c : std_logic;
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signal resample_cnt : natural range 1 to ratio_max;
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signal resample_cnt : natural range 1 to ratio;
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signal resample_vld : std_logic;
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BEGIN
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assert false report "min_gain_bits = " & natural'image(min_gain_bits) & "." severity note;
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assert false report "max_gain_bits = " & natural'image(max_gain_bits) & "." severity note;
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assert false report "integ. prec. = " & natural'image(integ_nbits) & ":" & natural'image(integ_nbits_frac) & "." severity note;
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assert false report "comb prec. = " & natural'image(comb_nbits) & ":" & natural'image(comb_nbits_frac) & "." severity note;
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@@ -132,9 +126,8 @@ input_scale:
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begin
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if rising_edge(clk) then
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x := resize(din, x);
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xs := x sra min_gain_bits;
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xsi := xs sra shift_in;
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word_i_pipe(0) <= xsi;
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xs := x sra scale_nbits;
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word_i_pipe(0) <= xs;
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vld_i_pipe(0) <= vld_in;
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end if;
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end process;
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@@ -159,7 +152,7 @@ input_scale:
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);
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end generate;
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word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0));
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word_c_pipe(0) <= resize(word_i_pipe(nstages), word_c_pipe(0), fixed_wrap, fixed_truncate);
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vld_c_pipe(0) <= resample_vld;
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vld_c <= vld_c_pipe(nstages);
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@@ -171,7 +164,7 @@ input_scale:
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inst_cic_c_pipe: cic_c_pipe
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GENERIC MAP
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(
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max_diff_delay => max_diff_delay,
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max_diff_delay => diff_delay,
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max_width => comb_nbits,
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max_width_frac => comb_nbits_frac
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||||
)
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@@ -29,10 +29,8 @@ ENTITY tb_cic_decim_pipe IS
|
||||
Generic
|
||||
(
|
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nstages : integer := 3;
|
||||
ratio_max : integer := 1024;
|
||||
scale_nbits_min : integer := 9;
|
||||
scale_nbits_max : integer := 32;
|
||||
max_diff_delay : integer := 2;
|
||||
ratio : integer := 64;
|
||||
scale_nbits : integer := 18;
|
||||
in_width : integer := 18;
|
||||
in_width_frac : integer := 16;
|
||||
out_width : integer := 18;
|
||||
@@ -47,10 +45,8 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
|
||||
GENERIC
|
||||
(
|
||||
nstages : integer;
|
||||
ratio_max : integer;
|
||||
scale_nbits_min : integer;
|
||||
scale_nbits_max : integer;
|
||||
max_diff_delay : integer;
|
||||
ratio : integer;
|
||||
scale_nbits : integer;
|
||||
in_width : integer;
|
||||
in_width_frac : integer;
|
||||
out_width : integer;
|
||||
@@ -61,9 +57,6 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
vld_in : in std_logic;
|
||||
ratio : in natural range 1 to ratio_max;
|
||||
diff_delay : in natural range 1 to max_diff_delay;
|
||||
shift_in : in natural range 0 to scale_nbits_max;
|
||||
din : in sfixed;
|
||||
dout : out sfixed;
|
||||
vld_out : out std_logic
|
||||
@@ -79,9 +72,6 @@ ARCHITECTURE behavior OF tb_cic_decim_pipe IS
|
||||
SIGNAL srst : std_logic := '1';
|
||||
SIGNAL vld_in : std_logic := '0';
|
||||
SIGNAL din : sfixed(shi(in_width, in_width_frac) downto slo(in_width, in_width_frac));
|
||||
SIGNAL diff_delay : natural := 1;
|
||||
SIGNAL ratio : natural := 64;
|
||||
SIGNAL shift_in : natural := 18-scale_nbits_min;
|
||||
|
||||
--Outputs
|
||||
SIGNAL dout : sfixed(shi(out_width, out_width_frac) downto slo(out_width, out_width_frac));
|
||||
@@ -101,10 +91,8 @@ BEGIN
|
||||
GENERIC MAP
|
||||
(
|
||||
nstages => nstages,
|
||||
ratio_max => ratio_max,
|
||||
scale_nbits_min => scale_nbits_min,
|
||||
scale_nbits_max => scale_nbits_max,
|
||||
max_diff_delay => max_diff_delay,
|
||||
ratio => ratio,
|
||||
scale_nbits => scale_nbits,
|
||||
in_width => in_width,
|
||||
in_width_frac => in_width_frac,
|
||||
out_width => out_width,
|
||||
@@ -115,9 +103,6 @@ BEGIN
|
||||
clk => clk,
|
||||
rst => srst,
|
||||
vld_in => vld_in,
|
||||
ratio => ratio,
|
||||
diff_delay => diff_delay,
|
||||
shift_in => shift_in,
|
||||
din => din,
|
||||
dout => dout,
|
||||
vld_out => vld_out
|
||||
|
||||
Reference in New Issue
Block a user