[uart]

- added simulation entities

git-svn-id: http://moon:8086/svn/vhdl/trunk@1079 cc03376c-175c-47c8-b038-4cd826a8556b

lib/uart/uart_tx_sim.vhd

@@ -0,0 +1,65 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+use std.textio.all; --  Imports the standard textio package.
+--
+------------------------------------------------------------------------------------
+--
+-- Main Entity for UART_TX
+--
+entity uart_tx is
+    Port (            data_in : in std_logic_vector(7 downto 0);
+                 write_buffer : in std_logic;
+                 reset_buffer : in std_logic;
+                 en_16_x_baud : in std_logic;
+                   serial_out : out std_logic;
+                  buffer_full : out std_logic;
+             buffer_half_full : out std_logic;
+             tx_complete	  : out std_logic;
+             tx_empty		  : out std_logic;
+                          clk : in std_logic);
+    end uart_tx;
+
+------------------------------------------------------------------------------------
+--
+-- Start of UART_TX circuit description
+--
+------------------------------------------------------------------------------------
+--	
+
+ARCHITECTURE behavior OF uart_tx IS
+
+begin
+
+serial_out <= '0';
+buffer_full <= '0';
+buffer_half_full <= '0';
+tx_complete		<= '1';
+tx_empty		<= '1';
+
+registers_write: 
+	process(clk)
+	file output:	      text open write_mode is "STD_OUTPUT"; 
+	variable L : line; 
+	begin
+		if rising_edge(clk) then
+			if write_buffer = '1' then
+				if data_in /= X"0D" then
+					write(L, character'val(to_integer(unsigned(data_in))));
+				end if;	
+				if data_in = X"0A" then
+					writeline(output, L);
+				end if;
+			end if;	
+		end if;	
+	end process;
+
+end behavior;
+
+------------------------------------------------------------------------------------
+--
+-- END OF FILE UART_TX.VHD
+--
+------------------------------------------------------------------------------------
+
+